ANALOG DEVICES AD5684R English products handbook
Contents
1. 4 0 Vpp 5V 3 9 Ta 25 C INTERNAL REFERENCE 2 5V 3 8 3 7 _ 36 5 35 1 3 4 3 3 3 2 IEEE E a Ta 25 C INT L REFERENCE y 3 0 E 1 590 1 595 1 600 1 605 1 610 1 615 1 620 1 625 1 630 CH1 10uV M1 0s A CH1 802mV 2 TIME ms Figure 44 0 1 Hz to 10 Hz Output Noise Plot 2 5 V Internal Reference Figure 47 Settling Time vs Capacitive Load 0 1600 Yop BA FULL SCALE AT MIDSCALE 1400 INTERNAL REFERENCE 2 5V ZERO SCALE 10 1200 a 2 q 1000 N I B 30 800 a 2 lt x 2 600 m 40 400 50 Vpp 5V 200 TA 25 C o EXTERNAL REFERENCE 2 5V 0 1V p p 0 10k 100k 1M 10M 7 10 100 1k 10k 100k M 5 FREQUENCY Hz 3 FREQUENCY Hz m Figure 48 Multiplying Bandwidth External Reference 2 5 V 0 1 V p p Figure 45 Noise Spectral Density 10kHz to 10 MHz 20 Vpp 5V 0 Ta 25 C INTERNAL REFERENCE 2 5V 20 40 s 60 a 80 a x 100 120 340 U Ai kl aL bl an duit ad a 160 180 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 FREQUENCY Hz 10485 149 Figure 46 Total Harmonic Distortion 1 kHz Rev 0 Page 17 of 32 AD5686R AD5685R AD5684R TERMINOLOGY Relative Accuracy or Integral Nonlinearity INL For the DAC relative accuracy or integral nonlinearity is a measurement of the2. tc EXTERNAL REFERENCE FULL SCALE lt 02 E 23 o 04 SOURCING 5V 0 6 SOURCING 2 7V 0 8 1 0 A g 0 5 10 15 20 25 30 5 40 10 60 110 b LOAD CURRENT mA 3 TEMPERATURE C Figure 34 Headroom Footroom vs Load Current Figure 37 Supply Current vs Temperature Rev 0 Page 15 of 32 AD5686R AD5685R AD5684R 2 5008 2 5003 3 3 E E 2 4998 gt CHANNEL B 24993 T 25 C Vpp 5V Vpp 5 25V Ta 25 C INTERNAL REFERENCE INTERNAL REFERENCE 2 5V CODE 7FFF TO 8000 TO SCALE ENERGY 0 227206nV sec z 2 4988 10 20 40 80 160 320 i TIME us E TIME us Figure 38 Settling Time 5 25 V Figure 41 Digital to Analog Glitch Impulse 0 003 0 002 S 0001 3 a E A 2 3 P 8 Q 0 M o 0 001 Ta 25 C INTERNAL REFERENCE 2 5V g 0 002 2 M 0 5 10 15 20 25 TIME us TIME us E Figure 39 Power On Reset to 0 V Figure 42 Analog Crosstalk Channel A c E 1 Vpp 5V TA 25 C nane an testaenna nanem INTERNAL REFERENCE 2 5V 0 2 E TIME us 3 CH1 10pV M1 0s A CH1 802mV Figure 40 Exiting Power Down to Midscale Figure 43 0 1 Hz to 10 Hz Output Noise Plot External Reference Rev 0 Page 16 of 32 AD5686R AD5685R AD5684R
3. 501 2 502 Vrer V Figure 58 Reference Drift Through to 1000 Hours 10485 061 Rev 0 Page 26 of 32 AD5686R AD5685R AD5684R THERMAL HYSTERESIS 1 FIRST TEMPERATURE SWEEP Thermal hysteresis is the voltage difference induced on the C SUBSEQUENT TEMPERATURE SWEEPS reference voltage by sweeping the temperature from ambient to cold to hot and then back to ambient Thermal hysteresis data is shown in Figure 59 It is measured by sweeping the temperature from ambient to 40 C then to 105 C and returning to ambient The Vrer delta is then measured between the two ambient measurements and HITS shown in blue in Figure 59 The same temperature sweep and measurements were immediately repeated and the results are shown in red in Figure 59 200 150 100 50 0 50 DISTORTION ppm 10485 062 Figure 59 Thermal Hysteresis Table 15 24 Bit Input Shift Register Contents for Internal Reference Setup Command DB23 MSB DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DBO LSB 0 1 1 1 X X X X X 1 0 Command bits C3 to CO Address bits A2 to AO Don t care Reference setup register 1X don t care Rev 0 Page 27 of 32 AD5686R AD5685R AD5684R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5686R AD5685R AD5684R is via a serial bus that uses a standard protocol that is compatible with DSP processors an
4. 65 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters Rev 0 Page 30 of 32 AD5686R AD5685R AD5684R ORDERING GUIDE Reference Temperature Tempco Package Package Model Resolution Range Accuracy ppm C Description Option Branding AD5686RACPZ RL7 16 Bits 40 C to 105 C 8 LSB INL 5 typ 16 Lead LFCSP_WQ CP 16 22 DJM AD5686RBCPZ RL7 16 Bits 40 C to 105 C 2 LSB INL 5 max 16 Lead LFCSP_WQ CP 16 22 DJN AD5686RARUZ 16 Bits 40 C to 105 C 8 LSB INL 5 typ 16 Lead TSSOP RU 16 AD5686RARUZ RL7 16 Bits 40 C to 105 C 8 LSB INL 5 typ 16 Lead TSSOP RU 16 AD5686RBRUZ 16 Bits 40 C to 105 C 2 LSB INL 5 max 16 Lead TSSOP RU 16 AD5686RBRUZ RL7 16 Bits 40 C to 105 C 2 LSB INL 5 max 16 Lead TSSOP RU 16 AD5685RBCPZ RL7 14 Bits 40 C to 105 C 1 LSB INL 5 max 16 Lead LFCSP_WQ CP 16 22 DJK AD5685RARUZ 14 Bits 40 C to 105 C 4 LSB INL 5 typ 16 Lead TSSOP RU 16 AD5685RARUZ RL7 14 Bits 40 C to 105 C 4 LSB INL 5 typ 16 Lead TSSOP RU 16 AD5685RBRUZ 14 Bits 40 C to 105 C 1 LSB INL 5 max 16 Lead TSSOP RU 16 AD5685RBRUZ RL7 14 Bits 40 C to 105 C 1 LSB INL 5 max 16 Lead TSSOP RU 16 AD5684RBCPZ RL7 12 Bits 40 C to 105 C 1 LSB INL 5 max 16 Lead LFCSP_WQ CP 16 22 DJG AD5684RARUZ 12 Bits 40 C to 105 C 2 LSB INL 5 typ 16 Lead TSSOP RU 16 AD5684RARUZ RL7 12 Bits 40 C to 105 C 2 LSB INL 5 typ 16 Le
5. Circuit Current 40 40 mA Load Impedance at Rails 25 25 Q See Figure 34 Power Up Time 2 5 2 5 us Coming out of power down mode Vop 5V Rev 0 Page 3 of 32 AD5686R AD5685R AD5684R A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions Comments REFERENCE OUTPUT Output Voltage 2 4975 2 5025 2 4975 2 5025 V At ambient Reference TC 5 20 2 5 ppm C See the Terminology section Output Impedance 0 04 0 04 Q Output Voltage Noise 12 12 uV p p 0 1 Hz to 10 Hz Output Voltage Noise 240 240 nV VHz At ambient f 10 kHz C 10 nF Density Load Regulation Sourcing 20 20 uV mA Atambient Load Regulation Sinking 40 40 uV mA Atambient Output Current Load 5 5 mA Voo 2 3 V Capability Line Regulation 100 100 V V At ambient Long Term Stability Drift 12 12 ppm After 1000 hours at 125 C Thermal Hysteresis 125 125 ppm First cycle 25 25 ppm Additional cycles LOGIC INPUTS Input Current 2 2 uA Per pin Vint Input Low Voltage 0 3 x Vioac 0 3 x Vioaic V Vs Input High Voltage 0 7 x Vioaic 0 7 x Vioaic V Pin Capacitance 2 2 pF LOGIC OUTPUTS SDO Output Low Voltage Vo 0 4 0 4 V Isink 200 pA Output High Voltage Vox Vioaic 0 4 Vioaic 0 4 V Isource 200 pA Floating State Output 4 4 pF Capacitance POWER REQUIREMENTS Vioaic 1 8 5 5 1 8 5 5 V lLoaic 3 3 pA Voo 2 7 5 5 2 7 5 5 V Gain 1 Voo Vner 1 5 5 5 Vrer 1 5 5 5 V Gain 2 lop Vi Vop Vi GND Voo 2 7 V to 5 5 V No
6. E E 5 d 0 2 4996 z 2 2 4995 m 6 2 4994 g Vop 5V TA 25 C 2 4993 _40 INTERNAL REFERENCE 2 5V g 0 005 0 003 0 001 0 001 0 003 0 005 0 2500 5000 7500 10000 12500 1500016348 lLoAp A CODE 3 Figure 14 Internal Reference Voltage vs Load Current Figure 17 AD5685R INL 2 5002 TA 25 C D1 2 5000 2 4998 D3 E y 4 2 4996 9 gt a z 2 4994 2 4992 D2 2 4990 is 25 M 40 aa 30 sa m 0 625 1250 1875 2500 3125 3750 4096 Von V CODE E Figure 15 Internal Reference Voltage vs Supply Voltage Figure 18 AD5684R INL a a TELLE a ao mpm d a E z a TA 25 C INTERNAL REFERENCE 2 5V INTERNAL REFERENCE 2 5V 0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000 CODE CODE Figure 16 AD5686R INL Figure 19 AD5686R DNL Rev 0 Page 12 of 32 AD5686R AD5685R AD5684R a g E a m z 2 A 0 2 E Vpp 5V Ta 25 C INTERNAL REFERENCE 2 5V 0 2500 5000 7500 10000 12500 1500016383 F 0 05 10 15 20 25 30 35 40 45 50 F CODE 3 Vner V 3 Figure 20 AD5685R DNL Figure 23 INL Error and DNL Error vs Veer E E 2 2 a o a E 0 2 z 0 4 Vpp 5V A 25 C INTERNAL REFERENCE 2 5V 0 625 1250 1875 2500 3125 3750 4096 2 7 3 2 37 4 2 4 7 5 2 CODE E SUPPLY VOLTAGE V Figure 21 AD5684R DNL Figure 24 INL Error and
7. and invalid data may be loaded to the DAC SYNC must be brought high for a minimum of 20 ns single channel see ts in Figure 2 before the next write sequence so that a falling edge of SYNC can initiate the next write sequence SYNC should be idled at rails between write sequences for even lower power operation of the part The SYNC line is kept low for 24 falling edges of SCLK and the DAC is updated on the rising edge of SYNC When the data has been transferred into the input register of the addressed DAC all DAC registers and outputs can be updated by taking LDAC low while the SYNC line is high WRITE AND UPDATE COMMANDS Write to Input Register n Dependent on LDAC Command 0001 allows the user to write to each DAC s dedicated input register individually When LDAC is low the input register is transparent if not controlled by the LDAC mask register Update DAC Register n with Contents of Input Register n Command 0010 loads the DAC registers outputs with the contents of the input registers selected and updates the DAC outputs directly Write to and Update DAC Channel n Independent of LDAC Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly Rev 0 Page 22 of 32 AD5686R AD5685R AD5684R DAISY CHAIN OPERATION For systems that contain several DACs the SDO pin can be used to daisy chain several devices together and is enabled through a
8. available Because the input coding to the DAC is straight binary the ideal output voltage when using an external reference is given by D Vour Veer X Gain Ix where D is the decimal equivalent of the binary code that is loaded to the DAC register as follows 0 to 4 095 for the 12 bit device 0 to 16 383 for the 14 bit device 0 to 65 535 for the 16 bit device N is the DAC resolution Gain is the gain of the output amplifier and is set to 1 by default This can be set to x1 or x2 using the gain select pin When this pin is tied to GND all four DAC outputs have a span from 0 V to Vrer If this pin is tied to Vpp all four DACs output a span of 0 V to 2 x Vir DAC ARCHITECTURE The DAC architecture consists of a string DAC followed by an output amplifier Figure 49 shows a block diagram of the DAC architecture VREF REF INPUT RESISTOR REGISTER STRING REF lt o c 4 x lt GAIN GAIN 1 OR 2 10485 052 GND Figure 49 Single DAC Channel Architecture Block Diagram The resistor string structure is shown in Figure 50 It is a string of resistors each of Value R The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier The voltage is tapped off by closing one of the switches connecting the string to the amplifier Because it is a string of resistors it is guaranteed monotonic VREF R R R TO OUTP
9. result from its use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2012 Analog Devices Inc All rights reserved AD5686R AD5685R AD5684R TABLE OF CONTENTS Features occa cece R Tuer 1 Applications tone bee UD OEC RIP REI 1 Functional Block Diagram sse 1 General Description oco ett e I EA IDEE 1 Product Highlights ert eem 1 REVISIONS HistOEye sere ORDER easter 2 Specifications issii eet ite i ero Rer pedis ties 3 AC Characteristics ni tnos nee ERI e Extel ie irte 5 Timing Characteristics sse 6 Daisy Chain and Readback Timing Characteristics 7 Absolute Maximum Ratings esee 9 ESD Caution ceteri terneteitetesi rteesi eerie tins 9 Pin Configuration and Function Descriptions 10 Typical Performance Characteristics wll Terminology yine a RENNER 18 Theory of Operation zoe e E E OOE 20 Digital to Analog Converter sse 20 Transfer FUnCtions ie tette ttes eee it ee ebat 20 DAC Architecture zia ES 20 Serial Interface ccccs ERREUR ERIT m 21 Standalone Operation eerte 22 REVISION HISTORY 4
10. software executable daisy chain enable DCEN command Command 1000 is reserved for this DCEN function see Table 7 The daisy chain mode is enabled by setting Bit DBO in the DCEN register The default setting is standalone mode where DBO 0 Table 9 shows how the state of the bit corresponds to the mode of operation of the device Table 9 Daisy Chain Enable DCEN Register DBO Description 0 Standalone mode default 1 DCEN mode AD5686R 68HC11 AD5685R AD5684R AD5686R AD5685R AD5684R SCLK SYNC LDAC SDO Q SDIN AD5686R AD5685R AD5684R SCLK SYNC LDAC SDO ADDITIONAL PINS OMITTED FOR CLARITY Figure 54 Daisy Chaining the AD5686R AD5685R AD5684R 10485 057 The SCLK pin is continuously applied to the input shift register when SYNC is low If more than 24 clock pulses are applied the data ripples out of the input shift register and appears on the SDO line This data is clocked out on the rising edge of SCLK and is valid on the falling edge By connecting this line to the SDIN input on the next DAC in the chain a daisy chain interface is constructed Each DAC in the system requires 24 clock pulses Therefore the total number of clock cycles must equal 24 x N where N is the total number of devices that are updated If SYNC is taken high at a clock that is not a multiple of 24 it is considered a valid frame and invalid data may be loaded to the DAC When the serial transfer to all dev
11. 0 0 1 DACA register on the 24 falling edges of SCLK and are updated on the 0 0 1 0 DACB rising edge of SYNC 0 1 0 0 DACC Commands can be executed on individual DAC channels pd j 0 0 1 1 DAC A and DAC B combined DAC channels or on all DACs depending on the 1 1 1 1 All DACs address bits selected 1 Any combination of DAC channels can be selected using the address bits DB23 MSB DBO LSB pac pac pac pac x DATA BITS Nee t t COMMAND BITS ADDRESS BITS Figure 51 AD5686R Input Shift Register Content 10485 054 DB23 MSB DBO LSB DAC DAC DAC DAC m DATA BITS gt Hu 1 COMMAND BITS ADDRESS BITS Figure 52 AD5685R Input Shift Register Content 10485 055 DB23 MSB DBO LSB DAC DAC DAC DAC DATA BITS gt 10485 056 COMMAND BITS ADDRESS BITS Figure 53 AD5684R Input Shift Register Content Rev 0 Page 21 of 32 AD5686R AD5685R AD5684R STANDALONE OPERATION The write sequence begins by bringing the SYNC line low Data from the SDIN line is clocked into the 24 bit input shift register on the falling edge of SCLK After the last of 24 data bits is clocked in SYNC should be brought high The programmed function is then executed that is an LDAC dependent change in DAC register contents and or a change in the mode of operation If SYNC is taken high at a clock before the 24 clock it is considered a valid frame
12. 03 SCLK ty to SYNC E a te son C A AeA XX X A A INPUT WORD FOR DAC N INPUT WORD FOR DAC N 1 tio svo OOCR EA 936 X 3X UNDEFINED INPUT WORD FOR DAC N 3 Figure 4 Daisy Chain Timing Diagram Rev 0 Page 7 of 32 AD5686R AD5685R AD5684R t SCLK 1 24 t 3 t t t h tg SYNC on Cs INPUT WORD SPECIFIES NOP oo REGISTER TO BE READ a eec Boe UNDEFINED SELECTED REGISTER DATA CLOCKED OUT 10485 005 Figure 5 Readback Timing Diagram Rev 0 Page 8 of 32 AD5686R AD5685R AD5684R ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 5 Parameter Rating Vop to GND 0 3V to 47V Vioac to GND 0 3 V to 7 V Vout to GND 0 3 V to Vpp 0 3 V Vrer to GND 0 3 V to Voo 0 3 V Digital Input Voltage to GND 0 3 V to Vioac 0 3 V Operating Temperature Range 40 C to 105 C Storage Temperature Range 65 C to 150 C Junction Temperature 125 C 16 Lead TSSOP Oja Thermal 112 6 C W Impedance 0 Airflow 4 Layer Board 16 Lead LFCSP Oja Thermal 70 C W Impedance 0 Airflow 4 Layer Board Reflow Soldering Peak 260 C Temperature Pb Free J STD 020 ESD 4kV FICDM 1 5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of t
13. 12 Revision 0 Initial Version Write and Update Commands sss 22 Daisy Chain Operation seen 23 Readback Operation sse 23 Power Down Operation sse 24 Load DAC Hardware LDAC Pin 5h ctscciticie ts eei HS 25 LDAC Mask Registet ssnstkar nice a as 25 Hardware Reset RESET sscsscsssssssssesssssuesssssssesessecsesssesessueeesseee 26 Reset Select Pin RSTSEL eese 26 Internal Reference Setup etii seitin 26 Solder Heat Reflow iiesccssissssssssnsssssscvnssisssnsstsevesascnasessesvenveeteeess 26 Long Term Temperature Drift sse 26 Thermal Hysteresis ze Re eret DE 27 Applications Information eeeeeeeeeteentnn 28 Microprocessor Interfacing seen 28 AD5686R AD5685R AD5684R to ADSP BF531 Interface 28 AD5686R AD5685R AD5684R to SPORT Interface 28 Layout Guidelines 5 eoo en Re 28 Galvanically Isolated Interface sss 29 Outline Dimensions petenti tte i pee edes 30 Ordering Gilde eei tete etie iip Asti 31 Rev 0 Page 2 of 32 AD5686R AD5685R AD5684R SPECIFICATIONS Vpp 2 7 V to 5 5 V 1 8 V Viocic lt 5 5 V all specifications Tu to Tmax unless otherwise noted Ri 2 KQ C 200 pF Table 2 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions Comments STATIC PERFORMANCE AD5686R Resolution 16 16 Bits Rel
14. 3 to CO Address bits Power Down Power Down Power Down Power Down Don t care Select DAC D Select DAC C Select DAC B Select DAC A 1X don t care Rev 0 Page 24 of 32 AD5686R AD5685R AD5684R LOAD DAC HARDWARE LDAC PIN The AD5686R AD5685R AD5684R DACs have double buffered interfaces consisting of two banks of registers input registers and DAC registers The user can write to any combination of the input registers Updates to the DAC register are controlled by the LDAC pin OUTPUT AMPLIFIER VourX DAC LDAC REGISTER SDO 10485 059 Figure 56 Simplified Diagram of Input Loading Circuitry for a Single DAC Instantaneous DAC Updating LDAC Held Low LDAC is held low while data is clocked into the input register using Command 0001 Both the addressed input register and the DAC register are updated on the rising edge of SYNC and the output begins to change see Table 13 Deferred DAC Updating LDAC is Pulsed Low LDAC is held high while data is clocked into the input register using Command 0001 All DAC outputs are asynchronously updated by taking LDAC low after SYNC has been taken high The update now occurs on the falling edge of LDAC Table 13 Write Commands and LDAC Pin Truth Table LDAC MASK REGISTER Command 0101 is reserved for this software LDAC function Address bits are ignored Writing to the DAC using Command 0101 loads the 4 bit LDAC register DB
15. 3 to DBO The default for each channel is 0 that is the LDAC pin works normally Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin regardless of the state of the hardware LDAC pin This flexibility is useful in applications where the user wishes to select which channels respond to the LDAC pin Table 12 LDAC Overwrite Definition Load LDAC Register LDAC Bits DB3 to DBO LDACPin LDAC Operation 0 1or0 Determined by the LDAC pin 1 x DAC channels update and override the LDAC pin DAC channels see LDAC as 1 X don t care The LDAC register gives the user extra flexibility and control over the hardware LDAC pin see Table 12 Setting the LDAC bits DBO to DB3 to 0 for a DAC channel means that this channel s update is controlled by the hardware LDAC pin Hardware LDAC Input Register Commands Description Pin State Contents DAC Register Contents 0001 Write to Input Register n dependent on LDAC Vioaic Data update No change no update GND Data update Data update 0010 Update DAC Register n with contents of Input Vioaic No change Updated with input register Register n contents GND No change Updated with input register contents 0011 Write to and update DAC Channel n Vioaic Data update Data update GND Data update Data update A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC reg
16. 5R AD5684R operation 32 clock edge to 90 of DAC midscale value with output unloaded SCLK SYNC SDIN LDAC LDAC2 T Ada Vour li gt TASYNCHRONOUS LDAC UPDATE MODE 2SYNCHRONOUS LDAC UPDATE MODE 10485 002 Figure 2 Serial Write Operation Rev 0 Page 6 of 32 AD5686R AD5685R AD5684R DAISY CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tr tr 1 ns V 10 to 90 of Vp and timed from a voltage level of Vi Vm 2 See Figure 4 and Figure 5 Vpp 2 7 V to 5 5 V 1 8 V Vioaic 5 5 V Vrer 2 5 V All specifications Tmn to Tmax unless otherwise noted Vp 2 7 V to 5 5 V Table 5 1 8 V lt Vicac lt 2 7 V 2 7 V lt Vioac lt 5 5 V Parameter Symbol Min Max Min Max Unit SCLK Cycle Time ti 66 40 ns SCLK High Time t 33 20 ns SCLK Low Time ts 33 20 ns SYNC to SCLK Falling Edge ta 33 20 ns Data Setup Time ts 5 5 ns Data Hold Time te 5 5 ns SCLK Falling Edge to SYNC Rising Edge t 15 10 ns Minimum SYNC High Time ts 60 30 ns Minimum SYNC High Time t 60 30 ns SDO Data Valid from SCLK Rising Edge tio 36 25 ns SCLK Falling Edge to SYNC Rising Edge ti 15 10 ns SYNC Rising Edge to SCLK Rising Edge ti 15 10 ns 1 Maximum SCLK frequency is 25 MHz or 15 MHz at Voo 2 7 V to 5 5 V 1 8 V Vioac Voo Guaranteed by design and characterization not production tested Circuit and Timing Diagrams Von MIN 10485 0
17. ANALOG Quad 16 14 12 Bit nanoDAC DEVICES with 2 ppm C Reference SPI Interface AD5686R AD5685R AD5684R FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy INL 2 LSB maximum 16 bits Low drift 2 5 V reference 2 ppm C typical Vop GND VREF Tiny package 3 mm x 3 mm 16 lead LFCSP Total unadjusted error TUE 0 1 of FSR maximum Vioaic O DUT a Offset error 1 5 mV maximum SCLK O 2 Gain error 0 1 of FSR maximum High drive capability 20 mA 0 5 V from supply rails SYNC REGISTER GIST o oO VourB User selectable gain of 1 or 2 GAIN pin Reset to zero scale or midscale RSTSEL pin SDIN T o1ro O Vourc 1 8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch 0 5 nV sec Robust 4 kV HBM and 1 5 kV FICDM ESD rating Low power 3 3 mW at 3 V DAC REGISTER in 9 0 O VourD O O O 8 2 7 V to 5 5 V power supply LDAC RESET RSTSEL GAIN 8 40 C to 105 C temperature range Figure 1 APPLICATIONS Optical transceivers Base station power amplifiers Process control PLC I O cards Industrial automation Data acquisition systems GENERAL DESCRIPTION Table 1 Quad nanoDAC Devices The AD5686R AD5685R AD5684R members of the Interface Reference eee oa a nanoDAC family are low power quad 16 14 12 bit nerna PC Internal AD5696R AD5695R AD5694R buffered voltage output DACs The devices include a 2 5 V 2 ppm C internal re
18. C Figure 29 TUE vs Temperature Vpp 5V Ta 25 C INTERNAL REFERENCE 2 5V 27 3 2 3 7 4 2 47 5 2 SUPPLY VOLTAGE V Figure 30 TUE vs Supply Gain 1 Vpp 5V Ta 25 C INTERNAL REFERENCE 2 5V 0 10000 20000 30000 40000 50000 60000 65535 CODE Figure 31 TUE vs Code 10485 131 10485 132 10485 133 AD5686R AD5685R AD5684R Vpp 5V Vpp 5V Ta 25 C e Ta 25 C EXTERNAL GAIN 2 REFERENCE 2 5V INTERNAL 5 REFERENCE 2 5V 4 o 3 E 5 2 2 1 0 E g 3 540 560 580 600 620 640 0 00 0 04 0 02 0 0 02 0 04 006 Ipp V E LOAD CURRENT A Figure 35 Source and Sink Capability at 5 V 5 Vpp 5V Vpp 5V Ta 25 C Ty 25 C INTERNAL 4 EXTERNAL REFERENCE 2 5V REFERENCE 2 5V GAIN 1 OxFFFF 3 0xC000 2 2 o 0x8000 5 2 a 0x4000 0 0x0000 ill 0 L C LI 1 2 1000 1020 1040 1060 1080 1100 1120 1140 7 0 06 0 04 0 02 0 0 02 0 04 0 06 Ipp FULLSCALE V E LOAD CURRENT A 8 Figure 33 loo Histogram with Internal Reference Vrerour 2 5 V Gain 2 Figure 36 Source and Sink Capability at 3 V 1 0 0 8 0 6 i FULL SCALE 0 4 SINKING 2 7V o ZERO CODE s 0 SINKING 5V 5 o A gt
19. DEVICE 3 500 HOURS DEVICE 4 1000 HOURS 2 5010 DEVICE 5 50 2 5005 40 z g u 2 5 E pe T 30 gt 2 4995 20 2 4990 10 2 4985 2 4980 a 40 20 0 20 40 60 80 100 120 5 2 498 2 499 2 500 2 501 2 502 8 TEMPERATURE C 8 Veer V i Figure 8 Internal Reference Voltage vs Temperature Grade B Figure 11 Reference Long Term Stability Drift 2 5020 1600 DEVICE 1 DEVICE 2 2 5015 DEVICE 3 1400 DEVICE 4 2 5010 DEVICE 5 1200 2 5005 1000 r z 4 2 5000 800 c gt E 2 4995 600 2 4990 400 2 4985 200 Vpp 5V 2 4980 0 40 20 0 20 40 60 80 100 120 10 100 1k 10k 100k iM 3 TEMPERATURE C FREQUENCY MHz Figure 9 Internal Reference Voltage vs Temperature Grade A Figure 12 Internal Reference Noise Spectral Density vs Frequency 90 80 70 Z l b 7 NULLE A M AL A 2 m i ui n 1 i n n V VP NATAL j i EAT PE 20 10 0 R 0 05 10 15 20 25 30 35 40 45 50 TEMPERATURE DRIFT ppm C E CH1 10V M1 0s A CHi 160mv Figure 10 Reference Output Temperature Drift Histogram Figure 13 Internal Reference Noise 0 1 Hz to 10 Hz Rev 0 Page 11 of 32 AD5686R AD5685R AD5684R 2 5000 10 8 2 4999 6 2 4998 4 2 gt 2 4997 a
20. DNL Error vs Supply Voltage __ FULL SCALE ERROR GAIN ERROR ERROR LSB 40 20 0 20 40 60 80 100 120 TEMPERATURE C Figure 25 Gain Error and Full Scale Error vs Temperature 40 10 60 110 TEMPERATURE C Figure 22 INL Error and DNL Error vs Temperature 10485 124 10485 127 Rev 0 Page 13 of 32 AD5686R AD5685R AD5684R ERROR mV ERROR of FSR ERROR mV Vpp 5V 14 Ta 25 C INTERNAL REFERENCE 2 5V 40 20 0 20 40 60 80 100 120 TEMPERATURE C Figure 26 Zero Code Error and Offset Error vs Temperature FULL SCALE ERROR 2 7 3 2 3 7 4 2 4 7 5 2 SUPPLY VOLTAGE V Figure 27 Gain Error and Full Scale Error vs Supply ZERO CODE ERROR ee OFFSET ERROR Vpp 5V Ta 25 C INTERNAL REFERENCE 2 5V 2 7 3 2 3 7 4 2 4 7 5 2 SUPPLY VOLTAGE V Figure 28 Zero Code Error and Offset Error vs Supply TOTAL UNADJUSTED ERROR of FSR 10485 128 TOTAL UNADJUSTED ERROR of FSR 10485 129 TOTAL UNADJUSTED ERROR of FSR 10485 130 Rev 0 Page 14 of 32 0 10 Vpp 5V 0 09 Ta 25 C INTERNAL REFERENCE 2 5V 0 08 0 07 0 06 0 05 0 04 0 03 0 02 0 01 40 20 0 20 40 60 80 100 120 TEMPERATURE
21. UT AMPLIFIER l I l l l l l l l l R R 10485 053 Figure 50 Resistor String Structure Internal Reference The AD5686R AD5685R AD5684R on chip reference is on at power up but can be disabled via a write to a control register See the Internal Reference Setup section for details The AD5686R AD5685R AD5684R have a 2 5 V 2 ppm C reference giving a full scale output of 2 5 V or 5 V depending on the state of the GAIN pin The internal reference associated with the device is available at the Vrer pin This buffered reference is capable of driving external loads of up to 10 mA Output Amplifiers The output buffer amplifier can generate rail to rail voltages on its output which gives an output range of 0 V to Vpp The actual range depends on the value of Vrer the GAIN pin offset error and gain error The GAIN pin selects the gain of the output e If this pin is tied to GND all four outputs have a gain of 1 and the output range is 0 V to Vrer e If this pin is tied to Viocic all four outputs have a gain of 2 and the output range is 0 V to 2 x Vnzr These amplifiers are capable of driving a load of 1 KQ in parallel with 2 nF to GND The slew rate is 0 8 V us with a 4 to scale settling time of 5 us Rev 0 Page 20 of 32 AD5686R AD5685R AD5684R SERIAL INTERFACE Table 7 Command Definitions The AD5686R AD5685R AD5684R have a 3 wire serial command interface SYNC SCLK and SDIN that is
22. ad TSSOP RU 16 AD5684RBRUZ 12 Bits 40 C to 105 C 1 LSB INL 5 max 16 Lead TSSOP RU 16 AD5684RBRUZ RL7 12 Bits 40 C to 105 C 1 LSB INL 5 max 16 Lead TSSOP RU 16 EVAL AD5686RSDZ AD5686R TSSOP Evaluation Board EVAL AD5684RSDZ AD5684R TSSOP Evaluation Board 1 Z RoHS Compliant Part Rev 0 Page 31 of 32 AD5686R AD5685R AD5684R NOTES 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners DiOA25 04 12 0 DEVICES www analog com Rev 0 Page 32 of 32
23. asurement of the change in offset error with a change in temperature It is expressed in uV C Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature It is expressed in ppm of FSR C Offset Error Offset error is a measure of the difference between Vour actual and Vour ideal expressed in mV in the linear region of the transfer function Offset error is measured on the AD5686R with Code 512 loaded in the DAC register It can be negative or positive DC Power Supply Rejection Ratio PSRR This indicates how the output of the DAC is affected by changes in the supply voltage PSRR is the ratio of the change in Vovr to a change in Vpp for full scale output of the DAC It is measured in mV V Vrer is held at 2 V and Vpn is varied by 10 Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1 4 to full scale input change and is measured from the rising edge of SYNC Digital to Analog Glitch Impulse Digital to analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state It is normally specified as the area of the glitch in nV sec and is measured when the digital input code is changed by 1 LSB at the major carry transition 0x7FFF to 0x8000 see Figure 41 Digital Feedthrough Digital feedthrough is a measure of the impulse injected into t
24. ative Accuracy 2 8 1 2 LSB Gain 2 2 8 1 3 Gain 1 Differential Nonlinearity 1 1 LSB Guaranteed monotonic by design AD5685R Resolution 14 14 Bits Relative Accuracy 0 5 4 0 5 1 LSB Differential Nonlinearity 1 1 LSB Guaranteed monotonic by design AD5684R Resolution 12 12 Bits Relative Accuracy 0 12 2 0 12 1 LSB Differential Nonlinearity 1 1 LSB Guaranteed monotonic by design Zero Code Error 0 4 4 0 4 15 mV All zeros loaded to DAC register Offset Error 0 1 4 0 1 1 5 mV Full Scale Error 0 01 0 2 40 001 0 1 96 of All ones loaded to DAC register FSR Gain Error 0 02 0 2 0 02 0 1 of FSR Total Unadjusted Error 0 01 0 25 0 01 0 1 of External reference gain 2 TSSOP FSR 0 25 0 2 of Internal reference gain 1 TSSOP FSR Offset Error Drift 1 1 uV C Gain Temperature 1 ppm Of FSR C Coefficient DC Power Supply Rejection 0 15 0 15 mvV V DAC code midscale Voo 5 V 1096 Ratio DC Crosstalk 2 2 uV Due to single channel full scale output change 3 1 3 puV mA Due to load current change 2 2 uV Due to powering down per channel OUTPUT CHARACTERISTICS Output Voltage Range 0 VREF 0 VREF V Gain 1 0 2 x VREF 0 2 X VREE V Gain 2 see Figure 34 Capacitive Load Stability 2 2 nF Ri 10 10 nF RL 1kQ Resistive Load 1 1 kQ Load Regulation 80 80 uV mA 5 V 1096 DAC code midscale 30 mA x lout x 30 mA 80 80 uV mA 3 V 1096 DAC code midscale 20 mA x lout lt 20 mA Short
25. compatible with C3 ER EET EN peseipien 0 0 0 0 No operation SPI QSPI and MICROWIRE interface standards as well as 4 o o 1 Write to Input Register n dependent on IDAG most DSPs See Figure 2 for a timing diagram of a typical os Wy U Update DAC Register n with contents of input write sequence The AD5686R AD5685R AD5684R contain Register n an SDO pin to allow the user to daisy chain multiple devices o 0 1 1 Write to and update DAC Channel n together see the Daisy Chain Operation section or for 0 1 0 0 Power down power up DAC readback 0 1 0 1 Hardware LDAC mask register 0 1 1 0 Software reset power on reset Input Shift Register 0 1 1 1 Internal os setup ll The input shift register ofthe AD5686R AD5685R AD5684R is 1 0 0 0 Set up DCEN register daisy chain enable 24 bits wide Data is loaded MSB first DB23 and the first four 1 0 0 1 Set up readback register readback enable bits are the command bits C3 to CO see Table 7 followed by 1 0 1 0 Reserved the 4 bit DAC address bits DAC A DAC B DAC C DAC D vee vse oe ae Reserved see Table 8 and finally the bit data word 1 1 1 1 Reserved The data word comprises 16 bit 14 bit or 12 bit input code Table 8 Address Commands followed by zero two or four dont care bits for the AD5686R Address n AD5685R and AD5684R respectively see Figure 51 Figure 52 DACD DACC DACB DACA Selected DAC Channel and Figure 53 These data bits are transferred to the input 0
26. d microcontrollers The communications channel requires a 3 or 4 wire interface consisting of a clock signal a data signal and a synchronization signal The devices require a 24 bit data word with data valid on the rising edge of SYNC AD5686R AD5685R AD5684R TO ADSP BF531 INTERFACE The SPI interface of the AD5686R AD5685R AD5684R is designed to be easily connected to industry standard DSPs and microcontrollers Figure 60 shows the AD5686R AD5685R AD5684R connected to the Analog Devices Blackfin DSP The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5686R AD5685R AD5684R AD5686R m AD5684R ADSP BF531 10485 164 Figure 60 ADSP BF531 Interface AD5686R AD5685R AD5684R TO SPORT INTERFACE The Analog Devices ADSP BF527 has one SPORT serial port Figure 61 shows how one SPORT interface can be used to control the AD5686R AD5685R AD5684R MEA ADSP BF527 AD5686R AD5685R AD5684R SPORT_TFS SPORT_TSCK SPORT_DTO 10485 165 Figure 61 SPORT Interface LAYOUT GUIDELINES In any circuit where accuracy is important careful consider ation of the power supply and ground return layout helps to ensure the rated performance The PCB on which the AD5686R AD5685R AD5684R are mounted should be designed so that the AD5686R AD5685R AD5684R lie on the analog plane The AD5686R AD5685R AD5684R should have ample supply bypassing of 10 uF in parallel
27. efault To reduce the supply current this reference can be turned off by setting software programmable bit DBO in the control register Table 14 shows how the state of the bit corresponds to the mode of operation Command 0111 is reserved for setting up the internal reference see Figure 9 Table 14 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup Table 14 Reference Setup Register Internal Reference Setup Register DBO Action 0 Reference on default 1 Reference off SOLDER HEAT REFLOW As with all IC reference voltage circuits the reference value experiences a shift induced by the soldering process Analog Devices Inc performs a reliability test called precondition to mimic the effect of soldering a device to a board The output voltage specification quoted previously includes the effect of this reliability test Figure 57 shows the effect of solder heat reflow SHR as measured through the reliability test precondition POSTSOLDER HEAT REFLOW PRESOLDER HEAT REFLOW HITS 2 498 2 499 2 500 2 501 2 502 Vrer V Figure 57 SHR Reference Voltage Shift LONG TERM TEMPERATURE DRIFT Figure 58 shows the change in Vs value after 1000 hours in life test at 150 C 10485 060 0 HOUR 500 HOURS 1000 HOURS HITS 2 498 2 499 2 500 2
28. fects of preconditioning drift See the Internal Reference Setup section 8 Reference is trimmed and tested at two temperatures and is characterized from 40 C to 105 C Reference temperature coefficient calculated as per the box method See the Terminology section for further information 1 Interface inactive All DACs active DAC outputs unloaded All DACs powered down Rev 0 Page 4 of 32 AD5686R AD5685R AD5684R AC CHARACTERISTICS Vpp 2 7 V to 5 5 V Ri 2 KQ to GND C 200 pF to GND 1 8 V lt Vioaic 5 5 V all specifications Tus to Tmax unless otherwise noted Table 3 Parameter Min Typ Max Unit Test Conditions Comments Output Voltage Settling Time AD5686R 5 8 Hs 4 to scale settling to 2 LSB AD5685R 5 8 Hs Y to 34 scale settling to 2 LSB AD5684R 5 7 Hs to scale settling to 2 LSB Slew Rate 0 8 V us Digital to Analog Glitch Impulse 0 5 nV sec 1 LSB change around major carry Digital Feedthrough 0 13 nV sec Digital Crosstalk 0 1 nV sec Analog Crosstalk 0 2 nV sec DAC to DAC Crosstalk 0 3 nV sec Total Harmonic Distortion 80 dB At ambient BW 20 kHz Voo 5 V four 1 kHz Output Noise Spectral Density 300 nV 4Hz DAC code midscale 10 kHz gain 2 Output Noise 6 uV p p 0 1 Hz to 10 Hz SNR 90 dB At ambient BW 20 kHz Voo 5 V four 1 kHz SFDR 83 dB At ambient BW 20 kHz Voo 5 V four 1 kHz SINAD 80 dB At ambient BW 20 kHz Vo 5 V four 1 kHz 1 Guaran
29. ference enabled by default and a gain select pin giving a full scale output of 2 5 V gain 1 or 5 V gain 2 All devices operate from a single 2 7 V to 5 5 V PRODUCT HIGHLIGHTS supply are guaranteed monotonic by design and exhibit less than 0 1 FSR gain error and 1 5 mV offset error performance The devices are available in a 3 mm x 3 mm LFCSP anda TSSOP package 1 High Relative Accuracy INL AD5686R 16 bit 2 LSB maximum AD5685R 14 bit 1 LSB maximum AD5684R 12 bit 1 LSB maximum The AD5686R AD5685R AD5684R also incorporate a power 2 Low Drift 2 5 V On Chip Reference on reset circuit and a RSTSEL pin that ensures that the DAC 2 ppm C typical temperature coefficient outputs power up to zero scale or midscale and remains there 5 ppm C maximum temperature coefficient until a valid write takes place Each part contains a per channel 3 Two Package Options power down feature that reduces the current consumption of 3 mm x 3 mm 16 lead LECSP the device to 4 uA at 3 V while in power down mode 16 lead TSSOP The AD5686R AD5685R AD5684R employ a versatile SPI interface that operates at clock rates up to 50 MHz and all devices contain a Viocic pin intended for 1 8 V 3 V 5 V logic Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may
30. he analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated It is specified in nV sec and measured with a full scale code change on the data bus that is from all 0s to all 1s and vice versa Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated It is expressed in dB Noise Spectral Density This is a measurement of the internally generated random noise Random noise is characterized as a spectral density nV VHz It is measured by loading the DAC to midscale and measuring noise at the output It is measured in nV VHz A plot of noise spectral density is shown in Figure 45 DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC It is measured with a full scale output change on one DAC or soft power down and power up while monitoring another DAC kept at midscale It is expressed in uV DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale It is expressed in uV mA Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full scale code change all 0s to all 1s and vice versa in the input register of another DAC It is measured in standalone mode a
31. he device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Human body model HBM classification ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge y without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 9 of 32 AD5686R AD5685R AD5684R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5686R AD5685R AD5684R Table 6 Pin Function Descriptions NOTES 1 THE EXPOSED PAD MUST BE TIED TO GND Figure 6 16 Lead LFCSP Pin Configuration I 14 RSTSEL Lu o Lu tc e TOP VIEW Not to Scale nny vy 12 SDIN 11 SYNC 10 SCLK AD5686R AD5685R AD5684R TOP VIEW Not to Scale 9 Viocic 10485 006 10485 007 Figure 7 16 Lead TSSOP Pin Configuration Pin No LFCSP TSSOP 1 3 2 4 3 5 4 6 5 7 6 8 7 9 8 10 9 11 10 12 11 13 12 14 13 15 14 16 15 1 16 2 17 N A Mnemonic VourA GND LDAC GAIN Vioaic SCLK SYNC SDIN RESET RSTSEL VREF VourB EPAD Description Analog Output Voltage fr
32. ices is complete SYNC is taken high This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register The serial clock can be continuous or a gated clock A continuous SCLK source can be used only if SYNC can be held low for the correct number of clock cycles In gated clock mode a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data READBACK OPERATION Readback mode is invoked through a software executable readback command If the SDO output is disabled via the daisy chain mode disable bit in the control register it is automatically enabled for the duration of the read operation after which it is disabled again Command 1001 is reserved for the readback function This command in association with selecting one of address bits DAC A to DAC D selects the register to read Note that only one DAC register can be selected during readback The remaining three address bits must be set to Logic 0 The remaining data bits in the write sequence are don t care bits If more than one or no bits are selected DAC Channel A is read back by default During the next SPI write the data appearing on the SDO output contains the data from the previously addressed register For example to read back the DAC register for Channel A the following sequence should be implemented 1 Write 0x900000
33. in on the falling edges of the next 24 clocks Serial Data Input This device has a 24 bit input shift register Data is clocked into the register on the falling edge of the serial clock input Asynchronous Reset Input The RESET input is falling edge sensitive When RESET is low all LDAC pulses are ignored When RESET is activated the input register and the DAC register are updated with zero scale or midscale depending on the state of the RSTSEL pin Power On Reset Pin Tying this pin to GND powers up all four DACs to zero scale Tying this pin to Voo powers up all four DACs to midscale Reference Voltage The AD5686R AD5685R AD5684R have a common reference pin When using the internal reference this is the reference output pin When using an external reference this is the reference input pin The default for this pin is as a reference output Analog Output Voltage from DAC B The output amplifier has rail to rail operation Exposed Pad The exposed pad must be tied to GND Rev 0 Page 10 of 32 AD5686R AD5685R AD5684R TYPICAL PERFORMANCE CHARACTERISTICS 2 5020 DEVICE 1 0 HOUR DEVICE 2 60 168 HOURS 2 5015 L
34. ister with the contents of the input register on channels that are not masked blocked by the LDAC mask register When LDAC is permanently tied low the LDAC mask bits are ignored Rev 0 Page 25 of 32 AD5686R AD5685R AD5684R HARDWARE RESET RESET RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale The clear code value is user selectable via the RESET select pin It is necessary to keep RESET low for a minimum amount of time to complete the operation see Figure 2 When the RESET signal is returned high the output remains at the cleared value until a new value is programmed The outputs cannot be updated with a new value while the RESET pin is low There is also a software executable reset function that resets the DAC to the power on reset code Command 0110 is designated for this software reset function see Table 7 Any events on LDAC or RESET during power on reset are ignored RESET SELECT PIN RSTSEL The AD5686R AD5685R AD5684R contain a power on reset circuit that controls the output voltage during power up By connecting the RSTSEL pin low the output powers up to zero scale Note that this is outside the linear region of the DAC by connecting the RSTSEL pin high Vour powers up to midscale The output remains powered up at this level until a valid write sequence is made to the DAC INTERNAL REFERENCE SETUP The on chip reference is on at power up by d
35. maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function A typical INL vs code plot is shown in Figure 16 Differential Nonlinearity DNL Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity This DAC is guaranteed monotonic by design A typical DNL vs code plot can be seen in Figure 19 Zero Code Error Zero code error is a measurement of the output error when zero code 0x0000 is loaded to the DAC register Ideally the output should be 0 V The zero code error is always positive in the AD5686R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier Zero code error is expressed in mV A plot of zero code error vs temperature can be seen in Figure 26 Full Scale Error Full scale error is a measurement of the output error when full scale code OxFFFF is loaded to the DAC register Ideally the output should be Vp 1 LSB Full scale error is expressed in percent of full scale range of FSR A plot of full scale error vs temperature can be seen in Figure 25 Gain Error This is a measure of the span error of the DAC It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as of FSR Offset Error Drift This is a me
36. n of 4 mA at 5 V However for the three power down modes the supply current falls to 4 uA at 5 V Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values This has the advantage that the output impedance of the part is known while the part is in power down mode There are three different power down options The output is connected internally to GND through either a 1 kQ or a 100 KQ resistor or it is left open circuited three state The output stage is illustrated in Figure 55 VourX POWER DOWN RESISTOR CIRCUITRY NETWORK Figure 55 Output Stage During Power Down 10485 058 The bias generator output amplifier resistor string and other associated linear circuitry are shut down when the power down mode is activated However the contents of the DAC register are unaffected when in power down The DAC register can be updated while the device is in power down mode The time required to exit power down is typically 4 5 us for Vpp 5 V To reduce the current consumption further the on chip reference can be powered off See the Internal Reference Setup section Table 11 24 Bit Input Shift Register Contents of Power Down Power Up Operation DB15 to DBO DB23 DB22 DB21 DB20 DB19 to DB16 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB 0 1 0 0 X X PDD1 PDDO PDC1 PDCO PDB1 PDBO PDA1 PDAO Command bits C
37. nd is expressed in nV sec Rev 0 Page 18 of 32 AD5686R AD5685R AD5684R Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC It is measured by loading one of the input registers with a full scale code change all Os to all 1s and vice versa Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed The area of the glitch is expressed in nV sec DAC to DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC It is measured by loading the attack channel with a full scale code change all 0s to all 1s and vice versa using the write to and update commands while monitor ing the output of the victim channel that is at midscale The energy of the glitch is expressed in nV sec Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth The multiplying bandwidth is a measure of this A sine wave on the reference with full scale code loaded to the DAC appears on the output The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input Total Harmonic Distortion THD This is the difference between an ideal sine wave and its attenuated version using the DAC The sine wave is used as the reference for the DAC and the THD is a measurement of the harmonics present
38. om DAC A The output amplifier has rail to rail operation Ground Reference Point for All Circuitry on the Part Power Supply Input These parts can be operated from 2 7 V to 5 5 V and the supply should be decoupled with a 10 pF capacitor in parallel with a 0 1 uF capacitor to GND Analog Output Voltage from DAC C The output amplifier has rail to rail operation Analog Output Voltage from DAC D The output amplifier has rail to rail operation Serial Data Output Can be used to daisy chain a number of AD5686R AD5685R AD5684R devices together or can be used for readback The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock LDAC can be operated in two modes asynchronously and synchronously Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data This allows all DAC outputs to simultaneously update This pin can also be tied permanently low Span Set Pin When this pin is tied to GND all four DAC outputs have a span from OV to Veer If this pin is tied to Von all four DACs output a span of OV to 2 x Var Digital Power Supply Voltage ranges from 1 8 V to 5 5 V Serial Clock Input Data is clocked into the input shift register on the falling edge of the serial clock input Data can be transferred at rates of up to 50 MHz Active Low Control Input This is the frame synchronization signal for the input data When SYNC goes low data is transferred
39. on the DAC output It is measured in dB Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature The reference TC is calculated using the box method which defines the TC as the maximum change in the reference output over a given tempera ture range expressed in ppm C as follows V TC VREFmax REFmin x 10 Varrnom X TempRange where Vrermax is the maximum reference output measured over the total temperature range Vrermin is the minimum reference output measured over the total temperature range VreFnom is the nominal reference output voltage 2 5 V TempRange is the specified temperature range of 40 C to 105 C Rev 0 Page 19 of 32 AD5686R AD5685R AD5684R THEORY OF OPERATION DIGITAL TO ANALOG CONVERTER The AD5686R AD5685R AD5684R are quad 16 14 12 bit serial input voltage output DACs with an internal reference The parts operate from supply voltages of 2 7 V to 5 5 V Data is written to the AD5686R AD5685R AD5684R in a 24 bit word format via a 3 wire serial interface The AD5686R AD5685R AD5684R incorporate a power on reset circuit to ensure that the DAC output powers up to a known output state The devices also have a software power down mode that reduces the typical current consumption to typically 4 uA TRANSFER FUNCTION The internal reference is on by default To use an external reference only a nonreference option is
40. rmal Mode 0 59 0 7 0 59 0 7 mA Internal reference off 1 1 1 3 1 1 1 3 mA Internal reference on at full scale All Power Down 1 4 1 4 uA 40 C to 85 C Modes 6 6 yA 40 C to 105 C Temperature range A and B grade 40 C to 105 C DC specifications tested with the outputs unloaded unless otherwise noted Upper dead band 10 mV and exists only when Vre Voo with gain 1 or when Vper 2 Voo with gain 2 Linearity calculated using a reduced code range of 256 to 65 280 AD5686R 64 to 16 320 AD5685R and 12 to 4080 AD5684R 3 Guaranteed by design and characterization not production tested Channel A and Channel B can have a combined output current of up to 30 mA Similarly Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110 C gt Voo 5 V The device includes current limiting that is intended to protect the device during temporary overload conditions Junction temperature can be exceeded during current limit Operation above the specified maximum operation junction temperature may impair device reliability When drawing a load current at either rail the output voltage headroom with respect to that rail is limited by the 25 O typical channel resistance of the output devices For example when sinking 1 mA the minimum output voltage 25 Q x 1 mA 25 mV see Figure 34 7 Initial accuracy presolder reflow is 750 uV output voltage includes the ef
41. teed by design and characterization not production tested See the Terminology section 3 Temperature range is 40 C to 105 C typical 25 C 4 Digitally generated sine wave 1 kHz Rev 0 Page 5 of 32 AD5686R AD5685R AD5684R TIMING CHARACTERISTICS All input signals are specified with tr tr 1 ns V 10 to 90 of Vp and timed from a voltage level of Vi Viu 2 See Figure 2 Vo 2 7 V to 5 5 V 1 8 V Vioaic 5 5 V Vrern 2 5 V All specifications Twin to Tmax unless otherwise noted Table 4 1 8 V sVioac lt 2 7 V 2 7 V lt Vioac lt 5 5 V Parameter Symbol Min Max Min Max Unit SCLK Cycle Time ti 33 20 ns SCLK High Time t 16 10 ns SCLK Low Time ts 16 10 ns SYNC to SCLK Falling Edge Setup Time ta 15 10 ns Data Setup Time ts 5 5 ns Data Hold Time te 5 5 ns SCLK Falling Edge to SYNC Rising Edge t 15 10 ns Minimum SYNC High Time Single Combined or All Channel Update ts 20 20 ns SYNC Falling Edge to SCLK Fall Ignore to 16 10 ns LDAC Pulse Width Low tio 25 15 ns SCLK Falling Edge to LDAC Rising Edge ti 30 20 ns SCLK Falling Edge to LDAC Falling Edge ti 20 20 ns RESET Minimum Pulse Width Low tis 30 30 ns RESET Pulse Activation Time ti 30 30 ns Power Up Time 45 4 5 us 1 Maximum SCLK frequency is 50 MHz at Vop 2 7 V to 5 5 V 1 8 V Vioac lt Voo Guaranteed by design and characterization not production tested 2 Time to exit power down to normal mode of AD5686R AD568
42. to the AD5686R AD5685R AD5684R input register This configures the part for read mode with the DAC register of Channel A selected Note that all data bits DB15 to DBO are dont care bits 2 Follow this with a second write a NOP condition 0x000000 During this write the data from the register is clocked out on the SDO line DB23 to DB20 contain undefined data and the last 16 bits contain the DB19 to DB4 DAC register contents Rev 0 Page 23 of 32 AD5686R AD5685R AD5684R POWER DOWN OPERATION The AD5686R AD5685R AD5684R contain three separate power down modes Command 0100 is designated for the power down function see Table 7 These power down modes are software programmable by setting eight bits Bit DB7 to Bit DBO in the input shift register There are two bits associated with each DAC channel Table 10 shows how the state of the two bits corresponds to the mode of operation of the device Table 10 Modes of Operation Operating Mode PDx1 PDxO Normal Operation 0 0 Power Down Modes 1 kQ to GND 0 1 100 kO to GND 1 0 Three State 1 1 Any or all DACs DAC A to DAC D can be powered down to the selected mode by setting the corresponding bits See Table 11 for the contents of the input shift register during the power down power up operation When both Bit PDx1 and Bit PDx0 where x is the channel selected in the input shift register are set to 0 the parts work normally with its normal power consumptio
43. troller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common mode voltages that SDIN may occur iCoupler products from Analog Devices provide voltage isolation in excess of 2 5 kV The serial loading struc ture of the AD5686R AD5685R AD5684R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum Figure 63 shows a 4 channel o LDAC isolated interface to the AD5686R AD5685R AD5684R 5 using an ADuM1400 For further information visit 1 ADDITIONAL PINS OMITTED FOR CLARITY i http www analog com icouplers Figure 63 Isolated Interface Rev 0 Page 29 of 32 AD5686R AD5685R AD5684R OUTLINE DIMENSIONS PIN 1 PiN INDICATOR INDICATOR 1 75 1 60 SQ 1 45 0 50 0 25 MIN TOP VIEW Q040 BOTTOM VIEW 0 30 0 80 FOR PROPER CONNECTION OF 0 75 THE EXPOSED PAD REFER TO m La uns 0 05 MAX THE EIL CONFIGURATION AND 0 02 Nom FUNCTION DESCRIPTION E 1 COPLANARITY SECTION OF THIS DATA SHEET SEATING 0 08 PLANE 0 20 REF 08 16 2010 E COMPLIANT TO JEDEC STANDARDS MO 220 WEED 6 Figure 64 16 Lead Lead Frame Chip Scale Package LFCSP_WQ 3mm x 3 mm Body Very Very Thin Quad CP 16 22 Dimensions shown in millimeters 3 VC 0 75 4 J D 0 30 4 8 gt e 0 60 0 65 M4019 SEATING 9 0 45 BSC PLANE COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure
44. with 0 1 uF on each supply located as close to the package as possible ideally right up against the device The 10 uF capacitors are the tantalum bead type The 0 1 uF capacitor should have low effective series resistance ESR and low effective series inductance ESI such as the common ceramic types which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching In systems where there are many devices on one board it is often useful to provide some heat sinking capability to allow the power to dissipate easily The AD5686R AD5685R AD5684R have an exposed paddle beneath the device Connect this paddle to the GND supply for the part For optimum performance use special considerations to design the motherboard and to mount the package For enhanced thermal electrical and board level performance solder the exposed paddle on the bottom of the package to the corresponding thermal land paddle on the PCB Design thermal vias into the PCB land paddle area to further improve heat dissipation The GND plane on the device can be increased as shown in Figure 62 to provide a natural heat sinking effect AD5686R AD5685R AD5684R i I 10485 166 Figure 62 Paddle Connection to Board Rev 0 Page 28 of 32 AD5686R AD5685R AD5684R GALVANICALLY ISOLATED INTERFACE In many process control applications it is necessary to provide an isolation barrier between the con
Download Pdf Manuals
Related Search
ANALOG DEVICES AD5684R English products handbook