CYPRESS CY2SSTU32864 Manual
Contents
1. 1234 5 6 652324 gt 6 gt S 2 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC MO 205 PKG WEIGHT 0 23 gms OO SUSAN 6 00 340000000 SOIO OU 13 50 0 10 13 50 010 12 00 G C 2 C C DA ka CC PART BF96A STANDARD PKG BP96A LEAD FREE PKG 11 20 OO 900000 5 e DOO 0 80 7 C lt 5 50 0 10 4 00 51 85202 4 550400 4 RQ osc w A 0 15 4 T PUT IU Y SEATING PLANE m 040 0 05 2 1025 026 0533005 1 20 MAX All product and company names mentioned in this document are trademarks of their respective holders Document 38 07576 Rev D Page 9 of 10 Cypress Semiconductor Corporation 2005 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cyp2. por D X Do 2 3 4 5 6 1 1 Register 0 1 0 1 2 Register 0 C1 1 1 2 Register 1 1 1 Cypress Semiconductor Corporation Document 38 07576 Rev D 3901 North First Street San Jose 95134 408 943 2600 29 2005 V CYPRESS PRELIMINARY CY2SSTU32864 Pin Definitions Pin Number Pin Number Pin Number Pin Name CO 0 C1 0 0 0 1 1 CO 1 C1 1 Description GND B3 B4 D4 F3 F4 B4 D3 DA F3 B3 B4 D3 DA F3 Ground H4 4 F4 4 H4 P3 P4 4 P3 P4 4 P4 VDD CA E4 63 4 CA A4 C3 C4 Power Supply Voltage G4 J3 L3 L4 E4 G3 G4 J3 E4 G3 J3 N4 R3 R4 T4 L3 L4 N4 R3 L3 L4 4 R3 R4 T4 R4 T4 VREF A3 T3 A3 T3 A3 T3 Input Reference Voltage ZOH J5 J5 J5 Reserved ZOL J6 J6 J6 Reserved CK H1 H1 H1 Positive Master Clock J1 J1 J1 Negative Master Clock CO G6 G6 G6 Configuration Control Input C1 G5 G5 G5 Configuration Control Input RESET G2 G2 G2 Asynchronous Reset resets registers and disables Vref data and clock differential input receivers CSR J2 J2 J2 Chip Sele
3. outputs that will not be suspended by DCS and CSR control QCKEB A6 T6 Data outputs that will not be suspended by the DCS and CSR control NC 2 A6 D2 D6 G1 H6 2 B2 C2 D2 A2 B2 C2 D2 No Connect Pins E2 F2 G1 K2 L2 M2 N2 P2 R2 T2 E2 F2 G1 K2 L2 M2 N2 P2 R2 T2 Document 38 07576 Rev D Page 3 of 10 Ji CYPRESS PRELIMINARY CY2SSTU32864 Table 1 Flip Flop Function Table Inputs Outputs RESET DCS CSR CK CK DODT DCKE Qn QCS QODT QCKE H L L 1 L L L L H L L 1 H H L H H L L L or H L or H X QO QO QO H L H 1 L L L L H L H 1 H H L H H L H L or H L or H X QO QO QO H H L 1 L L H L H H L 1 H H H H H H L L or H L or H X QO QO QO H H H 1 L QO H L H H H i 1 H Q0 H H H H H L or H L or H X QO QO QO L X or Floating X or Floating X or Floating X or Floating X or Floating L L L Document 38 07576 Rev D Page 4 of 10 Tj CYPRESS PRELIMINARY CY2SSTU32864 Absolute Maximum Conditions Parameter Description Condition Min Max Unit ViN Input Voltage Rangel 3l 0 5 0 5 V VouT Output Voltage 31 0 5 Vpp 0 5 V Ts Storage Temperature 65 150 Supply Voltage Range 0 5 2 5 V lik Input
4. 3278919 010 62632888 62636888
5. Clamp Current Vo lt 0 gt Vpp 50 50 mA lok Output Clamp Current Vo lt 0 or gt Vpp 50 50 lo Continuous Output Current Vo 0 to Vpp 50 50 Continuous Current through VDD GND 100 100 mA DC Electrical Specifications Parameter Description Conditions Min Max Unit TA Ambient Operating Temp 0 70 C Operating Voltage 1 7 1 9 V VicR Input Differential Common 0 675 1 125 V Mode Voltage Range Vip Input Differential Voltage 600 VREF Voltage Reference 0 49 Vpp 0 51 Vpp V Terminating Voltage Vngr 40 mV Veer 40 mV V VI Input Voltage 0 V Input Current Vi Vpp or GND 5 5 AC Input Low Voltage Data Inputs zx Vngr 250 mV V DC Input Low Voltage Data Inputs Vngr 125mV V Input High Voltage Data Inputs Veer 250 mV V DC Input High Voltage Data Inputs 125 mV V VoL Output Low Voltage lo 100 uA Vec 1 7V to 1 9V 0 2 V lo 6 mA Vcc 1 7V 0 5 V Vou Output High Voltage 7100 Voc 1 7V to 1 9V Vpp 0 2 V lon 6 MA 1 7V 1 2 V lou Output High Current 8 mA Output Low Current 8 mA Ipp Static Standby Power RESET IO 0 Vpp 1 9V 100 Supply Current Static Operating Power RESET Vpp Vinc Vit aC 40 mA Supply Current IO 0 1 9V Notes 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device T
6. Vpp V OF Vii ac 2 typical 2 per each Data Input switching 50 duty cycle Vpp 1 8V 1 IO switching 1 1 configuration CS Enabled RESET Vi VIH AC or AC 2 2 switching 50 duty cycle Vpp 1 8V 110 switching 1 2 configuration CS Enabled CiN Ci Data Vi 250 mV 2 5 3 5 pF Ci CK and CK Vix 0 9V Vip 600 mV 2 3 pF Ci RESET Vi Vpp or GND 2 5 pF AC Timing Specifications Parameter Description Conditions Min Max Unit 500 MHz Tw Pulse Duration CK CK H or L 1 Differential Input Active Time 10 ns Differential Input Inactive Time 15 5 Tsy Set up Time DCS before crossing CK CK 0 7 ns CSR CK going high DCS before crossing CK CK 0 5 ns CSR L CK going high CSR ODT CKE and data 0 5 before crossing CK CK CK going high DCS CSRT ODT and 0 5 ns data after crossing CK going high Propagation Delay without Switching From CK CK to 1 86 ns TPpMs Propagation Delay with Switching From CK to Q 1 87 ns simultaneous switching T PHL Propagation Delay from High to Low RESET Start to Q Low 3 ns Rate Rising dv dt 20 to 80 1 4 Vins Slew Rate Falling dv dt_f 20 to 80 1 4 Vins dv dt A Delta between Rising Falling Rates 1 Vins Notes 4 Data and Veer inp
7. ct Disables D1 D24 when both CSR and DCS are High VDD DCS H2 H2 H2 Chip Select Disables D1 D24 when both CSR and DCS are High VDD D1 1 Data Input clocked in on the crossing points of CK and D2 3 B1 C1 B1 C1 B1 C1 Data Input clocked in on the crossing points of CK and 04 D1 Data Input clocked in on the crossing points of CK and D5 6 8 9 ET F1 L1 M1 F1 K1 L1 M1 E1 L1 M1 Data Input clocked in on the crossing points of 10 CK and D11 N1 N1 Data Input clocked in on the crossing points of CK and D12 13 P1 R1 P1 R1 P1 R1 Data Input clocked in on the crossing points of CK and D14 T1 T1 Data Input clocked in on the crossing points of CK and D15 25 B2 C2 E2 K2 L2 Data Input clocked in on the crossing points of M2 N2 P2 R2 T2 CK and DODT D1 D1 N1 The outputs of this register bit will not be suspended by the DCS and CSR Control DCKE A1 A1 T1 The outputs of this register bit will not be suspended by the DCS and CSR Control Q1A A5 Data Outputs that are suspended by the DCS and CSR control 2 5 5 5 5 5 5 Data Outputs that are suspended by the DCS and CSR control 4 05 Data Outputs that are suspended by the DCS and CSR control Q5A 6A 8A E5 F5 K5 L5 M5 E5 F5 K5 L5 M5 E5 F5 K5 L5 5 Data Outputs that are suspended by the DCS 9A 10A CSR contro
8. hese are stresses ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 3 This value is limited to 2 5V max Document 38 07576 Rev D Page 5 of 10 4 y CYPRESS PRELIMINARY CY2SSTU32864 DC Electrical Specifications continued Parameter Description Conditions Min Max Unit Ippp Power Supply Current RESET Vpp Vi OF Vii ac 28 pA MHz Dynamic Operating Clock CK switching 50 duty cycle Only Vpp 1 8V Dynamic Operating per RESET Vpp Vi Vit ac 18 typical 2 each Data Input switching 50 duty cycle Vpp 1 8V 1 IO switching 1 1 configuration RESET VDD VI or VIL AC CK 36 typical 2 switching 50 duty cycle Vpp 1 8V 1 IO switching 1 2 configuration Low Power Active Mode RESET Vpp Vi Vinac OF Vii ac 27 typical uA MHz CLK only switching 5096 duty cycle Vpp 7 1 8V CS Enabled Low Power Active Mode RESET
9. hich case the set up time requirement for DCS would be the same as for the other D data inputs The device supports low power standby operation When the reset input RESET is low the differential input receivers disabled and undriven floating data clock and reference voltage VREF inputs are allowed In addition when RESET is low all registers are reset and all outputs are forced low The LVCMOS RESET and Cn inputs must always be held at a valid logic high or low level To ensure defined outputs from the register before a stable clock has been supplied RESET must be held in the low state during power up In the DDR II RDIMM application RESET is specified to be completely asynchronous with respect to CK Therefore no timing relationship can be guaranteed between the two When entering reset the register will be cleared and the outputs will be driven low quickly relative to the time to disable the differential input receivers However when coming out of reset the register will become active quickly relative to the time to enable the differential input receivers Pin Configurations 1 2 3 4 57 6 poe 15 Jas pe po 7 7 pis joo 8 pio 09 ipi ob oo 2 on 2 o 02 13 Do
10. l Q11A N5 N5 Document 38 07576 Rev D Page 2 of 10 ji Ji CYPRESS PRELIMINARY CY2SSTU32864 Pin De Definitions continued Pin Number Pin Number Pin Number Pin Name CO 20 C1 0 CO 0 C1 1 CO 1 1 Description Q12A 1 5 R5 P5 R5 P5 R5 Q14A T5 5 Data Outputs that are suspended by the DCS and CSR control Q1B A6 Data Outputs that are suspended by the DCS and CSR control Q2B 3B B6 C6 B6 C6 Data Outputs that are suspended by the DCS CSR control Q4B D6 Data Outputs that are suspended by the DCS and CSR control Q5B 6B 8B E6 F6 6 16 M6 E6 F6 K6 16 M6 Data Outputs that are suspended by the DCS 9B 10B and CSR control Q11B N6 Data Outputs that are suspended by the DCS and CSR control Q12B 13B P6 R6 P6 R6 Data Outputs that are suspended by the DCS and CSR control Q14B T6 Data Outputs that are suspended by the DCS and CSR control Q15 25 B6 C6 E6 F6 K6 L6 Data Outputs that are suspended by the DCS M6 N6 P6 R6 T6 CSR control QCSA H5 H5 H5 Data outputs that will not be suspended by the DCS and CSR control QCSB H6 H6 Data outputs that will not be suspended by the DCS and CSR control QODTA D5 D5 N5 Data outputs that will not be suspended by the DCS and CSR control QODTB D6 N6 Data outputs that will not be suspended by the DCS and CSR control QCKEA 5 5 5 Data
11. ress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges F CYPRESS PRELIMINARY 2551 32864 Document History Page Document Title CY2SSTU32864 1 8V 25 bit 1 1 or 14 bit 1 2 JEDEC Compliant Data Register Document Number 38 07576 Orig of Rev ECN Issue Date Change Description of Change 129199 09 09 03 New data sheet 224102 Added more information to complete the data sheet B 269293 See ECN RGL Removed Industrial Temp Added slew rate test loads 326621 RGL Data sheet re write D 341657 See ECN RGL Minor Change Corrected the lead free coding in the Ordering table Document 38 07576 Rev D Page 10 of 10 WWW ZFA CN 150 WWW 2 CA PAK R 41662 gl 0755 83278916 8
12. uts must be low a minimum time of Tacr max after RESET is taken high 5 Data Vggr and clock inputs must be held at valid levels not floating a minimum time max after RESET is taken low Document 38 07576 Rev D Page 6 of 10 CYPRESS PRELIMINARY CY2SSTU32864 VDD R 10000 T 350ps 500 CK Inputs Test Point Test Point R 10000 R 1002 Test Point Note C includes probe and jig capacitance Figure 1 Test Load for Timing Measurements 1 R 500 OUT Test Point Figure 2 Slew Rate Measurement Load High to Low DUT OUT e e lest Point C 10pF 7 gt 57 57 t 1 1 inact D i act Figure 4 Active and Inactive Times Figure 5 Pulse Duration Document 38 07576 Rev D Page 7 of 10 RESET Output PRELIMINARY Figure 6 Set up and Hold Times CY2SSTU32864 VID Figure 8 Propagation Delay after RESET Ordering Information Part Number Package Type Product Flow CY2SSTU32864BFXC 96 pin FBGA Commercial 0 to 85 C CY2SSTU32864BFXCT 96 FBGA Tape and Reel Commercial 0 to 85 C Document 38 07576 Rev D Page 8 of 10 PRELIMINARY CY2SSTU32864 Package Drawing and Dimensions 00 05 96 5 5 13 5 1 2 96 00 50 0 05 96 TOP VIEW BOTTOM VIEW A1 CORNER 1
13. zi8gCcY2LL843ZI f hv 79 E CY2SSTU32864 CYPRESS PRELIMINARY Features Operating frequency DC to 500 MHz Supports DDRII SDRAM Two operations modes 25 bit 1 1 and 14 bit 1 2 1 8V operation Fully JEDEC compliant JESD82 7A 96 ball FBGA Functional Description All clock and data inputs are compatible with the JEDEC standard for SSTL 18 The control inputs are LVCMOS All outputs are 1 8V CMOS drivers that have been optimized to drive the DDR II DIMM load The CY2SSTU32864 operates from a differential clock CK and CK Data are registered at the crossing of CK going high and going low The input controls the pinout configuration of the 1 2 pinout from A configuration when low to B configuration when high The C1 input controls the pinout configuration from 25 bit 1 1 when low to 14 bit 1 2 when high CO lt 1 and C1 015 not allowed and it will default to the CO C1 0 state 1 8V 25 bit 1 1 or 14 bit 1 2 JEDEC Compliant Data Register The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high If either DCS or input is low the Qn outputs will function normally The RESET input has priority over the DCS and control and will force the outputs low If the DCS control functionality is not desired the CSR input can be hardwired to ground in w
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CYPRESS CY2SSTU32864 Manual