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ANALOG DEVICES ADV7188 English products handbook Rev A

Contents

1. Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes CSFM 2 0 C shaping filter mode These 0 0 0 Automatic selection of 15 MHz Automatically selects optimum bits allow selection from a range of low olol1 Automatic selection of 2 17 MHz C shaping filter for the specified pass chrominance filters SH1to SH5 and bandwidth based on video quality wideband mode 0 1 0 SH1 0 1 1 SH2 1 0 0 SH3 1 0 1 SH4 1 1 0 SH5 1 1 1 Wideband mode 0x18 Shaping Filter WYSFM 4 0 Wideband Y shaping filter 0 0 0 0 0 Reserved do not use Control 2 mode These bits allow the user to select 0101 01 01 1 Reserved do not use which Y shaping filter is used for the Y component of Y C YPbPr B W input signals 0 1 0 SVHS1 it is also used when a good quality input 0 0 0 1 1 SVHS2 CVBS signal is detected For all other inputs ololilolo svHs3 the Y shaping filter chosen is controlled by YSFM 4 0 0 0 1 0 1 SvHS4 0 0 1 1 0 SVHS5 0 0 1 1 1 SVHS6 0 1 0 0 0 SVHS7 0 1 0 0 1 SvHS8 0 1 0 1 0 SVHS9 0 1 0 1 1 SVHS 10 0 1 1 0 0 SVHS 11 0 1 1 0 1 SVHS 12 0 1 1 1 0 SVHS 13 0 1 1 1 1 SVHS 14 1 0 0 0 0 SVHS 15 1 0 0 0 1 SVHS 16 1 0 0 1 0 SVHS 17 1 0 0 1 1 SVHS 18 CCIR 601 110 1 10 0 Reserved do not use Reserved do not use 111111
2. Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP Word 7 4 0 0 User data words 7 EP EP 0 0 CCAP Word 3 0 0 0 User data words 8 EP EP 0 0 CCAP Word 7 4 0 0 User data words 9 EP EP 0 0 CCAP Word 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum 1 The bold values represent Gemstar or CC specific values Table 93 PAL CC Data Full Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5S CS 4 CST3 CS 2 CS 1 CS 0 Checksum The bold values represent Gemstar or CC specific values NTSC CC Data Half byte output mode is sele
3. Address Register Bit Description 7 6 5 4 Comments Notes ADC3 SW 3 0 0 0 0 0 No connection 0 0 0 1 No connection 0 0 1 0 No connection 0 0 1 1 No connection 0 1 0 0 AIN4 0 1 0 1 No connection 0 1 1 0 No connection 0 1 1 1 No connection 1 0 0 0 No connection 1 0 0 1 AIN7 1 0 1 0 No connection 1 0 1 1 No connection 1 1 0 0 No connection 1 1 0 1 No connection 1 1 1 0 No connection 1 1 1 1 No connection OxF4 Drive Strength DR_STR_S 1 0 These bits select the drive 0 0 Reserved strength for the sync output signals 0 1 Medium low drive strength 2x 1 0 Medium high drive strength 3x 1 1 High drive strength 4x DR STR C 1 0 These bits select the drive 0 0 Reserved strength for the clock output signal 0 1 Medium low drive strength 2x 1 0 Medium high drive strength 3x 1 1 High drive strength 4x DR_STR 1 0 These bits select the drive 0 0 Reserved strength for the data output signals Can be 0 1 Medium low drive strength 2x increased or decreased for EMC or crosstalk ilo Medium high drive strength n reasons 1 1 High drive strength 4x Reserved No delay OxF8 IF Comp Control IFFILTSEL 2 0 IF filter selection for PAL and Bypass mode OdB NISC 2 MHz 5 MHz NTSC filters 0 0 1 3dB 2 dB 0 1 0 6dB 3 5 dB 0 1 1 10dB 5 dB 1 0 O Reserved 3 MHz 6 MHz PAL filters 2 dB 2 dB 5 dB 3 dB 7 dB 5 dB Rese
4. Bit Address Register Bit Description 7 6 5 4 3 2 Comments Notes Ox6F VDP_LINE_019 VBI_DATA_P329_N277 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 329 PAL 277 NTSC 1 for these bits to be effective VBI DATA P16 N14 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 16 PAL 14 NTSC 0x70 VDP LINE 01A VBI DATA P330 N278 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 330 PAL 278 NTSC 1 for these bits to be effective VBI_DATA_P17_N15 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 17 PAL 15 NTSC 0x71 VDP LINE 01B VBI DATA P331 N279 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 331 PAL 279 NTSC 1 for these bits to be effective VBI DATA P18 N16 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 18 PAL 16 NTSC 0x72 VDP LINE 01C VBI DATA P332 N280 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 332 PAL 280 NTSC 1 for these bits to be effective VBI DATA P19 N17 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 19 PAL 17 NTSC 0x73 VDP_LINE_01D VBI_DATA_P333_N281 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 333 PAL 281 NTSC 1 for these bits to be effective VBI_DATA_P20_N18 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 20 PAL 18 NTSC 0x74 VDP_LINE_O1E VBI_DATA_P334_N282
5. The ADV7188 is a Pb free environmentally friendly product It is manufactured using the most up to date materials and processes The coating on the leads of each device is 100 pure Sn electroplate The device is suitable for Pb free applications and is able to withstand surface mount soldering of up to 255 C 5 C In addition it is backward compatible with conventional SnPb soldering processes This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220 C to 235 C 2 Z Pb free part Purchase of licensed C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips PC Patent Rights to use these components in an lC system provided that the system conforms to the I C Standard Specification as defined by Philips 2007 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05478 0 1 07 A ANALOG DEVICES Rev A Page 112 of 112 www analog com
6. 05478 019 FREQUENCY MHz Figure 19 Y NTSC Notch Filter Responses CHROMA FILTER Data from the digital fine clamp block is processed by three sets of filters The data format at this point is CVBS for CVBS inputs chroma only for Y C or Cr Cb interleaved for YPrPb input formats e Chroma Antialias CAA Filter The ADV7188 oversamples the CVBS by a factor of 2 and the chroma or Cr Cb by a factor of 4 CAA a decimating filter is used to preserve the active video band and to remove any out of band components The CAA filter has a fixed response e Chroma Shaping CSH Filters These filters can be programmed to perform a variety of low pass responses They can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression e Digital Resampling Filter This filter is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system without user intervention Figure 20 shows the overall response of all filters from SH1 narrowest to SH5 widest in addition to the wideband mode in red COMBINED C ANTIALIAS C SHAPING FILTER C RESAMPLER 10 20 30 ATTENUATION dB 05478 020 0 1 2 3 4 5 6 FREQUENCY MHz Figure 20 Chroma Shaping Filter Responses CSFM 2 0 C Shaping Filter Mode Address 0x
7. FB MODE 1 0 Description 00 default Static switch mode 01 Fixed alpha blending 10 Dynamic switching fast mux 11 Dynamic switching with edge enhancement Static Mux Selection Control CVBS RGB SEL Address OxED 2 CVBS RGB SEL controls whether the video from the CVBS or RGB source is selected for output from the ADV7188 0 default Data from the CVBS source is selected for output 1 Data from the RGB source is selected for output Alpha Blend Coefficient MAN ALPHA VAL 6 0 Address OxEE 6 0 When fixed alpha blending is selected FB MODE 1 0 01 MAN ALPHA VAL 6 0 determines the proportion in which the video from the CVBS and RGB sources are blended Equation 1 shows how these bits affect the video output 64 MAN ALPHA VAL 6 0 64 MAN ALPHA VAL 6 0 Video Video cyps X 1 1 Video pcp X The maximum valid value for MAN ALPHA VAL 6 0 is 1000000 such that the alpha blender coefficients remain between 0 and 1 The default value for MAN ALPHA VAL 6 0 is 0000000 Rev A Page 17 of 112 ADV7188 FAST BLANK FB PIN FAST BLANK POSITION RESOLVER SIGNAL CVBS CONDITIONING CLAMPING AND DECIMATION EXTRACTION TIMING VIDEO D PROCESSING 9 YPrPb 12C CONTROL OUTPUT FORMATTER RGB gt YPrPb CONVERSION 2 8 S o g 3 Figure 9 Fast Blanking Configuration Fast Blank Edge Shaping FB EDGE SHAPE 2 0 Address Ox
8. Rev A Page 100 of 112 Table 107 provides a detailed description of the registers located in the user sub map Table 107 User Sub Map Detailed Description ADV7188 Address Register Bit Description 1 0 Comments Notes 0x40 Interrupt Configuration 1 INTRO OP SEL 1 0 Interrupt drive 0 0 Opendrain level select 0 1 Drive low when active 1 0 Drive high when active 1 1 Reserved MPU STIM INTRO 1 0 Manual interrupt Manual interrupt mode disabled set mode Manual interrupt mode enabled Reserved Not used MV INTRO SEL 1 0 Macrovision 0 0 Reserved interrupt select 0 1 Pseudosync only 1 0 Color stripe only 1 1 Pseudosync or color stripe INTRO DUR SEL 1 0 Interrupt duration 0 0 3 XTAL periods select 0 1 15 XTAL periods 1 0 63 XTAL periods 1 1 Active until cleared 0x42 Interrupt Status 1 SD LOCK Q No change These bits can be cleared or Read Only SD input has caused the decoder masked in Registers 0x43 and to go from an unlocked state to a 0x44 respectively locked state SD_UNLOCK_Q No change SD input has caused the decoder to go from a locked state to an unlocked state Reserved Reserved Reserved SD_FR_CHNG_Q No change Denotes a change in the free run status MV PS CS Q No change Pseudosync color striping detected See Register 0x40 MV_INTRQ_SEL 1 0 f
9. Rev A Page 92 of 112 ADV7188 Address Register Bit Description Bit Comments Notes 0x69 Configuration 1 SDM SEL 1 0 Y C and CVBS autodetect mode select INSEL selects analog input muxing Composite AIN11 lolo o o o S video Y on AIN10 and C on AIN12 Composite S video autodetect Composite on AIN11 YonAIN11 ConAIN12 Reserved 0x86 STDI Control Reserved Reserved STDI LINE COUNT MODE Disables STDI functionality Enables STDI functionality Reserved Ox8F Free Run Line Length 1 Reserved Set to default LLC_PAD_SEL 2 0 These bits enable manual selection of a clock for the LLC1 pin LLC1 nominally 27 MHz selected output on LLC1 pin LLC2 nominally 13 5 MHz selected output on LLC1 pin For 16 bit 4 2 2 out OF SEL 3 0 0010 Reserved Set to default 0x99 CCAP1 Read Only CCAP1 7 0 Closed caption data bits CCAP1 7 contains parity bit for Byte 0 Only for use with VBI System 2 Ox9A CCAP2 Read Only CCAP2 7 0 Closed caption data bits CCAP2 7 contains parity bit for Byte 0 Only for use with VBI System 2 Ox9B Letterbox 1 Read Only LB LCT 7 0 Letterbox data register Reports the number of black lines detected at the top of active video Ox9C Letterbox 2 Read Only LB_LCM 7 0 Letterbox data register Report
10. lt 0 0 1 1 ADVANCE BY 0 5 LINE 1 0 0 ADVANCE BY 0 5 LINE VSYNC BEGIN Figure 29 NTSC Vsync Begin 05478 029 NVBEGDELO NTSC Vsync Begin Delay on Odd Field Address 0xE5 7 0 default No delay 1 Delays vsync going high on an odd field by a line relative to NVBEG NVBEGDELE NTSC Vsync Begin Delay on Even Field Address 0xE5 6 0 default No delay 1 Delays vsync going high on an even field by a line relative to NVBEG NVBEGSIGN NTSC Vsync Begin Sign Address 0xE5 5 0 Delays the start of vsync Set for user manual programming 1 default Advances the start of vsync Not recommended for user programming NVBEG 4 0 NTSC Vsync Begin Address OxE5 4 0 The default value of NVBEG is 00101 indicating the NTSC vsync begin position For all NTSC PAL vsync timing controls both the V bit in the AV code and the vsync on the VS pin are modified DELAY END OF VSYNC BY NVEND 4 0 ADVANCE END OF VSYNC BY NVEND 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 1 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 05478 030 VSYNC END Figure 30 NTSC Vsync End NVENDDELO NTSC Vsync End Delay on Odd Field Address OxE6 7 0 default No delay 1 Delays vsync from going low on an odd field by a line relative to NVEND NVENDDELE NTSC Vsync End Delay on Even Field Address 0xE6 6 O default No delay 1 Delays v
11. 50 75 a lalolo 2 o 23 o 10096 FB LEVEL 1 0 These bits control reference level for fast blank comparator CNTR ENABLE 0 FB threshold 1 4 V CNTR ENABLE 1 FB threshold 1 6 V CNTR ENABLE 0 FB threshold 1 6 V CNTR ENABLE 1 FB threshold 1 8 V CNTR ENABLE 0 FB threshold 1 8 V CNTR ENABLE 1 FB threshold 2 V CNTR ENABLE 0 FB threshold 2 V CNTR ENABLE 1 FB threshold not used CNTR LEVEL 1 0 These bits control reference level for contrast reduction comparator 0 4 V contrast reduction threshold 0 6 V contrast reduction threshold 0 8 V contrast reduction threshold o nm Not used CNTR ENABLE 1 OxF3 AFE CONTROL 1 AA FILT EN 0 Disables the internal antialiasing filter on Channel 0 Enables the internal antialiasing filter on Channel 0 AA FILT EN Disables the internal antialiasing filter on Channel 1 Enables the internal antialiasing filter on Channel 1 AA FILT EN 2 Disables the internal antialiasing filter on Channel 2 Enables the internal antialiasing filter on Channel 2 AA FILT EN 3 Disables the internal antialiasing filter on Channel 3 Enables the internal antialiasing filter on Channel 3 Rev A Page 97 of 112 ADV7188
12. Reserved 0 Set to default RES Chip Reset This bit loads all PC bits with 0 Normal operation Executing reset takes approximately default values 1 Start reset sequence 2ms This bit is self clearing 0x10 Status Register 1 IN_LOCK x 1 in lock now Provides information about the Read Only LOST_LOCK x 1 lost lock since last read internal status of the decoder FSC_LOCK x 1 Fsc lock now FOLLOW_PW x 1 peak white AGC mode active AD_RESULT 2 0 Autodetection result These 010 0 NTSM M J Detected standard bits report the standard of the input video olol NTSC 443 0 1 0 PALM 0 1 1 PAL 60 1 0 0 PAL B G H I D 1 0 1 SECAM 1 1 0 PAL Combination N 1 1 1 SECAM 525 COL KILL x 1 color kill is active Color kill Ox11 IDENT Read Only IDENT 7 0 These bits provide identification x x x X X X X X on the revision of the part 0x12 Status Register 2 MVCS DET x MV color striping detected 1 detected Read Only MVCS T3 x MV color striping type 0 Type 2 1 Type 3 MV PS DET x MV pseudosync detected 1 detected MV AGC DET x MV AGC pulses detected 1 detected LL NSTD x Nonstandard line length 1 detected FSC NSTD x Fsc frequency nonstandard 1 detected Reserved x X 0x13 Status Register 3 INST_HLOCK x 1 horizontal lock achieved Unfiltered Read only GEMD x 1 Gemstar data detected When the GEMD bit goes high it remains high until the end of the active video lines in that field SD OP 50Hz x SD field r
13. 10 Medium high drive strength 3x 11 High drive strength 4x DR STR 1 0 Description 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Enable Subcarrier Frequency Lock Pin EN SFL PIN Address 0x04 1 The EN SFL PIN bit enables the output of subcarrier lock information also known as genlock from the ADV7188 core to an encoder in a decoder encoder back to back arrangement 0 default The subcarrier frequency lock output is disabled 1 The subcarrier frequency lock information is presented on the SFL pin Polarity LLC Pin PCLK Address 0x37 0 The polarity of the clock that leaves the ADV7188 via the LLCI and LLC2 pins can be inverted using the PCLK bit Changing the polarity of the LLC clock output may be necessary to meet the setup time and hold time expectations of follow on chips This bit also inverts the polarity of the LLC2 clock 0 The LLC output polarity is inverted 1 default The LLC output polarity is normal as per the timing diagrams see Figure 2 to Figure 4 Rev A Page 22 of 112 GLOBAL STATUS REGISTERS Three registers provide summary information about the video decoder Status Register 1 Status Register 2 and Status Register 3 These registers contain status bits that report operational information to the user Status Register 1 7 0 Address 0x10 7 0 This read only register provides information abo
14. 2 Truncate to integer value 1071 6 1071 3 Convert to hexadecimal 1071d 0x42F 4 Split into two registers and program Luma Gain Control 1 3 0 0x4 Luma Gain Control 2 7 0 0x2F 5 Enable manual fixed gain mode Set LAGC 2 0 to 000 Rev A Page 36 of 112 BETACAM Enable BETACAM Levels Address 0x01 5 If YPrPb data is routed through the ADV7188 the automatic gain control modes can target different video input levels as outlined in Table 44 Note that the BETACAM bit is valid only if the input mode is YPrPb component The BETACAM bit sets the target value for AGC operation A review of the following sections is useful e The INSEL 3 0 Input Selection Address 0x00 3 0 section describes how component video YPrPb can be routed through the ADV7188 e The Video Standard Selection section describes the various standards for example with and without pedestal The automatic gain control AGC algorithms adjust the levels based on the setting of the BETACAM bit Table 43 BETACAM Function BETACAM Description 0 default Standard video input assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE 1 BETACAM input enable assuming YPrPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting P
15. Enable content based updating of Gemstar VPS PDC and UTC data The AVAILABLE bit shows the availability of data only when its content changes I2C GS VPS PDC UTC 1 0 0 0 Gemstar 1x 2x 0 1 VPS 1 0 PDC 1 1 UTC Standard expected to be decoded 1 Shading indicates default settings Rev A Page 108 of 112 PCB LAYOUT RECOMMENDATIONS The ADV7188 is a high precision high speed mixed signal device To achieve the maximum performance from the part it is important to have a well laid out PCB board The following is a guide for designing a board using the ADV7188 ANALOG INTERFACE INPUTS Care should be taken when routing the inputs on the PCB Track lengths should be kept to a minimum and 75 Q trace impedances should be used when possible Trace impedances other than 75 Q increase the chance of reflections POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0 1 uF and 10 nF capacitors The fundamental idea is to have a decoupling capacitor within about 0 5 cm of each power pin Also avoid placing the capacitor on the side of the PC board opposite from the ADV7188 because doing so interposes resistive vias in the path The decoupling capacitors should be located between the power plane and the power pin Current should flow from the power plane to the capacitor to the power pin Do not make the power connection between the capacitor a
16. SD FIELD CHNGD MSKB 0 Masks SD FIELD CHNGD OQ bit 1 Unmasks SD FIELD CHNGD OQ bit Reserved 0 0 Not used MPU STIM INTRO MSKB 0 Masks MPU_STIM_INTRQ_Q bit 1 Unmasks MPU_STIM_INTRQ_Q bit 0x49 Raw Status 3 SD OP 50Hz This bit indicates if the SD 60 Hz signal output These bits are status bits only Read Only SD 60 Hz or SD 50 Hz frame rate is at output SD 50 Hz signal output They cannot be cleared or masked Register 0x4A is used SD_V_LOCK SD vertical sync lock not established for this purpose SD vertical sync lock established SD_H_LOCK 0 SD horizontal sync lock not established 1 SD horizontal sync lock established Reserved x Not used SCM_LOCK 0 SECAM lock not established 1 SECAM lock established Reserved x Not used Reserved x Not used Reserved x Not used Rev A Page 102 of 112 ADV7188 Bit Address Register Bit Description 4 3 Comments Notes Ox4A Interrupt Status 3 SD OP CHNG Q This bit indicates if the No change in SD signal standard These bits can be cleared and Read Only SD 60 Hz or SD 50 Hz frame rate is at output detected at the output masked by Register Ox4B if no A change in SD signal standard is change is detected and by detected at the output Register Ox4C if a change is detected SD V LOCK CHNG Q
17. a o FILTER RESPONSE dB 1 a l e 05478 024 0 1 2 3 4 5 6 7 FREQUENCY MHz Figure 24 Peaking Filter Responses DNR TH2 7 0 DNR Noise Threshold 2 Address OxFC 7 0 The DNR2 block is positioned after the luma peaking block and therefore affects the amplified luma signal It operates in the same way as the DNRI block but has an independent threshold control DNR_TH2 7 0 This value is an unsigned 8 bit number that determines the maximum edge that is interpreted as noise and therefore blanked from the luma data Programming a large value into DNR_TH2 7 0 causes the DNR block to interpret even large transients as noise and remove them As a result the effect on the video data is more visible Programming a small value causes only small transients to be seen as noise and to be removed COMB FILTERS The comb filters of the ADV7188 have been greatly improved to automatically handle video of all types standards and levels of quality The NTSC and PAL configuration registers allow the user to customize comb filter operation depending on which video standard is detected by autodetection or selected by manual programming In addition to the bits listed in this section there are other Analog Devices internal controls Contact an Analog Devices representative for more information NTSC Comb Filter Settings Used for NTSC M and NTSC J CVBS inputs NSFSEL 1 0 Split Filter Selection NTSC
18. 0 default Gemstar PDC UTC or VPS data was not detected 1 Gemstar PDC UTC or VPS data was detected VDP VITC Q Address 0x4E 6 User Sub Map Read Only 0 default VITC data was not detected 1 VITC data was detected Interrupt Status Clear Register Details It is not necessary to write 0 to these write only bits because they automatically reset when they are set self clearing VDP_CCAPD_CLR Address 0x4F 0 User Sub Map 1 Clears the VDP_CCAP_Q bit Rev A Page 61 of 112 ADV7188 VDP CGMS WSS CHNGD CLR Address Ox4F 2 User Sub Map 1 Clears the VDP CGMS WSS CHNGD Q bit VDP GS VPS PDC UTC CHNG CIR Address 0x4F 4 User Sub Map 1 Clears the VDP GS VPS PDC UTC CHNG Q bit VDP VITC CLR Address 0x4F 6 User Sub Map 1 Clears the VDP VITC Q bit STANDARD DETECTION AND IDENTIFICATION The standard detection and identification STDI block of the ADV7188 monitors the synchronization signals received on the SOY pin STDI LINE COUNT MODE must be set to 1 to enable the STDI block and achieve valid synchronization signal analysis Four key measurements are performed e Block Length BL 13 0 This is the number of clock cycles in a block of eight lines From this the time duration of one line can be concluded Please note that the crystal frequency determines the clock cycle and that a crystal frequency of 28 63636 MHz should be used for the ADV7188 e Line Count in Field LCF
19. 0010 Autodetect PAL N without pedestal NTSC M without pedestal SECAM 0011 Autodetect PAL N with pedestal NTSC M with pedestal SECAM 0100 NTSC J 1 0101 NTSC M 1 0110 PAL 60 0111 NTSC 4 43 1 1000 PAL B G H I D 1001 PAL N PAL B G H I D without pedestal 1010 PAL M without pedestal 1011 PAL M 1100 PAL Combination N 1101 PAL Combination N with pedestal 1110 SECAM 1111 SECAM with pedestal Rev A Page 25 of 112 ADV7188 AD_SEC525_EN SECAM 525 Autodetect Enable Address 0x07 7 O default Disables the autodetection of a 525 line system with a SECAM style FM modulated color component 1 Enables autodetection AD_SECAM_EN SECAM Autodetect Enable Address 0x07 6 0 Disables the autodetection of SECAM 1 default Enables autodetection AD_N443_EN NTSC 443 Autodetect Enable Address 0x07 5 0 Disables the autodetection of NTSC style systems with a 4 43 MHz color subcarrier 1 default Enables autodetection AD_P60_EN PAL 60 Autodetect Enable Address 0x07 4 0 Disables the autodetection of PAL systems with a 60 Hz field rate 1 default Enables autodetection AD_PALN_EN PAL N Autodetect Enable Address 0x07 3 0 Disables the autodetection of the PAL N standard 1 default Enables autodetection AD PALM EN PAL M Autodetect Enable Address 0x07 2 0 Disables the autodetection of PAL M 1 default Enables autodetection AD NTSC EN
20. 1 Reserved do not use Reserved 0 0 Set to default WYSFMOVR Enables the use of the manual 0 Automatic selection of best WYSFM filter selection wideband Y shaping filter 1 Manual selection of filter using WYSFM 4 0 0x19 Comb Filter Control PSFSEL 1 0 These bits control the signal 0 0 Narrow bandwidth that is fed to the comb filters PAL 0 17 Medium 1 0 Wide 1 1 Widest NSFSEL 1 0 These bits control the signal 0 0 Narrow bandwidth that is fed to the comb filters NTSC 011 Medium 1 0 Medium 1 1 Wide Reserved 1 1 1 1 Set as default 0x1D ADI Control 2 Reserved 0 0 0 x x x Set to default EN28XTAL 0 Use 27 MHz crystal 1 Use 28 63636 MHz crystal TRI LLC 0 LLC pin active Applies to both LLC1 and LLC2 1 LLC pin three stated 0x27 Pixel Delay Control LTA 1 0 Luma timing adjust These bits allow 0 0 No delay CVBS mode LTA 1 0 00b the user to specify a timing difference between 0 1 Luma one clock 37 ns delayed S video mode LTA 1 0 01b chroma and luma samples YPrPb mode LTA 1 0 01b 1 0 Luma two clock 74 ns early 1 1 Luma one clock 37 ns early Reserved 0 Setto O Rev A Page 88 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes CTA 2 0 Chroma timin
21. 1 0 These bits control the first combed line after VBI on PAL even field Iuma comb 01 default ITU R BT 470 compliant blank Lines 624 to 22 311 to 335 comb half lines NVBIOCOM 1 0 NTSC VBI Odd Field Chroma Comb Mode Address OxEC 7 6 These bits control the first combed line after VBI on NTSC odd field chroma comb 01 default SMPTE170 TTU R BT 470 compliant no color on Lines 1 to 20 264 to 282 chroma present on half lines NVBIECCM 1 0 NTSC VBI Even Field Chroma Comb Mode Address OxEC 5 4 These bits control the first combed line after VBI on NTSC even field chroma comb 01 default SMPTE170 ITU R BT 470 compliant no color on Lines 1 to 20 264 to 282 chroma present on half lines PVBIOCCM 1 0 PAL VBI Odd Field Chroma Comb Mode Address OxEC 3 2 These bits control the first combed line after VBI on PAL odd field chroma comb 01 default ITU R BT 470 compliant no color on Lines 624 to 22 311 to 335 chroma present on half lines PVBIECOCM 1 0 PAL VBI Even Field Chroma Comb Mode Address OxEC 1 0 These bits control the position of the first combed line after VBI on PAL even field chroma comb 01 default ITU R BT 470 compliant no color on Lines 624 to 22 311 to 335 chroma present on half lines AV CODE INSERTION AND CONTROLS This section describes the IC based controls that affect e Insertion of AV codes into the data stream e Data blanking during
22. Address 0x19 3 2 NSFSEL 1 0 selects how much of the overall signal bandwidth is fed to the combs A narrow bandwidth split filter results in better performance on diagonal lines but more dot crawl in the final output image The opposite is true for a wide bandwidth split filter Table 50 NSFSEL 1 0 Function NSFSEL 1 0 Description 00 default Narrow 01 Medium 10 Medium 11 Wide CTAPSN 1 0 Chroma Comb Taps NTSC Address 0x38 7 6 Table 51 CTAPSN 1 0 Function CTAPSN 1 0 Description 00 Do not use 01 NTSC chroma comb adapts three lines three taps to two lines two taps NTSC chroma comb adapts five lines five taps to three lines three taps 11 NTSC chroma comb adapts five lines five taps to four lines four taps 10 default Rev A Page 40 of 112 ADV7188 CCMN 2 0 Chroma Comb Mode NTSC Address 0x38 5 3 Table 52 CCMN 1 0 Function CCMN 2 0 Description Configuration 000 default Adaptive comb mode Adaptive 3 line chroma comb for CTAPSN 01 Adaptive 4 line chroma comb for CTAPSN 10 Adaptive 5 line chroma comb for CTAPSN 11 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 110 Fixed chroma comb all lines of line memory Fixed 3 line chroma comb for CTAPSN 01 Fixed 4 line chroma comb for CTAPSN
23. CC e Macrovision protection presence e Gemstar compatible data slicing e Teletext e VITC VPS The ADV7188 is also capable of automatically detecting the incoming video standard with respect to e Color subcarrier frequency e Field rate Line rate The ADV7188 can configure itself to support PAL B G H I D M N PAL Combination N NTSC M NTSC J SECAM 50 Hz 60 Hz NTSC 4 43 and PAL 60 ADV7188 GENERAL SETUP Video Standard Selection The VID_SEL 3 0 bits allow the user to force the digital core into a specific video standard Under normal circumstances this should not be necessary The VID_SEL 3 0 bits default to an autodetection mode that supports PAL NTSC SECAM and variants thereof The following section describes the autodetec tion system Autodetection of SD Modes To guide the autodetection system individual enable bits are provided for each of the supported video standards Setting the relevant bit to 0 inhibits the standard from being automatically detected Instead the system selects the closest of the remaining enabled standards The results of the autodetection can be read back via the status registers See the Global Status Registers section for more information VID_SEL 3 0 Address 0x00 7 4 Table 24 VID_SEL Function VID_SEL 3 0 Description 0000 default Autodetect PAL B G H I D NTSC without pedestal SECAM 0001 Autodetect PAL B G H I D NTSC M with pedestal SECAM
24. CTI chroma threshold These 0 0 0 0 1 0 0 0 bits specify how big the amplitude step must be to be steepened by the CTI block 0x50 CTI DNR Control 4 DNR TH 7 0 DNR threshold These bits 0 0 0 0 1 0 0 0 Setto 0x04 for A V input set to specify the maximum edge that is interpreted Ox0A for tuner input as noise and is therefore blanked 0x51 Lock Count CIL 2 0 Count into lock These bits determine 1line of video the number of lines the system must remain in lock before reporting a locked status 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video W olololo alolol alalolo oj 0 O 100 000 lines of video COL 2 0 Count out of lock These bits determine the number of lines the system must remain out of lock before reporting an unlocked status 1 line of video 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 2 2 2 21lol ololo o W lolo lolalolalo lalo 100 000 lines of video SRLS Select raw lock signal Selects the source for determining the lock status Over field with vertical information Line to line evaluation FSCLE Fsc lock enable Lock status set only by horizontal lock Lock status set by horizontal lock and subcarrier lock
25. DIGITIZED CVBS DIGITAL L CHROMA oi CHROMA DIGITIZED C Y C FINE 1 DEMOD 1 FILTER i CLAMP 3 1 CHROMA AIN i I CONTROL SLLC CONTROL LUMA LUM MILLE 2D COMB RESAMPLE VIDEO DATA CONTROL CODE OUTPUT l CHROMA CHROMA El MEASUREMENT ME 2D COMB BLOCK gt 12C VIDEO DATA 173 PROCESSING BLOCK 05478 012 Figure 12 Block Diagram of the Standard Definition Processor A block diagram of the ADV7188 standard definition processor SDP is shown in Figure 12 The SDP can handle standard definition video in CVBS Y C and YPrPb formats It can be divided into a luminance path and a chrominance path If the input video is of a composite type CVBS both processing paths are fed with the CVBS input SD LUMA PATH The input signal is processed by the following blocks e Luma Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Luma Filter This block contains a luma decimation filter YAA with a fixed response and some luma shaping filters YSH that have selectable responses e Luma Gain Control The automatic gain control AGC can operate on a variety of modes including a mode based on the depth of the horizontal sync pulse a mode based on the peak white mode and a mode that uses a fixed manual gain e Luma Resample To correct for errors and dynamic changes in line lengths the data is digitally resampled e Luma 2D Comb The two dimensional
26. NTSC Autodetect Enable Address 0x07 1 0 Disables the autodetection of standard NTSC 1 default Enables autodetection AD_PAL_EN PAL B G I H Autodetect Enable Address 0x07 0 0 Disables the autodetection of standard PAL 1 default Enables autodetection Subcarrier Frequency Lock Inversion The SFL_INV bit of Register 0x41 controls the behavior of the PAL switch bit in the SFL genlock telegram data stream It was implemented to solve some compatibility issues with video encoders It solves two problems First the PAL switch bit is only meaningful in PAL Some encoders including Analog Devices encoders also look at the state of this bit in NTSC Second there was a design change in Analog Devices encoders from ADV717x to ADV719x The older versions used the SFL genlock telegram bit directly whereas the more recent versions invert the bit prior to using it to compensate for the 1 line delay of an SFL genlock telegram transmission As a result to be compatible with NTSC format the PAL switch bit in the SFL genlock telegram must be 1 for ADV717x encoders and 0 for ADV7190 ADV7191 ADV7194 encoders If the state of the PAL switch bit is set incorrectly a 180 phase shift occurs In a decoder encoder back to back system in which SFL is used this bit must be set up properly for the specific encoder used SFL_INV Address 0x41 6 0 default Makes the part SFL compatible with ADV717x and ADV73xx e
27. No change in SD vertical sync lock status SD vertical sync lock status has changed SD H LOCK CHNG Q No change in SD horizontal sync lock status SD horizontal sync lock status has changed SD AD CHNG Q SD autodetect changed 0 No change in AD RESULT 2 0 bits in Status Register 1 1 AD RESULT 2 0 bits in Status Register 1 have changed SCM LOCK CHNG Q SECAM lock No change in SECAM lock status SECAM lock status has changed PAL SW LK CHNG Q No change in PAL swinging burst lock status PAL swinging burst lock status has changed Reserved Not used Reserved Not used Ox4B Interrupt Clear 3 SD OP CHNG CLR Do not clear Write Only Clears SD OP CHNG Q bit SD V LOCK CHNG CLR Do not clear Clears SD V LOCK CHNG Qbit SD H LOCK CHNG CLR Do not clear Clears SD H LOCK CHNG OQ bit SD AD CHNG CLR 0 Do not clear 1 Clears SD AD CHNG O bit SCM LOCK CHNG CLR 0 Do not clear Clears SCM LOCK CHNG O bit PAL SW LK CHNG CLR Do not clear Clears PAL SW LK CHNG O bit Reserved Not used Reserved Not used Ox4C Interrupt Mask 2 SD OP CHNG MSKB Masks SD OP CHNG O bit Read Write Unmasks SD OP CHNG Q bit SD V LOCK CHNG MSKB Masks SD V LOCK CHNG OQ bit Unmasks SD V LOCK CHNG O bit SD H LOCK CHNG MSKB Masks SD H LOCK CHNG OQ bit Unmasks SD H LOCK CHNG O bit SD AD CHNG MSKB 0 Masks SD_AD_CHNG_Q bit 1 Unmasks SD_AD_CHNG_Q bit SCM_LOCK_CHNG_MSKB Masks SCM_LOCK_CHNG_Q bit Unmasks SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_MSK
28. R G and B signals can be input either on AIN4 AIN5 and AIN6 or on AIN7 AINS and AIN9 O default B is input on AIN4 R is input on AIN5 and G is input on AIN6 1 B is input on AIN7 R is input on AINS and G is input on AINO MANUAL INPUT MUXING By accessing a set of manual override muxing registers the analog input muxes of the ADV7188 can be controlled directly This is referred to as manual input muxing Manual input muxing overrides other input muxing control bits including INSEL and SDM SEL Manual muxing is activated by setting the ADC SW MAN EN bit It only affects the analog switches in front of the ADCs Therefore if the settings of INSEL and the manual input muxing bits ADCO SW ADCI SW ADC2 SW ADC3 SW contradict each other the ADCO_SW ADC1_SW ADC2_SW ADC3 SW settings apply and INSEL and SDM SEL are ignored Manual input muxing controls only the analog input muxes For the follow on blocks to process video data in the correct format however INSEL must still be used to indicate whether the input signal is of YPbPr Y C or CVBS format Restrictions in the channel routing are imposed by the analog signal routing inside the IC each input pin cannot be routed to each ADC Refer to Figure 6 for an overview on the routing cap abilities inside the chip The four mux sections can be controlled by the reserved control signal buses ADCO SW 3 0 ADC1_SW 3 0 ADC2 SW 3 0 and ADC3 SW 3 0 Table 11 exp
29. Read Only Reserved ojololo Ox7E VDP_CGMS_WSS_DATA_1 CGMS_WSS 13 8 X X X X X Decoded CGMS WSS data Read Only CGMS_CRC 1 0 x x Decoded CRC sequence for CGMS Ox7F VDP CGMS WSS DATA 2 CGMS WSS 7 0 X X X X X X X Decoded CGMS WSS data Read Only 0x84 VDP GS VPS PDC UTC 0 GS VPS PDC UTC BYTE O X X X X X X X Decoded Gemstar VPS PDC UTC data Read Only 0x85 VDP GS VPS PDC UTC 1 GS VPS PDC UTC BYTE 1 X X X X X X X Decoded Gemstar VPS PDC UTC data Read Only 0x86 VDP GS VPS PDC UTC 2 GS VPS PDC UTC BYTE 2 X X X X X X X Decoded Gemstar VPS PDC UTC data Read Only 0x87 VDP GS VPS PDC UTC 3 GS VPS PDC UTC BYTE 3 X X X X X X X Decoded Gemstar VPS PDC UTC data Read Only 0x88 VDP VPS PDC UTC 4 VPS PDC UTC BYTE 4 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only 0x89 VDP VPS PDC UTC 5 VPS PDC UTC BYTE 5 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only 0x8A VDP VPS PDC UTC 6 VPS PDC UTC BYTE 6 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only 0x8B VDP VPS PDC UTC 7 VPS PDC UTC BYTE 7 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only 0x8C VDP VPS PDC UTC 8 VPS PDC UTC BYTE 8 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only 0x8D VDP VPS PDC UTC 9 VPS PDC UTC BYTE 9 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only Ox8E VDP_VPS_PDC_UTC_10 VPS_PDC_UTC_BYTE_10 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only Ox8F VDP VPS PDC UTC 11 VPS PDC UTC BYTE 11 7 0
30. The crystal frequency is 28 63636 MHz ANTIALIASING FILTERS The ADV7188 has optional antialiasing filters on each of the four input channels The filters are designed for SD video with approximately 6 MHz bandwidth A plot of the filter response is shown in Figure 8 The filters can be individually enabled via I C under the control of AA FILT EN 3 0 AA FILT EN 0 Address OxF3 0 0 default The filter on Channel 0 is disabled 1 The filter on Channel 0 is enabled AA FILT EN 1 Address OxF3 1 O default The filter on Channel 1 is disabled 1 The filter on Channel 1 is enabled AA FILT EN 2 Address OxF3 2 O default The filter on Channel 2 is disabled 1 The filter on Channel 2 is enabled AA FILT EN 3 Address OxF3 3 O default The filter on Channel 3 is disabled 1 The filter on Channel 3 is enabled RESPONSE OF AA FILTER WITH CALIBRATED CAPACITORS FAIL ATTENUATION dB S o N 05478 008 o o e z o FREQUENCY Hz Figure 8 Frequency Response of Internal ADV7188 Antialiasing Filters SCART AND FAST BLANKING The ADV7188 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality This function is available when INSEL 3 0 is set appropriately see Ta
31. The values for Cr and Cb are set by the DEF C 7 0 bits A value of 0x7C in conjunction with the DEF Y 5 0 default setting produces a blue color DEF VAL EN Default Value Enable Address 0x0C 0 This bit forces the use of the default values for Y Cr and Cb Refer to the descriptions in the DEF Y 5 0 Default Value Y Address 0x0C 7 2 and DEF C 7 0 Default Value C Address 0x0D 7 0 sections for additional information In this mode the decoder also outputs a stable 27 MHz clock HS and VS O default Outputs a colored screen determined by user programmable Y Cr and Cb values when the decoder free runs Free run mode is turned on and off via DEF VAL AUTO EN 1 Forces a colored screen output determined by user programmable Y Cr and Cb values This overrides picture data even if the decoder is locked Rev A Page 29 of 112 ADV7188 DEF VAL AUTO EN Default Value Automatic Enable Address Ox0C 1 This bit enables the automatic use of the default values for Y Cr and Cb when the ADV7188 cannot lock to the video signal 0 Disables free run mode If the decoder is unlocked it outputs noise 1 default Enables free run mode A colored screen set by the user programmable Y Cr and Cb values is displayed when the decoder loses lock CLAMP OPERATION The input video is ac coupled into the ADV7188 through a 0 1 uF capacitor It is recommended that the range of the input video signal is 0 5 V to 1
32. This can easily be accomplished by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV7188 creating more digital noise on its power supplies Rev A Page 109 of 112 ADV7188 DIGITAL INPUTS The digital inputs on the ADV7188 are designed to work with 3 3 V signals and are not tolerant of 5 V signals Extra compo nents are needed if 5 V logic signals are required to be applied to the decoder XTAL AND LOAD CAPACITOR VALUES SELECTION Figure 51 shows an example reference clock circuit for the ADV7188 Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7188 Small variations in reference clock frequency may cause autodetection issues and impair the ADV7188 performance XTAL 28 63636MHz R 1MQ Figure 51 Crystal Circuit C1 47pF C2 47pF 05478 054 Use the following guidelines to ensure correct operation e Usea crystal of the correct frequency 28 63636 MHz Tolerance should be 50 ppm or better e User a parallel resonant crystal e Knowthe Cia for the crystal part selected The values of the C1 and C2 capacitors must be calculated using this Cis value To find C1 and C2 use the following formula C MCioaa Cstray Cpg where Ci is usually 2 pF to 3 pF depending on board traces and C pin to ground capacitance is 4 pF for the ADV7188 Fo
33. VBI DATA P22 VBI DATA P22 VBI DATA P22 VBI DATA P335 VBI DATA P335 VBI DATA P335 VBI DATA 00000000 00 P22 N20 3 N20 2 N20 1 N20 0 N283 3 N283 2 N283 1 P335 N283 0 118 76 VDP LINE 020 RW VBI DATA VBI DATA P23 VBI DATA P23 VBI DATA P23 VBI DATA P336 VBI DATA P336 VBI DATA P336 VBI DATA 00000000 00 P23 N21 3 N21 2 N21 1 N21 0 N284 3 N284 2 N284 1 P336 N284 0 119 77 VDP LINE 021 RW VBI DATA VBI DATA P24 VBI DATA P24 VBI DATA P24 VBI DATA P337 VBI DATA P337 VBI DATA P337 VBI DATA 00000000 00 P24 N22 3 N22 2 N22 1 N22 0 N285 3 N285 2 N285 1 P337 N285 0 120 78 VDP STATUS w VITC_CLEAR GS_PDC_VPS_ CGMS_WSS_ CC_CLEAR 00000000 00 CLEAR UTC_CLEAR CLEAR 120 78 VDP STATUS R TTXT AVL VITC_AVL GS DATA TYPE GS_PDC_VPS_ CGMS WSS AVL CC EVEN FIELD CC AVL UTC AVL 121 79 VDP_CCAP_ R CCAP BYTE 17 CCAP BYTE 1 6 CCAP BYTE 1 5 CCAP BYTE 14 CCAP BYTE 13 CCAP BYTE 12 CCAP BYTE 1 1 CCAP_ DATA 0 BYTE 1 0 122 7A VDP CCAP R CCAP BYTE 27 CCAP BYTE 26 CCAP BYTE 2 5 CCAP BYTE 24 CCAP BYTE 23 CCAP BYTE 22 CCAP BYTE 2 1 CCAP_ DATA_1 BYTE_2 0 125 7D CGMS WSS R zero zero zero zero CGMS CRC 5 CGMS CRCA CGMS CRC3 CGMS DATA 0 CRC2 126 7E CGMS_WSS_ R CGMS CRC 1 CGMS CRCO CGMS WSS 13 CGMS WSS 12 CGMS WSS 11 CGMS WSS 10 CGMS WSS 9 CGMS_ DATA_1 WSS 8 127 7F CGMS_WSS_ R CGMS_WSS 7 CGMS_WSS 6 CGMS WSS 5 CGMS_WSS 4 CGMS WSS 3 CGMS WSS 2 CGMS WSS 1 CGMS_ DATA_2 WSS O 132 84 VDP_GS_VPS_ R GS VPS PDC
34. and VITC Because teletext is a high data rate standard data extraction is supported only through the ancillary data packet The details of these registers and their access procedures are described in this section User Interface for PC Readback Registers The VDP decodes all enabled VBI data standards in real time Because the IC access speed is much slower than the decoded rate the registers may be updated with data from the next line when they are being accessed To avoid this VDP has a self clearing CLEAR bit and an AVAILABLE status bit accompanying all the C readback registers The user has to clear the PC readback register by writing a high to the CLEAR bit This resets the state of the AVAILABLE bit to low and indicates that the data in the associated readback registers is not valid After the VDP decodes the next line of the corresponding VBI data the decoded data is placed in the I C readback register and the AVAILABLE bit is set high to indicate that valid data is now available Although the VDP if present decodes this VBI data in subsequent lines the decoded data is not updated to the readback registers until the CLEAR bit is set high again However this data is available through the 656 ancillary data packets The CLEAR and AVAILABLE bits are in the VDP_STATUS_CLEAR Address 0x78 user sub map write only and VDP_STATUS 0x78 User Sub Map read only registers Example lC Readback Procedure To read one packet li
35. automatically set to 0 UDWS9 5 2 0000 undefined bits automatically set to 0 UDW10 5 2 0000 undefined bits automatically set to 0 and for the byte mode UDWS5 9 2 0010_0111 UDW6 9 2 0000 0000 undefined bits automatically set to 0 UDW7 9 2 0000_0000 undefined bits automatically set to 0 Data Bytes VBI_WORD_4 to VBI WORD N 3 contain the data words that were decoded by the VDP in the order of transmission The position of bits in bytes is in the reverse order of transmission For example closed captioning has two user data bytes as shown in Table 80 The data bytes in the ancillary data stream in this case are as follows VBI WORD 4 BYTEI 7 0 VBI WORD 5 BYTE2 7 0 The number of VBI WORDS for each VBI data standard and the total number of UDWs in the ancillary data stream are shown in Table 75 Rev A Page 58 of 112 Table 74 Framing Code Sequence for Different VBI Standards ADV7188 VBI Standard Length in Bits Error Free Framing Code Bits In Order of Transmission Error Free Framing Code Reported by VDP In Reverse Order of Transmission TTXT_SYSTEM_A PAL 8 11100111 11100111 TTXT SYSTEM B PAL 8 11100100 00100111 TTXT SYSTEM B NTSC 8 11100100 00100111 TTXT SYSTEM C PAL and NTSC 8 11100111 11100111 TTXT SYSTEM D PAL and NTSC 8 11100101 10100111 VPS PAL 16 10001010100011001 1001100101010001 VITC NTSC and PAL 1 0 0 WSS P
36. default 1 lt Y lt 254 1 lt C lt 254 AUTO_PDC_EN Automatic Programmed Delay Control Address 0x27 6 Enabling AUTO_PDC_EN activates a function within the ADV7188 that automatically programs LTA 1 0 and CTA 2 0 to have the chroma and luma data match delays for all modes of operation 0 The ADV7188 uses the LTA 1 0 and CTA 2 0 values for delaying luma and chroma samples Refer to the LTA 1 0 Luma Timing Adjust Address 0x27 1 0 and the CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 sections 1 default The ADV7188 automatically programs the LTA and CTA values to have luma and chroma aligned at the output Manual registers LTA 1 0 and CTA 2 0 are not used LTA 1 0 Luma Timing Adjust Address 0x27 1 0 These bits allow the user to specify a timing difference between chroma and luma samples Note that there is a certain functionality overlap with the CTA 2 0 bits For manual programming use the following defaults e CVBS input LTA 1 0 00 e Y Cinput LTA 1 0 01 e YPrPb input LTA 1 0 01 Table 59 LTA 1 0 Function CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 These bits allow the user to specify a timing difference between chroma and luma samples This may be used to compensate for external filter group delay differences in the luma vs chroma path and to allow a different number of pipeline delays while processing the video downstream Review this functionality toge
37. in the VDP STATUS register is set high and the content in the PC registers for that standard is set to 0 The user must write high to the corresponding CLEAR bit so that when a subsequent valid line is decoded the decoded results are available in the PC registers with the AVAILABLE status bit set high If content based updating is enabled the AVAILABLE bit is set high assuming the CLEAR bit was written to in the following cases e The data contents changed e Data was being decoded and four lines with no data have been detected e No data was being decoded and new data is now being decoded GS VPS PDC UTC CB CHANGE Enable Content Based Updating for Gemstar VPS PDC UTC Address 0x9C 5 User Sub Map 0 Disables content based updating 1 default Enables content based updating WSS_CGMS_CB_CHANGE Enable Content Based Updating for WSS CGMS Address 0x9C 4 User Sub Map 0 Disables content based updating 1 default Enables content based updating Rev A Page 60 of 112 ADV7188 VDP Interrupt Based Reading of VDP PC Registers Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the AVAILABLE status bit The user can configure the video decoder to trigger an interrupt request on the INTRQ pin in response to the valid data available in I C registers This function is available for the following data types e CGMS or WSS The user can se
38. precise clamping of the input signal within the analog domain is unnecessary if the video signal fits within the ADC range After digitization the digital fine clamp block corrects for any remaining variations in dc level Because the dc level of an input video signal refers directly to the brightness of the picture transmitted it is important to perform a fine clamp with high accuracy otherwise brightness variations may occur Further more dynamic changes in the dc level usually lead to significant artifacts and must therefore be prohibited The clamping scheme must be able to acquire a newly connected video signal with a completely unknown dc level and it must maintain the dc level during normal operation To quickly acquire an unknown video signal activate the large current clamps It is assumed that the amplitude of the video signal at this point is ofa nominal value Control of the coarse and fine current clamp parameters is automatically performed by the decoder Standard definition video signals may contain excessive noise In particular CVBS signals transmitted by terrestrial broadcast and then demodulated using a tuner usually show very large levels of noise gt 100 mV A voltage clamp would be unsuitable for this type of video signal Instead the ADV7188 uses a set of four current sources that can cause coarse gt 0 5 mA and fine lt 0 1 mA currents to flow into and away from the high impedance node that carries th
39. 0 Automatic gain Based on color burst 1 1 Freeze chroma gain Reserved 1 1 Set to 1 LAGC 2 0 Luma automatic gain control 0 0 0 Manual fixed gain Use LMG 11 0 These bits select the mode of operation for olol1 Reserved Blank level to sync tip the gain control in the luma path 01 0 AGC peak white algorithm enabled Blank level to sync tip 01 1 Reserved 1 0 0 AGC peak white algorithm disabled Blank level to sync tip 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Freeze gain Reserved 1 Setto 1 0x2D Chroma Gain CG 11 8 CMG 11 8 Chroma manual gain OR RIR EON CAGC 1 0 must be set to 00 manual Control 1 These bits can be used to program a desired fixed gain to use CMG 11 0 manual chroma gain Reading back from these bits in AGC mode gives the current gain Reserved 1 1 Set to 1 CAGT 1 0 Chroma automatic gain timing 0 0 Slow TC 2 sec Has an effect only if CAGC 1 0 is set These bits allow adjustment of the chroma 0 1 Medium TC 1 sec to 10 automatic gain AGC tracking speed 1 0 Fast TC 0 2 sec 1 1 Adaptive Ox2E Chroma Gain CG 7 0 CMG 7 0 Lower eight bits of chroma 0 0 0 0 0 0 0 0 CMG 11 0 750d gain is 1 in Minimum value is Od G 60 dB Control 2 manual gain See CG 11 8 CMG 11 8 for NTSC CMG 11 0 741d gain maximum value is 3750d G 5 dB description is 1 in PAL Ox2F Luma Gain Control 1 LG 11 8 LMG 11 8 Luma manual gain x x x x LAGC 2 0 settings decide in These bi
40. 0 0 111 8 bit format at LLC1 4 2 2 ITU R BT 656 0 1 0 0 Not used 0 1 011 Not used 0 1 1110 Not used 0 1 111 Not used 1 0 0 0 Not used 1 0 0 1 Not used 1 0 1 0 Not used 1 0 1 1 Not used 1 1 0 0 Not used 1 1 0 1 Not used 1 1 1 0 Not used 1 1 1 1 Not used TOD Three state output drivers This bit 0 Output pins enabled See also TIM OE and TRI LLC allows the user to three state the output 1 Drivers three stated drivers P 19 0 HS VS FIELD and SFL VBI EN This bit allows VBI data Lines 1 to 21 0 All lines filtered and scaled to be passed through with minimum filtering 1 Only active video region filtered 0x04 Extended Output RANGE This bit allows the user to select the 0 16 lt Y lt 235 16 lt C lt 240 ITU R BT 656 Control range of output values It can be ITU R BT 656 1 1 Y 254 1 C 254 Extended range compliant or fill the whole accessible number range EN SFL PIN 0 SFL output is disabled SFL output enables connecting 1 SFL information output encoder and decoder directly on the SFL pin BL C VBI Blank chroma during VBI When 0 Decode and output color During VBI set this bit enables data in the VBI region to 1 Blank Cr and Cb be passed through the decoder undistorted TIM OE Timing signals output enable 0 HS VS FIELD three stated Controlled by TOD bit 1 HS VS FIELD forced active Reserved x x Reserved 1 BT 656 ITU R BT 656 4 enable This bit allows 0 ITU R BT 656 3 compatible the user to select an output
41. 08 Contrast RW CON 7 CON 6 CON 5 CON 4 CON 3 CON 2 CON 1 CON 0 10000000 80 10 OA Brightness RW BRI 7 BRI 6 BRI 5 BRI 4 BRI 3 BRI 2 BRI 1 BRI O 00000000 00 11 OB Hue RW HUE 7 HUE 6 HUE 5 HUE 4 HUE 3 HUE 2 HUE 1 HUE O 00000000 00 12 OC Default Value Y RW DEF Y 5 DEF Y 4 DEF Y 3 DEF Y 2 DEF Y 1 DEF Y 0 DEF VAL AUTO DEF VAL EN 00110110 36 _EN 13 OD Default Value C RW DEF C7 DEF C6 DEF C 5 DEF C4 DEF C3 DEF C2 DEF C 1 DEF CO 01111100 7C 14 OE Analog Devices SUB USR EN 00000000 00 Control 15 OF Power Management RW RES PWRDN PDBP FB PWRDN 00000000 00 16 10 Status 1 R COL KILL AD RESULT 2 AD RESULT 1 AD RESULT O FOLLOW PW FSC LOCK LOST LOCK IN LOCK 18 12 Status 2 R FSC NSTD LL NSTD MV AGCDET MV PS DET MVCS T3 MVCS DET 19 13 Status3 R PAL SW LOCK INTERLACE STDFLD LEN FREE RUN ACT CVBS SD OP 50Hz GEMD INST HLOCK 19 13 Analog Control Ww XTAL TTL SEL 00000000 00 Internal 20 14 Analog Clamp RW CCLEN 00010010 12 Control 21 15 Digital Clamp RW DCT 1 DCT o 0000xxxx 00 Control 1 23 17 Shaping Filter RW CSFM 2 CSFM 1 CSFM O YSFM 4 YSFM 3 YSFM 2 YSFM 1 YSFM O 00000001 01 Control 24 18 Shaping Filter RW WYSFMOVR WYSFM 4 WYSFM 3 WYSFM 2 WYSFM 1 WYSFM O 10010011 93 Control 2 25 19 Comb Filter Control RW NSFSEL 1 NSFSEL O PSFSEL 1 PSFSEL O 11110001 F1 29 1D Analog Devices RW TRI LLC EN28XTAL 00000xxx 00 Control 2 39 27 Pixel Delay Control RW SWPC AUTO PDC EN CTA 2 CTA 1 CTA O LT
42. 10 0 The LCF 10 0 readback value is the number of lines between two vsyncs that is over one field e Line Count in Vsync LCVS 4 0 The LCVS 4 0 readback value is the number of lines within one vsync period e Field Length FCL 12 0 This is the number of clock cycles in 1 256 of a field Multiplying this value by 256 calculates the field length in clock cycles By interpreting these four parameters it is possible to distinguish among the types of input signals A data valid flag STDI VALID is provided that is held low during the measurements The four parameters should only be read after the STDI VALID flag has gone high Refer to Table 76 for information on the readback values Notes e Types of synchronization pulses include horizontal synchronization pulses equalization and serration pulses and Macrovision pulses e Macrovision pseudosynchronization and AGC pulses are counted by the STDI block in normal readback mode This does not prohibit the identification of the video signal e The ADV7188 only measures the parameters it does not take any action based on these measurements Therefore the part helps to identify the input to avoid problems in the scheduling of a system controller but it does not reconfigure itself STDI DVALID Standard Identification Data Valid Read Back Address 0xB1 7 X This bit is set by the ADV7188 as soon as the measurements of the STDI block are finished A high level signals
43. 3 0 3 3 3 6 V PLL Power Supply Pvop 1 71 1 8 1 89 V Analog Power Supply Avoo 3 15 3 3 3 45 V Digital Core Supply Current lovop 105 mA Digital Input Output Supply Current Ipvbpio 4 mA PLL Supply Current lpvop 11 mA Analog Supply Current lavop CVBS input 99 mA SCART RGB FB input 269 mA Power Down Current IpwrDN 0 65 mA Power Up Time tewrup 20 ms 1 All ADC linearity tests performed with the input range at full scale 12 5 and at zero scale 12 5 Maximum INL and DNL specifications obtained with the part configured for component video input 3 Temperature range Tmn to Tmax 40 C to 85 C The minimum maximum specifications are guaranteed over this range To obtain specified Vi level on Pin 29 Register 0x13 write only must be programmed with Value 0x04 If Register 0x13 is programmed with Value 0x00 then Vmon Pin 29 is 1 2 V 5 To obtain specified Vi level on Pin 29 Register 0x13 write only must be programmed with Value 0x04 If Register 0x13 is programmed with Value 0x00 then Vi on Pin 29 is 0 4 V 5 Pins 36 64 79 7 Excluding all TEST pins TESTO to TEST8 8 Vos and Vo levels obtained using default drive strength value 0xD5 in Register OxF4 Guaranteed by characterization 1 Only ADCO is powered on All four ADCs powered on Rev A Page 5 of 112 ADV7188 VIDEO SPECIFICATIONS At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V Pypp 1 71 V to 1 89 V operat
44. 6 BYTE 6 5 BYTE 64 BYTE 6 3 BYTE 6 2 BYTE 6 1 UTC BYTE 6 0 139 8B VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 7 BYTE 7 7 BYTE 7 6 BYTE 7 5 BYTE 74 BYTE 7 3 BYTE 7 2 BYTE 7 1 UTC BYTE 7 0 140 8C VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 8 BYTE 87 BYTE 8 6 BYTE 8 5 BYTE 84 BYTE 8 3 BYTE 82 BYTE 8 1 UTC BYTE 8 0 141 8D VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 9 BYTE 9 7 BYTE 9 6 BYTE 9 5 BYTE 94 BYTE 9 3 BYTE 92 BYTE 9 1 UTC BYTE 9 0 142 8E VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 10 BYTE 107 BYTE 10 6 BYTE 10 5 BYTE 10 4 BYTE 10 3 BYTE 10 2 BYTE 10 1 UTC BYTE 10 0 143 8F VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 11 BYTE 11 7 BYTE 11 6 BYTE 11 5 BYTE 11 4 BYTE 11 3 BYTE 11 2 BYTE 11 1 UTC BYTE 11 0 144 90 VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 12 BYTE 127 BYTE 12 6 BYTE 12 5 BYTE 12 4 BYTE 12 3 BYTE 12 2 BYTE 12 1 UTC BYTE 12 0 146 92 VDP VITC R VITC DATA 1 7 VITC DATA 1 6 VITC DATA 1 5 VITC DATA 1 4 VITC DATA 1 3 VITC DATA 1 2 VITC DATA 1 1 VITC DAT
45. 6 V typically 1 V p p If the signal exceeds this range it cannot be processed correctly in the decoder Because the input signal is ac coupled into the decoder its dc value needs to be restored This process is referred to as clamping the video This section explains the general process of clamping for the ADV7188 and shows the different ways that a user can configure the device s behavior The ADV7188 uses a combination of current sources and a digital processing block for clamping as shown in Figure 14 There are three analog processing channels like the one shown in Figure 14 inside the IC Although only one channel and only one ADC is needed for a CVBS signal two independent channels are needed for S video Y C type signals and three independent channels are needed to allow component YPrPb signals to be processed The clamping can be divided into two sections e Clamping before the ADC analog domain current sources e Clamping after the ADC digital domain digital processing block The ADCs can digitize an input signal only if it is within the 1 6 V input voltage range An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range FINE CURRENT SOURCES ANALOG Eu VIDEO INPUT The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog to digital conversion can occur Therefore
46. 7 6 These bits allow the user to influence the tracking speed of the chroma automatic gain control but have an effect only if the CAGC 1 0 bits are set to 10 automatic gain Table 46 CAGT 1 0 Function CAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive CMG 11 0 CG 11 0 Chroma Manual Gain Chroma Gain Address 0x2D 3 0 Address 0x2E 7 0 CMG 11 0 are dual function bits If these bits are written to a desired manual chroma gain can be programmed This gain becomes active if the CAGC 1 0 mode is switched to manual fixed gain Refer to Equation 4 to calculate a desired gain If read back these bits return the current gain value Depending on the setting in the CAGC 1 0 bits this is either e Chroma manual gain value CAGC 1 0 set to chroma manual gain mode e Chroma automatic gain value CAGC 1 0 set to any of the automatic modes Table 47 CG 11 0 CMG 11 0 Function For example freezing the automatic gain loop results in a readback value of 0x47A for the CMG 11 0 bits 1 Convert the readback value to decimal 0x47A 1146d 2 Apply Equation 4 to convert the readback value 1146 1024 1 12 CKE Color Kill Enable Address 0x2B 6 This bit allows the optional color kill function to be switched on or off For QAM based video standards PAL and NTSC and FM based systems SECAM the threshold for the color kill d
47. A follow on video compression stage may work more efficiently if the video is low pass filtered The ADV7188 has two responses for the shaping filter one that is used for good quality composite component and S video type sources and a second for nonstandard composite signals The YSH filter responses also include a set of notches for PAL and NTSC However it is recommended to use the comb filters for Y C separation e Digital Resampling Filter This block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system without requiring user intervention Figure 16 through Figure 19 show the responses of all luma filters Unless otherwise noted the filters are set in a typical wideband mode Y Shaping Filter For input signals in CVBS format the luma shaping filters play an essential role in removing the chroma component from a composite signal Y C separation must aim for best possible crosstalk reduction while retaining as much bandwidth especially on the luma component as possible High quality Y C separation can be achieved by using the internal comb filters of the ADV7188 Comb filtering however relies on the frequency relationship of the luma component multiples of the video line rate and the color subcarrier Fsc For good quality CVBS signals this relationship is known and
48. ADC1_SW ADC2 SW and ADC3 SW This is provided for applications with special requirements such as number combinations of signals that are not served by the preassigned input connections This is referred to as manual input muxing Figure 7 shows an overview of the two methods of controlling input muxing CONNECTING ANALOG SIGNALS TO ADV7188 RECOMMENDED INPUT MUXING SEE TABLE 8 AND TABLE 9 SET INSEL 3 0 AND SET INSEL 3 0 TO SDM SEL 1 0 CONFIGURE ADV7188 FOR REQUIRED MUXING TO DECODE VIDEO FORMAT CONFIGURATION CVBS 0000 YIC 0110 YPrPb 1001 SCART CVBS RGB 1111 SET SDM SEL 1 0 FOR S VIDEO COMPOSITE AUTODETECT USE MANUAL INPUT MUXING ADC SW MAN EN ADCO SW ADC1 SW ADC2 SW ADC3 SW 05478 007 Figure 7 Input Muxing Overview ADV7188 Recommended Input Muxing A maximum of 12 CVBS inputs can be connected and decoded by the ADV7188 meaning that the sources must be connected to adjacent pins on the IC as seen in Figure 5 This calls for a careful design of the PCB layout for example placing ground shielding between all signals routed through tracks that are physically close together SDM SEL 1 0 Y C and CVBS Autodetect Mode Select Address 0x69 1 0 The SDM SEL bits decide on input routing and whether INSEL 3 0 is used to govern input routing decisions The S video composite autodetection feature is enabled using SDM SEL 11 Table 8 SDM SEL 1 0 SDM SEL 1 0 Mode Analog
49. Address OxOE 5 This bit splits the register map at Register 0x40 O default The register map does not split and the user map is enabled 1 The register map splits and the user sub map is enabled USER MAP USER SUB MAP COMMON I2C SPACE ADDRESSES 0x00 TO 0x3F ADDRESS 0x0E BIT 5 0b ADDRESS 0x0E BIT 5 1b I2C SPACE ADDRESSES 0x40 TO 0x9C INTERRUPT AND VDP REGISTER SPACE Figure 48 Register Access User Map and User Sub Map 12C SPACE ADDRESSES 0x40 TO 0xFF NORMAL REGISTER SPACE 05478 048 ADV7188 PC SEQUENCER An PC sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more I C registers for example HSB 11 0 When such a parameter is changed using two or more I C write operations the parameter may hold an invalid value for the time between the first and last PCs In other words the top bits of the parameter may hold the new value while the remaining bits of the parameter still hold the previous value To avoid this problem the IC sequencer holds the already updated bits of the parameter in local memory All bits of the parameter are updated together after the last register write operation has completed The correct operation of the C sequencer relies on the following e AI TC registers for the parameter in question must be written to in order of ascending addresses For example for HSB 10 0 write to Address 0x34 first followe
50. D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 Gemstar Word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar Word1 3 0 0 0 User data words 8 EP EP 0 0 Gemstar Word2 7 4 0 0 User data words 9 EP EP 0 0 Gemstar Word2 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum The bold values represent Gemstar or CC specific values Rev A Page 72 of 112 Table 89 Gemstar 1x Data Full Byte Mode ADV7188 Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar Word1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum The bold val
51. DATA P330 VBI DATA P330 VBI DATA P330 VBI DATA P330 00000000 00 P17 N15 3 N15 2 N15 1 N15 0 N278 3 N278 2 N278 1 N278 0 113 71 VDP LINE 01B RW VBI DATA VBI DATA P18 VBI DATA P18 VBI DATA P18 VBI DATA P331 VBI DATA P331 VBI DATA P331 VBI DATA P331 00000000 00 P18 N16 3 N16 2 N16 1 N16 0 N279 3 N279 2 N279 1 N279 0 114 72 VDP LINE 01C RW VBI DATA VBI DATA P19 VBI DATA P19 VBI DATA P19 VBI DATA P332 VBI DATA P332 VBI DATA P332 VBI DATA 00000000 00 P19_N17 3 N17 2 N17 1 N17 0 N280 3 N280 2 N280 1 P332_N280 0 115 73 VDP LINE 01D RW VBI DATA VBI DATA P20 VBI DATA P20 VBI DATA P20 VBI DATA P333 VBI DATA P333 VBI DATA P333 VBI DATA 00000000 00 P20 N18 3 N18 2 N18 1 N18 0 N281 3 N281 2 N281 1 P333 N281 0 Rev A Page 99 of 112 ADV7188 Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 116 74 VDP LINE O1E RW VBI DATA VBI DATA P21 VBI DATA P21 VBI DATA P21 VBI DATA P334 VBI DATA P334 VBI DATA P334 VBI DATA 00000000 00 P21 N19 3 N19 2 N19 1 N19 0 N282 3 N282 2 N282 1 P334 N282 0 117 75 VDP LINE O1F RW VBI DATA
52. OP SEL1 INTRQ_OP_SEL O 0001x000 10 Configuration 0 SEL 1 SELO SEL 1 SELO NTRQ 66 42 InterruptStatus 1 R MV PS CS Q SD FR SD UNLOCK Q SD LOCK Q m s HNG_Q 67 43 InterruptClear1 W MV_PS_CS_CLR SD_FR_ SD_UNLOCK_CLR SD_LOCK_CLR x0000000 00 CHNG_CLR 68 44 InterruptMask1 RW MV_PS_CS_MSKB SD_FR_CHNG_ SD_UNLOCK_ SD LOCK MSKB x0000000 00 MSKB MSKB 69 45 Raw Status 2 R MPU STIM INTRO EVEN FIELD CCAPD 70 46 InterruptStatus2 R MPU STIM INTRO Q SD FIELD GEMD_Q CCAPD_Q CHNGD_Q 71 47 InterruptClear2 W MPU_STIM_ SD_FIELD_ GEMD_CLR CCAPD_CLR 0xx00000 00 INTRQ_CLR CHNGD_CLR 72 48 InterruptMask2 RW MPU_STIM_ SD_FIELD_ GEMD_MSKB CCAPD_MSKB 0xx00000 00 INTRQ_MSKB CHNGD_MSKB 73 49 Raw Status 3 R SCM LOCK SD H LOCK SD V LOCK SD OP 50Hz 74 4A InterruptStatus3 R PAL SW LK SCM LOCK SD AD CHNG OQ SD H LOCK SD V LOCK SD OP CHNG O E CHNG Q CHNG_Q CHNG_Q CHNG_Q 75 4B InterruptClear3 W PAL_SW_LK_ SCM_LOCK_ SD_AD_CHNG_ SD_H_LOCK_ SD_V_LOCK_ SD_OP_ xx000000 00 CHNG_CLR CHNG_CLR CLR CHNG_CLR CHNG_CLR CHNG_CLR 76 4C Interrupt Mask3 RW PAL SW LK SCM LOCK SD AD CHNG SD H LOCK SD V LOCK SD OP xx000000 00 CHNG MSKB CHNG MSKB MSKB CHNG MSKB CHNG MSKB CHNG MSKB 78 ME Interrupt Status 4 R VDP VITC Q VDP GS VPS VDP_ VDP_CCAPD_Q PDC UTC CGMS_WSS_ CHNG_Q CHNGD_Q 79 4F InterruptClear4 W VDP_VITC_CLR VDP_GS_VPS_ VDP_CGMS_WSS_ VDP CCAPD CLR 00x0xOxO 00 PDC UTC CHNGD CLR CHNG CLR 80 50 InterruptMask4 RW VD
53. SAT CR 7 SD SAT CR6 SD SAT CR 5 SD SAT CR4 SD SAT CR3 SD SAT CR2 SD SAT CR 1 SD SAT CR O 10000000 80 229 E5 NTSCV bit begin RW NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG 4 NVBEG 3 NVBEG 2 NVBEG 1 NVBEG O 00100101 25 230 E6 NTSCV bit end RW NVENDDELO NVENDDELE NVENDSIGN NVEND 4 NVEND 3 NVEND 2 NVEND 1 NVEND O 00000100 04 231 E7 NTSCF bit toggle RW NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 NFTOG 3 NFTOG 2 NFTOG 1 NFTOG 0 01100011 63 232 E8 PALV bit begin RW PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 PVBEG 3 PVBEG 2 PVBEG 1 PVBEG O 01100101 65 233 E9 PALV bit end RW PVENDDELO PVENDDELE PVENDSIGN PVEND 4 PVEND 3 PVEND 2 PVEND 1 PVEND O 0001010014 234 EA PALF bit toggle RW PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG4 PFTOG 3 PFTOG 2 PFTOG 1 PFTOG O 01100011 63 235 EB Vblank RW NVBIOLCM 1 NVBIOLCM O NVBIELCM 1 NVBIELCM O PVBIOLCM 1 PVBIOLCM O PVBIELCM 1 PVBIELCM O 01010101 55 Control 1 236 EC Vblank Control 2 RW NVBIOCCM 1 NVBIOCCM O NVBIECCM 1 NVBIECCM 0 PVBIOCCM 1 PVBIOCCM O PVBIECCM 1 PVBIECCM O 01010101 55 237 ED FB STATUS R FB STATUS 3 FB STATUS 2 FB STATUS 1 FB STATUS 0 237 ED FB_CONTROL1 Ww FB INV CVBS RGB SEL FB MODE 1 FB MODEO 00010000 10 238 EE FB CONTROL 2 RW FB CSC MAN MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA 00000000 00 VAL 6 VAL VALA VAL3 VAL 2 VAL 1 VAL O 239 EF FB_CONTROL 3 RW FB SP FB SP FB SP FB SP CNTR_ FB_EDGE_ FB_EDGE_ FB_EDGE_ 01001010 4A ADJU
54. Taken from luma path YPrPb Dependent on horizontal sync depth Taken from luma path Rev A Page 35 of 112 ADV7188 Luma Gain LAGC 2 0 Luma Automatic Gain Control Address 0x2C 6 4 The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path Analog Devices internal parameters can be used to customize the peak white gain control Contact an Analog Devices representative for more information Table 40 LAGC 2 0 Function LAGC 2 0 Description 000 Manual fixed gain use LMG 11 0 001 Reserved 010 default AGC peak white algorithm enabled blank level to sync tip 011 Reserved 100 AGC peak white algorithm disabled blank level to sync tip 101 Reserved 110 Reserved 111 Freeze gain LAGT 1 0 Luma Automatic Gain Timing Address 0x2F 7 6 The luma automatic gain timing bits allow the user to influence the tracking speed of the luminance automatic gain control Note that these bits only have an effect if the LAGC 2 0 bits are set to 010 or 100 automatic gain control modes If peak white AGC is enabled and active see the Status Register 1 7 0 Address 0x10 7 0 section the actual gain update speed is dictated by the peak white AGC loop and as a result the LAGT settings have no effect As soon as the part leaves peak white AGC LAGT becomes relevant The update speed for the peak white algorithm can be customized by using inter
55. This contains the checksum of the packet Table 84 lists the values within a generic data packet that are output by the ADV7188 in 10 bit format 05478 045 USER DATA FOUR OR EIGHT WORDS Figure 43 Gemstar and CC Embedded Data Packet Generic Table 84 Generic Data Output Packet Byte D 9 D 8 DI7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 2X line 3 0 0 0 SDID 5 EP EP 0 0 0 0 DC 1 DC 0 0 0 Data count DC 6 EP EP 0 0 word1 7 4 0 0 User data words 7 EP EP 0 0 word1 3 0 0 0 User data words 8 EP EP 0 0 word 7 4 0 0 User data words 9 EP EP 0 0 word2 3 0 0 0 User data words 10 EP EP 0 0 word3 7 4 0 0 User data words 11 EP EP 0 0 word3 3 0 0 0 User data words 12 EP EP 0 0 word4 7 4 0 0 User data words 13 EP EP 0 0 word4 3 0 0 0 User data words 14 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 0 0 Checksum Rev A Page 70 of 112 Table 85 Data Byte Allocation ADV7188 Raw Information Bytes User Data Words Gemstar 2x Retrieved from the Video Line GDECAD Including Padding Padding Bytes DC 1 0 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 Gemstar Bit Names DID The data identification value is 0x140 10 bi
56. Video Inputs 00 As per INSEL 3 0 As per INSEL 3 0 01 CVBS AIN11 10 Y C Y AIN1O C AIN12 11 S video composite CVBS AIN11 autodetection Y AIN11 C AIN12 Rev A Page 13 of 112 ADV7188 INSEL 3 0 Input Selection Address 0x00 3 0 The INSEL bits allow the user to select the input channel and format Depending on the PCB connections only a subset of the INSEL modes is valid INSEL 3 0 not only switches the analog input muxing but also configures the ADV7188 to process composite CVBS S video Y C or component YPbPr format signals The recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity Table 10 summarizes how the PCB layout should connect analog video signals to the ADV7188 It is strongly recommended that users connect any unused analog input pins to AGND to act as a shield Connect the AIN7 to AIN11 inputs to AGND when only six input channels are used This improves the quality of the sampling due to better isolation between the channels AIN12 is not controlled by INSEL 3 0 It can be routed to ADCO ADCI ADC2 only by manual muxing See Table 11 for details Table 9 Input Channel Switching Using INSEL 3 0 INSEL 3 0 Description Analog Input Pins Video Format 0000 default 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 111
57. Write 0x31 Vsync Field Control 1 Ox1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Position 1 0x00 0x35 Hsync Position 2 0x00 0x36 Hsync Position 3 0x7D 0x37 Polarity OxA1 OxE5 NTSV V bit begin 0x41 OxE6 NTSC V bit end 0x84 OxE7 NTSC F bit toggle 0x06 Rev A Page 47 of 112 ADV7188 OUTPUT VIDEO FIELD 1 2 OUTPUT VIDEO NVEND A4 0 0x4 BT 656 4 REG 0x04 BIT 7 1 NFTOG 4 0 0x3 FIELD 2 264 265 266 267 268 269 270 274 272 273 274 275 276eeel OUTPUT VIDEO HS OUTPUT vs OUTPUT FIELD OUTPUT OUTPUT VIDEO HS OUTPUT vs OUTPUT FIELD OUTPUT NVEND 4 0 0x4 BT 656 4 i REG 0x04 BIT 7 2 1 NFTOG 4 0 0x3 APPLIES IF NEMAVMODE 0 MUST BE MANUALLY SHIFTED IF NEWAVMODE 1 Figure 27 NTSC Default ITU R BT 656 the Polarities of HS VS and FIELD are Embedded in the Data FIELD 1 NVBEG 4 0 0x0 NVEND 4 0 0x3 NFTOG 4 0 0x5 FIELD 2 264 265 266 267 268 269 270 271 272 273 274 275 276 277eeel T i 2 OTTO Ua uU NVBEG 4 0 0x0 NVEND 4 0 0x3 gt tt o NFTOG 4 0 0x5 Figure 28 NTSC Typical VS FIELD Positions Using Register Writes in Table 62 Rev A Page 48 of 112 05478 027 05478 028 ADV7188 ADVANCE BEGIN OF DELAY BEGIN OF VSYNC BY NVBEG 4 0 VSYNC BY NVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO NVBEGDELO
58. at lt 4 0 100 default Kill at lt 9 5 Kill at lt 8 5 101 Kill at lt 15 Kill at lt 16 0 110 Kill at lt 32 Kill at lt 32 0 111 Reserved for Analog Devices internal use only do not select Rev A Page 38 of 112 ADV7188 CHROMA TRANSIENT IMPROVEMENT CTI The signal bandwidth allocated for chroma is typically much smaller than that of luminance With older devices this was a valid way to fit a color video signal into a given overall band width because the human eye is less sensitive to chrominance than to luminance The uneven bandwidth however may lead to visual artifacts during sharp color transitions At the border of two bars of color both components luma and chroma change at the same time see Figure 22 Due to the higher bandwidth the signal transition of the luma component is usually much sharper than that of the chroma component The color edge is not sharp and can be blurred in the worst case over several pixels LUMA SIGNAL WITHA TRANSITION ACCOMPANIED BY A CHROMA TRANSITION LUMA SIGNAL 7 Pad P a ORIGINAL SLOW CHROMA D o ee e e DEMODULATED CHROMA TRANSITION PRIOR TO CTI SIGNAL SHARPENED CHROMA TRANSITION AT THE OUTPUT OF CTI 05478 022 Figure 22 CTI Luma Chroma Transition To correct for such uneven bandwidths the CTI block examines the input video data It detects transitions of chroma and can be programmed to create steeper chroma edges
59. bits of Register 0xF4 O default The output drivers are enabled 1 The output drivers are three stated Three State LLC Drivers TRI LLC Address 0x1D 7 This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7188 to be three stated For more information on three state control refer to the Three State Output Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR S DR STR C and DR STR bits 0 default The LLC pin drivers work according to the DR STR C 1 0 setting pin enabled 1 The LLC pin drivers are three stated Timing Signals Output Enable TIM_OE Address 0x04 3 The TIM OE bit should be regarded as an addition to the TOD bit Setting it high forces the output drivers for HS VS and FIELD into the active that is driving state even if the TOD bit is set If the TIM_OE bit is set to low the HS VS and FIELD pins are three stated depending on the TOD bit This functionality is useful if the decoder is to be used only as a timing generator This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free run mode where for example a separate chip can output a company logo For more information on three state control refer to the Three State Output Drivers and the Three State LLC Drivers sections Individual drive strength controls are provided via the DR_STR_S DR_S
60. by 2 version of the LLC1 output clock for the pixel data output by the ADV7188 Nominally 13 5 MHz but varies according to video line length 29 XTAL Crystal Input This is the input pin for the 28 63636 MHz crystal or it can be overdriven by an external 3 3 V 28 63636 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 28 XTAL1 O This pin should be connected to the 28 63636 MHz crystal or left as a no connect if an external 3 3 V 28 63636 MHz clock oscillator source is used to clock the ADV7188 In crystal mode the crystal must be a fundamental crystal 36 PWRDN Logic 0 on this pin places the ADV7188 in a power down mode Refer to the I2C Register Maps section for more options on power down modes for the ADV7188 79 OE When set to Logic 0 OE enables the pixel output bus P19 to PO of the ADV7188 Logic 1 on the OE pin places P19 to PO HS VS and SFL into a high impedance state 37 ELPF The recommended external loop filter must be connected to this ELPF pin as shown in Figure 52 12 SFL O Subcarrier Frequency Lock This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices Inc digital video encoder 63 SOY SYNC on Y This input pin should only be used with the standard detection and identification function see the Standard Detection and Identification section This pin should be connected to the Y signal of a
61. component input for standard identification function 51 REFOUT O Internal Voltage Reference Output Refer to Figure 52 for a recommended capacitor network for this pin 52 CML O Common Mode Level The CML pin is a common mode level for the internal ADCs Refer to Figure 52 for a recommended capacitor network for this pin 48 49 CAPY1 ADC Capacitor Network Refer to Figure 52 for a recommended capacitor network for this pin CAPY2 54 55 CAPC1 ADC Capacitor Network Refer to Figure 52 for a recommended capacitor network for this pin CAPC2 Rev A Page 11 of 112 ADV7188 ANALOG FRONT END O AIN1 O AIN7 O AIN2 O AIN8 O AIN3 O AIN9 O AIN4 O AIN10 O AIN5 O AIN11 O AING ADC SW MAN EN O AIN12 Figure 6 Internal Pin Connections Rev A Page 12 of 112 ADCO SW 3 0 INTERNAL MAPPING FUNCTIONS 05478 057 ANALOG INPUT MUXING The ADV7188 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder Figure 6 outlines the overall structure of the input muxing provided in the ADV7188 As can be seen in Figure 6 the analog input muxes can be controlled in two ways e Bythe functional register INSEL Using INSEL 3 0 simplifies the setup of the muxes and minimizes crosstalk between channels by preassigning the input channels This is referred to as the recommended input muxing e ByanI C manual override ADC SW MAN EN ADCO SW
62. data Rev A Page 75 of 112 ADV7188 GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 The 16 bits of the GDECOL 15 0 form a collection of 16 indi vidual line decode enable signals See Table 94 and Table 95 To retrieve closed caption data services on NTSC Line 21 GDECOL 11 must be set To retrieve closed caption data services on PAL Line 22 GDECOL 14 must be set The default value of GDECOL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CC data from any line in the odd field The user should only enable Gemstar slicing on lines where VBI data is expected GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 The decoded data from Gemstar compatible transmissions or closed caption transmission is inserted into the horizontal blanking period of the respective line of video A potential problem can arise if the retrieved data bytes have the value 0x00 or OxFE In an ITU R BT 656 compatible data stream these values are reserved and used only to form a fixed preamble The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways e Insert all data straight into the data stream even the reserved values of 0x00 and OxFF if they occur This may violate the output data format specification ITU R BT 1364 e Split all data into nibbles and insert the half bytes over twice the number of cycles in a 4 bit
63. data in the event of video 000 1 line of video being lost These controls are independent of any other control 001 2 lines of video For instance brightness control is independent of picture clamping 010 5 lines of video although both controls affect the dc level of the signal 011 10 lines of video CON 7 0 Contrast Adjust Address 0x08 7 0 100 default 100 lines of video These bits allow the user to adjust the contrast of the picture 101 500 lines of vid i E ines of video 110 1000 lines of video Table 28 CON 7 0 Function 111 100 000 lines of video CON 7 0 Description 0x80 default Gain on luma channel 1 COL 2 0 Count Out of Lock Address 0x51 5 3 0x00 Gain on luma channel 0 COL 2 0 determines the number of consecutive lines the system OxFF Gain on luma channel 2 must be in the out of lock condition before reporting an unlocked state in Status Register 0 1 0 It counts the value in lines of video Table 26 COL 2 0 Function SD SAT CB 7 0 SD Saturation Cb Channel Address OxE3 7 0 These bits allow the user to control only the gain of the Cb COL 2 0 Description channel The user can adjust the saturation of the picture 000 1 line of video g 001 2 lines of video Table 29 SD_SAT_CB 7 0 Function 010 5 lines of video SD_SAT_CB 7 0 Description 011 10 lines of video 0x80 default Gain on Cb channel 1 100 default 100 lines of video 0x00 Gain on Cb channel 0 101 500
64. electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features A patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD A Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev A Page 9 of 112 ADV7188 a aaeFy o Elf N du gertseBs nasos228052z ilorcr amp amp amp hk a arrcooxrrocaxdx 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 o vs 1 60 AINS Hs 2 Ns 59 AIN11 DGND 3 58 AIN4 DVDDIO 4 57 AIN10 P15 5 56 AGND P14 6 55 CAPC2 P13 7 ADV7188 54 CAPC1 P12 s 53 AGND TOP VIEW DGND 9 Not to Scale 52 CML DVDD 10 51 REFOUT INT 1 50 AVDD SFL 12 49 CAPY2 TEST2 13 48 CAPY1 DGND 14 47 AGND DVDDIO 15 46 AIN3 TESTS 16 45 AIN9 p11 17 44 AIN2 P10 18 43 AIN8 P9 19 42 AIN1 ps 20 41 AIN7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 aterros g UIIELas E mag Figure 5 80 Lead LQFP Pin Configuration Table 7 Pin Function Descriptions Pin No Mnemonic Type Description 3 9 14 31 71 DGND G Digital Ground 39 47 53 56 AGND G Analog Ground 4 15 DVDDIO P Digital I O Supply Voltage 3 3 V 10 30 72 DVDD P Digital Core Supply Voltage 1 8 V 50 AVDD P Analog
65. format 0 default The data is split into half bytes and inserted 1 The data is output straight in 8 bit format Letterbox Detection Incoming video signals may conform to different aspect ratios 16 9 wide screen or 4 3 standard For certain transmissions in the wide screen format a digital sequence WSS is transmitted with the video signal If a WSS sequence is provided the aspect ratio of the video can be derived from the digitally decoded bits that WSS contains In the absence of a WSS sequence letterbox detection can be used to find wide screen signals The detection algorithm examines the active video content of lines at the start and end of a field If black lines are detected this may indicate that the currently shown picture is in wide screen format The active video content luminance magnitude over a line of video is summed together At the end of a line this accumulated value is compared with a threshold and a decision is made as to whether a particular line is black The threshold value needed may depend on the type of input signal some control is provided via LB_TH 4 0 Detection at the Start of a Field The ADV7188 expects a section of at least six consecutive black lines of video at the top of a field Once those lines are detected Register LB_LCT 7 0 is updated Register LB_LCT 7 0 reports the number of black lines that were actually found By default the ADV7188 starts looking for those black line
66. lines to three lines alalolo RD O Adapts five lines to four lines 0x39 PAL Comb Control YCMP 2 0 Luma comb mode PAL Adaptive 5 line 3 tap luma comb Use low pass notch Fixed luma comb three lines Top lines of memory Fixed luma comb five lines All lines of memory o o Hm 2 o 2 o o Fixed luma comb three lines Bottom lines of memory CCMP 2 0 Chroma comb mode PAL Adaptive 3 line for CTAPSP 01 Adaptive 4 line for CTAPSP 10 Adaptive 5 line for CTAPSP 11 Disable chroma comb Fixed 2 line for CTAPSP 01 Fixed 3 line for CTAPSP 10 Fixed 4 line for CTAPSP 11 Top lines of memory Fixed 3 line for CTAPSP 01 Fixed 4 line for CTAPSP 10 Fixed 5 line for CTAPSP 11 All lines of memory Fixed 2 line for CTAPSP 01 Fixed 3 line for CTAPSP 10 Fixed 4 line for CTAPSP 11 Bottom lines of memory CTAPSP 1 0 Chroma comb taps PAL Not used Adapts five lines to two lines two taps Adapts five lines to three lines three taps Adapts five lines to four lines four taps 0x3A ADC Control PWRDN ADC 3 This bit enables power down of ADC3 ADC3 normal operation Power down ADC3 PWRDN ADC 2 This bit enables power down of ADC2 ADC2 normal operation Power down ADC2 PWRDN_ADC_1 This bit enables power down of ADC1 ADC1 normal operation Power do
67. outputs Figure 44 and Figure 45 show IF filter compensation for NTSC and PAL The options for this feature are as follows e Bypass mode default e NTSC consists of three filter characteristics e PAL consists of three filter characteristics See Table 105 for programming details ADV7188 AMPLITUDE dB 05478 046 FREQUENCY MHz Figure 44 NTSC IF Compensation Filter Responses AMPLITUDE dB 05478 047 FREQUENCY MHz Figure 45 PAL IF Compensation Filter Responses PC Interrupt System The ADV7188 has a comprehensive interrupt register set This map is located in the user sub map See Table 107 for details of the interrupt register map Figure 48 describes how to access this map Rev A Page 77 of 112 ADV7188 Interrupt Request Output Operation When an interrupt event occurs the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL 1 0 INTRQ DUR SEL 1 0 Interrupt Duration Select Address 0x40 7 6 User Sub Map Table 98 INTRQ DUR SEL 1 0 Function INTRQ OP SEL 1 0 Interrupt Duration Select Address 0x40 1 0 User Sub Map Table 99 INTRQ OP SEL 1 0 Function INTRQ OP SEL 1 0 Description 00 default Open drain 01 Driven low when active 10 Driven high when active 11 Reserved INTRO DUR SEL 1 0 Description 00 default 3 XTAL periods 01 15 XTAL periods 10 63 XTAL periods 11 A
68. polarity of LLC 0 Invert polarity Sets the polarity of LLC on both LLC1 1 Normal polarity as per the timing and LLC2 diagrams Figure 2 to Figure 4 Reserved 010 Set to 0 PF Sets the FIELD polarity 0 Active high 1 Active low Reserved 0 Set to 0 PVS Sets the VS polarity 0 Active high 1 Active low Reserved Set to 0 PHS Sets the HS polarity Active high Active low 0x38 NTSC Comb Control YCMN 2 0 Luma comb mode NTSC 0 0 0 Adaptive 3 line 3 tap luma 1 0 0 Use low pass notch 110 1 Fixed luma comb two lines Top lines of memory 1 1 0 Fixed luma comb three lines All lines of memory 1 1 1 Fixed luma comb two lines Bottom lines of memory Rev A Page 90 of 112 ADV7188 Address Register Bit Description Comments Notes CCMN 2 0 Chroma comb mode NTSC Adaptive 3 line for CTAPSN 01 Adaptive 4 line for CTAPSN 10 Adaptive 5 line for CTAPSN 11 Disable chroma comb Fixed 2 line for CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Top lines of memory Fixed 3 line for CTAPSN 01 Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 All lines of memory Fixed 2 line for CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Bottom lines of memory CTAPSN 1 0 Chroma comb taps NTSC Not used Adapts three lines to two lines Adapts five
69. register to signify that the CC data has been read and the VDP CC can be updated at the next occurrence of CC 7 BacktoStep 2 Interrupt Mask Register Details The following bits set the interrupt mask on the signal from the VDP VBI data slicer VDP CCAPD MSKB Address 0x50 0 User Sub Map O default Disables interrupt on VDP CCAPD Q signal 1 Enables interrupt on VDP CCAPD Q signal VDP CGMS WSS CHNGD MSKB Address 0x50 2 User Sub Map O default Disables interrupt on VDP CGMS WSS CHNGD Q signal 1 Enables interrupt on VDP CGMS WSS CHNGD Q signal VDP GS VPS PDC UTC CHNG MSKB Address 0x50 4 User Sub Map O default Disables interrupt on VDP GS VPS PDC UTC CHNG Q signal 1 Enables interrupt on VDP GS VPS PDC UTC CHNG Q signal VDP VITC MSKB Address 0x50 6 User Sub Map 0 default Disables interrupt on VDP_VITC_Q signal 1 Enables interrupt on VDP_VITC_Q signal Interrupt Status Register Details The following read only bits contain data detection information from the VDP module since the status bit was last cleared or unmasked VDP CCAPD Q Address Ox4E 0 User Sub Map 0 default Closed caption data was not detected 1 Closed caption data was detected VDP CGMS WSS CHNGD OQ Address Ox4E 2 User Sub Map 0 default CGMS or WSS data was not detected 1 CGM or WSS data was detected VDP GS VPS PDC UTC CHNG Q Address 0x4E 4 User Sub Map
70. replaced by OxFE 11 Reserved The ancillary data packet sequence is explained in Table 71 and Table 72 The nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is enabled This format complies with ITU R BT 1364 Some definitions of the abbreviations used in Table 71 and Table 72 are as follows e EP Even parity for Bits B8 to B2 This means that Parity Bit EP is set so that an even number of 1s are in Bits B8 to B2 including the D8 parity bit e CS Checksum word The CS word is used to increase the integrity of the ancillary data packet from the DID SDID and dc through user data words UDWs It consists of 10 bits a 9 bit calculated value and B9 as the inverse of B8 Rev A Page 56 of 112 The checksum value of B8 to BO is equal to the nine LSBs of the sum of the nine LSBs of the DID SDID and dc as well as all UDWs in the packet Prior to the start of the checksum count cycle all checksum and carry bits are preset to 0 Any carry resulting from the checksum count cycle is ignored EP The MSB B9 is the inverse of EP This ensures that restricted Codes 0x00 and OxFF do not occur Line number 9 0 The number of the line that immediately precedes the ancillary data packet This number is as per the Table 71 Ancillary Data in Nibble Output Format ADV7188 numbering system of ITU R BT 470 ranging from 1 to 625 in a 625 line system and from 1 to 263 in a
71. the overall part is reset using the RESET pin Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7188 O default The chip is operational 1 The ADV7188 is in chip wide power down mode ADC Power Down Control The ADV7188 contains four 12 bit ADCs ADCO ADCI ADC2 and ADC3 If required it is possible to power down each ADC individually e In CVBS mode ADCI and ADC2 should be powered down to reduce power consumption e In S video mode ADC2 should be powered down to reduce power consumption PWRDN ADC 0 Address 0x3A 3 O default The ADC is in normal operation 1 ADOO is powered down PWRDN ADC 1 Address 0x3A 2 O default The ADC is in normal operation 1 ADCI is powered down PWRDN ADC 2 Address 0x3A 1 0 default The ADC is in normal operation 1 ADC2 is powered down PWRDN ADC 3 Address 0x3A 0 0 default The ADC is in normal operation 1 ADC3 is powered down FB PWRDN Address 0x0F 1 To achieve a very low power down current it is necessary to prevent activity on toggling input pins from reaching circuitry where it could consume current FB PWRDN gates signals from the FB input pin O default The FB input is in normal operation 1 The FB input is in the power saving mode RESET CONTROL RES Chip Reset Address OxOF 7 Setting this bit which is equivalent to controlling the RESET pin on the ADV7188 issues a chip reset A
72. 0 1111 CVBS1 AIN1 B AIN4 or AIN7 R AIN5 or AIN8 G AIN6 or AIN9 CVBS2 AIN2 B AIN4 or AIN7 R AIN5 or AIN8 G AIN6 or AIN9 CVBS3 AIN3 B AIN4 or AIN7 R AIN5 or AIN8 G AIN6 or AIN9 CVBS4 AIN4 B AIN7 R AIN8 G AIN9 CVBS1 AIN5 B AIN4 R AIN5 G AIN6 CVBS1 AIN1 B AIN4 R AIN5 G AIN6 Y1 AIN1 C1 AIN4 Y2 AIN2 C2 AIN5 Y3 AIN3 C3 AIN6 Y1 AIN1 PB1 AIN4 PR1 AIN5 Y2 AIN2 PB2 AIN3 PR2 AIN6 CVBS7 AIN7 B AIN4 R AIN5 G AIN6 CVBS8 AIN8 B AIN4 R AIN5 G AIN6 CVBS9 AIN9 B AIN4 R AIN5 G AIN6 CVBS10 AIN10 B AIN4 or AIN7 R AIN5 or AIN8 G AIN6 or AIN9 CVBS11 AIN11 B AIN4 or AIN7 R AIN5 or AIN8 G AIN6 or AIN9 SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B Y C Y C Y C YPrPb YPrPb SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B SCART CVBS and R G B 1 Selectable via RGB IP SEL Rev A Page 14 of 112 Table 10 Input Channel Assignments ADV7188 Input Channel Pin Recommended Input Muxing Control INSEL 3 0 AIN7 41 CVBS7 SCART1 B AIN1 42 CVBS1 YC1 Y YPrPb1 Y SCART2 CVBS AIN8 43 CVBS8 SCART1 R AIN2 44 CVBS2 YC2 Y YPrPb2 Y AIN9 45 CVBS9 SCART1 G AIN3 46 CVBS3 YC3 Y YPrPb2 Pb A
73. 0 Bypasses DNR disables it 1 default Enables DNR on the luma data DNR TH 7 0 DNR NoiseThreshold Address 0x50 7 0 The DNRI block is positioned before the luma peaking block The DNR TH 7 0 value is an unsigned 8 bit number that determines the maximum edge that is interpreted as noise and therefore blanked from the luma data Programming a large value into DNR TH 7 0 causes the DNR block to interpret even large transients as noise and remove them As a result the effect on the video data is more visible Programming a small value causes only small transients to be seen as noise and to be removed The recommended DNR TH 7 0 setting for A V inputs is 0x04 and the recommended DNR TH 7 0 setting for tuner inputs is OxOA The default value for DNR TH 7 0 is 0x08 indicating the threshold for maximum luma edges to be interpreted as noise PEAKING GAIN 7 0 Luma Peaking Gain Address OxFB 7 0 This filter can be manually enabled The user can boost or attenuate the mid region of the Y spectrum around 3 MHz The peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 MHz The default value 0x40 in this register passes through the luma data unaltered 0 dB response A lower value attenuates the signal and a higher value amplifies it A plot of the filter responses is shown in Figure 24 15 PEAKING GAIN USING BP FILTER
74. 0 default Teletext ITU R Reserved BT 653 625 50 A 01 Teletext ITU R Teletext ITU R BT 653 BT 653 625 50 B 525 60 B WST 10 Teletext ITU R Teletext ITU R BT 653 BT 653 625 50 C 525 60 C or EIA516 NABTS 11 Teletext ITU R Teletext ITU R BT 653 BT 653 625 50 D 525 60 D VDP Ancillary Data Output Reading the data back via I C may not be feasible for VBI data standards with high data rates for example teletext An alternative is to place the sliced data in a packet within the line blanking of the digital output CCIR 656 stream This is available for all standards sliced by the VDP module When data is sliced on a given line the corresponding ancillary data packet is placed immediately after the next EAV code that occurs at the output that is data sliced from multiple lines is not buffered up and then emitted in a burst Note that the line on which the packet is placed differs from the line on which the data was sliced due to the vertical delay through the comb filters The user can enable or disable the insertion of VDP decoded results into the 656 ancillary streams by using the ADF_ENABLE bit ADF_ENABLE Enable Ancillary Data Output Through 656 Stream Address 0x62 7 User Sub Map O default Disables insertion of VBI decoded data into an ancillary 656 stream 1 Enables insertion of VBI decoded data into an ancillary 656 stream The user can select the data identification word DID and the seconda
75. 0 0 0 0 0 Automatically uses wide notch Decoder selects optimum Y shaping Control when in CVBS only mode These bits allow filter for poor quality sources and filter depending on CVBS quality the user to select a wide range of low pass wideband filter with comb for and notch filters good quality input 0 0 0 0 1 Automatically uses narrow notch filter for poor quality sources and wideband filter with comb for good quality input SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 CCIR 601 PAL NN 1 PALNN 2 PAL NN 3 PAL WN 1 PAL WN 2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN 1 NTSC WN 2 NTSC WN 3 a fo ofofo o oa ojo oto ofa ot 2 S lololololololo olololoiololo 2 2 2 2 2 2 2 olololololololo 2 25 2 2 2 2 2 olololololo 2 2 2 2lolololo i2 2 2 l olololoi2 2i 2 iolololioi i ii olo s alololal alolo l l alolol a lolol a alolo l a l slolol alolola Oo 2 o 2 o 2 o 25 OoO 2 O 2 OoO 2 OoO 2 O 2 OoO 25 oO 2 Oo 5 Oo 25 OoO Oo Reserved If one of these modes is selected the decoder does not change filter modes A fixed filter response the one selected is used regardless of video quality Rev A Page 87 of 112 ADV7188
76. 10 Fixed 5 line chroma comb for CTAPSN 11 111 Fixed chroma comb bottom lines of line memory Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 YCMN 2 0 Luma Comb Mode NTSC Address 0x38 2 0 Table 53 YCMN 2 0 Function YCMN 2 0 Description Configuration 000 default Adaptive comb mode Adaptive 3 line three taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 2 line two taps luma comb 110 Fixed luma comb all lines of line memory Fixed 3 line three taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 2 line two taps luma comb Rev A Page 41 of 112 ADV7188 PAL Comb Filter Settings Used for PAL B G H I D PAL M PAL Combinational N PAL 60 and NTSC 4 43 CVBS inputs PSFSEL 1 0 Split Filter Selection PAL Address 0x19 1 0 PFSEL 1 0 selects how much of the overall signal bandwidth is fed to the combs A wide bandwidth split filter eliminates dot crawl but shows imperfections on diagonal lines The opposite is true for a narrow bandwidth split filter Table 54 PSFSEL 1 0 Function CCMP 2 0 Chroma Comb Mode PAL Address 0x39 5 3 Table 56 CCMP 2 0 Function PSFSEL 1 0 Description 00 Narrow 01 default Medium 10 Wide 11 Widest CTAPSP 1 0 Chroma Comb Ta
77. 17 7 5 The C shaping filter mode bits allow the user to select from a range of low pass filters for the chrominance signal Table 38 CSFM 2 0 Function CSFM 2 0 Description 000 default 1 5 MHz bandwidth filter 001 2 17 MHz bandwidth filter 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband mode Rev A Page 34 of 112 GAIN OPERATION The gain control within the ADV7188 is done on a purely digital basis The input ADCs support a 12 bit range mapped into a 1 6 V analog voltage range Gain correction takes place after the digitization in the form of a digital multiplier This architecture is advantageous because unlike the commonly used programmable gain amplifier PGA placed in front of the ADCs the gain is completely independent of supply temperature and process variations As shown in Figure 21 the ADV7188 can decode a video signal as long as it fits into the ADC window The two components of decoding a video signal are the amplitude of the input signal and the dc level on which it resides The dc level is set by the clamping circuitry see the Clamp Operation section If the amplitude of the analog video signal is too high clipping can occur resulting in visual artifacts The analog input range of the ADC together with the clamp level determines the maximum supported amplitude of the video signal ADV7188 The minimum supported amplitude of the input video is determined by the abi
78. 188 VBI_DATA_Px_Ny PAL 625 50 NTSC 525 60 0000 Disable VDP Disable VDP 0001 Teletext system identified by VDP_TTXT_TYPE Teletext system identified by VDP_TTXT_TYPE 0010 VPS ETSI EN 300 231 V 1 3 1 Reserved 0011 VITC VITC 0100 WSS ITU R BT 1119 1 ETSI EN 300294 CGMS EIA J CPR 1204 IEC 61880 0101 Reserved Gemstar 1x 0110 Reserved Gemstar 2x 0111 CC CC EIA 608 1000 to 1111 Reserved Reserved Table 68 VBI Data Standards to be Decoded on Line Px PAL or Line Ny NTSC Address Signal Name Register Location Dec Hex VBI DATA P6 N23 VDP LINE OOF 7 4 101 0x65 VBI DATA P7 N24 VDP LINE 010 7 4 102 0x66 VBI DATA P8 N25 VDP LINE 011 7 4 103 0x67 VBI DATA P9 VDP LINE 012 7 4 104 0x68 VBI DATA P10 VDP LINE 013 7 4 105 0x69 VBI DATA P11 VDP LINE 014 7 4 106 0x6A VBI DATA P12 N10 VDP LINE 015 7 4 107 Ox6B VBI DATA P13 N11 VDP LINE 016 7 4 108 Ox6C VBI DATA P14 N12 VDP LINE 017 7 4 109 0x6D VBI_DATA_P15_N13 VDP_LINE_018 7 4 110 Ox6E VBI_DATA_P16_N14 VDP_LINE_019 7 4 111 Ox6F VBI_DATA_P17_N15 VDP_LINE_01A 7 4 112 0x70 VBI_DATA_P18_N16 VDP_LINE_01B 7 4 113 0x71 VBI_DATA_P19_N17 VDP_LINE_01C 7 4 114 0x72 VBI DATA P20 N18 VDP LINE 01D 7 4 115 0x73 VBI DATA P21 N19 VDP LINE 01E 7 4 116 0x74 VBI DATA P22 N20 VDP LINE 01F 7 4 117 0x75 VBI DATA P23 N21 VDP LINE 020 7 4 118 0x76 VBI DATA P24 N22 VDP LINE 021 7 4 119 0x77 VBI DATA P318 VDP LINE OOE 3 0 100 0x64 VBI DATA P319 N28
79. 25 compatible data on any lines that the decoder checks for Lines 10 to 25 in even fields Gemstar compatible data 0x4A Gemstar Control 3 GDECOL 15 8 See the Comments column 0 0 0 0 0 0 0 0 GDECOLT 15 0 The 16 individual LSB Line 10 MSB Line 25 enable bits that select the lines of Default do not check for Gemstar video odd field Lines 10 to 25 ible d li Ox4B Gemstar Control 4 GDECOL 7 0 See the Comments column ojololololololo compatible data on any lines 7 0 that the decoder checks for Lines 10 to 25 in odd fields Gemstar compatible data 0x4C Gemstar Control 5 GDECAD This bit controls the manner in 0 Split data into half byte To avoid 0x00 and OxFF codes which decoded Gemstar data is inserted into 1 Output in straight 8 bit format the horizontal blanking period Reserved X x x x 0 0 0O Undefined Ox4D CTI DNR Control 1 CTI EN CTI enable 0 Disable CTI 1 Enable CTI CTI AB EN CTI alpha blend enable This bit 0 Disable CTI alpha blender enables the mixing of the transient improved 1 Enable CTI alpha blender chroma with the original signal CTI_AB 1 0 CTI alpha blend control These 0 0 Sharpest mixing bits control the behavior of the alpha blend 0 1 Sharp mixing circuitry 1 0 Smooth mixing 1 1 Smoothest mixing Reserved 0 Set to default DNR_EN This bit enables or bypasses the 0 Bypass the DNR block DNR block 1 Enable the DNR block Reserved 1 1 Set to default Ox4E CTI DNR Control 2 CTI C TH 7 0
80. 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 334 PAL 282 NTSC 1 for these bits to be effective VBI_DATA_P21_N19 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 21 PAL 19 NTSC 0x75 VDP LINE 01F VBI DATA P335 N283 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 335 PAL 283 NTSC 1 for these bits to be effective VBI DATA P22 N20 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 22 PAL 20 NTSC 0x76 VDP_LINE_020 VBI_DATA_P336_N284 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 336 PAL 284 NTSC 1 for these bits to be effective VBI DATA P23 N21 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 23 PAL 21 NTSC 0x77 VDP LINE 021 VBI DATA P337 N285 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 337 PAL 285 NTSC 1 for these bits to be effective VBI_DATA_P24_N22 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 24 PAL 22 NTSC 0x78 VDP STATUS CC AVL Closed captioning not detected CC CLEAR resets the CC AVL Read Only Closed captioning detected bit CC EVEN FIELD Closed captioning decoded from odd field Closed captioning decoded from even field CGMS WSS AVL 0 CGMS WSS not detected CGMS WSS CLEAR resets the 1 CGMS WSS detected CGMS_WSS_AVL bit Reserved 0 GS_PDC_VPS_UTC_AVL 0 VPS not detected GS_PDC_VPS_UTC_CLEAR 1 VPS detected resets th
81. 46 Interrupt Status 2 CCAPD Q Closed captioning not detected in These bits can be cleared or Read Only the input video signal masked by Registers 0x47 and Closed caption data detected in the 0x48 respectively video input signal GEMD Q Gemstar data not detected in the Note that interrupt in input video signal Register 0x46 for the CC Gemstar data detected in the input Gemstar COMS ane s data video signal is using the Mode 1 data slicer Reserved x x SD_FIELD_CHNGD_Q 0 SD signal has not changed the field from odd to even or vice versa 1 SD signal has changed the field from odd to even or vice versa Reserved x Not used Reserved x Not used MPU_STIM_INTRQ_Q 0 Manual interrupt not set 1 Manual interrupt set 0x47 Interrupt Clear 2 CCAPD_CLR Does not clear Note that interrupt in Write Only Clears CCAPD Q bit Register 0x46 for the CC Gemstar CGMS and WSS data GEMD CLR Does not clear is using the Mode 1 data Clears GEMD_Q bit slicer Reserved 0 0 SD FIELD CHNGD CLR 0 Does not Clear 1 Clears SD_FIELD_CHNGD_Q bit Reserved x Not used Reserved x Not used MPU_STIM_INTRQ_CLR 0 Does not clear 1 Clears MPU_STIM_INTRQ_Q bit 0x48 Interrupt Mask 2 CCAPD_MSKB Masks CCAPD_Q bit Note that interrupt in Read Write Unmasks CCAPD Q bit Register 0x46 for the CC Gemstar CGMS and WSS data GEMD MSKB Masks GEMD_Q bit is using the Mode 1 data Unmasks GEMD_Q bit slicer CGMS_MSKB 0 0 Masks CGMS CHNGD O bit
82. 525 line system Note that the line on which the packet is output differs from the line on which the VBI data was sliced due to the vertical delay through the comb filters Data Count The data count specifies the number of UDWs in the ancillary stream for the standard The total number of user data words is four times the data count Padding words can be introduced so that the total number of UDWs is divisible by 4 Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 Ancillary data preamble 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 0 I2C DID6 2 4 0 0 0 DID data identification word 4 EP EP I2C SDID7 2 5 0 0 0 SDID secondary data identification word 5 EP EP 0 DC 4 0 0 0 Data count 6 EP EP padding 1 0 VBI DATA STD 3 0 0 0 IDO User Data Word 1 7 EP EP 0 Line number 9 5 0 0 ID1 User Data Word 2 8 EP EP Even Field Line number 4 0 0 0 ID2 User Data Word 3 9 EP EP 0 0 0 0 VDP TTXT TYPE O 0 ID3 User Data Word 4 1 0 10 EP EP 0 0 VBI WORD 1 7 4 0 0 User Data Word 5 11 EP EP 0 0 VBI WORD 1 3 0 0 0 User Data Word 6 12 EP EP 0 0 VBI WORD 2 7 4 0 0 User Data Word 7 13 EP EP 0 0 VBI WORD 2 3 0 0 0 User Data Word 8 14 EP EP 0 0 VBI WORD 3 7 4 0 0 User Data Word 9 Pad 0x200 These padding words may not be present depending on ancillary dat
83. 6 VDP LINE OOF 3 0 101 0x65 VBI DATA P320 N287 VDP LINE 010 3 0 102 0x66 VBI DATA P321 N288 VDP LINE 011 3 0 103 0x67 VBI DATA P322 VDP LINE 012 3 0 104 0x68 VBI DATA P323 VDP LINE 013 3 0 105 0x69 VBI DATA P324 N272 VDP LINE 014 3 0 106 0x6A VBI DATA P325 N273 VDP LINE 015 3 0 107 Ox6B VBI DATA P326 N274 VDP LINE 016 3 0 108 Ox6C VBI DATA P327 N275 VDP LINE 017 3 0 109 0x6D VBI_DATA_P328_N276 VDP_LINE_018 3 0 110 Ox6E VBI_DATA_P329_N277 VDP_LINE_019 3 0 111 Ox6F VBI_DATA_P330_N278 VDP_LINE_01A 3 0 112 0x70 VBI_DATA_P331_N279 VDP_LINE_01B 3 0 113 0x71 VBI_DATA_P332_N280 VDP_LINE_01C 3 0 114 0x72 VBI_DATA_P333_N281 VDP_LINE_01D 3 0 115 0x73 VBI_DATA_P334_N282 VDP_LINE_01E 3 0 116 0x74 VBI_DATA_P335_N283 VDP_LINE_01F 3 0 117 0x75 VBI_DATA_P336_N284 VDP_LINE_020 3 0 118 0x76 VBI_DATA_P337_N285 VDP_LINE_021 3 0 119 0x77 Rev A Page 55 of 112 ADV7188 VDP_TTXT_TYPE_MAN_ENABLE Enable Manual Selection of Teletext Type Address 0x60 2 User Sub Map O default Manual programming of the teletext type is disabled 1 Manual programming of the teletext type is enabled VDP TTXT TYPE MAN 1 0 Specify the Teletext Type Address 0x60 1 0 User Sub Map These bits specify the teletext type to be decoded These bits are functional only ifVDP TTXT TYPE MAN ENABLE is set to 1 Table 69 VDP TTXT TYPE MAN Function VDP TTXT Description TYPE MAN 1 0 625 50 PAL 525 60 NTSC 0
84. 8 4 0 FREQUENCY e The WYSFM 4 0 bits allow the user to select a wideband RES Y shaping filter manually for good quality video signals for COMBINED Y ANTIALIAS CCIR MODE SHAPING FILTER example CVBS with a stable time base a luma component of o e YPrPb or a luma component of Y C The WYSEM bits are active only if the WYSFMOVR bit is set to 1 See the general discussion 20 of the shaping filter settings in the Y Shaping Filter section Table 37 WYSFM 4 0 Function g p WYSFM 4 0 Description E Zen 00000 Reserved do not use d 00001 Reserved do not use E 80 00010 SVHS 1 00011 SVHS 2 100 00100 SVHS 3 E 00101 SVHS 4 120 0 2 4 6 8 10 12 00110 SVHS 5 FREQUENCY MHz 00111 SVHS 6 Figure 17 Y SVHS 18 Extra Wideband Filter CCIR 601 Compliant 01000 SVHS 7 01001 SVHS 8 COMBINED VAN Eira FILTERS 01010 SVHS 9 01011 SVHS 10 01100 SVHS 11 01101 SVHS 12 01110 SVHS 13 e 01111 SVHS 14 a 10000 SVHS 15 5 10001 SVHS 16 z 10010 SVHS 17 10011 default SVHS 18 CCIR 601 10100 to 11111 Reserved do not use E Figure 16 shows the filter responses of the SVHS 1 narrowest FREQUENCY MHz to SVHS 18 widest shaping filter settings Figure 18 shows the Figure 18 Y PAL Notch Filter Responses PAL notch filter responses and Figure 19 shows the NTSC notch filter responses Rev A Page 33 of 112 ADV7188 COMBINED Y ANTIALIAS NTSC NOTCH FILTERS Y RESAMPLE AMPLITUDE dB
85. A 1 0 DATA 0 147 93 VDP VITC R VITC DATA 27 VITC DATA 26 VITC DATA 2 5 VITC DATA 24 VITC DATA 2 3 VITC DATA 2 2 VITC DATA 2 1 VITC DATA 2 0 DATA 1 148 94 VDP VITC R VITC DATA 37 VITC DATA 36 VITC DATA 3 5 VITC DATA 34 VITC DATA 3 3 VITC DATA 3 2 VITC DATA 3 1 VITC DATA 3 0 DATA 2 149 95 VDP VITC R VITC DATA 47 VITC DATA 46 VITC DATA 45 VITC DATA 44 VITC DATA 4 3 VITC DATA 4 2 VITC DATA 4 1 VITC DATA 4 0 DATA 3 150 96 VDP VITC R VITC DATA 5 7 VITC DATA 5 6 VITC DATA 5 5 VITC DATA 54 VITC DATA 5 3 VITC DATA 5 2 VITC DATA 5 1 VITC DATA 5 0 DATA 4 151 97 VDP VITC R VITC DATA 6 7 VITC DATA 6 6 VITC DATA 6 5 VITC DATA 64 VITC DATA 6 3 VITC DATA 6 2 VITC DATA 6 1 VITC DATA 6 0 DATA 5 152 98 VDP VITC R VITC DATA 7 7 VITC DATA 7 6 VITC DATA 7 5 VITC DATA 74 I VITC DATA 7 3 VITC DATA 7 2 VITC DATA 7 1 VITC DATA 7 0 D 153 99 VDP_VITC_ R VITC DATA 87 VITC DATA 86 VITC DATA 8 5 VITC DATA 84 VITC DATA 8 3 VITC DATA 8 2 VITC DATA 8 1 VITC DATA 8 0 DATA_7 154 9A VDP_VITC_ R VITC DATA 97 VITC DATA 9 6 VITC DATA 9 5 VITC DATA 94 VITC DATA 9 3 VITC DATA 9 2 VITC DATA 9 1 VITC DATA 9 0 D 155 9B VDP VITC R VITC CRC7 VITC_CRC 6 VITC_CRC 5 VITC_CRC 4 VITC_CRC 3 VITC_CRC 2 VITC_CRC 1 VITC CRCO CALC CRC 156 9C VDP RW I2C GS VPS I2C GS VPS GS VPS PDC WSS CGMS 00110000 30 OUTPUT_SEL PDC_UTC 1 PDC UTCO UTC CB CB CHANGE CHANGE
86. A 1 LTA O 01011000 58 43 2B Misc Gain Control RW CKE PW UPD 11100001 E1 44 2C AGC Mode Control RW LAGC 2 LAGC 1 LAGC O CAGC 1 CAGC O 10101110 AE 45 2D Chroma Gain W CAGT 1 CAGT O CMG 11 CMG 10 CMG 9 CMG 8 11110100 FA Control 1 46 2E Chroma Gain W CMG 7 CMG 6 CMG 5 CMG 4 CMG 3 CMG 2 CMG 1 CMG 0 00000000 00 Control 2 47 2F Luma Gain Control 1 W LAGT 1 LAGT O LMG 11 LMG 10 LMG 9 LMG 8 1111xxxx FO 48 30 Luma Gain Control 2 W LMG 7 LMG 6 LMG 5 LMGA LMG 3 LMG 2 LMG 1 LMG 0 XXXXXXXX 00 49 31 Vsync Field RW NEWAVMODE HVSTIM 00010010 12 Control 1 50 32 VsyncField Control 2 RW VSBHO VSBHE 01000001 41 51 33 VsyncField Control 3 RW VSEHO VSEHE 1000010084 52 34 Hsync Position RW HSB 10 HSB 9 HSB 8 HSE 10 HSE 9 HSE 8 00000000 00 Control 1 53 35 Hsync Position RW HSB 7 HSB 6 HSB 5 HSB 4 HSB 3 HSB 2 HSB 1 HSB O 0000001002 Control 2 54 36 Hsync Position RW HSE 7 HSE 6 HSE 5 HSE 4 HSE 3 HSE 2 HSE 1 HSE O 00000000 00 Control 3 55 37 Polarity RW PHS PVS PF PCLK 00000001 01 56 38 NTSC Comb Control RW CTAPSN 1 CTAPSN O CCMN 2 CCMN 1 CCMN O YCMN 2 YCMN 1 YCMN O 10000000 80 57 39 PALComb Control RW CTAPSP 1 CTAPSP 0 CCMP 2 CCMP 1 CCMP 0 YCMP 2 YCMP 1 YCMP 0 11000000 CO 58 3A ADC Control RW PDN ADCO PDN ADCI PDN ADC2 PDN ADC3 00010001 11 61 3D Manual Window RW CKILLTHR 2 CKILLTHR 1 CKILLTHR O 01000011 43 Control 65 41 Resample Control RW SFL_INV 00000001 01 72 48 Gemstar Control 1 RW
87. AL 24 000111100011110000011111 111110000011110001111000 Gemstar 1x NTSC 3 001 100 Gemstar 2x NTSC 11 1001 1011 101 101 1101 1001 CC NTSC and PAL 3 001 100 CGMS NTSC 1 0 0 Table 75 Total User Data Words for Different VBI Standards Framing Code VBI Data Number of VBI Standard ADF Mode UDWs Words Padding Words Total UDWs TTXT SYSTEM A PAL 00 nibble mode 6 74 0 84 01 10 byte mode 3 37 0 44 TTXT SYSTEM B PAL 00 nibble mode 6 84 2 96 01 10 byte mode 3 42 3 52 TTXT SYSTEM B NTSC 00 nibble mode 6 68 2 80 01 10 byte mode 3 34 3 44 TTXT SYSTEM C PAL and NTSC 00 nibble mode 6 66 0 76 01 10 byte mode 3 33 2 42 TTXT SYSTEM D PAL and NTSC 00 nibble mode 6 68 2 80 01 10 byte mode 3 34 3 44 VPS PAL 00 nibble mode 6 26 0 36 01 10 byte mode 3 13 0 20 VITC NTSC and PAL 00 nibble mode 6 18 0 28 01 10 byte mode 3 9 0 16 WSS PAL 00 nibble mode 6 4 2 16 01 10 byte mode 3 2 3 12 Gemstar 1x NTSC 00 nibble mode 6 4 2 16 01 10 byte mode 3 2 3 12 Gemstar 2x NTSC 00 nibble mode 6 8 2 20 01 10 byte mode 3 4 1 12 CC NTSC and PAL 00 nibble mode 6 4 2 16 01 10 byte mode 3 2 3 12 CGMS NTSC 00 nibble mode 6 6 0 16 01 10 byte mode 3 343 2 12 The first four UDWs are always the identification word Rev A Page 59 of 112 ADV7188 PC INTERFACE Dedicated IC readback registers are available for CC CGMS WSS Gemstar VPS PDC UTC
88. AL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant Table 44 BETACAM Levels ADV7188 PW UPD Peak White Update Address 0x2B 0 The peak white and average video algorithms determine the gain based on measurements taken from the active video The PW UPD bit determines the rate of gain change LAGC 2 0 must be set to the appropriate mode to enable the peak white or average video mode For more information refer to the LAGC 2 0 Luma Automatic Gain Control Address 0x2C 6 4 section 0 Updates the gain once per video line 1 default Updates the gain once per field Name BETACAM mV BETACAM Variant mV SMPTE mV MII mV Y Range Oto 714 including 7 596 pedestal Oto 714 O to 700 0 to 700 including 7 5 pedestal Prand Pb Ranges 467 to 467 505 to 505 350 to 350 324 to 324 Sync Depth 286 286 300 300 Rev A Page 37 of 112 ADV7188 Chroma Gain CAGC 1 0 Chroma Automatic Gain Control Address 0x2C 1 0 These two bits select the basic mode of operation for automatic gain control in the chroma path Table 45 CAGC 1 0 Function CAGC 1 0 Description 00 Manual fixed gain use CMG 11 0 01 Use luma gain for chroma 10 default Automatic gain based on color burst 11 Freeze chroma gain CAGT 1 0 Chroma Automatic Gain Timing Address 0x2D
89. ANALOG DEVICES Multiformat SDTV Video Decoder with Fast Switch Overlay Support ADV7188 FEATURES Multiformat video decoder supports NTSC J M 4 43 PAL B D G H I M N SECAM Integrates four 54 MHz Noise Shaped Video NSV 12 bit ADCs SCART fast blank support Clocked from a single 28 63636 MHz crystal Line locked clock compatible LLC Adaptive Digital Line Length Tracking ADLLT signal processing and enhanced FIFO management give mini TBC functionality 5 line adaptive comb filters Proprietary architecture for locking to weak noisy and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated automatic gain control AGC with adaptive peak white mode Macrovision copy protection detection Chroma transient improvement CTI Digital noise reduction DNR Multiple programmable analog input formats CVBS composite video Y C S video YPrPb component VESA MII SMPTE and BETACAM 12 analog video input channels Integrated antialiasing filters Programmable interrupt request output pin GENERAL DESCRIPTION The ADV7188 integrated video decoder automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC PAL and SECAM standards into 4 2 2 component video data compatible with 20 16 10 8 bit CCIR 601 CCIR 656 The advanced highly flexible digital output interface enables performance video decod
90. AUTO_EN 1 Force free run mode on and output blue screen DEF_VAL_AUTO_EN Default value 0 Disable free run mode When lock is lost free run mode can 1 Enable automatic free run mode be enabled to output stable timing blue screen clock and a set color DEF Y 5 0 Default value Y These bits hold 0 0 1 1 0 1 Y 7 0 DEF Y 5 0 0 0 Default Y value output in free run the Y default value mode 0xoD Default Value C DEF C 7 0 Default value C The Cr and Cb 0 1 1 1 1 1 0 0 Cr 7 0 DEF C 7 4 0 0 0 0 Default Cb Cr value output in free run default values are defined in these bits Cb 7 0 DEF C 3 0 O 0 0 0 mode Default values give blue screen output OxOE Analog Devices Reserved 0 0 0 0 0 Setas default Control SUB USR EN This bit enables the user to 0 Access user map See Figure 48 access the user sub map 1 Access user sub map Reserved 0 0 Set as default OxOF Power Management Reserved 0 Set to default FB_PWRDN 0 FB input operational 1 FB input in power saving mode PDBP Power down bit priority This bit selects 0 Chip power down controlled by pin This bit must be set to 1 for the PWRDN between the PWRDN bit and the PWRDN pin 1 Bit has priority pin disregarded bit to power down the part Reserved 0 0 Set to default PWRDN Power down This bit places the 0 System functional The PDBP bit must be set to 1 for the decoder in full power down mode 1 Powered down PWRDN bit to power down the part see PDBP OxOF Bit 2
91. B Masks PAL_SW_LK_CHNG_Q bit Unmasks PAL_SW_LK_CHNG_Q bit Reserved Not used Reserved Not used Ox4E Interrupt Status 4 VDP CCAPD OQ Closed captioning not detected These bits can be cleared by Read Only Closed captioning detected Register Ox4F and masked by Register 0x50 Reserved j Note that an interrupt in VDP_CGMS_WSS_CHNGD_Q See Register CGMS WSS data is not changed not Register Ox4E for the CC Ox9C Bit 4 of the user sub map to available Gemstar CGMS WSS VPS determine whether an interrupt is issued for CGMS WSS data is changed available PDC UTC and VITC data can a change in detected data or when data be initiated by using the VDP is detected regardless of content data slicer Reserved x Rev A Page 103 of 112 ADV7188 Bit Address Register Bit Description 3 Comments Notes VDP_GS_VPS_PDC_UTC_CHNG_Q See Gemstar PDC VPS UTC data is not Register 0x9C Bit 5 of the user sub map to changed available determine whether an interrupt is issued for Gemstar PDC VPS UTC data is a change in detected data or when data changed available is detected regardless of content Reserved VDP_VITC_Q VITC data is not available in the VDP VITC data is available in the VDP Reserved Ox4F Interrupt Clear 4 VDP CCAPD CLR Does not clear Note that an in
92. Begin Address 0x34 6 4 Address 0x35 7 0 The position of this edge is controlled by placing a binary number into HSB 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF 00 00 XY see Figure 26 HSB 10 0 is set to 00000000010 which is two LLCI clock cycles from Count 0 The default value of HSB 10 0 is 0x002 indicating that the HS pulse starts two pixels after the falling edge of HS Rev A Page 45 of 112 ADV7188 Table 61 HS Timing Parameters see Figure 26 Characteristics HS to Active Video Active Video Total LLC1 HS Begin Adjust HS End Adjust LLC1 Clock Cycles Samples Line Clock Cycles Standard HSB 10 0 Default HSE 10 0 Default Cin Figure 26 Default Din Figure 26 E in Figure 26 NTSC 00000000010 00000000000 272 720Y 720C 1440 1716 NTSC Square 00000000010 00000000000 276 640Y 640C 1280 1560 Pixel PAL 00000000010 00000000000 284 720Y 720C 1440 1728 ue eus SA SA Y Are 0 Koo X xy Koo Ko oo Ao oo Ko eese Arr 00 Ao Xx Kcr X v Kor K Y X ce A v Aer eA Qe ACTIVE pe Ay dt H BLANK pie say Ri ACTIVE VIDEO d i e a 9 ss hr p See E D e 3 E T Sa 1478 0 Figure 26 HS Timing HSE 10 0 HS End Address 0x34 2 0 Address 0x36 7 0 VS and FIELD Configur
93. C 12 registers and the GS VPS PDC UTC AVL bit is set The full packet data is also available in the ancillary data format Note that the data available in the C register depends on the status ofthe WST PKT DECODE DISABLE bit Bit 3 Subaddress 0x60 user sub map VBI System 2 The user can choose to use an alternative VBI data slicer called VBI System 2 This data slicer is used to decode Gemstar and closed caption VBI signals only Using this system the Gemstar data is only available in the ancillary data stream A special mode enables one line of data to be read back via PC For more information contact an Analog Devices representative for an engineering note on ADV7188 VBI processing Gemstar Data Recovery The Gemstar compatible data recovery block GSCD supports Gemstar 1x and Gemstar 2x data transmissions In addition it can serve as a decoder for closed captioning Gemstar compatible data transmissions can occur only in NTSC mode Closed caption data can be decoded in both PAL and NTSC modes The block is configured via the PC in the following ways e GDECEL 15 0 allows data recovery for selected video lines on even fields to be enabled and disabled e GDECOL 15 0 enables the data recovery for selected lines for odd fields e GDECAD configures the way in which data is embedded in the video data stream The recovered data is not available through PC but is inserted into the horizontal blanking period of
94. CAP1 3 CCAP1 2 CCAP1 1 CCAP1 0 154 9A CCAP 2 R CCAP27 CCAP2 6 CCAP2 5 CCAP2 4 CCAP2 3 CCAP2 2 CCAP2 1 CCAP2 0 155 9B Letterbox 1 R LB LCT 7 LB LCT 6 LB LCT 5 LB LCT 4 LB LCT 3 LB LCT 2 LB LCT 1 LB LCT O 156 9C Letterbox 2 R LB LCM 7 LB LCM 6 LB LCM 5 LB LCM 4 LB LCM 3 LB LCM 2 LB LCM 1 LB LCM O 157 9D Letterbox 3 R LB LCB 7 LB LCB 6 LB LCB 5 LB LCB 4 LB LCB 3 LB LCB 2 LB LCB 1 LB LCB 0 195 C3 ADC Switch 1 RW ADC1 SW 3 ADC1_SW 2 ADC1 SW 1 ADC1_SW 0 ADCO SW 3 ADCO SW 2 ADCO SW 1 ADCO SW 0 xxxxxxxx 00 196 C4 ADC Switch 2 RW ADC SW MAN ADC2 SW3 ADC2 SW 2 ADC2 SW 1 ADC2 SW 0 Oxxxxxxx 00 220 DC Letterbox Control 1 RW LB TH 4 LB TH 3 LB TH 2 LB TH 1 LB TH O 10101100 AC 221 DD Letterbox Control2 RW LB SL 3 LB SL 2 LB_SL 1 LB SLO LB EL 3 LB EL 2 LB EL 1 LB ELO 01001100 4C 222 DE ST Noise Readback 1 R ST NOISE VLD ST NOISE 10 ST NOISE 9 ST NOISE8 223 DF ST Noise Readback2 R ST NOISE7 ST NOISE 6 ST NOISE5 ST NOISE 4 ST NOISE 3 ST NOISE 2 ST NOISE 1 ST NOISEO 225 E1 SD Offset Cb RW SD OFF CB7 SD OFF CB6 SD OFF CB 5 SD OFF CB4 SD OFF CB3 SD_OFF_CB 2 SD OFF CB 1 SD OFF CB 0 10000000 80 226 E2 SD Offset Cr RW SD OFF CR7 SD OFF CR6 SD OFF CR 5 SD OFF CR4 SD OFF CR3 SD OFF CR2 SD OFF CR1 SD OFF CR 10000000 80 227 E3 SD Saturation CB RW SD SAT CB 7 SD SAT CB6 SD SAT CB 5 SD SAT CB4 SD SAT CB 3 SD SAT CB2 SD SAT CB 1 SD SAT CB 0 10000000 80 228 E4 SD Saturation Cr RW SD
95. Cx 7 0 Access Information Signal Name Address LB LCT 7 0 Ox9B LB LCM 7 0 Ox9C LB_LCB 7 0 Ox9D 1 This register is a readback register the default value does not apply Rev A Page 76 of 112 LB_TH 4 0 Letterbox Threshold Control Address 0xDC 4 0 Table 97 LB_TH 4 0 Function LB_TH 4 0 Description 01100 Default threshold for detection of black lines default 01101 to Increase threshold need larger active video 10000 content before identifying nonblack lines 00000 to Decrease threshold even small noise levels can 01011 cause the detection of nonblack lines LB SL 3 0 Letterbox Start Line Address OxDD 7 4 The LB SL 3 0 bits are set at 0100 by default For an NTSC signal the letterbox detection is from Line 23 to Line 286 By changing the bits to 0101 the detection starts on Line 24 and ends on Line 287 LB EL 3 0 Letterbox End Line Address OxDD 3 0 The LB EL 3 0 bits are set at 1101 by default This means that letterbox detection ends with the last active video line For an NTSC signal the detection is from Line 262 to Line 525 By changing the settings of the bits to 1100 the detection starts on Line 261 and ends on Line 254 IF Compensation Filter IFFILTSEL 2 0 IF Filter Select Address OxF8 2 0 The IFFILTSEL 2 0 register allows the user to compensate for SAW filter characteristics on a composite input such as those associated with tuner
96. DATA VBI DATA P10 2 VBI DATA P10 1 VBI DATA P10 0 VBI DATA P323 3 VBI DATA P3232 VBI DATA VBI DATA P323 0 00000000 00 P10 3 P323 1 106 6A VDP LINE 014 RW VBI DATA VBI DATA P11 2 VBI DATA P11 1 VBI DATA P11 0 VBI DATA P324 VBI DATA P324 VBI DATA P324 VBI DATA P324 00000000 00 P11 3 N272 3 N272 2 N272 1 N272 0 107 6B VDP LINE 015 RW VBI DATA VBI DATA P12 VBI DATA P12 VBI DATA P12 VBI DATA P325 VBI DATA P325 VBI DATA P325 VBI DATA P325 00000000 00 P12 N10 3 N10 2 N10 1 N10 0 N273 3 N273 2 N273 1 N273 0 108 6C VDP LINE 016 RW VBI DATA VBI DATA P13 VBI DATA P13 VBI DATA P13 VBI DATA P326 VBI DATA P326 VBI DATA P326 VBI DATA P326 00000000 00 P13 N11 3 N11 2 N11 1 N11 0 N274 3 N274 2 N274 1 N274 0 109 6D VDP LINE 017 RW VBI DATA VBI DATA P14 VBI DATA P14 VBI DATA P14 VBI DATA P327 VBI DATA P327 VBI DATA P327 VBI DATA P327 00000000 00 P14 N123 N12 2 N12 1 N12 0 N275 3 N275 2 N275 1 N275 0 110 6E VDP LINE 018 RW VBI DATA VBI DATA P15 VBI DATA P15 VBI DATA P15 VBI DATA P328 VBI DATA P328 VBI DATA P328 VBI DATA P328 00000000 00 P15 N13 3 N13 2 N13 1 N13 0 N276 3 N276 2 N276 1 N276 0 111 6F VDP LINE 019 RW VBI DATA VBI DATA P16 VBI DATA P16 VBI DATA P16 VBI DATA P329 VBI DATA P329 VBI DATA P329 VBI DATA P329 00000000 00 P16 N14 3 N14 2 N14 1 N14 0 N277 3 N277 2 N277 1 N277 0 112 70 VDP LINE 01A RW VBI DATA VBI DATA P17 VBI DATA P17 VBI DATA P17 VBI
97. EF 2 0 To improve the picture transition for high speed fast blank switching an edge shaping mode is available on the ADV7188 Depending on the format of the RGB inputs it may be advan tageous to apply different levels of edge shaping The levels are selected via the FB EDGE SHAPE 2 0 bits Users are advised to try each of the settings and select the setting that is most visually pleasing on their system Table 13 FB EDGE SHAPE 2 0 Function FB EDGE SHAPE 2 0 Description 000 No edge shaping 001 Level 1 edge shaping 010 default Level 2 edge shaping 011 Level 3 edge shaping 100 Level 4 edge shaping 101 to 111 Not valid Contrast Reduction For overlay applications text can be more readable if the contrast of the video directly behind the text is reduced To enable the definition of a window of reduced contrast behind inserted text the signal applied to the FB pin can be interpreted as a trilevel signal as shown in Figure 10 RGB SOURCE 100 CVBS SOURCE 50 CONTRAST SANDCASTLE CVBS SOURCE 05478 010 100 Figure 10 Fast Blank Signal Representation with Contrast Reduction Enabled Contrast Reduction Enable CNTR ENABLE Address OxEF 3 This bit enables the contrast reduction feature and changes the meaning of the signal applied to the FB pin 0 default The contrast reduction feature is disabled and the fast blank signal is interpreted as a bilevel signal 1 The con
98. FB Signal FB DELAY 3 0 Address OxFO 3 0 In the event of misalignment between the FB input signal and the other input signals CVBS and RGB or unequalized delays in their processing it is possible to alter the delay of the FB signal in 28 63636 MHz clock cycles For a finer granularity delay of the FB signal refer to the FB SP ADJUST 3 0 Address OxEF 7 4 section The default value of FB DELAY 3 0 is 0100 Color Space Converter Manual Adjust FB CSC MAN Address OxEE 7 As shown in Figure 9 the data from the CVBS and RGB sources are converted to YPbPr before being combined For the RGB source CSC must be used to perform this conversion When SCART support is enabled the parameters for CSC are automatically configured for this operation If the user wishes to use a different conversion matrix this autoconfiguration can be disabled and the CSC can be manually programmed For details on this manual configuration contact an Analog Devices representative 0 default The CSC is configured automatically for the RGB to YPrPb conversion 1 The CSC can be configured manually not recommended FB STATUS 3 0 Bit Name Description 0 FB STATUS 0 FB RISE A high value indicates that there has been a rising edge on FB since the last C read The value is cleared by an lC read this is a self clearing bit 1 FB STATUS 1 FB FALL A high value indicates that there has been a falling edge on FB since the last lC
99. GDECEL 15 GDECEL 14 GDECEL 13 GDECEL 12 GDECEL 11 GDECEL 10 GDECEL 9 GDECEL 8 00000000 00 Rev A Page 82 of 112 ADV7188 Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 73 49 Gemstar Control 2 RW GDECEL 7 GDECEL 6 GDECEL 5 GDECEL 4 GDECEL 3 GDECEL 2 GDECEL 1 GDECEL O 00000000 00 74 4A Gemstar Control3 RW GDECOL 15 GDECOL 14 GDECOL 13 GDECOL 12 GDECOL 11 GDECOL 10 GDECOL 9 GDECOL 8 00000000 00 75 4B GemstarControl4 RW GDECOL 7 GDECOL 6 GDECOL 5 GDECOLA GDECOL 3 GDECOL 2 GDECOL 1 GDECOL O 00000000 00 76 4C Gemstar Control 5 RW GDECAD xxxx0000 00 77 4D CTIDNR Control 1 RW DNR EN CTI AB 1 CTI AB O CTI AB EN CTI EN 11101111 EF 78 4E CTIDNR Control 2 RW CTI C TH 7 CTI C TH 6 CH CTHS5 CTILC_TH4 CTI C TH3 CTLC TH2 CTI C THA CTI C THO 00001000 08 80 50 CTI DNR Control 4 RW DNR TH 7 DNR TH 6 DNR TH 5 DNR_TH 4 DNR_TH 3 DNR_TH 2 DNR_TH 1 DNR TH O 00001000 08 81 51 Lock Count RW FSCLE SRLS COL 2 COL 1 COL O CIL 2 CIL 1 CIL O 00100100 24 105 69 Config 1 RW Reserved Reserved Reserved Reserved Reserved Reserved SDM_SEL 1 SDM_SEL O 00000x00 00 143 8F Free Run Line Ww LLC PAD LLC PAD LLC PAD 00000000 00 Length 1 SEL_MAN SEL 1 SEL O 153 99 CCAP 1 R CCAP1 7 CCAP1 6 CCAP1 5 CCAP 1 4 C
100. GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC PDC UTC 0 UTC BYTE 0 7 UTC BYTE 0 6 UTC BYTE 0 5 UTC BYTE 0 4 UTC BYTE 0 3 UTC BYTE 0 2 UTC BYTE 0 1 UTC BYTE 0 0 133 85 VDP GS VPS R GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC PDC UTC 1 UTC BYTE 1 7 UTC BYTE 1 6 UTC BYTE 1 5 UTC BYTE 1 4 UTC BYTE 1 3 UTC BYTE 1 2 UTC BYTE 1 1 UTC BYTE 1 0 134 86 VDP GS VPS R GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC PDC UTC 2 UTC BYTE 2 7 UTC BYTE 2 6 UTC BYTE 2 5 UTC BYTE 2 4 UTC BYTE 2 3 UTC BYTE 22 UTC BYTE 2 1 UTC BYTE 2 0 135 87 VDP GS VPS R GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC PDC UTC 3 UTC BYTE 3 7 UTC BYTE 3 6 UTC BYTE 3 5 UTC BYTE 3 4 UTC BYTE 3 3 UTC BYTE 3 2 UTC BYTE 3 1 UTC BYTE 3 0 136 88 VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC 4 BYTE 4 7 BYTE 4 6 BYTE 4 5 BYTE 44 BYTE 4 3 BYTE 42 BYTE 4 1 UTC BYTE 4 0 137 89 VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UTC VPS PDC UTC 5 BYTE 5 7 BYTE 5 6 BYTE 5 5 BYTE 5 4 BYTE 5 3 BYTE 5 2 BYTE 5 1 UTC BYTE 5 0 138 8A VDP VPS PDC R VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UTC VPS PDC UTC 6 BYTE 6 7 BYTE 6
101. IN10 57 CVBS10 AIN4 58 CVBS4 YC1 C YPrPb1 Pb SCART2 B AIN11 59 CVBS11 SCART1 CVBS AIN5 60 CVBS5 YC2 C YPrPb1 Pr SCART2 R AIN12 61 Not available AIN6 62 CVBS6 YC3 C YPrPb2 Pr SCART2 G Table 11 Manual Mux Settings for All ADCs Set ADC SW MAN EN to 1 ADCO ADC1 ADC2 ADC3 ADCO SW 3 0 Connected To ADC1 SW 3 0 Connected To ADC2 SW 3 0 Connected To ADC3 SW 3 0 Connected To 0000 No connection 0000 No connection 0000 No connection 0000 No connection 0001 AIN1 0001 No connection 0001 No connection 0001 No connection 0010 AIN2 0010 No connection 0010 AIN2 0010 No connection 0011 AIN3 0011 AIN3 0011 Noconnection 0011 No connection 0100 AIN4 0100 AIN4 0100 No connection 0100 AIN4 0101 AIN5 0101 AIN5 0101 AIN5 0101 No connection 0110 AIN6 0110 AIN6 0110 AIN6 0110 No connection 0111 No connection 0111 No connection 0111 No connection 0111 No connection 1000 No connection 1000 No connection 1000 No connection 1000 No connection 1001 AIN7 1001 No connection 1001 No connection 1001 AIN7 1010 AIN8 1010 Noconnection 1010 AIN8 1010 No connection 1011 AIN9 1011 AIN9 1011 Noconnection 1011 No connection 1100 AIN10 1100 AIN10 1100 Noconnection 1100 No connection 1101 AIN11 1101 AIN11 1101 AIN11 1101 No connection 1110 AIN12 1110 AIN12 1110 AIN12 1110 No connection 1111 Noconnection 1111 Noconnection 1111 Noconnection 1111 No connection RGB IP SEL Address OxF1 0 For SCART input
102. IN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN3 SCART G on AIN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN4 SCART G on AIN9 B on AIN7 Ron AIN8 CVBS in on AIN5 SCART G on AIN9 B on AIN7 Ron AIN8 CVBS in on AIN6 SCART G on AIN9 B on AIN7 Ron AIN8 Composite and SCART RGB RGB analog input options selectable via RGB IP SEL Y on AIN1 C on AIN4 Y on AIN2 C on AIN5 Y on AIN3 C on AING S video Y on AINT Pb on AIN4 Pr on AINS Y on AIN2 Pb on AIN3 Pr on AIN6 YPbPr 2 2 2 2 olo O jo 0 0O a a a lalololal la Oo 2 o 2 o CVBS in on AIN7 SCART G on AIN6 B on AIN4 R on AIN5 CVBS in on AIN8 SCART G on AIN6 B on AIN4 R on AIN5 CVBS in on AIN9 SCART G on AIN6 B on AIN4 R on AIN5 CVBS in on AIN10 SCART G on AIN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN11 SCART G on AIN6 AIN9 B on AIN4 AIN7 Ron AIN5 AIN8 Composite and SCART RGB RGB analog input options selectable via RGB IP SEL VID SEL 3 0 These bits allow the user to select the input video standard Autodetect PAL B G H I D NTSC without pedestal SECAM Autodetect PAL B G H I D NTSC M with pedestal SECAM Autodetect PAL N NTSC M without pedestal SECAM Autodetect PAL N NTSC M with pedestal SECAM NTSC NTSCM PAL 60 NTSC 4 43 PAL B G H I D PAL N B G H I D with
103. L 4 Gemstar 5 278 15 GDECEL 5 Gemstar 6 279 16 GDECEL 6 Gemstar 7 280 17 GDECEL 7 Gemstar 8 281 18 GDECEL 8 Gemstar 9 282 19 GDECEL 9 Gemstar 10 283 20 GDECEL 10 Gemstar 11 284 21 GDECEL 11 Gemstar or CC 12 285 22 GDECEL 12 Gemstar 13 286 23 GDECEL 13 Gemstar 14 287 24 GDECEL 14 Gemstar 15 288 25 GDECEL 15 Gemstar Line 3 0 ITU RBT 470 Enable Bit Comment 12 8 GDECOL 0 Not valid 13 9 GDECOL 1 Not valid 14 10 GDECOL 2 Not valid 15 11 GDECOL 3 Not valid 0 12 GDECOL 4 Not valid d 13 GDECOL 5 Not valid 2 14 GDECOL 6 Not valid 3 15 GDECOL 7 Not valid 4 16 GDECOL 8 Not valid 5 17 GDECOL 9 Not valid 6 18 GDECOL 10 Not valid 7 19 GDECOL 11 Not valid 8 20 GDECOL 12 Not valid 9 21 GDECOL 13 Not valid 10 22 GDECOL 14 CC 11 23 GDECOL 15 Not valid 12 321 8 GDECEL 0 Not valid 13 322 9 GDECEL 1 Not valid 14 323 10 GDECEL 2 Not valid 15 324 11 GDECEL 3 Not valid 0 325 12 GDECEL 4 Not valid 1 326 13 GDECEL 5 Not valid 2 327 14 GDECEL 6 Not valid 3 328 15 GDECEL 7 Not valid 4 329 16 GDECEL 8 Not valid 5 330 17 GDECEL 9 Not valid 6 331 18 GDECEL 10 Not valid 7 332 19 GDECEL 11 Not valid 8 333 20 GDECEL 12 Not valid 9 334 21 GDECEL 13 Not valid 10 335 22 GDECEL 14 cc 11 336 23 GDECEL 15 Not valid 1 As indicated by the bold rows two standards can use the same line for VBI
104. LINE COUNT MODE is set to 1 0xB4 Standard Ident 4 Read Only LCF 7 0 Data is valid only if STDI DVALID is 1 and STDI LINE COUNT MODE is set to 1 OxC3 ADC Switch 1 ADCO SW 3 0 Manual muxing control for ADCO No connection AINT AIN2 AIN3 AIN4 AIN5 AIN6 No connection No connecti o 3 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 2 2 2 212 2 2 2 o ololololo oilo 2 2 2 2lolololo 2 2 2 l olo oio l alololalalolol a lolola l alolo o 2 o 2 o 25 o 2 o 25 o 2 o 2 o No connection Set ADC SW MAN EN to 1 Rev A Page 93 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes ADC1_SW 3 0 Manual muxing control 0 0 0 0 No connection Set ADC SW MAN EN to 1 for ADC1 0 0 0 1 No connection 0 0 1 0 No connection 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 No connection 1 0 0 0 No connection 1 0 0 1 No connection 1 0 1 0 No connection 1 0 1 1 AIN9 1 1 0 0 AIN10 141 071 AIN11 1 1 1 0 AIN12 1 1 1 1 No connection OxC4 ADC Switch 2 ADC2_SW 3 0 Manual muxing control 0 0 0 0 No connection Set ADC SW MAN ENto for ADC2 0 0 0 1 Noconnection 0 0 1 0 AINZ 0 0 1 1 N
105. LOR SPACE B ET CONVERSION STANDARD DEFINITION PROCESSOR PIXEL DATA P19 TO P10 P9 TO PO SYNC EXTRACT CHROMA 2D COMB cb 4H MAX OUTPUT FORMATTER 1 SYNTHESIZED VBI DATA RECOVERY GLOBAL CONTROL LLC CONTROL I l I SCLK i SDA SERIAL INTERFACE 4 nn MACROVISION STANDARD FREE RUN CONTROL AND VBI DATA 1 DETECTION AUTODETECTION OUTPUT CONTROL ALSB gt CONTROL 1 AND DATA runt m 05478 001 Rev A Page 4 of 112 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvpnio 3 0 V to 3 6 V Pvpp 1 71 V to 1 89 V nominal input range 1 6 V Operating temperature range unless otherwise noted ADV7188 Table 1 Parameter Symbol Test Conditions Min Typ Max Unit STATIC PERFORMANCE 7 3 Resolution Each ADC N 12 Bits Integral Nonlinearity INL BSL at 54 MHz 1 5 2 5 8 LSB Differential Nonlinearity DNL BSL at 54 MHz 0 7 0 7 0 99 2 5 LSB DIGITAL INPUTS Input High Voltage Vin 2 V Input Low Voltage Vit 0 8 V Input Current 7 lin 50 50 yA 10 10 uA Input Capacitance Cin 10 pF DIGITAL OUTPUTS Output High Voltage Vou Isource 0 4 mA 2 4 V Output Low Voltage Vo Isink 3 2 mA 0 4 V High Impedance Leakage Current ILgak 10 yA Output Capacitance Cour 20 pF POWER REQUIREMENTS Digital Core Power Supply Dvoo 1 65 1 8 2 0 V Digital Input Output Power Supply Dvppio
106. NE_014 VBI_DATA_P324_N272 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 324 PAL 272 NTSC 1 for these bits to be effective VBI_DATA_P11 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 11 PAL NTSC N A Ox6B VDP LINE 015 VBI DATA P325 N273 3 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set to from Line 325 PAL 273 NTSC 1 for these bits to be effective VBI DATA P12 N10 3 0 0o 0 0 0 Sets VBI standard to be decoded from Line 12 PAL 10 NTSC 0x6C VDP LINE 016 VBI DATA P326 N274 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 326 PAL 274 NTSC 1 for these bits to be effective VBI DATA P13 N11 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 13 PAL 11 NTSC 0x6D VDP LINE 017 VBI DATA P327 N275 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 327 PAL 275 NTSC 1 for these bits to be effective VBI DATA P14 N12 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 14 PAL 12 NTSC Ox6E VDP LINE 018 VBI DATA P328 N276 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 328 PAL 276 NTSC 1 for these bits to be effective VBI DATA P15 N13 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 15 PAL 13 NTSC Rev A Page 105 of 112 ADV7188
107. NTRQ SEL 1 0 Description 00 Reserved 01 default Pseudosync only 10 Color stripe only 11 Either pseudosync or color stripe Additional information about the interrupt system is detailed in Table 107 Rev A Page 78 of 112 ADV7188 PIXEL PORT CONFIGURATION The ADV7188 has a very flexible pixel port that can be config ured in a variety of formats to accommodate downstream ICs Table 101 and Table 102 summarize the various functions that the ADV7188 pins can have in different modes of operation The order of components for example the order of Cr and Cb on the output pixel bus can be changed Refer to the SWPC Swap Pixel Cr Cb Address 0x27 7 section Table 101 indicates the default positions for the Cr Cb components PIXEL PORT RELATED CONTROLS OF SEL 3 0 Output Format Selection Address 0x03 5 2 The modes in which the ADV7188 pixel port can be configured are controlled by OF SEL 3 0 See Table 102 for details The default LLC frequency output on the LLCI pin is approxi mately 27 MHz For modes that operate with a nominal data rate of 13 5 MHz 0001 0010 the clock frequency on the LLCI pin stays at the higher rate of 27 MHz For information on outputting the nominal 13 5 MHz clock on the LLC1 pin see the LLC PAD SEL 2 0 LLC1 Output Selection Address 0x8F 6 4 section Table 101 P19 to PO Output Input Pin Mapping SWPC Swap Pixel Cr Cb Address 0x27 7 0 default No swapping i
108. O ACKNOWLEDGE BY MASTER 05478 050 Figure 47 Read and Write Sequence Rev A Page 80 of 112 REGISTER ACCESSES The MPU can write to and read from all of the ADV7188 s registers except those that are read only or write only The subaddress register determines which register the next read or write operation accesses All communications with the part through the bus start with an access to the subaddress register A read write operation is then performed from to the target address which then increments to the next address until a stop command on the bus is performed REGISTER PROGRAMMING The PC Register Maps section describes each register in terms of its configuration After the part has been accessed via the bus and a read write operation is selected the subaddress is set up The subaddress register determines to from which register the operation takes place Table 106 and Table 107 list the various operations controlled by the subaddress register As can be seen in Figure 48 the registers in the ADV7188 are arranged into two maps the user map enabled by default and the user sub map The user sub map has controls for the interrupt and VDP functionality of the ADV7188 and the user map controls everything else The user map and the user sub map consist of a common space from Address 0x00 to Address Ox3F Depending on how Bit 5 in Register 0x0E SUB USR EN is set the register map is then split into two sections SUB USR EN
109. OxE5 to OxEA Reserved 0 Set to default 0x32 Vsync Field Reserved 0 0 0 0 0 1 Set to default NEWAVMODE bit must be set high Control 2 VSBHE VS goes high in the middle of the ine even field VS changes state at the start of the ine even field VSBHO VS goes high in the middle of the ine odd field VS changes state at the start of the ine odd field 0x33 Vsync Field Reserved 0 0 0 1 0 0 Set to default Control 3 VSEHE VS goes low in the middle ofthe NEWAVMODE bit must be set high ine even field VS changes state at the start of the ine even field VSEHO VS goes low in the middle of the ine odd field VS changes state at the start of the ine odd field 0x34 Hsync Position HSE 10 8 HS end These bits allow the posi 0 0 0 HS output ends HSE 10 0 pixels Using HSB and HSE the user can Control 1 tioning of the HS output within the video line after the falling edge of hsync program the position and length of the output hsync Reserved 0 Set to 0 HSB 10 8 HS begin These bits allow the posi 00 HS output starts HSB 10 0 pixels tioning of the HS output within the video line after the falling edge of hsync Reserved Setto O 0x35 Hsync Position HSB 7 0 Using HSB 10 0 and HSE 10 0 0 0 0 0 1 0 Control 2 see Register 0x34 the user can program the position and length of the HS output signal 0x36 Hsync Position HSE 7 0 See Registers 0x34 and 0x35 010 0 0 0 0 Control 3 0x37 Polarity PCLK Sets the
110. P VITC MSKB VDP GS VPS VDP CGMS WSS VDP CCAPD 00x0x0x0 00 PDC_UTC_ CHNGD_MSKB MSKB CHNG_MSKB 96 60 VDP_Config_1 RW WST_PKT_ VDP_TTXT_TYPE_ VDP_TTXT_TYPE_ VDP_TTXT_ 10001000 88 DECOD_ MAN_ENABLE MAN 1 TYPE_MAN O DISABLE 97 61 VDP Config 2 RW AUTO DETECT 0001xx00 10 GS TYPE 98 62 VDP ADF RW ADF ENABLE ADF MODE 1 ADF MODEO ADF_DID 4 ADF_DID 3 ADF_DID 2 ADF_DID 1 ADF_DID O 00010101 15 Config 1 99 63 VDP ADF RW DUPLICATE ADF ADF SDID 5 ADF_SDID 4 ADF_SDID 3 ADF_SDID 2 ADF_SDID 1 ADF_SDID O 0x101010 2A Config 2 100 64 VDP LINE OOE RW MAN LINE PGM VBI DATA VBI DATA VBI DATA VBI DATA Oxxx0000 00 P318 3 P3182 P318 1 P318 0 101 65 VDP LINE OO0F RW VBI DATA VBI DATA P6 VBI DATA P6 VBI DATA P6 VBI DATA P319 VBI DATA P319 VBI DATA P319 VBI DATA P319 00000000 00 P6 N23 3 N23 2 N23 1 N23 0 N286 3 N286 2 N286 1 N286 0 102 66 VDP LINE 010 RW VBI DATA VBI DATA P7 VBI DATA P7 VBI DATA P7 VBI DATA P320 VBI DATA P320 VBI DATA P320 VBI DATA P320 00000000 00 P7 N243 N24 2 N24 1 N24 0 N287 3 N287 2 N287 1 N287 0 103 67 VDP LINE 011 RW VBI DATA VBI DATA P8 VBI DATA P8 VBI DATA P8 VBI DATA P321 VBI DATA P321 VBI DATA P321 VBI DATA P321 00000000 00 P8 N25 3 N25 2 N25 1 N25 0 N288 3 N288 2 N288 1 N288 0 104 68 VDP LINE 012 RW VBI DATA VBI DATA P9 2 VBI DATA P9 1 VBI DATA P9 0 VBI DATA VBI DATA P3222 VBI DATA VBI DATA P322 0 00000000 00 P9 3 P322 3 P322 1 105 69 VDP LINE 013 RW VBI
111. SIGN PAL Vsync End Sign Address OxE9 5 0 default Delays the end of vsync Set for user manual programming 1 Advances the end of vsync Not recommended for user programming ADVANCE END OF VSYNC BY PVEND 4 0 NOT VALID FOR USER PROGRAMMING YES i PVENDDELO I 0 0 A 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 05478 035 VSYNC END Figure 35 PAL Vsync End PVEND 4 0 PAL Vsync End Address 0xE9 4 0 The default value of PVEND is 10100 indicating the PAL vsync end position For all NTSC PAL vsync timing controls both the V bit in the AV code and the vsync on the VS pin are modified PFTOGDELO PAL Field Toggle Delay on Odd Field Address OxEA 7 O default No delay 1 Delays the F toggle transition on an odd field by a line relative to PFTOG PFTOGDELE PAL Field Toggle Delay on Even Field Address OxEA 6 O default No delay 1 default Delays the F toggle transition on an even field by a line relative to PFTOG Rev A Page 52 of 112 ADV7188 ENVSPROC Enable Vsync Processor Address 0x01 3 This block provides extra filtering of the detected vsyncs to PFTOGSIGN PAL Field Toggle Sign Address OxEA 5 0 Delays the field transition Set for manual programming 1 default Advances the field transition Not recommended for user programming PFTOG PAL Field Toggle Address OxEA 4 0 The default value of PFTOG is 00011 indicating t
112. ST 3 ADJUST 2 ADJUST 1 ADJUST O ENABLE SHAPE 2 SHAPE 1 SHAPE O 240 FO FB CONTROL 4 RW FB DELAY 3 FB DELAY 2 FB DELAY 1 FB DELAY O 01000100 44 241 F1 FB CONTROL 5 RW CNTR LEVEL 1 CNTR LEVELO FB LEVEL 1 FB LEVEL O CNTR MODE 1 CNTR MODE O RGB IP SEL 00001100 0C 243 F3 AFE CONTROL 1 RW ADC3 SW 3 ADC3 SW 2 ADC3 SW 1 ADC3 SW 0 AA FILT EN 3 AA FILT EN 2 AA FILT EN 1 AA FILT EN O 00000000 00 244 F4 Drive Strength RW DR STR DR STR O DR STR C DR STR CO DR STR S DR STR SO xx010101 15 248 F8 IF Comp Control RW IFFILTSEL 2 IFFILTSEL 1 IFFILTSEL O 00000000 00 249 F9 VS Mode Control RW VS COAST VS COAST EXTEND VS EXTEND VS 100000000 00 MODE 1 MODE O MIN_FREQ MAX FREQ 251 FB Peaking Control RW PEAKING_ PEAKING_ PEAKING_ PEAKING_ PEAKING_ PEAKING_ PEAKING_ PEAKING_ 01000000 40 GAIN 7 GAIN 6 GAIN 5 GAIN 4 GAIN 3 GAIN 2 GAIN 1 GAIN O 252 FC Coring Threshold 2 RW DNR TH 27 DNR_TH_2 6 DNR_TH_2 5 DNR TH 24 DNR TH 23 DNR TH 22 DNR_TH_2 1 DNR TH 2 0 00000100 04 Rev A Page 83 of 112 ADV7188 Table 105 provides a detailed description of the registers located in the user map Table 105 User Map Detailed Description Address Register Bit Description Bit 5 4 3 2 Comments Notes 0x00 Input Control INSEL 3 0 These bits allow the user to select an input channel and format 0 0 00 CVBS in on AIN1 SCART G on AIN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN2 SCART G on A
113. SULT 2 Result of autodetection 7 COL KILL Color kill is active Table 22 Status Register 2 Function Status Register 2 7 0 Bit Name Description 0 MVCS DET Detected Macrovision color striping 1 MVCS T3 Macrovision color striping protection Conforms to Type 3 if high Type 2 if low 2 MV PS DET Detected Macrovision pseudosync pulses 3 MV AGC DET Detected Macrovision AGC pulses 4 LL NSTD Line length is nonstandard 5 FSC NSTD Fsc frequency is nonstandard 6 Reserved 7 Reserved Table 23 Status Register 3 Function Status Register 3 7 0 Bit Name Description 0 INST HLOCK Horizontal lock indicator instantaneous 1 GEMD Gemstar detect 2 SD OP 50HZ Flags whether 50 Hz or 60 Hz is present at output 3 CVBS Indicates if a CVBS signal is detected in composite S video autodetection configuration 4 FREE RUN ACT Indicates if the ADV7188 is in free run mode Outputs a blue screen by default See the DEF VAL AUTO EN Default Value Automatic Enable Address OxOC 1 section for details about disabling this function 5 STD FLD LEN Field length is correct for currently selected video standard 6 INTERLACED Interlaced video detected field sequence found 7 PAL SW LOCK Reliable sequence of swinging bursts detected Rev A Page 23 of 112 ADV7188 STANDARD DEFINITION PROCESSOR SDP STANDARD DEFINITION PROCESSOR EJ AENEA DATA EUM ANDARD EJ AENEA EUM DIGITIZED CVBS DIGITAL i DIGITIZED Y Y C l CHROMA
114. Supply Voltage 3 3 V 38 PVDD P PLL Supply Voltage 1 8 V 42 44 46 58 AINT to Analog Video Input Channels 60 62 41 43 AIN12 45 57 59 61 11 INT O Interrupt Request Output An interrupt occurs when certain signals are detected on the input video See the User Sub Map register details in Table 107 40 FB Fast Blank FB is a fast switch overlay input that switches between CVBS and RGB analog signals 70 78 13 25 TESTO to Leave these pins unconnected 69 TEST4 77 65 TEST6 to Tie to AGND TEST7 16 TEST8 Tie to DVDDIO 35 to 32 PO to P19 O Video Pixel Output Ports 24 to 17 8to 5 76 to 73 2 HS O Horizontal Synchronization Output Signal 1 VS O Vertical Synchronization Output Signal 80 FIELD O Field Synchronization Output Signal 67 SDA 1 0 PC Port Serial Data Input Output Rev A Page 10 of 112 ADV7188 Pin No Mnemonic Type Description 68 SCLK PC Port Serial Clock Input Maximum clock rate of 400 kHz 66 ALSB This pin selects the I C address for the ADV7188 ALSB set to Logic 0 sets the address for a write to 0x40 set to Logic 1 sets the address to 0x42 64 RESET System Reset Input active low A minimum low reset pulse width of 5 ms is required to reset the ADV7188 circuitry 27 LLC1 O Line Locked Clock 1 This is a line locked output clock for the pixel data output by the ADV7188 Nominally 27 MHz but varies according to video line length 26 LLC2 O Line Locked Clock 2 This is a divide
115. T 88 BIT 89 VITC WAVEFORM Figure 42 VITC Waveform and Decoded Data Correlation 05478 040 Table 81 VITC Readback Registers Address User Sub Map Signal Name Register Location Dec Hex VITC DATA O 7 0 VDP VITC DATA O 7 0 VITC Bits 9 2 146d 0x92 VITC DATA 1 7 0 VDP VITC DATA 1 7 0 VITC Bits 19 12 147d 0x93 VITC DATA 2 7 0 VDP VITC DATA 2 7 0 VITC Bits 29 22 148d 0x94 VITC DATA 3 7 0 VDP VITC DATA 3 7 0 VITC Bits 39 32 149d 0x95 VITC DATA 4 7 0 VDP VITC DATA 4 7 0 VITC Bits 49 42 150d 0x96 VITC DATA 5 7 0 VDP VITC DATA 5 7 0 VITC Bits 59 52 151d 0x97 VITC DATA 6 7 0 VDP VITC DATA 6 7 0 VITC Bits 69 62 152d 0x98 VITC DATA 7 7 0 VDP VITC DATA 7 7 0 VITC Bits 79 72 153d 0x99 VITC DATA 8 7 0 VDP VITC DATA 8 7 0 VITC Bits 89 82 154d Ox9A VITC CALC CRC 7 0 VDP VITC CALC CRC 7 0 155d Ox9B The register is a readback register the default value does not apply Rev A Page 67 of 112 ADV7188 VPS PDC UTC Gemstar The readback registers for VPS PDC and UTC are shared Gemstar is a high data rate standard and therefore is available only through the ancillary stream For evaluation purposes any one line of Gemstar is available through the IC registers sharing the same register space as PDC UTC and VPS Therefore only one of the following standards can be read through the PC at a time VPS PDC UTC or Gemstar To identify the data that
116. TR_C and DR_STR bits O default HS VS and FIELD are three stated according to the TOD bit 1 HS VS and FIELD are forced active Drive Strength Selection Data DR STR 1 0 Address 0xF4 5 4 Because of EMC and crosstalk factors it may be desirable to strengthen or weaken the drive strength of the output drivers The DR STR 1 0 bits affect the P 19 0 output drivers For more information on three state control refer to the Drive Strength Selection Clock and the Drive Strength Selection Sync sections Table 17 DR STR Function Drive Strength Selection Clock DR STR C 1 0 Address 0xF4 3 2 The DR STR C 1 0 bits can be used to select the strength of the clock signal output driver LLC pin For more information refer to the Drive Strength Selection Sync and the Drive Strength Selection Data sections Table 18 DR STR C Function DR STR C 1 0 Description 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Drive Strength Selection Sync DR STR S 1 0 Address 0xF4 1 0 The DR STR S 1 0 bits allow the user to select the strength of the synchronization signals with which HS VS and FIELD are driven For more information refer to the Drive Strength Selection Clock and the Drive Strength Selection Data sections Table 19 DR STR S Function DR STR S 1 0 Description 01 default Medium low drive strength 2x
117. Value Y Address 0x0C 7 2 If the ADV7188 loses lock to the incoming video signal or if there is no input signal the DEF Y 5 0 bits allow the user to specify a default luma value to be output The register is used if e The DEF VAL AUTO EN bit is set high and the ADV7188 loses lock to the input video signal This is the intended mode of operation automatic mode e TheDEF VAL EN bit is set regardless of the lock status of the video decoder This is a forced mode that may be useful during configuration The DEF Y 5 0 values define the six MSBs of the output video The remaining LSBs are padded with 0s For example in 10 bit mode the output is Y 9 0 DEF Y 5 0 0 0 0 0 The value for Y is set by the DEF Y 5 0 bits A value of 0x0D in conjunction with the DEF C 7 0 default setting produces a blue color Register 0x0C has a default value of 0x36 DEF C 7 0 Default Value C Address OxOD 7 0 The DEF C 7 0 bits complement the DEF Y 5 0 bits These bits define the four MSBs of the Cr and Cb values to be output if e TheDEF VAL AUTO EN bit is set high and the ADV7188 cannot lock to the input video automatic mode e TheDEF VAL EN bit is set high forced output The data that is finally output from the ADV7188 for the chroma side is the output pixel buses Cr 7 0 DEF C 7 4 0 0 0 0 and Cb 7 0 DEF C 3 0 0 0 0 O In full 12 bit output mode two extra LSBs of value 00 are appended
118. X X X X X X X Decoded VPS PDC UTC data Read Only 0x90 VDP VPS PDC UTC 12 VPS PDC UTC BYTE 12 7 0 X X X X X X X Decoded VPS PDC UTC data Read Only 0x92 VDP VITC DATA O VITC DATA 0 7 0 X X X X X x x Decoded VITC data Read Only 0x93 VDP VITC DATA 1 VITC DATA 1 7 0 X X X X X X X Decoded VITC data Read Only 0x94 VDP VITC DATA 2 VITC DATA 2 7 0 X X X X X x x Decoded VITC data Read Only 0x95 VDP VITC DATA 3 VITC DATA 3 7 0 X X X X X x x Decoded VITC data Read Only 0x96 VDP VITC DATA 4 VITC DATA 4 7 0 X X X X X x x Decoded VITC data Read Only 0x97 VDP VITC DATA 5 VITC DATA 5 7 0 X X X X X x x Decoded VITC data Read Only 0x98 VDP VITC DATA 6 VITC DATA 6 7 0 X X X X X X x Decoded VITC data Read Only 0x99 VDP VITC DATA 7 VITC DATA 7 7 0 X X X X X x x Decoded VITC data Read Only Ox9A VDP VITC DATA 8 VITC DATA 8 7 0 X X X X X x x Decoded VITC data Read Only Ox9B VDP_VITC_CALC_CRC VITC_CRC 7 0 X X X X X x x Decoded VITC CRC data Read Only Rev A Page 107 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 Comments Notes Ox9C VDP OUTPUT SEL Reserved 0 0 0 WSS CGMS CB CHANGE Disable content based updating of CGMS and WSS data Enable content based updating of CGMS and WSS data GS VPS PDC UTC CB CHANGE Disable content based updating of Gemstar VPS PDC and UTC data
119. YCrCb 1 0 Three state Three state 0001 20 Bit at LLC2 4 2 2 Y 9 2 Y 1 0 CrCb 9 2 CrCb 1 0 0010 16 Bit at LLC2 4 2 2 Y 7 0 Three state CrCb 7 0 Three state 0011 default 8 Bit at LLC1 4 2 2 YCrCb 7 0 Three state Three state Three state 0110to 1111 Reserved Reserved do not use Rev A Page 79 of 112 ADV7188 MPU PORT DESCRIPTION The ADV7188 supports a 2 wire C compatible serial inter face Two inputs serial data SDA and serial clock SCLK carry information between the ADV7188 and the system PC master controller Each slave device is recognized by a unique address The ADV7188 s PC port allows the user to set up and configure the decoder and then to read back captured V BI data The ADV7188 has four possible slave addresses for both read and write operations depending on the logic level on the ALSB pin These four unique addresses are shown in Table 103 The ADV7188 s ALSB pin controls Bit 1 of the slave address By altering the ALSB it is possible to control two ADV7188s in an application without having a conflict with the same slave address The LSB Bit 0 sets either a read or write operation Logic 1 corresponds to a read operation Logic 0 corresponds to a write operation Table 103 PC Address ALSB R W Slave Address 0 0 0x40 0 1 0x41 1 0 0x42 1 1 0x43 To control the device on the bus a specific protocol must be followed First the master initiates a data transfer by establishi
120. _GS_VPS_PDC_UTC_0 7 0 132d 0x84 GS_VPS_PDC_UTC_BYTE_1 7 0 VDP_GS_VPS_PDC_UTC_1 7 0 133d 0x85 GS VPS PDC UTC BYTE 2 7 0 VDP GS VPS PDC UTC 2 7 0 134d 0x86 GS VPS PDC UTC BYTE 3 7 0 VDP GS VPS PDC UTC 3 7 0 135d 0x87 VPS PDC UTC BYTE 4 7 0 VDP VPS PDC UTC 4 7 0 136d 0x88 VPS PDC UTC BYTE 5 7 0 VDP VPS PDC UTC 5 7 0 137d 0x89 VPS PDC UTC BYTE 6 7 0 VDP VPS PDC UTC 6 7 0 138d 0x8A VPS PDC UTC BYTE 7 7 0 VDP VPS PDC UTC 7 7 0 139d 0x8B VPS PDC UTC BYTE 8 7 0 VDP VPS PDC UTC 8 7 0 140d Ox8C VPS PDC UTC BYTE 9 7 0 VDP VPS PDC UTC 9 7 0 141d 0x8D VPS PDC UTC BYTE 10 7 0 VDP VPS PDC UTC 10 7 0 142d Ox8E VPS PDC UTC BYTE 11 7 0 VDP VPS PDC UTC 11 7 0 143d Ox8F VPS PDC UTC BYTE 12 7 0 VDP VPS PDC UTC 12 7 0 144d 0x90 The register is a readback register the default value does not apply PDC UTC PDC and UTC are data transmitted through Teletext Packet 8 30 Format 2 Magazine 8 Row 30 Design Code 2 or 3 and Packet 8 30 Format 1 Magazine 8 Row 30 Design Code 0 or 1 Therefore if PDC or UTC data is to be read through I C the corresponding teletext standard WST or PAL System B should be decoded by VDP The whole teletext decoded packet is output on the ancillary data stream The user can look for the magazine number row number and design code and qualify the data as PDC UTC or neither of these If PDC UTC packets are identified Byte 0 to Byte 12 are updated to theGS VPS PDC UTC 0to VPS PDC UT
121. a 16 20 bit output interface where Y and Cr Cb are delivered via separate data buses the AV code is over the whole 16 20 bits The SD_DUP_AV bit allows the user to replicate the AV codes on both buses therefore the full AV sequence can be found on the Y data bus and on the Cr Cb data bus see Figure 25 0 default The AV codes are in single fashion to suit 8 10 bit interleaved data output 1 The AV codes are duplicated for 16 20 bit interfaces VBI_EN Vertical Blanking Interval Data Enable Address 0x03 7 The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering All data for Line 1 to Line 21 is passed through and available at the output port The ADV7188 does not blank the luma data but automatically switches all filters along the luma data path into their widest bandwidth For active video the filter settings for YSH and YPK are restored SD DUP AV 1 16 20 BIT INTERFACE comes De KCN CR ED oon D o Jn o ce prm QosmceEN UN NEU AV CODE SECTION 16 20 BIT INTERFACE EVES ES E2ER ES AV CODE SECTION Refer to the BL_C_VBI Blank Chroma During VBI Address 0x04 2 section for information on the chroma path O default All video lines are filtered and scaled 1 Only the active video region is filtered and scaled BL C VBI Blank Chroma During VBI Address 0x04 2 Setting BL_C_VBI hig
122. a type n 3 1 0 0 0 0 0 0 0 0 0 User Data Word XX n 2 1 0 0 0 0 0 0 0 0 0 n 1 B8 Checksum 0 0 CS checksum word Rev A Page 57 of 112 ADV7188 Table 72 Ancillary Data in Byte Output Format Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 Ancillary data preamble 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 0 12C_DID6_2 4 0 0 0 DID 4 EP EP I2C SDID7 2 5 0 0 0 SDID 5 EP EP 0 DC 4 0 0 0 Data count 6 EP EP padding 1 0 VBI DATA STD 3 0 0 0 IDO User Data Word 1 7 EP EP 0 Line number 9 5 0 0 ID1 User Data Word 2 8 EP EP Even Field Line number 4 0 0 0 ID2 User Data Word 3 9 EP EP 0 0 0 0 VDP_TTXT_TYPE 1 0 0 0 ID3 User Data Word 4 10 VBI WORD 1 7 0 0 0 User Data Word 5 11 VBI WORD 2 7 0 0 0 User Data Word 6 12 VBI WORD 3 7 0 0 0 User Data Word 7 13 VBI WORD 4 7 0 0 0 User Data Word 8 14 VBI WORD 5 7 0 0 0 User Data Word 9 Pad 0x200 These padding words may not be present depending on ancillary data f i type User Data Word XX n 3 1 0 0 0 0 0 0 0 0 0 n 2 1 0 0 0 0 0 0 0 0 0 n 1 B8 Checksum 0 0 CS checksum word This mode does not fully comply with ITU R BT 1364 Structure of VBI Words in Ancillary Data Stream Each VBI data standard has been split into a clock run in CRI a f
123. an ITU R BT 656 com patible data stream The data format is intended to comply with the ITU R BT 1364 recommendation by the International Telecommunications Union For more information visit the International Telecommunications Unions website See Figure 43 GDE SEL OLD ADR Address 0x4C 3 User Map The ADV7188 has an ancillary data output block that can be used by the VDP data slicer and the VBI System 2 data slicer The new ancillary data formatter is used by setting GDE SEL OLD ADF to 0 this is the default setting If this bit is set low refer to Table 71 and Table 72 for information about how the data is packaged in the ancillary data stream To use the old ancillary data formatter to be backward com patible with the ADV7189B set GDE SEL OLD ADF to 1 The ancillary data format in this section refers to the ADV7189B compatible ancillary data formatter 0 default Enables the new ancillary data system for use with VDP and VBI System 2 1 Enables the old ancillary data system for use with VBI System 2 only ADV7189B compatible Rev A Page 69 of 112 ADV7188 The format of the data packet depends on the following criteria e Transmission is Gemstar 1x or Gemstar 2x e Data is output in 8 bit or 4 bit format see the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section e Data is closed captioning CC or Gemstar compatible Data packets are output if the corresponding enable bit is s
124. at any time It is intended for users who do their own clamping Users should disable the current sources for analog clamping via the appropriate register bits wait until the digital clamp loop settles and then freeze it via the DCFE bit 0 default The digital clamp is operational 1 The digital clamp loop is frozen LUMA FILTER Data from the digital fine clamp block is processed by three sets of filters The data format at this point is CVBS for CVBS input format or luma only for Y C and YPrPb input formats e Luma Antialias YAA Filter The ADV7188 receives video at a rate of 27 MHz For 4x oversampled video the ADCs are sample at 54 MHz and the first decimation is performed inside the DPP filters Therefore the data rate into the ADV7188 is always 27 MHz The ITU R BT 601 standard recommends a sampling frequency of 13 5 MHz The luma antialias filter decimates the oversampled video using a high quality linear phase low pass filter that preserves the luma signal and simultaneously attenuates out of band components The luma antialias filter has a fixed response e Luma Shaping YSH Filters The shaping filter block is a programmable low pass filter with a wide variety of re sponses It can be used to selectively reduce the luma video signal bandwidth needed prior to scaling for example For some video sources that contain high frequency noise reducing the bandwidth of the luma signal improves visual picture quality
125. ata The decoded results are available as ancillary data in the output 656 data stream For low data rate VBI standards such as CC WSS CGMS the user can read the decoded data bytes from DC registers The VBI data standards that can be decoded by the VDP are shown in Table 64 and Table 65 Table 64 PAL Feature Standard Teletext System A or Cor D ITU R BT 653 Teletext System B WST ITU R BT 653 VPS Video Programming System VITC Vertical Interval Time Codes WSS Wide Screen Signaling CC Closed Captioning ETSI EN 300 231 V1 3 1 BT 1119 1 ETSI EN 300 294 Table 65 NTSC Feature Standard Teletext System B and D ITU R BT 653 Teletext System C NABTS ITU R BT 653 EIA 516 VITC Vertical Interval Time Codes CGMS Copy Generation EIA J CPR 1204 IEC 61880 Management System Gemstar CC Closed Captioning EIA 608 The VBI data standard that the VDP decodes on a particular line of incoming video has been set by default as described in Table 66 This can be overridden manually and any VBI data can be decoded on any line The details of manual program ming are described in Table 67 and Table 68 VDP Default Configuration The VDP can decode different VBI data standards on a line to line basis The various standards supported by default on different lines of VBI are explained in Table 66 Rev A Page 53 of 112 ADV7188 VDP Manual Configuration MAN_LINE_PGM Enable Manual Line Programmi
126. ate detect 0 SD 60 Hz detected 1 SD 50 Hz detected CVBS x Result of composite S video 0 x Y C 1 CVBS autodetection Rev A Page 86 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes FREE_RUN_ACT x 1 free run mode active Blue screen output STD_FLD_LEN x 1 field length standard Correct field length found INTERLACED x 1 interlaced video detected Field sequence found PAL_SW_LOCK x 1 swinging burst detected Reliable swinging burst sequence Analog Control Reserved 0 0 Internal Write Only XTAL TTL SEL 0 Crystal used to derive 28 63636 MHz clock 1 External TTL level clock supplied Reserved o 0 0 0 0 0x14 Analog Clamp Reserved 0 0 1 0 Set to default Control CCLEN Current clamp enable This bit allows 0 Current sources switched off the user to switch off the current sources in 1 Current sources enabled the analog front end Reserved 0 00 Set to default 0x15 Digital Clamp Reserved x x x x Set to default Control 1 DCFE Digital clamp freeze enable 0 Disable digital clamp freeze 1 Enable digital clamp freeze DCT 1 0 Digital clamp timing These bits 00 Slow TC 1 sec determine the time constant of the digital 0 1 Medium TC 0 5 sec fine clamp circuitry 1 0 Fast TC 0 1 sec 1 1 TC dependent on video Reserved 0 Set to default 0x17 Shaping Filter YSFM 4 0 Selects Y shaping filter mode
127. ate ground plane is smaller and long ground loops can result In some cases using separate ground planes is unavoidable For those cases it is recommended to place a single ground plane under the ADV7188 The location ofthe split should be under the ADV7188 For this case it is even more important to place components wisely because the current loops are much longer current takes the path of least resistance An example of a current loop is from the power plane to ADV7188 to digital output trace to digital data receiver to digital ground plane to analog ground plane PLL Place the PLL loop filter components as close as possible to the ELPF pin Do not place any digital or other high frequency traces near these components Use the values suggested in Figure 52 with tolerances of 1096 or less DIGITAL OUTPUTS BOTH DATA AND CLOCKS Try to minimize the trace length that the digital outputs drive Longer traces have higher capacitance which requires more current causing more internal digital noise Shorter traces reduce the possibility of reflections Adding a 30 Q to 50 Q series resistor can suppress reflections reduce EMI and reduce the current spikes inside the ADV7188 If series resistors are used place them as close as possible to the ADV7188 pins However try not to add vias or extra length to the output trace to make the resistors closer If possible limit the capacitance that each digital output drives to less than 15 pF
128. ation The position of this edge is controlled by placing a binary The following controls allow the user to configure the behavior number into HSE 10 0 The number applied offsets the edge of the VS and FIELD output pins and to generate the following with respect to an internal counter that is reset to 0 immediately embedded AV codes after EAV Code FE 00 00 XY see Figure 26 HSE is set to 00000000000 which is 0 LLC1 clock cycles from Count 0 ADV encoder compatible signals via NEWAVMODE The default value of HSE 10 0 is 000 indicating that the HS PVS PF pulse ends 0 pixels after the falling edge of HS HVSTIM For example VSBHO VSBHE 1 To shift the HS toward active video by 20 LLCIs add 20 LLCIs to both HSB and HSE that is HSB 10 0 00000010110 and HSE 10 0 00000010100 VSEHO VSEHE e For NTSC control 1696 LLC1s to both HSB and HSE for NTSC that is HSB 10 0 11010100010 and HSE 10 0 11010100000 e NVENDDELO NVENDDELE NVENDSIGN NVEND 4 0 The number 1696 is derived from the NTSC total number o e NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 0 of pixels 1716 To move 20 LLC1s away from active video is equal to subtracting e For PAL control an 10 0 e PVENDDELO PVENDDELE PVENDSIGN PVEND 4 0 PHS Polarity HS Address 0x37 7 The polarity of the HS pin can be inverted using the PHS bit e PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG 4 0 0 default HS is active hig
129. ble 9 Timing extraction is always performed by the ADV7188 on the CVBS signal However a combination of the CVBS and RGB inputs can be mixed and output under the control of the C registers and the FB pin Four basic modes are supported e Static Switch Mode The FB pin is not used The timing is extracted from the CVBS signal and either the CVBS content or RGB content can be output under the control of CVBS RGB SEL This mode allows the selection of a full screen picture from either source Overlay is not possible in static switch mode e Fixed Alpha Blending The FB pin is not used The timing is extracted from the CVBS signal and an alpha blended combination of the video from the CVBS and RGB sources is output This alpha blending is applied to the full screen The alpha blend factor is selected with the IC signal Rev A Page 16 of 112 ADV7188 MAN ALPHA VAL 6 0 Overlay is not possible in fixed alpha blending mode e Dynamic Switching Fast Mux The FB pin can be used to select the source This enables dynamic multiplexing between the CVBS and RGB sources With default settings when Logic 1 is applied to the FB pin the RGB source is selected when Logic 0 is applied to the FB pin the CVBS source is selected This mode is suitable for the overlay of subtitles teletext or other material Typically the CVBS source carries the main picture and the RGB source has the overlay data e Dynamic Switching with Edge Enhanc
130. comb filter provides Y C separation e AV Code Insertion At this point the decoded luma Y signal is merged with the retrieved chroma values AV codes as per ITU R BT 656 can be inserted SD CHROMA PATH The input signal is processed by the following blocks e Chroma Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Chroma Demodulation This block uses a color subcarrier Fsc recovery unit to regenerate the color subcarrier for any modulated chroma scheme and then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM e Chroma Filter This block contains a chroma decimation filter CAA with a fixed response and some chroma shaping filters CSH that have selectable responses e Chroma Gain Control Automatic gain control AGC can operate on several modes including a mode based on the color subcarrier s amplitude a mode based on the depth of the horizontal sync pulse on the luma channel and a mode that uses a fixed manual gain e Chroma Resample The chroma data is digitally resampled to keep it aligned with the luma data The resampling is done to correct for static and dynamic errors in the line lengths of the incoming video signal e Chroma 2D Comb The two dimensional 5 line super adaptive comb filter provides high quality Y C separation in case the input signal is CVBS e AV Code Insertion At this point the demodulated chroma Cr and Cb sig
131. cted by setting GDECAD to 0 full byte mode is enabled by setting GDECAD to 1 See the GDECAD Gemstar Decode Ancillary Data Format Address Ox4C 0 section The data packet formats are shown in Table 90 and Table 91 Only closed caption data can be embedded in the output data stream NTSC closed caption data is sliced on Line 21 on even and odd fields The corresponding enable bit must be set high See the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 sections PAL CC Data Half byte output mode is selected by setting GDECAD to 0 full byte output mode is selected by setting GDECAD to 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Table 92 and Table 93 list the bytes of the data packet PAL closed caption data is sliced from Line 22 and Line 335 The corresponding enable bits must be set Only closed caption data can be embedded in the output data stream See the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 sections GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 The 16 bits of GDECEL 15 0 are interpreted as a collection of 16 individual lines of decode enable signals Each bit refers to a line of video in a
132. ctive low Reserved 0 0 0 1 Rev A Page 96 of 112 ADV7188 Address Register Bit Description Comments Notes OxEE FB_CONTROL 2 MAN_ALPHA_VAL 6 0 These bits determine in what proportion the video from the CVBS and RGB sources are blended o o o eo eo FB CSC MAN Automatic configuration of the CSC for SCART support Enable manual programming of CSC CSC is used to convert RGB portion of SCART signal to YCrCb OxEF FB CONTROL 3 FB EDGE SHAPE 2 0 No edge shaping oj o Level 1 edge shaping Level 2 edge shaping Level 3 edge shaping o o o o o o Level 4 edge shaping Improves picture transition for high speed fast blank switching All other settings are invalid CNTR_ENABLE Contrast reduction mode disabled and FB signal interpreted as bilevel signal Contrast reduction mode enabled and FB signal interpreted as trilevel signal FB_SP_ADJUST Adjusts FB timing in reference to the sampling clock Each LSB corresponds to of a clock cycle OxFO FB_CONTROL 4 FB_DELAY 3 0 Delay on FB signal in 28 63636 MHz clock cycles Reserved OxF1 FB_CONTROL 5 RGB_IP_SEL SD RGB input for FB on AIN7 AIN8 and AIN9 SD RGB input for FB on AIN4 AIN5 and AIN6 Reserved Set to O CNTR_MODE 1 0 These bits allow adjustment of contrast level in the contrast reduction box 25
133. ctive until cleared When the active until cleared interrupt duration is selected and the event that caused the interrupt is no longer in force the interrupt persists until it is masked or cleared For example if the ADV7188 loses lock an interrupt is generated and the INTRQ pin goes low If the ADV7188 returns to the locked state INTRQ continues to be driven low until the SD LOCK bit is either masked or cleared Interrupt Drive Level The ADV7188 resets with open drain enabled and interrupt masking disabled Therefore INTRQ is in a high imped ance state after a reset Either 01 or 10 must be written to INTRQ OP SEL 1 0 for a logic level to be driven out from the INTRQ pin It is also possible to write to a bit in the ADV7188 that manually asserts the INTRQ pin This bitis MPU STIM INTRQ Multiple Interrupt Events If an interrupt event occurs and then another interrupt event occurs before the system controller has cleared or masked the first interrupt event the ADV7188 does not generate a second interrupt signal Therefore the system controller should check all unmasked interrupt status bits because more than one may be active Macrovision Interrupt Selection Bits The user can select between pseudosync pulse and color stripe detection as outlined in Table 100 MV INTRQ SEL 1 0 Macrovision Interrupt Selection Bits Address 0x40 5 4 User Sub Map Table 100 MV INTRQ SEL 1 0 Function MV I
134. d 0 Closed captioning was detected on an odd field 1 Closed captioning was detected on an even field VDP CCAP DATA 0 Address 0x79 7 0 User Sub Map Read Only Decoded Byte 1 of CC data VDP CCAP DATA 1 Address 0x7A 7 0 User Sub Map Read Only Decoded Byte 2 of CC data Rev A Page 65 of 112 ADV7188 VDP_CGMS_WSS_ VDP CGMS WSS DATA 2 DATA 1 5 0 7 1 RUN IN START SEQUENCE CODE ACTIVE VIDEO 11 00s 38 4us 42 5us Figure 39 WSS Waveform 100 IRE REF VDP CGMS WSS DATA 2 VDP CGMS WSS DATA 1 70 IRE 05478 037 VDP CGMS WSS DATA 0 3 0 05478 038 0 IRE 49 1us 0 5us MURES sis 11 2us CRC SEQUENCE 2 235ys 20ns Figure 40 CGMS Waveform 10 5 0 25us 12 91us SEVEN CYCLES OF 0 5035MHz CLOCK RUN IN OU CA A IA LR A 7 0 1 2 3 4 5 6 7 T P P A A 50 IRE A R R T I I T T Y Y 40 IRE REFERENCE COLOR BURST VDP CCAP DATA 0 VDP CCAP DATA 1 NINE CYCLES FREQUENCY Fs 3 579545MHz AMPLITUDE 40 IRE 10 003us a 27 382us 33 764us 2 i i b Figure 41 CC Waveform and Decoded Data Correlation Table 79 CGMS Readback Registers Address User Sub Map Signal Name Register Location Dec Hex CGMS_WSS_DATA_0 3 0 VDP CGMS WSS DATA 0 3 0 125d 0x7D CGMS_WSS_DATA_1 7 0 VDP CGMS WSS DATA 1 7 0 126d Ox7E CGMS WSS DATA 2 7 0 VDP CGMS WSS DATA 2 7 0 127d Ox7F The register is a readback reg
135. d by Address 0x35 e No other IC can take place between the two or more C writes for the sequence For example for HSB 10 0 write to Address 0x34 first immediately followed by Address 0x35 PC PROGRAMMING EXAMPLES A register programming script consisting of PC programming examples for all standard modes supported by the ADV7188 is available from the ADV7188 product page on the Analog Devices website The examples provided are applicable to a system with the analog inputs arranged as shown in Figure 52 The input selection registers change in accordance with the layout of the PCB Rev A Page 81 of 112 ADV7188 C REGISTER MAPS USER MAP The collective name for the registers in Table 104 is the user map Table 104 User Map Register Details Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex O 00 Input Control RW VID_SEL 3 VID_SEL 2 VID_SEL 1 VID_SEL O INSEL 3 INSEL 2 INSEL 1 INSEL O 00000000 00 1 01 Video Selection RW ENHSPLL BETACAM ENVSPROC 11001000 C8 3 03 Output Control RW VBI EN TOD OF SEL3 OF SEL2 OF SEL 1 OF SELO SD DUP AV 00001100 0C 4 04 Extended Output RW BT656 4 TIM OE BL C VBI EN SFL PIN RANGE 01xx0101 45 Control 7 07 Autodetect Enable RW AD SEC525 EN AD SECAM EN AD N443 EN AD P60 EN AD PALN EN AD PALM EN AD NTSC EN AD PAL EN 01111111 7F 8
136. ded analog input video signal range is 0 5 V to 1 6 V typically 1 V p p Table 3 Parameter Symbol Test Condition Min Typ Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0 1 UF Input Impedance Clamps switched off 10 MQ Input Impedance of Pin 40 FB 20 kQ Large Clamp Source Current 0 75 mA Large Clamp Sink Current 0 75 mA Fine Clamp Source Current 60 uA Fine Clamp Sink Current 60 uA 1 Temperature range Tmn to Tmax is 40 C to 85 C The minimum maximum specifications are guaranteed over this range Guaranteed by characterization 3 Except Pin 40 FB Rev A Page 6 of 112 THERMAL SPECIFICATIONS Table 4 ADV7188 Parameter Symbol Test Conditions Min Typ Max Unit Junction to Case Thermal Resistance Bic 4 layer PCB with solid ground plane 7 6 C W Junction to Ambient Thermal Resistance Still Air Osa 4 layer PCB with solid ground plane 38 1 C W TIMING SPECIFICATIONS Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvpnio 3 0 V to 3 6 V Pypp 1 71 V to 1 89 V operating temperature range unless otherwise noted Table 5 Parameter Symbol Test Conditions Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 28 63636 MHz Frequency Stability 50 ppm PC PORT SCLK Frequency 400 kHz SCLK Minimum Pulse Width High ti 0 6 Us SCLK Minimum Pulse Width Low t 1 3 us Hold Time Start Condition t3 0 6 us Setup Time Start Condit
137. e GS PDC VPS UTC AVL bit GS DATA TYPE 0 Gemstar 1x detected 1 Gemstar 2x detected VITC_AVL 0 VITC not detected VITC CLEAR resets the 1 VITC detected VITC_AVL bit TTXT AVL 0 Teletext not detected 1 Teletext detected VDP STATUS CLEAR CC CLEAR Does not reinitialize the CC registers This is a self clearing bit Write Only Reinitializes the CC readback registers Reserved CGMS WSS CLEAR 0 Does not reinitialize the This is a self clearing bit CGMS WSS registers 1 Reinitializes the CGMS WSS readback registers Reserved 0 Rev A Page 106 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 Comments Notes GS PDC VPS UTC CLEAR 0 Does not reinitialize the This is a self clearing bit GS PDC VPS UTC registers 1 Refreshes the GS PDC VPS UTC readback registers Reserved 0 VITC CLEAR 0 Does not reinitialize the VITC registers This is a self clearing bit 1 Reinitializes the VITC readback registers Reserved 0 0x79 VDP CCAP DATA O CCAP BYTE 1 7 0 XIXIX X X x x Decoded Byte 1 of CC Read Only Ox7A VDP CCAP DATA 1 CCAP BYTE 2 7 0 X X X X X x x Decoded Byte 2 of CC Read Only 0x7D VDP CGMS WSS DATA O CGMS CRC 5 2 x x x Decoded CRC sequence for CGMS
138. e alpha blender must be switched on via CTI AB EN Sharp blending maximizes the effect of CTI on the picture but may also increase the visual impact of small amplitude high frequency chroma noise Table 49 CTI AB 1 0 Function CTI AB 1 0 Description 00 Sharpest mixing 01 Sharp mixing 10 Smooth mixing 11 default Smoothest mixing CTI C TH 7 0 CTI Chroma Threshold Address Ox4E 7 0 The CTI C TH 7 0 value is an unsigned 8 bit number speci fying how big the amplitude step in a chroma transition must be to be steepened by the CTI block Programming a small value into this register causes even small edges to be steepened by the CTI block Making CTI C TH 7 0 a large value causes the block to only improve large transitions The default value for CTI C TH 7 0 is 0x08 indicating the threshold for the chroma edges prior to CTI DIGITAL NOISE REDUCTION DNR AND LUMA PEAKING FILTER DNR is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal therefore improves picture quality There are two DNR blocks in the ADV7188 the DNRI block before the luma peaking filter and the DNR2 block after the luma peaking filter as shown in Figure 23 LUMA LUMA LUMA PEAKING FILTER OUTPUT SIGNAL 05478 023 Figure 23 DNR and Peaking Block Diagram Rev A Page 39 of 112 ADV7188 DNR EN Digital Noise Reduction Enable Address Ox4D 5
139. e video signal see Figure 14 CCLEN DCT 1 0 DCFE are the PC signals that can be used to influence the behavior of the clamping block of the ADV7188 CCLEN Current Clamp Enable Address 0x14 4 The current clamp enable bit allows the user to switch off the current sources entirely in the analog front end This may be useful if the incoming analog video signal is clamped externally 0 The current sources are switched off 1 default The current sources are enabled COARSE CURRENT SOURCES 05478 014 Figure 14 Clamping Overview Rev A Page 30 of 112 ADV7188 DCT 1 0 Digital Clamp Timing Address 0x15 6 5 The clamp timing register determines the time constant of the digital fine current clamp circuitry It is important to realize that the digital fine current clamp reacts quickly correcting any residual dc level error for the active line immediately Therefore the time constant of the digital fine clamp must be much quicker than the one for the analog blocks By default the time constant of the digital fine current clamp is adjusted dynamically to suit the currently connected input signal Table 35 DCT 1 0 Function DCT 1 0 Description 00 default Slow TC 1 sec 01 Medium TC 0 5 sec 10 Fast TC 0 1 sec 11 TC determined by the input video parameters DCFE Digital Clamp Freeze Enable Address 0x15 4 This register bit allows the user to freeze the digital clamp loop
140. ecision is selectable via the CKILLTHR 2 0 bits Address 0x3D If color kill is enabled and the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines color processing is switched off black and white output To switch the color processing back on another 128 consecutive lines with a color burst greater than the threshold are required The color kill option only works for input signals with a modu lated chroma part For component YPrPb input there is no color kill 0 Disables color kill 1 default Enables color kill CKILLTHR 2 0 Color Kill Threshold Address 0x3D 6 4 The CKILLTHR 2 0 bits allow the user to select a threshold for the color kill function The threshold applies only to QAM based NTSC and PAL or FM modulated SECAM video standards To enable the color kill function the CKE bit must be set For CKILLTHR settings 000 001 010 and 011 chroma demodulation inside the ADV7188 may not work satisfactorily for poor input video signals Table 48 CKILLTHR 2 0 Function CG 11 0 CMG 11 0 Read Write Description CMG 11 0 Write Manual gain for chroma path CG 11 0 Read Currently active gain lt Chroma _Gain 05 CG 4095 _ 9 4 4 1024 Description CKILLTHR 2 0 SECAM NTSC PAL 000 No color kill Kill at lt 0 5 001 Kill at lt 5 Kill at lt 1 5 010 Kill at lt 7 Kill at lt 2 5 011 Kill at lt 8 Kill
141. eera a Pb PIO o O AINS P145 9 don OAIN11 PISO P16Q CVBSO OAING PATO SsSsSsSsSsRsR P19 Pd fo o A o fe TA a O CAPY1 LL O 27MHz OUTPUT CLOCK AGND 0 1pF 10pF 0 1pF 1nF LLC2Q 13 5MHz OUTPUT CLOCK ae QO CAPY2 0 1uF Q OUTPUT ENABLE INPUT AGND Kr tO carci y 10pF 0 1pF gt 1nF AGND CAPC2 ER cM INTO INTERRUPT OUTPUT O SELO SFL OUTPUT 10uF 0 1uF O REFOUT HSO HS OUTPUT g 10pF 0 1uF vs VS OUTPUT Tet FIELD OUTPUT 28 6363MHz AGND Q DVDDIO 4TpF mo L3 i ELPFO SELECT PC 9 DGND ATpF 10nF ADDRESS Y R trka i DGND Bank Dvss daLsB DVDDIO DVDDIO PVDD O Q 2kQ 2KO 4000 TESTe Q MPU INTERFACE w T TEST7 D CONTROL LINES o SDA o O v DVDDIO AGND O 4 70 TESTS O O RESET O RESET DVDDIO 100nF AGND DGND v Q Q DGND LOAD CAPACITOR VALUES AGND DGND ARE DEPENDENT ON CRYSTAL ATTRIBUTES 05478 053 Figure 52 Typical Connection Diagram Rev A Page 111 of 112 ADV7188 OUTLINE DIMENSIONS VIEW A ROTATED 90 CCW TOP VIEW 1420 PINS DOWN 14 00 SQ 13 80 AY BSC LEAD PITCH T COMPLIANT TO JEDEC STANDARDS MS 026 BEC Figure 53 80 Lead Low Profile Quad Flat Package LOFP ST 80 2 Dimensions shown in millimeters 051706 A ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7188BSTZ 40 C to 85 C 80 Lead Low Profile Quad Flat Package LOFP ST 80 2 EVAL ADV7188EB Evaluation Board
142. ement This provides the same functionality as the dynamic switching mode but with the benefit of Analog Devices proprietary edge enhancement algorithms which improve the visual appearance of transitions for signals from a wide variety of sources System Diagram A block diagram of the ADV7188 fast blanking configuration is shown in Figure 9 The CVBS signal is processed by the ADV7188 and converted to YPrPb The RGB signals are processed by a color space converter CSC and samples are converted to YPrPb Both sets of YPrPb signals are input to the subpixel blender which can be configured to operate in any of the four modes previously outlined in this section The fast blank position resolver determines the time position of the FB pin accurately 1 ns This position information is then used by the subpixel blender in dynamic switching modes enabling the ADV7188 to implement high performance multiplexing between the CVBS and RGB sources even when the RGB data source is completely asynchronous to the sampling crystal reference An antialiasing filter is required on all four data channels R G B and CVBS The order of this filter is reduced because all signals are sampled at 54 MHz The switched or blended data is output from the ADV7188 in the standard output formats see Table 102 FAST BLANK CONTROL FB MODE 1 0 Address OxED 1 0 FB MODE controls which fast blank mode is selected Table 12 FB MODE 1 0 Function
143. eo output with no input VBI decode support for close captioning including Gemstar 1x 2x XDS WSS CGMS teletext VITC VPS Power down mode 2 wire serial MPU interface IC compatible 3 3 V analog 1 8 V digital core 3 3 V input output supply Industrial temperature grade 40 C to 85 C 80 lead Pb free LOFP APPLICATIONS High end DVD recorders Video projectors HDD based PVRs DVDRs LCD TVs Set top boxes Professional video products AVR receiver AGC and clamp restore circuitry allow an input video signal peak to peak range of 0 5 V to 1 6 V Alternatively these can be bypassed for manual settings The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise accurate sampling and digital filtering The line locked clock output allows the output data rate timing signals and output clock signals to be synchronous asynchronous or line locked even with 5 variation in line length The output control signals allow glueless interface connections in most applications The ADV7188 modes are set up over a 2 wire serial bidirectional port PC compatible SCART and overlay functionality are enabled by the ability of the ADV7188 to process CVBS and standard definition RGB signals simultaneously Signal mixing is controlled by the fast blank pin The ADV7188 is fabricated in a 3 3 V CMOS process Its monolithic CMOS construction ensures greater functionality with lower power dissipation It is packaged i
144. equire the VS pin to change state only when HS is high or low Table 62 Recommended User Settings for NTSC See Figure 28 0 The VS pin goes high at the middle of a line of video even field 1 default The VS pin changes state at the start of a line even field VSEHO VS End Horizontal Position Odd Address 0x33 7 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes inactive Some follow on chips require the VS pin to change state only when HS is high or low 0 The VS pin goes low inactive at the middle of a line of video odd field 1 default The VS pin changes state at the start of a line odd field VSEHE VS End Horizontal Position Even Address 0x33 6 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes inactive Some follow on chips require the VS pin to change state only when HS is high or low 0 default The VS pin goes low inactive at the middle of a line of video even field 1 The VS pin changes state at the start of a line even field PVS Polarity VS Address 0x37 5 The polarity of the VS pin can be inverted using the PVS bit O default VS is active high 1 VS is active low PF Polarity FIELD Address 0x37 3 The polarity of the FIELD pin can be inverted using the PF bit 0 default FIELD is active high 1 FIELD is active low Register Register Name
145. erent video standards WSS is for PAL and CGMS is for NTSC therefore the CGMS and WSS readback registers are shared WSS is biphase coded and the VDP performs a biphase decoding to produce the 14 raw WSS bits in the CGMS WSS readback I C registers and to set the CGMS_WSS_AVL bit CGMS_WSS_CLEAR CGMS WSS Clear Address 0x78 2 User Sub Map Write Only Self Clearing 1 Reinitializes the CGMS WSS readback registers CGMS_WSS_AVL CGMS WSS Available Bit Address 0x78 2 User Sub Map Read Only 0 CGMS WSS was not detected 1 CGMS WSS was detected CGMS WSS DATA 90 3 0 Address 0x7D 3 0 CGMS WSS DATA 1 7 0 Address Ox7E 7 0 CGMS WSS DATA 2 7 0 Address Ox7F 7 0 These read only bits located in the user sub map hold the decoded CGMS or WSS data Refer to Figure 39 and Figure 40 for the PC to WSS and CGMS bit mapping cc Two bytes of decoded closed caption data are available in the PC registers The field information of the decoded CC data can be obtained from the CC EVEN FIELD bit Register 0x78 CC CLEAR Closed Captioning Clear Address 0x78 0 User Sub Map Write Only Self Clearing 1 Reinitializes the CC readback registers CC AVL Closed Captioning Available Address 0x78 0 User Sub Map Read Only 0 Closed captioning was not detected 1 Closed captioning was detected CC EVEN FIELD Address 0x78 1 User Sub Map Read Only Identifies the field from which the CC data was decode
146. et see the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 sections and the decoder detects the presence of data This means that for video lines where no data has been decoded no data packet is output even if the corresponding line enable bit is set Each data packet starts immediately after the EAV code of the preceding line Figure 43 and Table 84 show the overall structure of the data packet DATA IDENTIFICATION ATA DATA OPTIONAL PADDING Tm PREAMBLE FOR ANCILLARY DATA SECONDARY DATA IDENTIFICATION Entries within the packet are as follows e A fixed preamble sequence of 0x00 OxFE and OxFF e The data identification word DID 10 bit value the value of which is 0x140 for a Gemstar or CC data packet e The secondary data identification word SDID which contains information about the video line from which data was retrieved whether the Gemstar transmission was of 1x or 2x format and whether it was retrieved from an even or odd field e The data count byte which provides the number of user data words that follow e User data section This contains the user data which can be four or eight words of data e Optional padding to ensure that the length of the user data word section of a packet is a multiple of four bytes requirement as set in ITU R BT 1364 e Checksum byte
147. f 112 ADV7188 User Sub Map selon eee pO RES 99 Digital Inp tsz siena R aa EEES 110 PCB Layout Recommendations sse 109 XTAL and Load Capacitor Values Selection 110 Analog Interface IMPUS sinisesse 109 Typical Circuit Connection sentent 111 Power Supply Decoupling eee 109 Outline Dimensions seen tenentes 112 NX M M 109 Ordering Guide zie EIE 112 Digital Outputs Both Data and Clocks 109 REVISION HISTORY 1 07 Rev 0 to Rev A Corrected Register and Bit Names sss Universal Changes to Pin Configuration and Function Descriptions Section ssssssee 10 Ghange to Table 9 rct REY DDR pO 14 Change to T ble 17 ote RR Rte qs 22 Change to VBI Data Recovery Section 25 Changes to Table 24 isinisisi 25 Changes to SEL INV Address 0x41 6 Section 26 Change to Table 35 i eet d beenden tree E 31 Charge to Table 40 tret gets 36 Change to LAGT 1 0 Luma Automatic Gain Timing Address Ox2F 7 6 Section see 36 Change to NVBIOLCM 1 0 NTSC VBI Odd Field Luma Comb Mode Address OxEB 7 6 Section 43 Change to NVBIELCM 1 0 NTSC VBI Even Field Luma Comb Mode Address OxEB 5 4 Section 43 Change to NVBIOCCM 1 0 NTSC VBI Odd Field Chroma Comb Mode Address O
148. g adjust These bits ojojo Not a valid setting CVBS mode CTA 2 0 011b allow a specified timing difference between olol1 Chroma 4 two pixels early S video mode CTA 2 0 101b the luma and chroma samples YPrPb mode CTA 2 0 110b 0 1 10 Chroma one pixel early 0 111 No delay 110 0 Chroma one pixel delayed 1 0 1 Chroma two pixels delayed 1 1 0 Chroma three pixels delayed 1 1 1 Not a valid setting AUTO PDC EN This bit automatically 0 Use values in LTA 1 0 and CTA 2 0 programs the LTA CTA values to align luma for delaying luma and chroma and chroma at the output for all modes of 1 LTA and CTA values determined operation automatically SWPC This bit allows the Cr and Cb samples 0 No swapping to be swapped 1 Swap the Cr and Cb output samples 0x2B Miscellaneous PW_UPD Peak white update This bit 0 Update once per video line Peak white must be enabled see Gain Control determines the rate of gain change 1 Update once per field LAGC 2 0 Reserved 1 0 0 0 0 Set to default CKE Color kill enable This bit allows the 0 Color kill disabled For SECAM color kill threshold is set at color kill function to be switched on and off 1 Color kill enabled 8 see CKILLTHR 2 0 Reserved 1 Set to default 0x2C AGC Mode Control CAGC 1 0 Chroma automatic gain control 0 0 Manual fixed gain Use CMG 11 0 These bits select the basic mode of operation 0 1 Use luma gain for chroma for the AGC in the chroma path 1
149. h 1 HS is active low Rev A Page 46 of 112 ADV7188 NEWAVMODE New AV Mode Address 0x31 4 0 EAV SAV codes are generated to suit Analog Devices encoders No adjustments are possible 1 default Enables the manual position of VS FIELD and AV codes using Register 0x32 Register 0x33 and Register OxE5 to Register OxEA Default register settings are CCIR 656 compliant see Figure 27 for NTSC and Figure 32 for PAL For recommended manual user settings see Table 62 and Figure 28 for NTSC and Table 63 and Figure 33 for PAL HVSTIM Horizontal VS Timing Address 0x31 3 The HVSTIM bit allows the user to select where the VS signal is asserted within a line of video Some interface circuitry may require VS to go low while HS is low 0 default The start of the line is relative to HSE 1 The start of the line is relative to HSB VSBHO VS Begin Horizontal Position Odd Address 0x32 7 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high or low 0 default The VS pin goes high at the middle of a line of video odd field 1 The VS pin changes state at the start of a line odd field VSBHE VS Begin Horizontal Position Even Address 0x32 6 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips r
150. h blanks the Cr and Cb values of all VBI lines This is done to prevent data that arrives during VBI from being decoded as color and output through Cr and Cb As a result it is possible to send VBI lines into the decoder and then output them undistorted through an encoder Without this blanking any incorrectly decoded color would be encoded by the video encoder and therefore the VBI lines would be distorted 0 Decodes and outputs color during VBI 1 default Blanks Cr and Cb values during VBI SD DUP AV 0 8 10 BIT INTERFACE T ee inTERLEAVED FF 90 J 00 av ce STE AE AV CODE SECTION 05478 025 Figure 25 AV Code Duplication Control Rev A Page 44 of 112 ADV7188 RANGE Range Selection Address 0x04 0 AV codes as per ITU R BT 656 formerly known as CCIR 656 consist of a fixed header made up of OxFF and 0x00 values These two values are reserved and therefore are not to be used for active video Additionally the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and between 16 and 240 for chroma The RANGE bit allows the user to limit the range of values output by the ADV7188 to the recommended value range This ensures that the reserved values of 255d 0xFF and 00d 0x00 are not presented on the output pins unless they are part of an AV code header Table 58 RANGE Function RANGE Description 0 16 lt Y lt 235 16 lt C lt 240 1
151. hammed Byte 4 X 00 2 4 byte Row number dehammed Byte 5 3 byte Page number dehammed Byte 6 4 byte Page number dehammed Byte 7 5 to 10 byte 11 to 424 byte Control Bytes dehammed Byte 8 to Byte 13 Raw data bytes Text Packets 1 byte Magazine number dehammed Byte 4 X 01 to X 25 2 4 byte Row number dehammed Byte 5 3 to 42 byte Raw data bytes 8 30 Format 1 packet 1 byte Magazine number dehammed Byte 4 Design Code 0000 or 0001 24 byte Row number dehammed Byte 5 UTC 3 byte Design code dehammed Byte 6 4 to 10 byte 11 to 23 byte Dehammed Initial teletext page Byte 7 to Byte 12 UTC bytes dehammed Byte 13 to Byte 25 24th to 424 byte Raw status bytes 8 30 Format 2 packet 1 byte Magazine number dehammed Byte 4 Design Code 0010 or 0011 2 4 byte Row number dehammed Byte 5 PDC 3 byte Design code dehammed Byte 6 4 to 10 byte Dehammed Initial teletext page Byte 7 to Byte 12 11 to 23 byte PDC bytes dehammed Byte 13 to Byte 25 24 to 42d byte Raw status bytes X 26 X 27 X 28 X 29 X 30 X 31 1 byte Magazine number dehammed Byte 4 2 d byte Row number dehammed Byte 5 3 byte Design code dehammed Byte 6 4 to 42d byte Raw data bytes For X 26 X 28 and X 29 further decoding needs 24 x 18 hamming decoding Not supported at present Rev A Page 64 of 112 ADV7188 CGMS and WSS The CGMS and WSS data packets convey the same type of information for diff
152. he PAL field toggle position For all NTSC PAL field timing controls the F bit in the AV code and the field signal on the FIELD DE pin are modified NOT VALID FOR USER PROGRAMMING YES PFTOGDELO ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE 05478 036 TOGGLE Figure 36 PAL F Toggle SYNC PROCESSING The ADV7188 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video If desired the blocks can be disabled via the following two PC bits ENHSPLL Enable Hsync Processor Address 0x01 6 The hsync processor is designed to filter incoming hsyncs that have been corrupted by noise therefore it improves the per formance of the ADV7188 for video signals with stable time bases but poor SNR 0 Disables the hsync processor 1 default Enables the hsync processor improve vertical lock 0 Disables the vsync processor 1 default Enables the vsync processor VBI DATA DECODE There are two VBI data slicers on the ADV7188 The first is called the VBI data processor VDP and the second is called the VBI System 2 The VDP can slice both low bandwidth standards and high bandwidth standards such as teletext VBI System 2 can slice low data rate VBI standards only The VDP is capable of slicing multiple VBI data standards on SD video It decodes the VBI data on the incoming CVBS and Y C or YUV d
153. his highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention Video user controls such as brightness contrast saturation and hue are also available within the ADV7188 The ADV7188 implements the patented ADLLT algorithm to track varying video line lengths from sources such as a VCR ADLLT enables the ADV7188 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs VCD players and camcorders The ADV7188 contains a CTI processor that sharpens the edge rate of chroma transitions resulting in sharper vertical transitions The ADV7188 can process a variety of VBI data services such as closed captioning CC wide screen signaling WSS copy generation management system CGMS Gemstar 1x 2x extended data service XDS and teletext The ADV7188 is fully Macrovision certified detection circuitry enables Type I Type IL and Type III protection levels to be identified and reported to the user The decoder is also fully robust to all Macrovision signal inputs FUNCTIONAL BLOCK DIAGRAM 12 CLAMP Al DATA AIN1 E PREPROCESSOR AIN12 7 Al INPUT CLAMP MUX DECIMATION AND DOWNSAMPLING FILTERS CLAMP F CVBS S VIDEO YPrPb OR SCART RGB AND CVBS Al CLAMP SYNC PROCESSING AND q FI CLOCK GENERATION SYNC AND CLK CONTROL FB CVBS Y CO
154. ideband filters are used see Table 36 10010 NEDA 10011 SVHS 18 CCIR 601 10100 PALNN 1 10101 PAL NN 2 10110 PAL NN 3 10111 PAL WN 1 11000 PAL WN 2 11001 NTSC NN 1 11010 NTSC NN 2 11011 NTSC NN 3 11100 NTSC WN 1 11101 NTSC WN 2 11110 NTSC WN 3 11111 Reserved SET YSFM YSFM IN AUTO MODE 00000 OR 00001 NO USE YSFM SELECTED FILTER REGARDLESS OF VIDEO QUALITY AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB 1 0 SELECT WIDEBAND AUTOMATICALLY FILTER AS PER SELECT BEST WYSFM 4 0 WIDEBAND FILTER 05478 015 Figure 15 YSFM and WYSFM Control Flowchart Rev A Page 32 of 112 ADV7188 COMBINED Y ANTIALIAS S VHS LOW PASS FILTERS Y RESAMPLE WYSFMOVR Wideband Y Shaping Filter Override Address 0x18 7 pees ee Setting the WYSFMOVR bit enables the use of the WYSFM 4 0 o settings for good quality video signals For more information refer to the general discussion of the luma shaping filters in the a Ea Y Shaping Filter section and the flowchart shown in Figure 15 W un 2 0 The best wideband Y shaping filter for good quality video E ap signals is selected automatically z 50 f 1 default Enables manual selection of a wideband filter via Ht it is n N Mois L DUM fi ARA lil BAMAN 18 0 2 WYSFM 4 0 Wideband Y Shaping Filter Mode zy 10 12 Address 0x1
155. ied in the PC Interface section TTXT AVL Teletext Detected Status Bit Address 0x78 7 User Sub Map Read Only 0 T Teletext was not detected 1 Teletext was detected WST Packet Decoding For WST only the VDP decodes the magazine and row address of WST teletext packets and further decodes the packets 8 x 4 hamming coded words This feature can be disabled by using the WST PKT DECOD DISABLE bit Bit 3 Register 0x60 user sub map This feature is only valid for WST Table 78 WST Packet Description WST PKT DECOD DISABLE Disable Hamming Decoding of Bytes in WST Address 0x60 3 User Sub Map 0 Enables hamming decoding of WST packets 1 default Disables hamming decoding of WST packets For hamming coded bytes the dehammed nibbles along with error information from the hamming decoder are output as follows e Input hamming coded byte D3 P3 D2 P2 D1 P1 DO PO bits in decoded order e Output dehammed byte E1 EO 0 0 D3 D2 DI DO where Di is the corrected bit and Ei represents the error information Table 77 Explanation of Error Bits in the Dehammed Output Byte Output Data Bits E 1 0 Error Information in Nibble 00 No errors detected Okay 01 Error in P4 Okay 10 Double error Not okay 11 Single error found and corrected Okay The types of WST packets that are decoded are described in Table 78 Packet Byte Description Header Packet 1 byte Magazine number de
156. in an attempt to artificially restore lost color bandwidth By operating only on edges that are greater than a certain threshold the CTI block ensures that noise is not emphasized Care has also been taken to avoid edge ringing and undesirable saturation and hue distortion Chroma transient improvements are needed primarily for signals that have severe chroma bandwidth limitations For these types of signals it is strongly recommended to enable the CTI block via CTI EN CTI EN Chroma Transient Improvement Enable Address 0x4D 0 0 Disables the CTI block 1 default Enables the CTI block CTI AB EN Chroma Transient Improvement Alpha Blend Enable Address Ox4D 1 This bit enables an alpha blend function which mixes the transient improved chroma with the original signal The sharpness of the alpha blending can be configured via the CTI AB 1 0 bits For the alpha blender to be active the CTI block must be enabled via the CTI EN bit The settings of the CTI AB EN bit are as follows 0 Disables the CTI alpha blender 1 default Enables the CTI alpha blender CTI AB 1 0 Chroma Transient Improvement Alpha Blend Address 0x4D 3 2 The CTI AB 1 0 controls the behavior of alpha blend circuitry which mixes the sharpened chroma signal with the original one It thereby controls the visual impact of CTI on the output data For CTI AB 1 0 to become active the CTI block must be enabled via the CTI EN bit and th
157. ing and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video character istics including tape based sources broadcast sources security and surveillance cameras and professional systems The accurate 12 bit ADC provides professional quality video performance and is unmatched This allows true 10 bit resolution in the 10 bit output mode The 12 analog input channels accept standard composite S video and component video signals in an extensive number of combinations Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Automatic NTSC PAL SECAM identification Digital output formats 8 bit 10 bit 16 bit or 20 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD 0 5 V to 1 6 V analog signal input range Differential gain 0 4 typical Differential phase 0 4 typical Programmable video controls Peak white hue brightness saturation contrast Integrated on chip video timing generator Free run mode generates stable vid
158. ing temperature range unless otherwise noted Table 2 Parameter Symbol Test Conditions Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS input modulate five steps 0 4 0 6 Degree Differential Gain DG CVBS input modulate five steps 0 4 0 6 96 Luma Nonlinearity LNL CVBS input five steps 0 4 0 7 96 NOISE SPECIFICATIONS SNR Unweighted Luma ramp 61 63 dB Luma flat field 63 65 dB Analog Front End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range 5 5 Vertical Lock Range 40 70 Hz Fsc Subcarrier Lock Range 1 3 Hz Color Lock In Time 60 Lines Sync Depth Range 20 200 Color Burst Range 5 200 Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines CHROMA SPECIFICATIONS Hue Accuracy HUE 1 Degree Color Saturation Accuracy CL_AC 1 Color AGC Range 5 400 Chroma Amplitude Error 0 4 Chroma Phase Error 0 3 Degree Chroma Luma Intermodulation 0 1 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy CVBS 1 V input CVBS 1 V input 1 Temperature range Tmn to Tmax is 40 C to 85 C The minimum maximum specifications are guaranteed over this range Guaranteed by characterization 3 Nominal sync depth is 300 mV at 100 sync depth range ANALOG SPECIFICATIONS At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V Pypp 1 71 V to 1 89 V operating temperature range unless otherwise noted Recommen
159. ion t4 0 6 us SDA Setup Time ts 100 ns SCLK and SDA Rise Time te 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition ts 0 6 us RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio to tio 45 55 55 45 96 duty cycle LLC1 Rising to LLC2 Rising ti 1 ns LLC1 Rising to LLC2 Falling ti 1 ns DATA AND CONTROL OUTPUTS Data Output Transitional Time tis Negative clock edge to start of valid data 36 ns taccess tio t13 Data Output Transitional Time t14 End of valid data to negative clock edge 24 ns thoro to t14 Propagation Delay to Hi Z tis 6 ns Max Output Enable Access Time tie 7 ns Min Output Enable Access Time tiz 4 ns 1 Temperature range Tmn to Tmax is 40 C to 85 C The minimum maximum specifications are guaranteed over this range Guaranteed by characterization 3 TTL input values are 0 V to 3 V with rise fall times lt 3 ns measured between the 10 and 90 points 4 SDP timing figures obtained using default drive strength value 0xD5 in Register OxF4 Rev A Page 7 of 112 ADV7188 TIMING DIAGRAMS ts SDA SCLK t4 tg gt OUTPUT LLC1 OUTPUT LLC2 OUTPUTS P0 TO P19 VS HS FIELD SFL 05478 003 Figure 3 Pixel Port and Control Output Timing PO TO P19 HS VS FIELD SFL 05478 004 Figure 4 OE Timing Rev A Page 8 of 112 05478 002 ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rati
160. irte tete 17 Global Control Registers sente 21 Power Saving Modes sss 21 Reset Control oA DR RR HA 21 Global Pin Control ettet 21 Global Status Reglstetsa eret 23 Standard Definition Processor SDP sss 24 SD E rnjadPathz 4o ide ane De ca EU AC a 24 SD Chroma Paties eee eit e ERE 24 Sync reo T Jie 25 VBI Data Recovery essent 25 Generale tip zd tit Ree a as ee 25 Color Controls eie PR BUR RENS 28 Clamp Operation etiem en eid 30 D ma Filter ds eee ERR 31 Chroma Pilte aoaia RERO RET 34 Gain Operation codes eH enc ipte 35 Chroma Transient Improvement CTI ss 39 Digital Noise Reduction DNR and Luma Peaking Filter 39 Comb Eilters ione cte tds 40 AV Code Insertion and Controls sss 43 Synchronization Output Signals sss 45 Syne Processing osiers ErP 53 VBI Data Decode 53 PE T AOE NN 60 Standard Detection and Identification 62 PE Readback Registers iecit 64 Pixel Port Configuration seen 79 Pixel Port Related Controls sss 79 MPU Port Description 80 Register Accesses cane ee e De HERES 81 Register Programming eee rie 81 EG Sequencer ud cete e RR INR Rt 81 PC Programming Examples 81 PC Register Mipira iia e T R 82 User Map ctetu EE EEEE EE 82 Rev A Page 2 o
161. ister the default value does not apply Table 80 Closed Captioning Readback Registers Address User Sub Map Signal Name Register Location Dec Hex CCAP BYTE 1 7 0 VDP CCAP DATA 0 7 0 121d 0x79 CCAP BYTE 2 7 0 VDP CCAP DATA 1 7 0 122d Ox7A The register is a readback register the default value does not apply Rev A Page 66 of 112 ADV7188 VITC VITC_CLEAR VITC Clear Address 0x78 6 VITC has a sequence of 10 syncs in between each data byte The User Sub Map Weite Only Seli Clearing VDP strips these syncs from the data stream to output only the data 1 Reinitializes the VITC readback registers bytes The VITC results are available in the VDP_VITC_DATA_0 to VDP VITC DATA 8 registers Register 0x92 to Register 0x9A user sub map VITC_AVL VITC Available Address 0x78 6 User Sub Map 0 VTIC data was not detected The VITC has a CRC byte at the end the syncs in between each data byte are also used in this CRC calculation Because these syncs 1 VITC data was detected are not output the CRC is calculated internally The calculated CRC is also available for the user in the VDP VITC CALC CRC register Register 0x9B User Sub Map After the VDP completes See Figure 42 for the I C to VITC bit mapping decoding the VITC line the VDP VITC DATA x and VDP VITC CALC CRC registers are updated and the VITC_AVL bit is set VITC Readback Registers BIRO BIT Ts nine So oe oko soe e eH em sm p gt BI
162. isters the user must program I2C GS VPS PDC UTC to 00 as explained in Table 82 VDP supports autodetection of Gemstar distinguishing between Gemstar 1x and Gemstar 2x and decodes data accordingly For this autodetection mode to operate correctly the user must set the AUTO DETECT GS TYPE PC bit Register 0x61 user sub map and program the decoder to decode Gemstar 2x on the required lines through line programming The type of Gemstar decoding can be determined by observing the GS DATA TYPE bit Register 0x78 user sub map AUTO DETECT GS TYPE Address 0x61 4 User Sub Map 0 default Disables autodetection of Gemstar type 1 Enables autodetection of Gemstar type GS DATA TYPE Address 0x78 5 User Sub Map Read Only This bit identifies the decoded Gemstar data type 0 Gemstar 1x mode is detected Read two data bytes from 0x84 1 Gemstar 2x mode is detected Read four data bytes from 0x84 The Gemstar data that is available in the IC register may be from any line of the input video on which Gemstar was decoded To read the Gemstar data on a particular video line the user should use the manual configuration as described in Table 67 and Table 68 and enable Gemstar decoding only on the required line Rev A Page 68 of 112 Table 83 GS VPS PDC UTC Readback Registers ADV7188 Address User Sub Map Signal Name Register Location Dec Hex GS_VPS_PDC_UTC_BYTE_0 7 0 VDP
163. kets 1 Disables hamming decoding of WST packets Reserved 0 0x61 VDP Config 2 Reserved x AUTO DETECT GS TYPE Disables autodetection of Gemstar type Enables autodetection of Gemstar type Reserved Rev A Page 104 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 Comments Notes 0x62 VDP ADF Config 1 ADF_DID 4 0 1 0 1 User specified DID sent in the ancillary data stream with VDP decoded data ADF MODE 1 0 0 Nibble mode 1 Byte mode no code restrictions 1 0 Byte mode with values 0x00 and OxFF prevented 1 1 Reserved ADF ENABLE 0 Disable insertion of VBI decoded data into ancillary 656 stream 1 Enable insertion of VBI decoded data into ancillary 656 stream 0x63 VDP_ADF_Config_2 ADF_SDID 5 0 1 0 1 0 User specified SDID sent in the ancillary data stream with VDP decoded data Reserved x DUPLICATE_ADF 0 Ancillary data packet is spread across the Y and C data streams 1 Ancillary data packet is duplicated on the Y and C data streams 0x64 VDP LINE OOE VBI DATA P318 3 0 0 0 Sets VBI standard to be decoded from Line 318 PAL NTSC N A Reserved 0 0 0 MAN LINE PGM 0 Decode default standards on the If this bit is set to 1 all
164. lains the control words used Rev A Page 15 of 112 ADV7188 ADC_SW_MAN_EN Manual Input Muxing Enable Address 0xC4 7 ADCO SW 3 0 ADCO Mux Configuration Address 0xC3 3 0 ADC1 SW 3 0 ADC1 Mux Configuration Address 0xC3 7 4 ADC2 SW 3 0 ADC2 Mux Configuration Address 0xC4 3 0 ADC3 SW 3 0 ADC3 Mux Configuration Address OxF3 7 4 See Table 11 XTAL CLOCK INPUT PIN FUNCTIONALITY XTAL TTL SEL Address 0x13 2 The crystal pad is normally part of the crystal oscillator circuit powered from a 1 8 V supply For optimal clock generation the slice level of the input buffer of this circuit is at approximately half the supply voltage making it incompatible with TLL level signals O default A crystal is used to generate the ADV7188 clock 1 An external TTL level clock is supplied A different input buffer can be selected that slices at TTL compatible levels This inhibits operation of the crystal oscillator and therefore can only be used when a clock signal is applied 28 63636 MHz CRYSTAL OPERATION EN28XTAL Address 0x1D 6 The ADV7188 can operate on two different base crystal frequencies Selecting one over the other may be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals It is recommended to use a crystal of frequency 28 63636 MHz to clock the ADV7188 0 default The crystal frequency is 27 MHz 1
165. le luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb Fixed 3 line 2 tap top lines of line memory luma comb 110 Fixed luma comb Fixed 5 line 3 tap all lines of line memory luma comb 111 Fixed luma comb Fixed 3 line 2 tap bottom lines of line luma comb memory Rev A Page 42 of 112 ADV7188 Vertical Blank Control Each vertical blank control register Addresses 0xEB and 0xEC has the same meaning for the following bit settings 00 Early by one line 10 Delayed by one line 11 Delayed by two lines 01 default Described in each register section NVBIOLCM 1 0 NTSC VBI Odd Field Luma Comb Mode Address OxEB 7 6 These bits control the first combed line after VBI on NTSC odd field luma comb 01 default SMPTE170 ITU R BT 470 compliant blank Lines 1 to 20 264 to 282 comb half lines NVBIELCM 1 0 NTSC VBI Even Field Luma Comb Mode Address OxEB 5 4 These bits control the first combed line after VBI on NTSC even field luma comb 01 default SMPTE170 ITU R BT 470 compliant blank Lines 1 to 20 264 to 282 comb half lines PVBIOLCM 1 0 PAL VBI Odd Field Luma Comb Mode Address OxEB 3 2 These bits control the first combed line after VBI on PAL odd field Iuma comb 01 default ITU R BT 470 compliant blank Lines 624 to 22 311 to 335 comb half lines PVBIELCM 1 0 PAL VBI Even Field Luma Comb Mode Address OxEB
166. lect triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed Selection is made via the WSS CGMS CB CHANGE bit e Gemstar PDC VPS or UTC The user can select triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed Selection is made via the GS VPS PDC UTC CB CHANGE bit The sequence for the interrupt based reading of the VDP PC data registers is as follows for the CC standard 1 The user unmasks the CC interrupt mask bit Bit 0 of Address 0x50 user sub map set to 1 CC data occurs upon the incoming video VDP slices CC data and places it in the VDP readback registers 2 The VDP CC available bit goes high and the VDP module signals to the interrupt controller to stimulate an interrupt request for CC in this case 3 The user reads the interrupt status bits user sub map and sees that new CC data is available Bit 0 of Address Ox4E user sub map set to 1 4 The user writes 1 to the CC interrupt clear bit Bit 0 of Address 0x4F user sub map set to 1 in the interrupt PC space this is a self clearing bit This clears the interrupt on the INTRQ pin but does not have an effect in the VDP PC area 5 The user reads the CC data from the VDP IC area 6 The user writes to a bit CC CLEAR Bit 0 of Address 0x78 user sub map set to 1 in the VDP STATUS 0
167. lines indicated in Table 66 ee bits must t 1 Manually program the VBI standard RUDI TT to be decoded on each line See Table 67 0x65 VDP_LINE_OOF VBI_DATA_P319_N286 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 319 PAL 286 NTSC 1 for these bits to be effective VBI DATA P6 N23 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 6 PAL 23 NTSC 0x66 VDP_LINE_010 VBI_DATA_P320_N287 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 320 PAL 287 NTSC 1 for these bits to be effective VBI_DATA_P7_N24 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 7 PAL 24 NTSC 0x67 VDP LINE 011 VBI DATA P321 N288 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 321 PAL 288 NTSC 1 for these bits to be effective VBI DATA P8 N25 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 8 PAL 25 NTSC 0x68 VDP_LINE_012 VBI_DATA_P322 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 322 PAL NTSC N A 1 for these bits to be effective VBI_DATA_P9 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 9 PAL NTSC N A 0x69 VDP LINE 013 VBI DATA P323 3 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set to from Line 323 PAL NTSC N A 1 for these bits to be effective VBI_DATA_P10 3 0 0 0 0 0 Sets VBI standard to be decoded from Line 10 PAL NTSC N A Ox6A VDP_LI
168. lines of video OxFF Gain on Cb channel 2 110 1000 lines of vides SD_SAT_CR 7 0 SD Saturation Cr Channel 111 100 000 lines of video Address 0xE4 7 0 VS COAST MODE 1 0 Address OxF9 3 2 These bits allow the user to control only the gain of the Cr channel The user can adjust the saturation of the picture These bits are used to set the VS free run coast frequency Table 27 VS COAST MODE 1 0 Function Table 30 SD SAT CR 7 0 Function VS COAST MODE 1 0 Description SD SAT CR 7 0 Description 00 default 01 10 11 Autocoast mode follows VS frequency from last video input Forces 50 Hz coast mode Forces 60 Hz coast mode Reserved 0x80 default 0x00 OxFF Gain on Cr channel 1 Gain on Cr channel 2 0 Gain on Cr channel 2 Rev A Page 28 of 112 ADV7188 SD OFF CB 7 0 SD Offset Cb Channel Address OxE1 7 0 These bits allow the user to adjust the hue of the picture by selecting the offset for the Cb channel There is a functional overlap with the HUE 7 0 bits Table 31 SD OFF CB 7 0 Function SD OFF CB 7 0 Description 0x80 default 0 mV offset applied to the Cb channel 0x00 568 mV offset applied to the Cb channel OxFF 568 mV offset applied to the Cb channel SD OFF CR 7 0 SD Offset Cr Channel Address OxE2 7 0 These bits allow the user to select an offset for data on only the Cr channel and to adjust the hue of the pic
169. lity of the ADV7188 to retrieve horizontal and vertical timing and to lock to the color burst if present There are separate gain control units for luma and chroma data Both can operate independently of each other The chroma unit however can also take its gain value from the luma path The possible AGC modes are summarized in Table 39 It is possible to freeze the automatic gain control loops This causes the loops to stop updating and maintains the AGC determined gain that is active at the time of the freeze until the loop is either unfrozen or the gain mode of operation is changed The currently active gain from any of the modes can be read back Refer to the description of the dual function manual gain bits LMG 11 0 luma manual gain and CMG 11 0 chroma manual gain in the Luma Gain and the Chroma Gain sections ANALOG VOLTAGE RANGE SUPPORTED BY ADC 1 6V RANGE FOR ADV7188 MAXIMUM VOLTAGE SDP DATA GAIN SELECTION ONLY PRE 1 PROCESSOR L DPP MINIMUM CLAMP E VOLTAGE LEVEL Figure 21 Gain Control Overview Table 39 AGC Modes Input Video Type Luma Gain Chroma Gain Any Manual luma gain Manual chroma gain CVBS Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak white Dependent on color burst amplitude Taken from luma path Y C Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak white Dependent on color burst amplitude
170. ll PC registers are reset to their default values making these bits self clearing Some register bits do not have a reset value specified and instead keep the last value written to them These bits are marked as having a reset value of x in the register tables After the reset sequence the part immediately starts to acquire the incoming video signal Executing a software reset takes approximately 2 ms However it is recommended to wait 5 ms before performing subsequent PC writes The I C master controller receives a no acknowledge condition on the ninth clock cycle when a chip reset is implemented See the MPU Port Description section for a full description 0 default Operation is normal 1 The reset sequence starts GLOBAL PIN CONTROL Three State Output Drivers TOD Address 0x03 6 This bit allows the user to three state the output drivers ofthe ADV7188 Upon setting the TOD bit the P19 to PO HS VS FIELD and SFL pins are three stated The ADV7188 also supports three stating via a dedicated pin OE The output drivers are three stated if the TOD bit or the OE pin is set high The timing pins HS VS and FIELD can be forced active via the TIM_OE bit of Register 0x04 For more information on three state control refer to the Three State LLC Drivers and the Timing Signals Output Enable sections Individual drive Rev A Page 21 of 112 ADV7188 strength controls are provided by the DR_STR_S DR_STR_C and DR STR
171. mble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 1 0 0 0 Data count 6 EP EP 0 0 Gemstar Word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar Word 1 3 0 0 0 User data words 8 EP EP 0 0 Gemstar Word2 7 4 0 0 User data words 9 EP EP 0 0 Gemstar Word2 3 0 0 0 User data words 10 EP EP 0 0 Gemstar Word3 7 4 0 0 User data words 11 EP EP 0 0 Gemstar Word3 3 0 0 0 User data words 12 EP EP 0 0 Gemstar Word4 7 4 0 0 User data words 13 EP EP 0 0 Gemstar Word4 3 0 0 0 User data words 14 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum The bold values represent Gemstar or CC specific values Table 87 Gemstar 2x Data Full Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar Word1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 Gemstar Word3 7 0 0 0 User data words 9 Gemstar Word4 7 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum The bold values represent Gemstar or CC specific values Table 88 Gemstar 1x Data Half Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3
172. mode compatible 4 TU R BT 656 4 compatible with ITU R BT 656 3 or ITU R BT 656 4 0x07 Autodetect Enable AD_PAL_EN PAL B G I H autodetect enable 0 Disable 1 Enable AD_NTSC_EN NTSC autodetect enable 0 Disable 1 Enable AD_PALM_EN PAL M autodetect enable 0 Disable 1 Enable AD_PALN_EN PAL N autodetect enable 0 Disable 1 Enable AD P60 EN PAL 60 autodetect enable 0 Disable 1 Enable AD N443 EN NTSC 443 autodetect enable 0 Disable 1 Enable AD SECAM EN SECAM autodetect enable 0 Disable 1 Enable AD SEC525 EN SECAM 525 autodetect enable 0 Disable 1 Enable 0x08 Contrast Register CON 7 0 Contrast adjust This is the user 1 0 0 0 0 0 0 0 Lumagain 1 0x00 gain O control for contrast adjustment 0x80 gain 1 OxFF gain 2 0x09 Reserved Reserved 1 0 0 0 0 0 0 0 Rev A Page 85 of 112 ADV7188 Bit Address Register Bit Description 6 5 4 3 2 Comments Notes Ox0A Brightness Register BRI 7 0 These bits control the brightness of 0 0 0 0 0 0 0 0 0x00 2 0 mV the video signal Ox7F 204 mV 0x80 204 mV 0xoB Hue Register HUE 7 0 These bits contain the value for the 0 0 0 0 0 0 0 0 Hue range 90 to 90 color hue adjustment Ox0C Default Value Y DEF_VAL_EN Default value enable 0 Free run mode dependent on DEF_VAL_
173. mponents of YPrPb and Y C sources 00000 Automatic selection including a because they need not be combed For poor quality signals the wide notch response PAL NTSC SECAM system selects from a set of proprietary shaping filter responses 00001 default Automatic selection including a that complements comb filter operation to reduce visual artifacts narrow notch response PAL NTSC SECAM The control logic is shown in Figure 15 00010 SVHS 1 00011 SVHS 2 YSFM 4 0 Y Shaping Filter Mode Address 0x17 4 0 00100 SVHS 3 The Y shaping filter mode bits allow the user to select from a 00101 SVHS 4 wide range of low pass and notch filters When these bits are set 00110 SVHS 5 to either of the automatic selection modes the filter is selected 00111 SVHS 6 based on other bit selections such as detected video standard and 01000 SVHS 7 properties extracted from the incoming video itself such as quality 01001 SVHS 8 and time base stability The automatic selection always picks the 01010 SVHS 9 widest possible bandwidth for the video input encountered 01011 SVHS 10 01100 SVHS 11 If the YSFM settings specify a filter that is YSFM is set to values 01101 SVHS 12 other than 00000 or 00001 the chosen filter is applied to all video 01110 SVHS 13 regardless of its quality 01111 SVHS 14 10000 SVHS 15 In either of the automatic selection modes the notch filters are only used for poor quality video signals For all other video signals 19991 Vha 16 w
174. n Threshold V CNTR ENABLE FB LEVEL 1 0 CNTR LEVEL 1 0 0 00 default XX 0 01 XX 0 10 XX 0 11 XX 1 00 default 00 1 01 01 1 10 10 1 11 11 1 4 1 6 1 8 2 0 1 6 1 8 2 0 2 2 n a n a n a n a 0 4 0 6 0 8 2 0 Rev A Page 19 of 112 ADV7188 FB_INV Address OxED 3 Write Only The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV 0 default The fast blank pin is active high 1 The fast blank pin is active low Readback of FB Pin Status EB STATUS 3 0 Address OxED 7 4 FB STATUS 3 0 is a readback value that provides the system information on the status of the FB pins as shown in Table 16 FB Timing FB SP ADJUST 3 0 Address OxEF 7 4 The critical information extracted from the FB signal is the time at which it switches relative to the input video Due to small timing inequalities either on the IC or on the PCB it may be necessary to adjust the result by a fraction of one clock cycle This is controlled by FB SP ADJUST 3 0 Each LSB of FB SP ADJUST 3 0 corresponds to of an ADC clock cycle Increasing the value is equivalent to adding delay to the FB signal The reset value is chosen to produce equalized channels when the ADV7188 internal antialiasing filters are enabled and there are only intentional delays on the PCB The default value of FB SP ADJUST 3 0 is 0100 Table 16 FB STATUS Functions Alignment of
175. n a small Pb free 80 lead LQFP One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved ADV7188 TABLE OF CONTENTS Featu tess ione rr DRE viado secas E ias 1 AP PLICATIONS d 1 General DescriptlOlk oett mte e RR 1 Revision HIStory eene RUNDDUEDRURCBRIURNIIENN INE 3 Introduction eee ee e e CURRERE 4 Analog Front End seen 4 Standard Definition Processor SDP sssss 4 Functional Block Diagram senten 4 Specificationis eise MESH a EH aud 5 Electrical Characteristics tienen 5 Video Specifications iter ette 6 Analog Specifications essent 6 Thermal Specifications itte ten 7 Timing Specifications sssseeeeeeettetentntnns 7 Timing Diagrams ccccssesssssseseseesessessesessessessesesseesesessesnesees 8 Absolute Maximum Ratings esee 9 Package Thermal Performance sse 9 ESD Caution 9 Pin Configuration and Function Descriptions 10 Analog Front End serere aee IU 12 Analog Input Muxing eerte 13 Manual Input Muxing eerte 15 XTAL Clock Input Pin Functionality 16 28 63636 MHz Crystal Operation sse 16 Antialiasing Filtersz v a 16 SCART and Fast Blanking seen 16 Fast Blank Control
176. n even field Setting the bit enables the decoder block trying to find Gemstar or closed caption compatible data on that particular line Setting the bit to 0 prevents the decoder from trying to retrieve data See Table 94 and Table 95 To retrieve closed caption data services on NTSC Line 284 GDECEL 11 must be set Rev A Page 74 of 112 To retrieve closed caption data services on PAL Line 335 GDECEL 14 must be set The default value of GDECEL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CC data from any line in the even field The user should only enable Gemstar slicing on lines where VBI data is expected Table 94 NTSC Line Enable Bits and Corresponding Line Numbering Table 95 PAL Line Enable Bits and Corresponding Line Numbering ADV7188 Line Number Line Number line 3 0 ITU R BT 470 Enable Bit Comment 0 10 GDECOL 0 Gemstar 1 11 GDECOL 1 Gemstar 2 12 GDECOL 2 Gemstar 3 13 GDECOL 3 Gemstar 4 14 GDECOL 4 Gemstar 5 15 GDECOL 5 Gemstar 6 16 GDECOL 6 Gemstar 7 17 GDECOL 7 Gemstar 8 18 GDECOL 8 Gemstar 9 19 GDECOL 9 Gemstar 10 20 GDECOL 10 Gemstar 11 21 GDECOL 11 Gemstar or CC 12 22 GDECOL 12 Gemstar 13 23 GDECOL 13 Gemstar 14 24 GDECOL 14 Gemstar 15 25 GDECOL 15 Gemstar 0 273 10 GDECEL 0 Gemstar 1 274 11 GDECEL 1 Gemstar 2 275 12 GDECEL 2 Gemstar 3 276 13 GDECEL 3 Gemstar 4 277 14 GDECE
177. nal is merged with the retrieved luma values AV codes as per ITU R BT 656 can be inserted Rev A Page 24 of 112 SYNC PROCESSING The ADV7188 extracts syncs embedded in the video data stream There is currently no support for external HS VS inputs The sync extraction is optimized to support imperfect video sources such as videocassette recorders with head switches The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm The raw sync information is sent to a line length measurement and prediction block The output of this block is then used to drive the digital resampling section to ensure that the ADV7188 outputs 720 active pixels per line The sync processing on the ADV7188 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video e Vsync Processor This block provides extra filtering of the detected vsyncs to improve the vertical lock e Hsync Processor The hsync processor is designed to filter incoming hsyncs that have been corrupted by noise providing much improved performance for video signals with a stable time base but poor SNR VBI DATA RECOVERY The ADV7188 can retrieve the following information from the input video e Wide screen signaling WSS e Copy generation management system CGMS e Closed captioning
178. nal parameters Contact an Analog Devices representative for more information Table 41 LAGT 1 0 Function LMG 11 0 LG 11 0 Luma Manual Gain Luma Gain Address 0x2F 3 0 Address 0x30 7 0 Luma manual gain 11 0 are dual function bits If these bits are written to a desired manual luma gain can be programmed This gain becomes active if the LAGC 2 0 mode is switched to manual fixed gain Equation 2 and Equation 3 show how to calculate a desired gain for NTSC and PAL standards respectively NTSC Luma_Gain 1024 lt LMG 11 0 lt 4095 1128 PAL Luma_Gain 1024 lt LMG 11 0 lt 4095 1222 0 9078 3 63 2 0 838 3 351 3 If read back this register returns the current gain value Depending on the settings of the LAGC 2 0 bits this value is one of the following e Luma manual gain value LAGC 2 0 set to luma manual gain mode e Luma automatic gain value LAGC 2 0 set to any of the automatic modes Table 42 LG 11 0 LMG 11 0 Function LG 11 0 LMG 11 0 Read Write Description LMG 11 0 2 X Write Manual gain for luma path LG 11 0 Read Actual gain used LAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive For example to program the ADV7188 into manual fixed gain mode with a desired gain of 0 89 for the NTSC standard 1 Use Equation 2 to convert the gain 0 95 x 1128 1071 6
179. ncoders 1 Makes the part SFL compatible with ADV7190 ADV7191 ADV7194 encoders Rev A Page 26 of 112 ADV7188 Lock Related Controls The TIME_WIN signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video It Lock information is presented to the user through Bits 1 0 of reacts quickly Status Register 1 See the Status Register 1 7 0 Address 0x10 7 0 section Figure 13 outlines the signal flow and the controls The FREE RUN signal evaluates the properties of the incoming that are available to influence how the lock status information is video over several fields taking vertical synchronization generated information into account SRLS Select Raw Lock Signal Address 0x51 6 0 default Selects the FREE RUN signal Using the SRLS bit the user can choose between two sources for determining the lock status which is indicated via Status Register 1 Bits 1 0 1 Selects the TIME WIN signal SELECT THE RAW LOCK SIGNAL SRLS FILTER THE RAW LOCK SIGNAL CIL 2 0 COL 2 0 TIME WIN FREE RUN COUNTER INTO LOCK COUNTER OUT OF LOCK IN LOCK Fsc LOCK LOST_LOCK MEMORY TAKE Fsc LOCK INTO ACCOUNT FSCLE 05478 013 Figure 13 Lock Related Signal Path Rev A Page 27 of 112 ADV7188 FSCLE Fsc Lock Enable Address 0x51 7 The FSCLE bit allows the user to choose if the status of the color subcarrier loop is taken into account when the
180. nd the power pin Placing a via underneath the 100 nF capacitor pads down to the power plane is generally the best approach see Figure 49 VIA TO SUPPLY VIA TO GND 05478 051 Figure 49 Recommended Power Supply Decoupling It is particularly important to maintain low noise and good stability of PVDD Careful attention must be paid to regulation filtering and decoupling It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups AVDD DVDD DVDDIO and PVDD Some graphic controllers use substantially different levels of power when active during active picture time and when idle during horizontal and vertical sync periods This can result in a measurable change in the voltage supplied to the analog supply regulator which can in turn produce changes in the regulated analog supply voltage This can be mitigated by regulating the analog supply or at least PVDD from a different cleaner power source for example from a 12 V supply It is also recommended to use a single ground plane for the entire board This ground plane should have a space between the analog and digital sections of the PCB see Figure 50 ADV7188 ADV7188 ANALOG DIGITAL SECTION SECTION 05478 052 Figure 50 PCB Ground Layout Experience has repeatedly shown that the noise performance is the same or better with a single ground plane Using multiple ground planes can be detrimental because each separ
181. ne chroma comb mode 0 1 ITU R BT 470 compliant color that outputs color after VBI on output beginning Line 283 even field in NTSC 110 VBI ends one line later Line 284 1 1 Color output beginning Line 285 NVBIOCCM 1 0 NTSC VBI odd field 00 Color output beginning Line 20 Controls the position of first line chroma comb mode 0 1 ITU R BT 470 compliant color that outputs color after VBI on output beginning Line 21 odd field in NTSC 110 Color output beginning Line 22 1 1 Color output beginning Line 23 OxED FB STATUS Reserved x x x x Read Only FB_STATUS 3 0 These bits provide information about the status of the FB pin see individual entries for each bit FB_STATUS 0 x FB RISE 1 rising edge on the Self clearing bit FB pin since the last I C read FB STATUS 1 x FB FALL 1 falling edge on the Self clearing bit FB pin since the last PC read FB STATUS 2 x FB STAT provides instantaneous value of FB signal at time of the 2C read FB STATUS 3 x FB_HIGH indicates that the FB Self clearing bit signal has gone high since the last C read FB CONTROL 1 FB MODE 1 0 These bits select the FB mode 0 0 Static switch mode full RGB or Write Only full CVBS data 0 1 Fixed alpha blending see MAN ALPHA VAL 6 0 1 0 Dynamic switching fast mux 1 1 Dynamic switching with edge enhancement CVBS RGB SEL This bit selects either CVBS or 0 CVBS source RGB to be output 1 RGB source FB INV 0 FB pin active high 1 FB pin a
182. ne of PDC data from the decoder 1 Write 10 to I2C_GS_VPS_PDC_UTC 1 0 Address 0x9C user sub map to specify that PDC data has to be updated to PC registers 2 Write high to the GS PDC VPS UTC CLEAR bit Address 0x78 user sub map to enable I C register updating 3 PolltheGS PDC VPS UTC AVL bit Address 0x78 user sub map going high to check the availability of the PDC packets 4 Read the data bytes from the PDC IC registers To read another line or packet of data repeat the previous steps To read a packet of CC CGMS or WSS data only Steps 1 through 3 are required because these types of data have dedicated registers VDP Content Based Data Update For certain standards such as WSS CGMS Gemstar PDC UTC and VPS the information content in the signal transmitted remains the same over numerous lines and the user may want to be notified only when there is a change in the information content or loss of the information content The user needs to enable content based updating for the required standard through the GS VPS PDC UTC CB CHANGE and WSS CGMS CB CHANGE bits Therefore the AVAILABLE bit shows the availability of that standard only when its content has changed Content based updating also applies to loss of data at the lines where some data was previously present Thus for standards like VPS Gemstar CGMS and WSS if no data arrives in the next four lines programmed the corresponding AVAILABLE bit
183. ng Avoo to AGND 4V Dvpp to DGND 2 2V Pvop to AGND 22V Dvyopio to DGND 4V Dvopio to AVDD 0 3V to 40 3 V Pvpp to Dvop 0 3V to 40 3 V Dvopio to Pvop 0 3 V to 42V Dvovio to Dvop 0 3 V to 42V Avop to Pvop 0 3 V to 2 V Avop to Dvop 0 3 V to 2 V Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature T max Storage Temperature Range Infrared Reflow Soldering 20 sec 0 3 V to Dvopo 0 3 V 0 3 V to Dvopo 0 3 V AGND 0 3 V to Avon 0 3 V 125 C 65 C to 150 C 260 C ADV7188 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability PACKAGE THERMAL PERFORMANCE To reduce power consumption the user is advised to turn off any unused ADCs when using the part The junction temperature must always stay below the maximum junction temperature T max of 125 C Use the following equation to calculate the junction temperature Ty Ta max Oya x Wmax where Ta max 85 C 0j 30 C W W max Avpp x Tavpp T Dvbp x Ipvpp sk Dvppio x Ipvppio t Pvpp x Ipvpp ESD CAUTION ESD
184. ng a start condition which is defined by a high to low transition on SDA while SCLK remains high This indicates that an address data stream follows All peripherals respond to the start condition and shift the next eight bits 7 bit address R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse this is known as an acknowledge bit All other devices withdraw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the SDA and SCLK lines waiting for the start condition and the correct transmitted address SDATA SCLOCK 1 7 8 9 1 7 8 START ADDR R W ACK SUBADDRESS ACK The R W bit determines the direction of the data If the first byte of the LSB is Logic 0 the master writes information to the peripheral If the first byte of the LSB is Logic 1 the master reads information from the peripheral The ADV7188 acts as a standard slave device on the bus The data on the SDA pin is eight bits long supporting the 7 bit addresses plus the R W bit The ADV7188 has 249 subaddresses to enable access to the internal registers It therefore interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses autoincrement allowing data to be written to or read from the starting subaddress A data transfer is always terminated by a sto
185. ng of VBI Standards Address 0x64 7 User Sub Map The user can configure the VDP to decode different standards on a line to line basis through manual line programming For this the user must set the MAN_LINE_PGM bit and write to the VBI DATA Px Nyline programming bits see Register 0x64 to Register 0x77 of the user sub map O default The VDP decodes default standards on lines as shown in Table 66 1 The VBI standards to be decoded are manually programmed VBI DATA Px Ny 3 0 VBI Standard to be Decoded on Line x for PAL Line y for NTSC Addresses 0x64 to 0x77 User Sub Map These bits are related 4 bit clusters in Register 0x64 to Register 0x77 ofthe user sub map The 4 bit line programming registers named VBI DATA Px Ny identify the VBI data standard that would be decoded on Line x in PAL mode or on Line y in NTSC mode The Table 66 Default Line Standards for PAL and NTSC PAL 625 50 Default VBI Default VBI different types of VBI standards decoded by VBI DATA Px Ny are shown in Table 67 Note that the interpretation of its value depends on whether the ADV7188 is in PAL or NTSC mode Notes e Full field detection lines other than VBI lines of any standard can also be enabled by writing into the VBI DATA P24 N22 3 0 and VBI DATA P337 N285 3 0 bits Therefore if VBI DATA P24 N22 3 0 is programmed with any teletext standard then teletext is decoded from the entire odd field The corres
186. oconnection O 110 10 Noconnection 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 Noconnection 1 0 0 0 Noconnection 1 0 0171 Noconnection 1 0 1 0 AIN8 1 0 1 1 Noconnection 1 110 10 Noconnection 1 1 0 1 AIN11 1 1 1 0 AIN12 1 1 1 1 Noconnection Reserved x x x ADC SW MAN EN This bit enables manual 0 Disable setting of the input signal muxing 1 Enable OxDC Letterbox Control 1 LB TH 4 0 These bits set the threshold 0 1 1 0 0 Default threshold for the value that determines if a line is black detection of black lines Reserved 1 0 1 Set as default OxDD Letterbox Control 2 LB EL 3 0 These bits program the end 1 1 0 0 Letterbox detection ends with the line of letterbox detection end of field ast line of active video on a field 1100b 262 525 LB SL 3 0 These bits program the start 0 1 0 0 Letterbox detection aligned line of letterbox detection start of field with the start of active video 0100b 23 286 NTSC OxDE ST Noise Readback 1 ST NOISE 10 8 Sync tip noise measurement XIX x Read Only ST NOISE VLD x 1 ST NOISE 10 0 measurement is valid 0 ST_NOISE 10 0 measurement is invalid Reserved x x x x OxDF ST Noise Readback 2 ST NOISE 7 0 See ST NOISE 10 0 x xix x x x x x Read Only OxE1 SD Offset Cb SD OFF CB 7 0 These bits adjust the hue 1 0 0 0 0 0 0 0 by selecting the offset for the Cb channel OxE2 SD Offset Cr SD OFF CR 7 0 These bits adjust the hue 1 0 0 0 0 0 0 0 by
187. or selection Reserved 0x43 Interrupt Clear 1 SD_LOCK_CLR Does not clear Write Only Clears SD_LOCK_Q bit SD_UNLOCK_CLR Does not clear Clears SD_UNLOCK_Q bit Reserved Not used Reserved Not used Reserved Not used SD_FR_CHNG_CLR Do not clear Clears SD_FR_CHNG_Q bit MV PS CS CLR Does not clear Clears MV PS CS O bit Reserved Not used 0x44 Interrupt Mask 1 SD_LOCK_MSKB Masks SD_LOCK_Q bit Read Write Unmasks SD_LOCK_Q bit SD_UNLOCK_MSKB Masks SD_UNLOCK_Q bit Unmasks SD_UNLOCK_Q bit Reserved Not used Reserved Not used Reserved Not used SD_FR_CHNG_MSKB Masks SD_FR_CHNG_Q bit Unmasks SD_FR_CHNG_Q bit MV_PS_CS_MSKB Masks MV_PS_CS_Q bit Unmasks MV_PS_CS_Q bit Reserved Not used Rev A Page 101 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 Comments Notes 0x45 Raw Status 2 Read Only CCAPD No CCAPD data detected These bits are status bits only CCAPD data detected They cannot be cleared or masked Register 0x46 is used Reserved Xx X for this purpose EVEN FIELD 0 Current SD field is odd numbered 1 Current SD field is even numbered Reserved x x MPU_STIM_INTRQ 0 MPU STIM INT 0 1 MPU STIM INT 1 0x
188. out pedestal PAL M without pedestal PALM PAL Combination N PAL Combination N SECAM with pedestal 2 2 2 2 2 2 2 2 olololo 2 2 2 2 ololo o 2 23 2 2 2 2loloi2 i 2io oi2 i liolo Oo 25 oOo 2 o 2 o 2 o o SECAM with pedestal 0x01 Video Selection Reserved Set to default ENVSPROC Disable vsync processor Enable vsync processor Reserved Set to default BETACAM Enable BETACAM levels This bit sets the target value for AGC operation Standard video input BETACAM input enable ENHSPLL Disable hsync processor Enable hsync processor Reserved Set to default Rev A Page 84 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x03 Output Control SD DUP AV This bit duplicates the AV codes 0 AV codes to suit 8 10 bit from the luma into the chroma path interleaved data output 1 AV codes duplicated for 16 20 bit interfaces Reserved 0 Set as default OF SEL 3 0 These bits allow the user to 0 0 0 0 10 bit format at LLC1 4 2 2 choose from a set of output formats ololol1 20 bit format at LLC2 4 2 2 0 0 1 0 16 bit format at LLC2 4 2 2
189. overall lock status is determined and presented via Bits 1 0 in Status Register 1 The FSCLE bit must be set to 0 when operating in YPrPb component mode to generate a reliable horizontal lock status bit INST HLOCK O default Makes the overall lock status dependent on the horizontal sync lock 1 Makes the overall lock status dependent on the horizontal sync lock and the Fsc lock CIL 2 0 Count Into Lock Address 0x51 2 0 CIL 2 0 determines the number of consecutive lines the system must remain in the into lock condition before reporting a locked state in Status Register 1 1 0 It counts the value in lines of video Table 25 CIL 2 0 Function ST NOISE VLD Sync Tip Noise Measurement Valid Address OxDE 3 Read Only This read only bit measures whether ST NOISE is valid or invalid 0 The ST NOISE 10 0 measurement is invalid 1 default The ST NOISE 10 0 measurement is valid ST NOISE 10 0 Sync Tip Noise Measurement Addresses OxDE 2 0 OxDF 7 0 The ST NOISE 10 0 measures the noise in the horizontal sync tip over four fields and shows a readback value of the average noise ST NOISE VLD must be 1 for this measurement to be valid One bit of ST NOISE 10 0 one ADC code One bit of ST NOISE 10 0 1 6 V 4096 390 625 uV COLOR CONTROLS These registers allow the user to control the appearance of the CIL 2 0 Description picture including control of the active
190. p condition The user can also access any subaddress register on a one by one basis without updating all the registers Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCLK high period the user should issue only one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADV7188 does not issue an acknowledge and returns to the idle condition If the highest subaddress is exceeded in autoincrement mode the following action is taken 1 Duringa read the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read In a no acknowledge condition the SDA line is not pulled low on the ninth pulse 2 During a write the data for the invalid byte is not loaded into a subaddress register Instead a no acknowledge is issued by the ADV7188 and the part returns to the idle condition 9 1 7 8 9 05478 049 Figure 46 Bus Data Transfer WRITE SEQUENCE LSB 0 LSB 1 i seule 5 SAVE soon AS SUSADOR nS svenon n ona awl uma N S START BIT P STOP BIT A S ACKNOWLEDGE BY SLAVE A M ACKNOWLEDGE BY MASTER A S NO ACKNOWLEDGE BY SLAVE A M N
191. ponding bits for the even field are VBI DATA P337 N285 3 0 e Inteletext system identification VDP assumes that if teletext is present in a video channel all the teletext lines comply with a single standard system Therefore the line programming using VBI DATA Px Ny registers identifies whether the data in line is teletext the actual standard is identified by the VDP TTXT TYPE MAN bit To program the VDP TTXT TYPE MAN bit the VDP TTXT TYPE MAN ENABLE bit must be set to 1 NTSC 525 60 Default VBI Default VBI Line No Data Decoded Line No Data Decoded Line No Data Decoded Line No Data Decoded 6 WST 318 VPS 23 Gemstar 1x 7 WST 319 WST 24 Gemstar 1x 286 Gemstar 1x 8 WST 320 WST 25 Gemstar 1x 287 Gemstar 1x 9 WST 321 WST 288 Gemstar 1x 10 WST 322 WST 11 WST 323 WST 12 WST 324 WST 10 NABTS 272 NABTS 13 WST 325 WST 11 NABTS 273 NABTS 14 WST 326 WST 12 NABTS 274 NABTS 15 WST 327 WST 13 NABTS 275 NABTS 16 VPS 328 WST 14 VITC 276 NABTS 17 329 VPS 15 NABTS 277 VITC 18 330 16 VITC 278 NABTS 19 VITC 331 17 NABTS 279 VITC 20 WST 332 VITC 18 NABTS 280 NABTS 21 WST 333 WST 19 NABTS 281 NABTS 22 CC 334 WST 20 CGMS 282 NABTS 23 WSS 335 CC 21 CC 283 CGMS 24 full WST 336 WST 22 full NABTS 284 CC odd field odd field 337 4 full WST 285 full NABTS even field even field Rev A Page 54 of 112 Table 67 VBI Data Standards for Manual Configuration ADV7
192. ps PAL Address 0x39 7 6 Table 55 CTAPSP 1 0 Function CTAPSP 1 0 Description 00 Do not use 01 PAL chroma comb adapts five lines three taps to three lines two taps cancels cross luma only 10 PAL chroma comb adapts five lines five taps to three lines three taps cancels cross luma and hue error less well PAL chroma comb adapts five lines five taps to four lines four taps cancels cross luma and hue error well 11 default CCMP 2 0 Description Configuration 000 Adaptive comb mode Adaptive 3 line chroma default comb for CTAPSP 01 Adaptive 4 line chroma comb for CTAPSP 10 Adaptive 5 line chroma comb for CTAPSP 11 100 Disable chroma comb 101 Fixed chroma comb Fixed 2 line chroma top lines of line memory comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 110 Fixed chroma comb Fixed 3 line chroma 111 all lines of line memory Fixed chroma comb bottom lines of line memory comb for CTAPSP 01 Fixed 4 line chroma comb for CTAPSP 10 Fixed 5 line chroma comb for CTAPSP 11 Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 YCMP 2 0 Luma Comb Mode PAL Address 0x39 2 0 Table 57 YCMP 2 0 Function YCMP 2 0 Description Configuration Oxx Adaptive comb mode Adaptive 5 line 3 tap default luma comb 100 Disab
193. r example if Cia is 30 pF the values of C1 and C2 are calculated to be 50 pF each and the nearest standard capacitor value is 47 pE Rev A Page 110 of 112 ADV7188 TYPICAL CIRCUIT CONNECTION An example of how to connect the ADV7188 video decoder is shown in Figure 52 For a detailed schematic diagram for the ADV7188 refer to the ADV7188 evaluation note which can be obtained from an Analog Devices representative FERRITE BEAD DVDDIO c pl 4 3 3V i 334F 104F POWER SUPPLY DECOUPLING FOR 1 Voenp Voenp EACH POWER PIN FERRITE BEAD PVDD i USO 33uF A0pF POWER SUPPLY DECOUPLING FOR 1 AGND DGND Vacnp Vacno EACH POWER PIN FERRITE BEAD 4 AVDD o 3 3V r 334F 104F POWER SUPPLY DECOUPLING FOR 1 S7AGND S7AcnD EACH POWER PIN FERRITEBEAD DVDD 5 5 3 3V 1 8V Tour 10uF o4yF 0 01NF POWERSUPPLY T DECOUPLING FOR 1 AGND Vocnp Vocnp i Poeno YoenD EACH POWER PIN OO 3 OFB a a a o POO 100nF 88608 MO azaag RO 100nF a E Wi PAQ H E ir QAIN2 P50 H LL OO AIN P6O MULTIFORMAT PIXEL PORT o H EN ADV7188 B mu O AIN P8 P19 TO P10 10 BIT i ITU R BT 656 PIXEL DATA AT 27MHz 1 H CO AIN9 PIO P9 TO PO Cb AND Cr 20 BIT 1 a P10 O 1 ITU R BT 656 PIXEL DATA AT 13 5MHz o QAIN4 P10 1 P19 TO P10 Y 20 BIT Pr ITU R BT 656 PIXEL DATA AT 13 5MHz C AIN10 PAZ Soe SS Sara Sam
194. raming code FC and a number of data bytes n The data packet in the ancillary stream includes only the FC and data bytes The VBI WORD X in the ancillary data stream has the format described in Table 73 Table 73 Structure of VBI Data Words in Ancillary Stream Byte Ancillary Data Byte Number Type ByteDescription VBI WORD 1 FCO Framing Code 23 16 VBI WORD 2 FC1 Framing Code 15 8 VBI_WORD_3 FC2 Framing Code 7 0 VBI WORD 4 DB1 First data byte VBI WORD N43 DBn Last n data byte VDP Framing Code The length of the actual framing code depends on the VBI data standard For uniformity the length of the framing code reported in the ancillary data stream is always 24 bits For standards with a shorter framing code length the extra LSB bits are set to 0 The valid length of the framing code can be decoded from the VBI DATA STD bit available in IDO UDW1 The framing code is always reported in the reverse order of transmission Table 74 shows the framing code and its valid length for VBI data standards supported by VDP Example For teletext B WST the framing code byte is 11100100 0xE4 with bits shown in the order of transmission Thus VBI WORD 1 0x27 VBI WORD 2 0x00 and VBI WORD 3 0x00 Translating these into UDWSs in the ancillary data stream for the nibble mode UDWS 5 2 0010 UDW6 5 2 0111 UDW7 5 2 0000 undefined bits automatically set to 0 UDWS 5 2 0000 undefined bits
195. read The value is cleared by an lC read this is a self clearing bit 2 FB STATUS 2 FB STAT The value of the FB input pin at the time of the read 3 FB STATUS 3 FB HIGH A high value indicates that there has been a rising edge on FB since the last lC read The value is cleared by an lC read this is a self clearing bit Rev A Page 20 of 112 ADV7188 GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip POWER SAVING MODES Power Down PDBP Address 0x0F 2 The digital core of the ADV7188 can be shut down by using the PWRDN pin or the PWRDN bit The PDBP bit determines which of the two controls has the higher priority The default is to give the pin PWRDN priority This allows the user to have the ADV7188 powered down by default O default The digital core power is controlled by the PWRDN pin the bit is disregarded 1 The bit has priority the pin is disregarded PWRDN Address 0x0F 5 Setting the PWRDN bit switches the ADV7188 into a chip wide power down mode The power down stops the clock from entering the digital section of the chip thereby freezing its operation No PC bits are lost during power down The PWRDN bit also affects the analog blocks and switches them into low current modes The I C interface itself is unaffected and remains operational in power down mode The ADV7188 leaves the power down state if the PWRDN bit is set to O via TC or if
196. recommended 28 63636 MHz frequency Table 76 STDI Results for Video Standards SD PR and HD ENABLE STDI FUNCTION STDI_LINE_COUNT_MODE 1 MONITORS Video Standard BL 13 0 LCF 10 0 LCVS 4 0 shea 525160 14552280 261450 3 3 No 240p 60 14552 80 261450 2 2 625i 50 14653 80 311450 2 2 SYSTEM HAS 288p 50 14654 80 313450 2 2 480p 60 7271 40 524450 5 2 720p 50 6101 40 749 50 4 2 720p 60 5083 40 749 50 4 2 1035i 30 6780 40 562450 5 2 1080i 25 7322 40 1249450 0 2 1080i 30 6780 40 561 50 4 2 1080p 25 8137240 1124450 4 2 1080p 50 4064 40 1124 50 442 1080p 60 3385 40 1124450 4 2 YES 11521 50 Wide 7321 40 623 50 o 2 1152i 50 Full 7321240 623450 4 2 REAO AND INTERNETEKO LCF 10 0 LCVS 4 0 AND FCL 12 0 ADV7188 TO DETERMINE INPUT STANDARD SYSTEM SUPPORTS INPUT STANDARD 05478 056 Figure 37 Example Connection of SOY pin SYSTEM FLAGS RECONEIGURE UNSUPPORTED SYSTEM APPROPRIATELY INPUT 05478 055 Figure 38 Example Use of STDI Block Rev A Page 63 of 112 ADV7188 PC READBACK REGISTERS Teletext Because teletext is a high data rate standard the decoded bytes are available only as ancillary data However a TTX_AVL bit is provided in PC so that the user can check whether the VDP has detected teletext Note that the TTXT AVL bit is a plain status bit and does not use the protocol identif
197. red line after VBI on odd field in PAL 1 0 VBI ends one line later Line 24 1 1 VBI ends two lines later Line 25 NVBIELCM 1 0 NTSC VBI even field 0 0 VBI ends one line earlier Line 282 Controls position of first active luma comb mode 0 1 ITU R BT 470 compliant Line 283 comb filtered line after VBI on even field in NTSC 110 VBI ends one line later Line 284 1 1 VBI ends two lines later Line 285 NVBIOLCM 1 0 NTSC VBI odd field 0 0 VBI ends one line earlier Line 20 Controls position of first active luma comb mode 0 1 ITU R BT 470 compliant Line 21 comb filtered line after VBI on odd field in NTSC 110 VBI ends one line later Line 22 1 1 VBI ends two lines later Line 23 OxEC V Blank Control 2 PVBIECCM 1 0 PAL VBI even field 0 0 Color output beginning Line 335 Controls the position of first line chroma comb mode that outputs color after VBI on 0 1 ITU R BT 470 compliant color even field in PAL output beginning Line 336 1 0 Color output beginning Line 337 1 1 Color output beginning Line 338 PVBIOCCM 1 0 PAL VBI odd field ojo Color output beginning Line 22 Controls the position of first line chroma comb mode 0 1 ITU R BT 470 compliant color that outputs color after VBI on output beginning Line 23 odd field in PAL 1 0 Color output beginning Line 24 1 1 Color output beginning Line 25 NVBIECCM 1 0 NTSC VBI even field 0 0 Color output beginning Line 282 Controls the position of first li
198. rocessor SDP The analog front end uses differential channels for each ADC to ensure high performance in mixed signal applications The front end also includes a 12 channel input mux that enables multiple video signals to be applied to the ADV7188 Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7188 The ADCs are configured to run in 4x oversampling mode The ADV7188 has optional antialiasing filters on each of the four input channels The filters are designed for standard definition SD video with approximately 6 MHz bandwidth SCART and overlay functionality are enabled by the ability of the ADV7188 to process CVBS and standard definition RGB signals simultaneously Signal mixing is controlled by the fast blank FB pin STANDARD DEFINITION PROCESSOR SDP The ADV7188 is capable of decoding a large selection of baseband video signals in composite S video and component formats The video standards that are supported include PAL B D I G H PAL 60 PAL M PAL N PAL Nc NTSC M J NTSC 4 43 and SECAM B D G K L The ADV7188 can automatically detect the video standard and process it accordingly The ADV7188 has a 5 line superadaptive 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal T
199. rved OxF9 VS Mode Control EXTEND VS MAX FREQ Limit maximum vsync frequency to 66 25 Hz 475 lines frame Limit maximum vsync frequency to 70 09 Hz 449 lines frame EXTEND VS MIN FREQ Limit minimum vsync frequency to 42 75 Hz 731 lines frame Limit minimum vsync frequency to 39 51 Hz 791 lines frame VS COAST MODE 1 0 0 0 Autocoast mode This value sets up the output coast 0 1 50 Hz coast mode frequency 1 0 60 Hz coast mode 1 1 Reserved Reserved OxFB Peaking Control PEAKING GAIN 7 0 These bits increase decrease the gain for high frequency portions of the video signal OxFC Coring Threshold 2 DNR_TH2 7 0 DNR Threshold 2 These bits specify the maximum edge that is interpreted as noise and is therefore blanked 1 Shading indicates default settings Rev A Page 98 of 112 USER SUB MAP ADV7188 The collective name for the subaddress registers in Table 106 is user sub map To access the user sub map SUB_USR_EN in Register Address 0x0E user map must be programmed to 1 Table 106 User Sub Map Register Details Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 64 40 Interrupt RW INTRO DUR INTRO DUR MV INTRO MV INTRO MPU STIM INTRO
200. ry data identification word SDID by programming the ADF_DID 4 0 and ADF_SDID 5 0 bits respectively as explained in the following sections ADF_DID 4 0 User Specified Data ID Word in Ancillary Data Address 0x62 4 0 User Sub Map These bits select the DID to be inserted into the ancillary data stream with the data decoded by the VDP The default value of ADF_DID 4 0 is 10101 ADF_SDID 5 0 User Specified Secondary Data ID Word in Ancillary Data Address 0x63 5 0 User Sub Map These bits select the SDID to be inserted in the ancillary data stream with the data decoded by the VDP The default value of ADF_SDID 5 0 is 101010 DUPLICATE ADE Enable Duplication Spreading of Ancillary Data over Y and C Buses Address 0x63 7 User Sub Map This bit determines whether the ancillary data is duplicated over both the Y and C buses or if the data packets are spread between the two channels 0 default The ancillary data packet is spread across the Y and C data streams 1 The ancillary data packet is duplicated on the Y and C data streams ADF MODE 1 0 Determine the Ancillary Data Output Mode Address 0x62 6 5 User Sub Map These bits determine if the ancillary data output mode is in byte mode or nibble mode Table 70 ADF MODE 1 0 ADF_MODE 1 0 Description 00 default Nibble mode 01 Byte mode no code restrictions 10 Byte mode but 0x00 and OxFF are prevented 0x00 replaced by 0x01 OxFF
201. s 00011 indicating the NTSC field toggle position For all NTSC PAL field timing controls both the F bit in the AV code and the field signal on the FIELD DE pin are modified PVBEGDELO PAL Vsync Begin Delay on Odd Field Address OxES 7 0 default No delay 1 Delays vsync going high on an odd field by a line relative to PVBEG PVBEGDELE PAL Vsync Begin Delay on Even Field Address OxES 6 O default No delay 1 default Delays vsync going high on an even field by a line relative to PVBEG PVBEGSIGN PAL Vsync Begin Sign Address OxES 5 0 Delays the beginning of vsync Set for user manual programming 1 default Advances the beginning of vsync Not recommended for user programming PVBEG 4 0 PAL Vsync Begin Address 0xE8 4 0 The default value of PVBEG is 00101 indicating the PAL vsync begin position For all NTSC PAL vsync timing controls both the V bit in the AV code and the vsync on the VS pin are modified Register Register Name Write 0x31 Vsync Field Control 1 Ox1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Position 1 0x00 0x35 Hsync Position 2 0x00 0x36 Hsync Position 3 0x7D 0x37 Polarity OxA1 OxE8 PAL V bit begin 0x41 OxE9 PAL V bit end 0x84 OxEA PAL F bit toggle 0x06 Rev A Page 50 of 112 ADV7188 FIELD 1 624 625 1 2 3 4 5 6 7 8 9 10 ee OUTPUT VIDEO PVEND 4 0 0x4 PFTOG 4 0 0
202. s allowed 1 The Cr and Cb values can be swapped LLC PAD SEL 2 0 LLC1 Output Selection Address Ox8F 6 4 The following PC write allows the user to select between LLC1 nominally at 27 MHz and LLC2 nominally at 13 5 MHz The LLC2 signal is useful for LLC2 compatible wide bus 16 20 bit output modes See the OF SEL 3 0 Output Format Selection Address 0x03 5 2 section for additional information The LLC2 signal and data on the data bus are synchronized By default the rising edge of LLC1 LLC2 is aligned with the Y data the falling edge occurs when the data bus holds C data The polarity ofthe clock and therefore the Y C assignments for the clock edges can be altered by using the polarity LLC pin 000 default The output is nominally 27 MHz LLC on the LLCI1 pin 101 The output is nominally 13 5 MHz LLC on the LLCI pin Output of Data Port Pins P 19 0 Processor Format and Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Video Output 8 Bit 4 2 2 YCrCb 7 0 Video Output 10 Bit 4 2 2 YCrCb 9 0 Video Output 16 Bit 4 2 2 Y 7 0 CrCb 7 0 Video Output 20 Bit 4 2 2 Y 9 0 CrCb 9 0 Table 102 Standard Definition Pixel Port Modes Pixel Port Pins P 19 0 P 19 10 P9 9 0 OF SEL 3 0 Format P 19 12 P 11 10 P 9 2 P 1 0 0000 10 Bit at LLC1 4 2 2 YCrCb 9 2
203. s bit delays the V bit going 0 No delay low by one line relative to NVEND odd field 1 Additional delay by one line OxE7 NTSC F Bit Toggle NFTOG 4 0 These bits control the number 0 0 0 NTSC default of lines after Icount rollover to toggle F signal NFTOGSIGN 0 Setto low when manual programming 1 Not suitable for user programming NFTOGDELE This bit delays the F transition No delay by one line relative to NFTOG even field Additional delay by one line NFTOGDELO This bit delays the F transition O No delay by one line relative to NFTOG odd field 1 Additional delay by one line OxE8 PAL V Bit Begin PVBEG 4 0 These bits control the number of 0 0 1 PAL default ITU R BT 656 lines after Icounr rollover to set V high PVBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PVBEGDELE This bit delays the V bit going No delay high by one line relative to PVBEG even field Additional delay by one line PVBEGDELO This bit delays the V bit going 0 No delay high by one line relative to PVBEG odd field 1 Additional delay by one line OxE9 PAL V Bit End PVEND 4 0 These bits control the number of 1 01 PAL default ITU R BT 656 lines after Icounr rollover to set the V bit low PVENDSIGN 0 Setto low when manual programming 1 Not suitable for user programming PVENDDELE This bit delays the V bit going No delay low by one line relative to PVEND even field Additional delay by one line PVENDDELO This bit dela
204. s in sync with the beginning of active video for example immediately after the last VBI video line LB SL 3 0 allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis The letterbox detection ends in the middle of the field Detection at the End of a Field The ADV7188 expects at least six continuous lines of black video at the bottom of a field before reporting the number of lines actually found via the LB LCB 7 0 value The activity window for letterbox detection end of field starts in the middle of an active field Its end is programmable via LB EL 3 0 Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box If the ADV7188 finds at least two black lines followed by more nonblack video for example the subtitle followed by the remainder of the bottom black block it reports a midcount via LB LCM 7 0 If no subtitles are found LB LCM 7 0 reports the same number as LB LCB 7 0 There is a two field delay in the reporting of line count parameters There is no letterbox detected bit Read the LB LCT 7 0 and LB LCB 7 0 bit values to conclude whether or not the letterbox type of video is present in the software LB LCT 7 0 Letterbox Line Count Top Address 0x9B 7 0 LB LCM 7 0 Letterbox Line Count Mid Address 0x9C 7 0 LB LCB 7 0 Letterbox Line Count Bottom Address 0x9D 7 0 Table 96 LB L
205. s the number of black lines detected in the bottom half of active video if subtitles are detected Ox9D Letterbox 3 Read Only LB LCB 7 0 Letterbox data register Reports the number of black lines detected at the bottom of active video This feature examines the active video at the start and end of each field enabling format detection even if the video is not accompanied by a CGMS or WSS sequence OxB1 Standard Ident 1 Read Only BL 13 8 Block length data register BL 13 0 reports the number of clock cycles in a block of eight lines of incoming video Data is valid only if STDI DVALID is 1 and STDI LINE COUNT MODE is set to 1 Reserved Reserved STDI_DVALID Standard identification data valid readback Indicates that BL 13 0 LCF 10 0 and LCVS 4 0 are not valid parameters Indicates that BL 13 0 LCF 10 0 and LCVS 4 0 are valid parameters OxB2 Standard Ident 2 Read Only BL 7 0 Block length data register BL 13 0 reports the number of clock cycles in a block of eight lines of incoming video OxB3 Standard Ident 3 Read Only LCF 10 8 Line count in field Reports the number of lines between two vsyncs or one field Data is valid only if STDI DVALID is 1 and STDI LINE COUNT MODE is set to 1 LCVS 4 0 Reports the number of lines within a vertical synchronization period Data is valid only if STDI DVALID is 1 and STDI
206. selecting the offset for the Cr channel OxE3 SD Saturation Cb SD SAT CB 7 0 These bits adjust the 1 0 0 0 0 0 0 O0 Chroma gain 0 dB saturation of the picture by affecting gain on the Cb channel OxE4 SD Saturation Cr SD_SAT_CR 7 0 These bits adjust the 1 0 0 0 0 0 0 0 Chromagain 0dB saturation of the picture by affecting gain on the Cr channel Rev A Page 94 of 112 Bit Address Register Bit Description 7 5 4 3 2 Comments Notes OxE5 NTSC V Bit Begin NVBEG 4 0 Number of lines after Icounr 0 0 1 NTSC default ITU R BT 656 rollover to set V high NVBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programming NVBEGDELE This bit delays the V bit going No delay high by one line relative to NVBEG even field Additional delay by one line NVBEGDELO This bit delays the V bit going 0 No delay high by one line relative to NVBEG odd field 1 Additional delay by one line OxE6 NTSC V Bit End NVEND 4 0 These bits control the number 0 0 1 NTSC default ITU R BT 656 of lines after Icounr rollover to set V low NVENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming NVENDDELE This bit delays the V bit going No delay low by one line relative to NVEND even field Additional delay by one line NVENDDELO Thi
207. should be made available in the C registers the user must program I2C GS VPS PDC UTC 1 0 Address 0x9C user sub map DC GS VPS PDC UTC VDP 1 0 Address 0x9C 6 5 User Sub Map These bits specify which standard result is available for PC readback Table 82 I2C GS VPS PDC UTC 1 0 Function I2C GS VPS PDC UTC 1 0 Description 00 default Gemstar 1x 2x 01 VPS 10 PDC 11 UTC GS PDC VPS UTC CLEAR GS PDC VPS UTC Clear Address 0x78 4 User Sub Map Write Only Self Clearing 1 Reinitializes the GS PDC VPS UTC data readback registers GS PDC VPS UTC AVL GS PDC VPS UTC Available Address 0x78 4 User Sub Map Read Only 0 GS PDC VPS or UTC data was not detected 1 GS PDC VPS or UTC data was detected VDP GS VPS PDC UTC Readback Registers Addresses 0x84 to 0x90 User Sub Map See Table 83 VPS The VPS data bits are biphase decoded by the VDP The decoded data is available in both the ancillary stream and in the I C readback registers VPS decoded data is available in the VDP GS VPS PDC UTC Oto VDP VPS PDC UTC 12 registers Addresses 0x84 to 0x90 user sub map The GS VPS PDC UTC AVL bit is set if the user had programmed I2C GS VPS PDC UTC to 01 as explained in Table 82 Gemstar The Gemstar decoded data is available in the ancillary stream and any one line of Gemstar is available in IC registers for evaluation purposes To obtain the Gemstar results in the PC reg
208. sync from going low on an even field by a line relative to NVEND NVENDSIGN NTSC Vsync End Sign Address 0xE6 5 0 default Delays the end of vsync Set for user manual programming 1 Advances the end of vsync Not recommended for user programming NVEND 4 0 NTSC Vsync End Address 0xE6 4 0 The default value of NVEND is 00100 indicating the NTSC vsync end position Rev A Page 49 of 112 ADV7188 For all NTSC PAL vsync timing controls both the V bit in the AV code and the vsync on the VS pin are modified NFTOGDELO NTSC Field Toggle Delay on Odd Field Address OxE7 7 O default No delay 1 Delays the field toggle transition on an odd field by a line relative to NFTOG NFTOGDELE NTSC Field Toggle Delay on Even Field Address OxE7 6 0 No delay 1 default Delays the field toggle transition on an even field by a line relative to NFTOG ADVANCE TOGGLE OF FIELD BY NFTOG 4 0 NOT VALID FOR USER DELAY TOGGLE OF FIELD BY NFTOG 4 0 PROGRAMMING ODD FIELD YES NO 1 0 0 1 05478 031 FIELD TOGGLE Figure 31 NTSC Field Toggle Table 63 Recommended User Settings for PAL see Figure 33 NFTOGSIGN NTSC Field Toggle Sign Address OxE7 5 0 Delays the field transition Set for manual programming 1 default Advances the field transition Not recommended for user programming NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 The default value of NFTOG i
209. t value Care has been taken that in 8 bit systems the two LSBs do not carry vital information EP and EP The EP bit is set to ensure even parity on the data word D 8 0 Even parity means there is always an even number of 1s within the D 8 0 bit arrangement This includes the EP bit EP describes the logic inverse of EP and is output on D 9 The EP is output to ensure that the reserved codes of 00 and FF cannot occur EF Even field identifier EF 1 indicates that the data was recovered from a video line on an even field 2x This bit indicates whether the data sliced was in Gemstar 1x or 2x format A high indicates Gemstar 2x format The 2x bit determines whether the raw information retrieved from the video line was two or four bytes The state of the GDECAD bit affects whether the bytes are transmitted straight that is two bytes transmitted as two bytes or whether they are split into nibbles that is two bytes transmitted as four half bytes Padding bytes are then added where necessary line 3 0 This entry provides a code that is unique for each of the 16 possible source lines of video from which Gemstar data may have been retrieved Refer to Table 94 and Table 95 DC 1 0 Data count value The number of UDWs in the packet divided by 4 The number of UDWs in any packet must be an integral number of 4 Padding is required at the end if necessary as set in ITU R BT 1364 See Table 85 CS 8 2 The checksum is pro
210. terrupt in Write Only Clears VDP CCAPD O Register 0x4E for the CC Gemstar CGMS WSS VPS Reserved PDC UTC and VITC data can VDP CGMS WSS CHNGD CLR Does not clear be initiated by using the VDP Clears VDP CGMS WSS CHNGD Q data slicer Reserved x VDP GS VPS PDC UTC CHNG CLR Does not clear Clears VDP GS VPS PDC UTC CHNG Q Reserved VDP VITC CLR Does not clear Clears VDP VITC OQ Reserved 0x50 Interrupt Mask 4 VDP CCAPD MSKB Masks VDP CCAPD Q Note that an interrupt in Unmasks VDP CCAP D Q Register Ox4E for the CC Gemstar CGMS WSS VPS Reserved PDC UTC and VITC data can VDP_CGMS_WSS_CHNGD_MSKB Masks VDP CGMS WSS CHNGD Q be initiated by using the VDP Unmasks VDP CGMS WSS CHNGD Q data slicer Reserved x VDP GS VPS PDC UTC CHNG MSKB Masks VDP GS VPS PDC UTC CHNG Q Unmasks VDP GS VPS PDC UTC CHNG Q Reserved VDP VITC MSKB Masks VDP VITC Q Unmasks VDP VITC Q Reserved 0x60 VDP Config 1 VDP TTXT TYPE MAN 1 0 PAL teletext ITU R BT 653 625 50 A NTSC reserved PAL teletext ITU R BT 653 625 50 B WST NTSC teletext ITU R BT 653 525 60 B PAL teletext ITU R BT 653 625 50 C NTSC teletext ITU R BT 653 525 60 C or EIA516 NABTS PAL teletext ITU R BT 653 625 50 D NTSC teletext ITU R BT 653 525 60 D VDP_TTXT_TYPE_MAN_ENABLE User programming of teletext type disabled User programming of teletext type enabled WST_PKT_DECOD_DISABLE 0 Enables hamming decoding of WST pac
211. the validity of the BL LCVS LCF and STDI INTLCD parameters To prevent false readouts especially during the signal acquisition the DVALID bit only goes high after recording four fields with the same length As a result the measurements can require up to five fields to finish STDI LINE COUNT MODE Address 0x86 3 O default Disables the STDI functionality 1 Enables STDI functionality This enables valid readback of the STDI block registers BL 13 0 Block Length Readback Address OxB1 5 0 Address OxB2 7 0 XX XXXX XXXX XXXX Number of clock cycles in a block of eight lines of incoming video Data is only valid if STDI DVALID is high LCVS 4 0 Line Count in Vsync Readback Address 0xB3 7 3 X XXXX Number of lines within a vertical synchronization period Data is only valid if STDI_DVALID is high LCF 10 0 Line Count in Field Readback Address 0xB3 2 0 Address 0xB4 7 0 XX XXXX XXXX Number of lines between two vsyncs per one field frame Data is only valid if STDI DVALID is high FCL 12 0 1 256 of Field Length in Number of Crystal Clocks Read back Address OxCA 4 0 Address OxCB 7 0 XXX Number of crystal clocks with the recommended 28 63636 MHz frequency in 1 256 of a field Data is only valid if STDI_DVALID is high Rev A Page 62 of 112 ADV7188 STDI Readback Values for SD PR and HD The readback values provided are only valid when using a crystal with the
212. the vertical blanking interval VBI e The range of data values permitted in the output data stream e The relative delay of luma vs chroma signals Note that some of the decoded VBI data is inserted during the horizontal blanking interval See the Gemstar Data Recovery section for more information BT656 4 ITU R BT 656 4 Enable Address 0x04 7 Revisions 3 and 4 of the ITU R BT 656 standard have different positions for toggling the V bit within the SAV EAV codes for NTSC The BT656 4 bit allows the user to select an output mode that is compliant with either the previous or new standard For more information visit the International Telecommunication Unions website Note that the standard change affects only NTSC and has no bearing on PAL 0 default The ITU R BT 656 3 specification is used The V bit goes low at EAV of Lines 10 and 273 1 The ITU R BT 656 4 specification is used The V bit goes low at EAV of Lines 20 and 283 SD DUP AV Duplicate AV Codes Address 0x03 0 Depending on the output interface width it may be necessary to duplicate the AV codes from the luma path into the chroma path In an 8 10 bit wide output interface Cb Y Cr Y interleaved data the AV codes are defined as FF 00 00 AV with AV being the transmitted word that contains information about H V F In this output interface mode the following assignment takes place Cb FE Y 00 Cr 00 and Y AV Rev A Page 43 of 112 ADV7188 In
213. ther with that of the LTA 1 0 bits The chroma can be delayed or advanced only in chroma pixel steps One chroma pixel step is equal to two luma pixels The programmable delay occurs after demodulation when no delay by luma pixel steps are allowed For manual programming use the following defaults e CVBS input CTA 2 0 011 e Y Cinput CTA 2 0 101 e YPrPb input CTA 2 0 110 Table 60 CTA Function CTA 2 0 Description 000 Not used 001 Chroma plus two chroma pixels early 010 Chroma plus one chroma pixel early 011 default No delay 100 Chroma minus one chroma pixel delayed 101 Chroma minus two chroma pixels delayed 110 Chroma minus three chroma pixels delayed 111 Not used LTA 1 0 Description 00 default No delay 01 Luma 1 clock 37 ns delayed 10 Luma 2 clock 74 ns early 11 Luma 1 clock 37 ns early SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only e HSB 10 0 sets beginning of HS signal e HSE 10 0 sets end of HS signal e PHS sets polarity of HS The HS begin HSB and HS end HSE bits allow the user to position the HS output pin anywhere within the video line The values in HSB 10 0 and HSE 10 0 are measured in pixel units from the falling edge of HS Using both values the user can program both the position and length of the HS output signal HSB 10 0 HS
214. therefore the comb filter algorithms can be used to separate luma and chroma with high accuracy For nonstandard video signals the frequency relationship may have an offset and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of a shaping filter An automatic mode is provided In this mode the ADV7188 evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard YFSM WYSFMOVR and WYSFM allow the user to override the automatic decisions manually in part or in full see Figure 15 The luma shaping filter has three sets of control bits e YSFM 4 0 Address 0x17 allow the user to manually select a shaping filter mode applied to all video signals or to enable an automatic selection dependent on video quality and video standard e WYSFMOVR Address 0x18 allows the user to override the automatic WYSFM filter selection and enable manual selection of the WYSFM filter via WYSFM 4 0 e WYSFM 4 0 Address 0x18 allow the user to select a different shaping filter mode for good quality composite CVBS component YPrPb and S video Y C input signals Rev A Page 31 of 112 ADV7188 In automatic mode the system preserves the maximum possible Table 36 YSFM Function bandwidth for good CVBS sources because they can successfully YSFM 4 0 Description be combed and for luma co
215. trast reduction feature is enabled and the fast blank signal is interpreted as a trilevel signal Contrast Mode CNTR MODE 1 0 Address OxF1 3 2 The contrast level in the selected contrast reduction box is selected using the CNTR MODE 1 0 bits Table 14 CNTR MODE 1 0 Function CNTR_MODE 1 0 Description 00 default 25 01 50 10 75 11 100 Rev A Page 18 of 112 Fast Blank and Contrast Reduction Programmable Thresholds The internal fast blank and contrast reduction signals are resolved from the trilevel FB signal using two comparators as shown in Figure 11 To facilitate compliance with different input level standards the reference level to these comparators is programmable via FB_LEVEL 1 0 and CNTR_LEVEL 1 0 The resulting thresholds are given in Table 15 FB LEVEL 1 0 Address 0xF1 5 4 These bits control the reference level for the fast blank comparator CNTR LEVEL 1 0 Address OxF1 7 6 These bits control the reference level for the contrast reduction comparator FB PIN PROGRAMMABLE THRESHOLDS 1 0 1 0 CNTR ENABLE CNTR LEVEL FB LEVEL FAST BLANK COMPARATOR CONTRAST REDUCTION COMPARATOR ADV7188 FAST BLANK 05478 011 Figure 11 Fast Blank and Contrast Reduction Programmable Threshold Table 15 Fast Blank and Contrast Reduction Programmable Threshold I C Controls Fast Blanking Threshold V Contrast Reductio
216. ts can be used to program a desired which mode LMG 11 0 operates manual chroma gain or to read back the actual gain value used Reserved ti Setto 1 LAGT 1 0 Luma automatic gain timing 0 0 Slow TC 2 sec Only has an effect if LAGC 2 0 is set to These bits allow adjustment of the luma AGC 0 1 Medium TC 1 sec 010 or 100 autogain tracking speed 1 0 Fast TC 0 2 sec 1 1 Adaptive 0x30 Luma Gain Control 2 LG 7 0 LMG 7 0 Luma manual gain These x x x x x x x x LMG 11 0 1128d gain is 1 in Minimum value of NTSC is 1024 bits can be used to program a desired manual NTSC LMG 11 0 1222d gain G 0 90 and of PAL is 1024 G 0 84 chroma gain or to read back the actual gain is 1 in PAL Maximum value of NTSC is 4095 value used G 3 63 and of PAL is 4095 G 3 35 Rev A Page 89 of 112 ADV7188 Bit Address Register Bit Description 5 4 3 2 1 0 Comments Notes 0x31 Vsync Field Reserved 0 1 0 Set to default Control 1 HVSTIM This bit selects where within a line of 0 Start of line relative to HSE HSE hsync end video the VS signal is asserted 1 Start of line relative to HSB HSB hsync begin NEWAVMODE Sets the EAV SAV mode 0 EAV SAV codes generated to suit ADI encoders 1 Manual VS FIELD position controlled by Registers 0x32 0x33 and
217. ture There is a functional overlap with the HUE 7 0 bits Table 32 SD OFF CR 7 0 Function SD OFF CR 7 0 Description 0x80 default 0 mV offset applied to the Cr channel 0x00 568 mV offset applied to the Cr channel OxFF 568 mV offset applied to the Cr channel BRI 7 0 Brightness Adjust Address 0x0A 7 0 These bits control the brightness of the video signal and allow the user to adjust the brightness of the picture Table 33 BRI 7 0 Function BRI 7 0 Description 0x00 default Offset of the luma channel 0 mV Ox7F Offset of the luma channel 204 mV 0x80 Offset of the luma channel 204 mV HUE 7 0 Hue Adjust Address 0x0B 7 0 These bits contain the value for the color hue adjustment and allow the user to adjust the hue of the picture HUE 7 0 has a range of 90 with a value of 0x00 equivalent to an adjustment of 0 The resolution of HUE 7 0 for one bit is 0 7 The hue adjustment value is fed into the AM color demodulation block Therefore it only applies to video signals that contain chroma information in the form of an AM modulated carrier CVBS or Y C in PAL or NTSC It does not affect SECAM and does not work on component video inputs YPrPb Table 34 HUE 7 0 Function HUE 7 0 Description 0x00 default Phase of the chroma signal 0 Ox7F Phase of the chroma signal 90 0x80 Phase of the chroma signal 90 DEF Y 5 0 Default
218. ues represent Gemstar or CC specific values Table 90 NTSC CC Data Half Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP Word1 7 4 0 0 User data words 7 EP EP 0 0 CCAP Word 3 0 0 0 User data words 8 EP EP 0 0 CCAP Word 7 4 0 0 User data words 9 EP EP 0 0 CCAP Word 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum The bold values represent Gemstar or CC specific values Table 91 NTSC CC Data Full Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 CCAP Word 1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum The bold values represent Gemstar or CC specific values Rev A Page 73 of 112 ADV7188 Table 92 PAL CC Data Half Byte Mode
219. ut the internal status of the ADV7188 See the CIL 2 0 Count Into Lock Address 0x51 2 0 and the COL 2 0 Count Out of Lock Address 0x51 5 3 sections for information on the timing Depending on the setting of the FSCLE bit the IN_LOCK 0 and LOST_LOCK 1 bits of Status Register 1 are based solely on the horizontal timing information or on the horizontal timing and lock status of the color subcarrier See the FSCLE Fsc Lock Enable Address 0x51 7 section AD RESULT 2 0 Autodetection Result Address 0x10 6 4 These bits report the findings from the autodetection block For more information on enabling the autodetection block see the ADV7188 General Setup section For information on configuring this block see the Autodetection of SD Modes section Table 20 AD RESULT Function AD RESULT 2 0 Description 000 NTSC M J 001 NTSC 443 010 PALM 011 PAL 60 100 PAL B G H I D 101 SECAM 110 PAL Combination N 111 SECAM 525 Status Register 2 7 0 Address 0x12 7 0 See Table 22 Status Register 3 7 0 Address 0x13 7 0 See Table 23 Table 21 Status Register 1 Function Status Register 1 7 0 Bit Name Description 0 IN LOCK In lock now 1 LOST LOCK Lost lock since last read of this register 2 FSC LOCK Fsc locked now 3 FOLLOW PW AGC follows peak white algorithm 4 AD RESULT O Result of autodetection 5 AD RESULT 1 Result of autodetection 6 AD RE
220. vided to determine the integrity of the ancillary data packet It is calculated by summing up D 8 2 of DID SDID data count byte and all UDWs and ignoring any overflow during the summation Because all data bytes that are used to calculate the checksum have their two LSBs set to 0 the CS 1 0 bits are also always 0 CS 8 describes the logic inversion of CS 8 The value CS 8 is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and OxFF do not occur Table 86 to Table 91 outline the possible data packages Gemstar 2x Format Half Byte Output Mode Half byte output mode is selected by setting GDECAD to 0 full byte output mode is selected by setting GDECAD to 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Gemstar 1x Format Half Byte Output Mode Half byte output mode is selected by setting GDECAD to 0 full byte output mode is selected by setting GDECAD to 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Rev A Page 71 of 112 ADV7188 Table 86 Gemstar 2x Data Half Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed prea
221. wn ADC1 PWRDN_ADC_O This bit enables power down of ADCO ADCO normal operation Power down ADCO Reserved Set as default Ox3D Manual Window Control Reserved Set to default CKILLTHR 2 0 Color kill threshold Kill at 0 596 Kill at 1 596 Kill at 2 596 Kill at 4 096 Kill at 8 596 Kill at 16 096 Kill at 32 096 2 2 2 2lolololo 2 2l loloi2i iolo o l 0 O Reserved CKE 1 enables the color kill function and must be enabled for CKILLTHR 2 0 to take effect See Table 48 for kill thresholds for SECAM Reserved Set to default Rev A Page 91 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 0 Comments Notes 0x41 Resample Control Reserved 0 0 0 0 0 1 Set to default SFL_INV This bit controls the behavior of the 0 SFL compatible with ADV717x and PAL switch bit ADV73xx encoders SFL compatible with ADV7190 ADV7191 ADV7194 encoders Reserved 0 Set to default 0x48 Gemstar Control 1 GDECEL 15 8 See the Comments column 0 0 0 0 0 0 0 0 GDECEL 15 0 The 16 individual LSB Line 10 MSB Line 25 0x49 Gemstar Control2 GDECEL 7 0 See the Comments column olo o o o o o Jo enable bits that select the lines of Default do not check for Gemstar video even field Lines 10 to
222. x3 FIELD 2 am 312 313 314 315 316 317 318 319 320 321 322000 335 336 337 1 OUTPUT 2 VIDEO i PFTOG 4 0 0x3 Figure 32 PAL Default ITU R BT 656 the Polarities of HS VS and FIELD are Embedded in the Data 05478 032 623 624 625 output 7i VIDEO ER Hs OUTPUT uF MEME HEN OUTPUT FIELD PVBEG 4 0 0x1 PVEND 4 0 0x4 OUTPUT d PFTOG 4 0 0x6 FIELD 2 OUTPUT jl i VIDEO i OUTPUT i vs i d OUTPUT i gt PVBEG 4 0 0x1 PVEND 4 0 0x4 FIELD OUTPUT PFTOG 4 0 0x6 Figure 33 PAL Typical VS FIELD Positions Using Register Writes in Table 63 05478 033 Rev A Page 51 of 112 a ADVANCE BEGIN OF DELAY BEGIN OF VSYNC BY PVBEG 4 0 VSYNC BY PVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO PVBEGDELO PVBEGDELE 1 1 0 0 t ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE go 0 0 1 ADVANCE BY 0 5 LINE VSYNC BEGIN Figure 34 PAL Vsync Begin ADVANCE BY 0 5 LINE 05478 034 PVENDDELO PAL Vsync End Delay on Odd Field Address OxE9 7 O default No delay 1 Delays vsync going low on an odd field by a line relative to PVEND PVENDDELE PAL Vsync End Delay on Even Field Address 0xE9 6 O default No delay 1 Delays vsync going low on an even field by a line relative to PVEND PVEND
223. xEC 7 6 Section 43 Change to NVBIECCM 1 0 NTSC VBI Even Field Chroma Comb Mode Address OxEC 5 4 Section 43 Changes to NEWAVMODE New AV Mode Address 0x31 4 Section Change to Table 69 s Added Standard Detection and Identification Section 62 Changes to MPU Port Description Section 80 Changes to C Programming Examples Section 81 Change to Table 104 seen 82 Changes to Table 105 sss 84 Change to Table 107 t tt d 101 7 05 Revision 0 Initial Version Rev A Page 3 of 112 ADV7188 INTRODUCTION The ADV7188 is a high quality single chip multiformat video decoder that automatically detects and converts PAL NTSC and SECAM standards in the form of composite S video and component video into a digital ITU R BT 656 format The advanced highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video characteristics including tape based sources broadcast sources security and surveillance cameras and professional systems ANALOG FRONT END The ADV7188 analog front end includes four 12 bit NSV ADCs that digitize the analog video signal before applying it to the standard definition p
224. ys the V bit going 0 No delay low by one line relative to PVEND odd field 4 Additional delay by one line OxEA PALF Bit Toggle PFTOG 4 0 These bits control the number of 0 0 0 PAL default ITU R BT 656 lines after Icounr rollover to toggle the F signal PFTOGSIGN 0 Setto low when manual programming 1 Not suitable for user programming PFTOGDELE This bit delays the F transition No delay by one line relative to PFTOG even field Additional delay by one line PFTOGDELO This bit delays the F transition 0 No delay by one line relative to PFTOG odd field 1 Additional delay by one line Rev A Page 95 of 112 ADV7188 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes OxEB V Blank Control 1 PVBIELCM 1 0 PAL VBI even field 0 0 VBI ends one line earlier Line 335 Controls position of first active luma comb mode 0 1 ITU R BT 470 compliant Line 336 comb filtered line after VBI on even field in PAL 1 0 VBI ends one line later Line 337 1 1 VBI ends two lines later Line 338 PVBIOLCM 1 0 PAL VBI odd field ojo VBI ends one line earlier Line 22 Controls position of first active luma comb mode 0 1 ITU R BT 470 compliant Line 23 comb filte

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