ANALOG DEVICES AD1555 English products handbook Rev B
Contents
1. AD1555 AD1556 PIN CONFIGURATION 28 Lead PLCC P 28A AIN REFIN AIN REFCAP2 TIN AD1555 REFCAP1 TIN TOP VIEW AGND3 NC Not to Scale VA CBO VL NC NO CONNECT DO NOT CONNECT THIS PIN 44 Lead MQFP S 44A a ora 410104 2 41 m gt 44 43 42 41 40 39 138 37 36 35 34 NC IDENTIFIER CLKIN SYNC TDATA AD1556 TOP VIEW NC Not to Scale NC PWRDN RESET DGND DGND N gt a oot 6 REV 9 AD1555 AD1556 AD1555 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 AGND1 Analog Ground 2 PGAOUT Programmable Gain Amplifier Output The output of the on chip programmable gain amplifier is available at this pin Refer to Table for PGA gain settings selection 3 26 Positive Analog Supply Voltage 5 nominal 4 20 21 Va Negative Analog Supply Voltage 5 V nominal 5 AIN Mux Input Noninverting signal to the PGA mux input Refer to Table III for input selection 6 Mux Input Inverting signal to the PGA mux input Refer to Table for input selection 7 Mux Input Noninverting test signal to the PGA mux input Refer to Table for input selection 8 TINC Mux Input Inverting test signal to the PGA mux input Refer to Tabl2. 10 REV AD1555 AD1556 AD1556 PIN FUNCTION DESCRIPTIONS continued Pin No Mnemonic Description 14 15 16 17 18 19 20 25 26 29 30 31 32 35 36 37 38 43 39 DOUT DRDY RESET PWRDN CSEL TDATA SYNC CLKIN MCLK MDATA RESETD MFLG 4 Serial Data Output DOUT is used to access the conversion results or the contents of the Status Register depending on the logic state of the RSEL pin At the beginning of a read operation the first data bit is output MSB first The data changes on the rising edge of SCLK and is valid on the falling edge Data Ready A logic high output indicates that data is ready to be accessed from the Output Data Register DRDY goes low once a read operation is complete When selected the DRDY output pin has a type buffer that allows wired OR connection of multiple AD1556s Chip Select When set low the serial data interface pins DIN DOUT RWW and SCLK are active a logic high disables these pins and sets the DOUT pin to Hi Z Read Write A read operation is initiated if R W is high and CS is low A low sets the pin to Hi Z and allows a write operation to the device via the DIN pin Register Select When set high the Conversion Data Register contents are output on a read opera tion A low selects the Status Register Serial Data Input Used during a write operation Loads the Configuration R
3. MCLK Output Frequency 4 SYNC Setup Time ti 10 ns SYNC Hold Time to 10 ns CLKIN Rising to MCLK Output Falling on SYNC ts 20 ns CLKIN Falling to MCLK Output Rising ty 20 ns CLKIN Falling to MCLK Output Falling 5 20 ns MCLK Input Falling to MDATA Falling 16 30 ns Input Rising to MDATA and MFLG Valid t 100 ns TDATA Setup Time after SYNC tg 5 ns TDATA Hold Time to 5 ns RESET Setup Time tio 15 ns RESET Hold Time tu 15 ns CLKIN Falling to DRDY Rising 112 20 ns CLKIN Rising to DRDY Falling 20 ns CLKIN Rising to ERROR Falling tha 50 ns RSEL to Data Valid 55 25 ns RSEL Setup to SCLK Falling tis 10 ns DRDY to Data Valid t 25 ns DRDY High Setup to SCLK Falling tig 10 ns R W to Data Valid tio 25 ns R W High Setup to SCLK Falling t20 10 ns CS to Data Valid t21 25 ns CS Low Setup to SCLK Falling t22 10 ns SCLK Rising to DOUT Valid t23 25 ns SCLK High Pulsewidth toa 25 ns SCLK Low Pulsewidth 125 25 ns SCLK Period 156 70 ns SCLK Falling to DRDY Falling to7 20 ns CS High or Low to DOUT Hi Z tog 20 ns R W Low Setup to SCLK Falling 129 10 ns CS Low Setup to SCLK Falling t30 10 ns Data Setup Time to SCLK Falling ti 10 ns Data Hold Time after SCLK Falling 132 10 ns R W Hold Time after SCLK Falling t33 10 ns NOTES gain of the modulator is proportional to fc and MCLK frequency With DRDYBUF low only When DRDYBUF is high this timing also depends on the value of the external pull down re
4. grammable gain amplifier are shorted through an accurate internal 1 kQ resistor This combination allows accurate calibra tion of the offset of the AD1555 for each gain setting Also a system noise calibration can be done using the internal 1 kQ resistor as a noise reference Table PGA Input and Gain Control CB4 CB3 CB2 Description gt O O lt gt OOOO gt O gt Ground Input with PGA of 1 Ground Input with PGA Gain of 2 5 Ground Input with PGA Gain of 8 5 Ground Input with PGA Gain of 34 Ground Input with PGA Gain of 128 Test Inputs TIN and TIN with PGA Gain of 1 Test Inputs TIN with PGA Gain of 2 5 Test Inputs TIN and with PGA Gain of 8 5 Test Inputs TIN TIN with PGA Gain of 34 Test Inputs TIN with PGA Gain of 128 Signal Inputs AIN and with PGA Gain of 1 Signal Inputs AIN and AIN with PGA Gain of 2 5 Signal Inputs AIN and AIN with PGA Gain of 8 5 Signal Inputs AIN and AIN with PGA Gain of 34 Signal Inputs AIN and with PGA Gain of 128 Veer Input with PGA Gain of 1 Sensor Test 1 Signal inputs AIN and with AIN and inpu
5. 2 25 V to the full scale span 4 5 V after correction of the effects of the external components It is expressed in 90 GAIN ERROR STABILITY OVER TEMPERATURE change of the gain error over temperature It is expressed in 96 REV B Typical Performance Characteristics AD1555 AD1556 0 fin 24 4 2 520 SNR 116 7dB THD 120dB _ 60 8 1 80 5 5 100 E o 5 amp 120 lt 140 160 180 200 50 100 150 200 250 300 350 400 450 500 FREQUENCY Hz TEMPERATURE C TPC 1 FFT 2048 Points Full Scale MODIN Input TPC 4 Dynamic Range vs Temperature 0 35 20 30 40 _ 60 25 oO F4 80 5 5 20 100 m 15 5 120 5 140 10 160 5 180 200 0 50 100 150 200 250 300 350 400 450 500 122 121 119 118 117 116 FREQUENCY Hz DYNAMIC RANGE dB TPC 2 FFT 2048 Points Full Scale AIN Input Gain of 34 TPC 5 Dynamic Range Distribution 272 Units 150 fin 24 4Hz SNR 68 248 qz THD 120dB 140 1 5 130 m 1 G 2 5 8 t 120 lt 110 G 128 100 90 500 1000 1500 2000 2500 3000 3500 4000 55 35 15 5 25 45 65 85 105 1
6. PGA Gain of 2 5 95 102 91 5 102 dB PGA Gain of 8 5 34 95 5 108 94 5 108 dB PGA Gain of 128 108 108 dB Power Supply Rejection Ratio 50 50 dB AIN to TIN Crosstalk Isolation fw 200 Hz 130 130 dB Differential Input Current 130 130 nA TEMPERATURE RANGE Specified Performance Tmn to Tmax 55 85 0 85 C REFERENCE INPUT Input Voltage Range 2 990 3 0 3 010 2 990 3 0 3 010 Input Current 130 130 uA DIGITAL INPUTS OUTPUTS 0 3 0 8 0 3 0 8 Vin 2 0 0 3 2 0 03 Ig 10 10 10 10 10 10 10 10 Vor Igwk 2 mA 0 4 0 4 V Vou IsourcE 2 2 4 2 4 REV AD1555 AD1556 AD1555BP AD1555AP Parameter Notes Min Typ Max Min Typ Max Unit POWER SUPPLIES Recommended Operating Conditions TVA 4 75 5 5 25 4 75 5 5 25 Va 5 25 5 4 75 5 25 5 4 75 VL 4 75 5 5 25 4 75 5 5 25 Quiescent Currents I Va 8 10 8 10 mA I Vq 8 9 5 8 9 5 mA I Vi 30 42 30 42 Power Dissipation 77 96 77 96 mW PGA in Standby 56 70 56 70 mW In Power Down Mode Reference Input 3 V 650 650 uw Reference Input 0 V 250 250 uW NOTES Tested at the output word rate Fo 1 kHz Fo is the AD1556 output word rate the inverse of the sampling rate See Tables I Ia Ib for other output word rates Tested with a full scale input signal at approximately 24 Hz This parameter is guaranteed by design Tested at the output word rate Fo 1 kHz wit
7. subject to change without notice REV B 3 AD1555 AD1556 Table I Dynamic and Noise Typical Performances Input and Gain MODIN 1 048 2 5 848 8 5 19 dB PGA 34 31 dB 128 42 dB Input Range 1 6 V rms 1 6 Vrms 636 mV rms 187 mV rms 47 mV rms 12 4 mV rms Dynamic Range Fo 16 kHz 1 16 ms 40 dB 40 dB 40 dB 40 dB 40 dB 40 dB Fo 8 kHz 1 8 ms 69 dB 69 dB 69 dB 69 dB 69 dB 69 dB Fo 4 kHz 1 4 ms 98 dB 98 dB 98 dB 98 dB 97 dB 91 dB Fo 2 kHz 1 2 ms 117 dB 117 dB 116 5 dB 114 5 dB 106 5 dB 95 dB Fo 1 kHz 1 ms 120 dB 120 dB 119 5 dB 117 5 dB 109 5 dB 98 dB Fo 500 Hz 2 ms 123 dB 123 dB 122 5 dB 120 dB 112 5 dB 101 dB Fo 250 Hz 4 ms 126 dB 126 dB 125 5 dB 123 dB 115 5 dB 104 dB Equivalent Input Noise Fo 16 kHz 1 16 ms 15 5 mV rms 15 5 mV rms 6 17 mV rms 1 84 mV rms 470 rms 138 rms Fo 8 kHz 1 8 ms 560 uV rms 560 rms 220 rms 65 5 uV rms 16 4 rms 4 5 uV rms Fo 4 kHz 1 4 ms 20 rms 20 rms 8 uV rms 2 36 rms 661 nV rms 35 nV rms Fo 2 kHz 1 2 ms 2 25 rms 2 25 uV rms 952 nV rms 353 nV rms 225 nV rms 223 nV rms Fo 1 kHz 1 ms 1 59 uV rms 1 59 uV rms 674 nV rms 250 nV rms 159 nV rms 159 nV rms Fo 500 Hz 2 ms 1 13 uV rms 1 13 uV rms 477 nV rms 187 nV rms 113 nV rms 111 nV rms Fo 250 Hz 4 ms 797 nV rms 797 nV rms 338 nV rms 133 nV rms 80 nV rms 79 nV rms Table Ia Minimum D
8. synchronizes the AD1555 clock MCLK to the AD1556 BW2 BWO Output Rate ms clock CLKIN as shown in Figure 3 0 0 0 4 tclears the filter and then initiates the filter convolution 0 0 1 2 Exactly one sampling rate delay later the DRDY pin goes 0 1 0 1 high SYNC event occurs on the next CLKIN rising edge 0 1 1 1 2 after the SYNC input is brought high as shown in Figure 3 1 0 0 1 4 The DRDY output goes high on the next falling edge of 1 0 1 1 8 CLKIN SYNC may be applied once or kept high or applied 1 1 0 1 16 synchronously at the output word rate all with the same effect 1 1 1 Reserved Table V Configuration Register Data Bits Bit Number Name Description RESET State DB15 MSB x 14 X X 13 X X DB12 x X PWRDN Power Down Mode PWRDN DB10 CSEL Select TDATA Input CSEL DB9 X X DB8 BW2 Filter Bandwidth Selection BW2 DB7 Filter Bandwidth Selection DB6 BWO Filter Bandwidth Selection BWO DB5 DRDYBUF DRDY Output Mode 0 Push Pull DB4 CB4 PGA Input Select PGA4 DB3 CB3 PGA Input Select PGA3 DB2 CB2 PGA Gain Select PGA2 DBI CBI PGA Gain Select PGAI DBO LSB CBO PGA Gain Select PGAO 20 AD1555 AD1556 DRDYBUF 0 DRDYBUF 1 VL VL TO OTHER AD1556s TO THE MICROPROCESSOR AD1556 TO THE MICROPROCESSOR AD1556 DGND Figure 11 DRDY Output Pin Configuration Analog Input and Digital Output Data Format When operating with a nominal MCLK frequency of 256 k
9. the part to handle a total of five different input ranges 1 6 V rms 636 mV rms 187 mV rms 47 mV rms and 12 4 mV rms that are programmed via digital input pins CBO to CB4 The modulator that operates nominally at a sampling frequency of 256 kHz outputs a bit stream whose ones density is proportional to its input voltage This bitstream can be filtered using the AD1556 which is a digital finite impulse low pass filter FIR The AD1556 outputs the data in a 24 bit word over a serial interface The cutoff frequency and output rate of this filter can be programmed via an on chip register or by hardware through digital input pins The dynamic performance and the equivalent input noise vary with gain and output rate as shown in Table I The use of the different PGA gain settings allows enhancement of the total system dynamic range up to 146 dB gain of 34 or 128 and Fo 250 Hz AC SINE TEST DCTEST SOURCE SOURCE 5V Q Q DB DA Q 15 O V 9 8 Vour GND 2 0780 Vino 5V 100nF p AD1555 operates from a dual analog supply 5 V while the digital part of the AD1555 operates from a 5 V supply The AD1556 operates from a single 3 3 V or 5 V supply Each device exhibits low power dissipation and can be configured for standby mode Figure 7 illustrates a typical operating circuit MULTIPLEXER AND PROGRAMMABLE GAIN AMPLIFIER PGA Analog Inputs The AD1555 has two sets of ful
10. 18 8000 1 8 ms 8 4 64 184 4000 1 4 ms 16 4 128 184 2000 1 2 ms 32 4 256 184 1000 1 ms 64 4 512 184 500 2 ms 128 4 1024 184 250 4 ms 128 8 1024 364 REV 19 AD1555 AD1556 RESET Operation RESET pin initializes the AD1556 in a known state RESET is active on the next CLKIN rising edge after the RESET input is brought high as shown in Figure 4 The reset value of each bit of the configuration and the status registers are indicated in Table V and Table VIII The filter memories are not cleared by the reset Filter convolutions begin on the next CLKIN rising edge after the RESET input is returned low A RESET operation is done on power up independent of the RESET pin state In multiple ADCs applications where absolute synchroniza tion even below the noise floor is required RESETD which resets the decimator can be tied to RESET to ensure this synchronization Power Down Operation The PWRDN pin puts the AD1556 in a power down state PWRDN is active on the next CLKIN rising edge after the PWRDN input is brought high While in this state MCLK is held at a fixed level and the AD1555 is therefore powered down too The serial interface remains active allowing read and write operations of the AD1556 The configuration and status registers maintain their content during the power down state SYNC Operation SYNC is used to create a relationship between the analog input signal and the output samples of the A
11. 25 FREQUENCY Hz TEMPERATURE TPC 3 FFT 16384 Points Full Scale AIN Input Gain of 1 TPC 6 Common Mode Rejection vs Temperature REV 13 AD1555 AD1556 NUMBER OF UNITS TPC 7 Common Mode Rejection Distribution 272 Units 120 115 110 105 CMRR dB 100 95 90 113 105 CMRR dB 98 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY Hz TPC 8 Common Mode Rejection vs Frequency 0 20 0 15 0 10 0 05 0 00 AMPLITUDE dB 0 05 0 10 0 15 0 20 TPC 9 AD1556 Pass Band Ripple 250 Hz 4 ms 25 50 75 FREQUENCY Hz 100 125 14 0 20 0 15 0 10 0 05 0 00 0 05 AMPLITUDE dB 0 10 0 15 0 20 100 150 FREQUENCY Hz 200 TPC 10 AD1556 Pass Band Ripple Fo 500 Hz 2 ms 0 20 0 15 0 10 0 05 0 00 0 05 AMPLITUDE dB 0 10 0 15 0 20 100 200 300 FREQUENCY Hz 400 TPC 11 AD1556 Pass Band Ripple Fo 1 kHz 1 ms 0 20 0 15 0 10 0 05 0 00 AMPLITUDE dB 0 05 0 10 0 15 0 20 200 400 600 2 800 1000 TPC 12
12. 7 195 REV 23 0 9 0 690200 NI GALNIYd 24
13. AD1556 Pass Band Ripple Fo 2 kHz 1 2 ms REV B 1 o ADAD 996 0 20 0 15 0 10 0 05 0 00 0 05 AMPLITUDE dB 0 10 0 15 0 20 13 0 20 0 15 0 10 0 05 0 00 AMPLITUDE dB 0 05 0 10 0 15 0 20 14 REV 1000 1500 2000 FREQUENCY Hz AD1556 Pass Band Ripple Fo 4 kHz 1 4 ms 1000 2000 3000 4000 FREQUENCY Hz AD1556 Pass Band Ripple Fo 8 kHz 1 8 ms 15 AMPLITUDE dB 0 20 0 15 0 10 0 05 0 00 0 05 0 10 0 15 0 20 2000 4000 FREQUENCY Hz 6000 8000 TPC 15 AD1556 Pass Band Ripple Fo 16 kHz 1 16 ms AD1555 AD1556 CIRCUIT DESCRIPTION The AD1555 AD1556 chipset is a complete sigma delta 24 bit A D converter with very high dynamic range intended for the measurement of low frequency signals up to a few kHz such as those in seismic applications The AD1555 contains an analog multiplexer a fully differential programmable gain amplifier and a fourth order sigma delta modulator The analog multiplexer allows selection of one fully differential input from two different external inputs an internal ground reference or an internal full scale voltage reference The fully differential programmable gain amplifier PGA has five gain settings of 1 2 5 8 5 34 and 128 which allow
14. ANALOG DEVICES 24 Bit gt A ADC with Low Noise PGA AD1555 AD1556 FEATURES AD1555 Fourth Order Modulator Large Dynamic Range 116 dB Min 120 dB Typical 1 ms 117 dB Typical 0 5 ms Low Input Noise 80 nV rms 4 ms with Gain of 34 128 Low Distortion 111 dB Max 120 dB Typical Low Intermodulation 122 dB Sampling Rate at 256 kSPS Very High Jitter Tolerance No External Antialias Filter Required Programmable Gain Front End Input Range 2 25 V Robust Inputs Gain Settings 1 2 5 8 5 34 128 high dynamic range measurement applications The AD1555 outputs a ones density bitstream proportional to the analog input When used in conjunction with the AD1556 digital filter decimator a high performance ADC is realized The continuous time analog modulator input architecture avoids the need for an external antialias filter The programmable gain front end simplifies system design extends the dynamic range and reduces the system board area Low operating power and standby modes makes the AD 1555 ideal for remote battery pow ered data acquisition systems The AD1555 is fabricated on Analog Devices BiCMOS process that has high performance bipolar devices along with CMOS transistors The AD1555 and AD1556 are packaged respectively in 28 lead PLCC and 44 lead MQFP packages and are specified from 55 to 85 AD1556 and AD1555 Grade and from 0 C to 85 C AD1555 A Grade Common Mode Rejection DC
15. D1556 The SYNC event does two things Configuring and Interfacing the AD1556 The AD1556 configuration can be loaded either by hardware H S pin high or via the serial interface of the AD1556 H S pin low To operate with the AD1556 the CLKIN clock must be kept running at the nominal frequency of 1 024 MHz Table V gives the description of each bit of the configuration register and Table VI defines the selection of the filter bandwidth When the software mode is selected H S pin low the configuration register is loaded using the pins DIN SCLK CS and R W In this mode when RESET is active the configuration register mimics the selec tion of the hardware pins The AD1556 and the AD1555 can be put in power down by software The DRDYBUF bit controls the operating mode of the DRDY output pin When the DRDYBUF bit is low the DRDY is a con ventional CMOS push pull output buffer as shown in Figure 11 When the DRDYBUF bit is high the DRDY output pin is an open drain PMOS pull up as shown in Figure 11 Many DRDY pins may be connected with an external pull down resistor in a wired OR to minimize the interconnection between the AD1556s and the microprocessor in multichannel applications The DRDY pin is protected against bit contention By connecting DRDY to RSEL directly and applying 48 SCLK cycles both data and status can be read sequentially data register first Table VI Filter Bandwidth Selection
16. Hz the AD1555 is designed to output a ones density bitstream from 0 166 to 0 834 on its MDATA output pin corresponding to an input voltage from 2 25 V to 2 25 V on the MODIN pin The AD1556 computes a 24 bit two s complement output whose codes range from decimal 6 291 456 to 46 291 455 as shown in Table VII Table VII Output Coding Analog Input Output Code MODIN Hexa Decimal 42 526 V 5FFFFF 46291455 2 25 V 558105 45603589 2 4 00 8 4980968 0 000000 0 2 B3FF17 4980969 2 25 V 5603590 2 526 V 00000 6291456 Input out of range STATUS Register The AD1556 status register contains 24 bits that capture poten tial error conditions and readback the configuration settings The status register mapping is defined in Table VIII The ERROR bit is the logical OR of the other error bits OVWR and ACC ERROR and the other error bits are reset low after completing a status register read operation or upon RESET The ERROR bit is the inverse of the ERROR output pin The OVWR bit indicates if an unread conversion result is over written in the output data register If a data read was started but not completed when new data is loaded into the output data register the OVWR bit is set high The MFLG status bit is set to the state of the MFLG input pin on the rising edge of CLKIN MFLG will remain set high as long as the MFLG bit is set The MFLG status bit w
17. P2 Reference Filter The reference input is internally divided and available at this pin 25 REFIN Reference Input This input accepts a 3 V level that is internally divided to provide the reference for the modulator 27 AGND2 Analog Ground 28 MODIN Modulator Input Analog input to the modulator Normally this input is directly tied to PGAOUT output AD1556 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 21 27 28 NC No Connect 33 2 6 PGA0 PGA4 and MUX Control Inputs Sets the logic level of CBO CB4 output pins respectively and the state of the corresponding bit in the configuration register upon RESET or when in hardware mode Refer to Table III 7 9 BWO BW2 Output Rate Control Inputs Sets the digital filter decimation rate and the state of the correspond ing bit in the configuration register upon RESET or when in hardware mode Refer to the Filter Specifications and Table VI 10 H S Hardware Software Mode Select Determines how the device operation is controlled In hardware mode H S is high the state of hardware pins set the mode of operation When H S is low a write sequence to the Configuration Register or a previous write sequence sets the device operation 11 22 44 VL Positive Digital Supply Voltage 3 3 V or 5 V nominal 12 23 24 34 DGND Digital Ground 13 SCLK Serial Data Clock Synchronizes data transfer to either write data on the DIN input pin or read data on the DOUT output pin
18. The SYNC input can also be applied synchronously to the AD1556 decima tion rate without resetting the convolution cycles Clock Input The clock input signal nominally 1 024 MHz provides the necessary clock for the AD1556 This clock frequency is divided by four to generate the MCLK signal for the AD1555 Modulator Clock Provides the modulator sampling clock frequency The modulator always samples at one fourth the CLKIN frequency Modulator Data This input receives the ones density bit stream from the AD1555 for input to the digital filter Decimator Reset logic high resets the decimator of the digital filter Modulator Error The MFLG input is used to detect if an overrange condition occurred in the modulator Its logic level is sensed on the rising edge of CLKIN When overrange condition detected ERROR goes low and updates the status register Modulator Control These output control pins represent a portion of the data loaded into the AD1556 Configuration Register CB0 CB2 are generally used to set the PGA gain or cause it to enter in the PGA standby mode Refer to Table III CB3 and CB4 select the mux input voltage applied to the PGA as described in Table REV B 11 AD1555 AD1556 TERMINOLOGY DYNAMIC RANGE Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together in the bandwidth from 3 Hz to the Nyquist frequency 2 The value for dynamic rang
19. ated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 28 lead PLCC 36 C W 20 C W 44 lead MQFP 36 C W 14 C W 219155915 1 8W AD 556 ie 99 eR ERE EY on Sana dade 1 8W ORDERING GUIDE Temperature Package Package Model Range Description Option AD1555AP 0 to 85 Plastic Lead Chip Carrier P 28A AD1555APRL 0 to 85 C Plastic Lead Chip Carrier P 28A AD1555BP 55 C 85 C Plastic Lead Chip Carrier P 28A AD1555BPRL 55 to 85 C Plastic Lead Chip Carrier P 28A AD1556AS 55 C 85 C Plastic Quad Flatpack S 44A AD1556ASRL 55 C 85 C Plastic Quad Flatpack S 44A EVAL AD1555 AD1556EB Evaluation Board AD1555 56 REF Reference Design Contact factory for extended temperature range CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD1555 AD1556 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ESD SENSITIVE DEVICE 8
20. citors should be located in the vicinity of the ADC to further reduce low frequency ripple The Vi supply of the AD1555 can either be a separate supply or come from the analog supply V4 When the system digital supply is noisy or fast switching digital signals are present it is recommended if no separate supply is available to connect the digital supply to the analog supply through an RC filter as shown in Figure 7 21 AD1555 AD1556 Table VIII Status Register Data Bits Bit Number Name Description RESET State DB23 MSB ERROR Detects One of the Following Errors 0 DB22 OVWR Read Sequence Overwrite Error 0 DB21 MFLG Modulator Flag Error MFLG DB20 X DB19 ACC Accumulator Error 0 DB18 DRDY Data Ready 0 DB17 FLSTL Filter Settled 0 1816 DRNG Output Data Not within AD1555 Range 0 DB15 X X 14 X X DB13 X X DB12 X X PWRDN Power Down Mode PWRDN DB10 CSEL Select TDATA Input CSEL DB9 X X DB8 BW2 Filter Bandwidth Selection BW2 DB7 Filter Bandwidth Selection DB6 BWO Filter Bandwidth Selection BWO DB5 X X DB4 CB4 Input Select PGA4 DB3 CB3 Input Select PGA3 DB2 CB2 PGA Gain Select PGA2 PGA Gain Select DBO LSB CBO PGA Gain Select PGAO The AD1555 has three different ground pins AGND1 AGND2 and AGND3 plane depending on the configuration AGNDI should be a star point and be connected to the analog ground point AGND2 should be directly tied t
21. d to ease the design The external voltage spike is generally clamped by devices T1 and T2 at about hundred volts for instance devices T1 and T2 can be gas discharge tubes and then generates a pulsed current in the serial resistances R1 R3 and R2 R4 The AD1555 AIN inputs using robust internal clamping diodes to the analog supply rails can handle this huge pulsed input current 1 5 A during 2 15 without experiencing any destructive damages or latch up whether or not the AD1555 is powered on Mean while enough time should be left between multiple spikes to avoid excessive power dissipation Programming the AD1555 The different hardware events of the AD1555 as multiplexer inputs selection programmable gain settings and power down modes are selectable using the control pins bus 4 according to the Table III This table is only valid when MCLK is toggling otherwise the AD1555 is powered down When used in combination with the AD1556 this control bus could either be loaded by hardware H S pin high or via the serial interface of the AD1556 H S pin low The multiplexer which exhibits break before make switching action allows various combinations TIN TIN JO REFIN 2 AD1555 Figure 8 Simplified AD1555 Input Multiplexer When the ground input is selected 53 and 53 are closed all the other switches are opened and the inputs of the pro
22. e for input selection 9 NC Pin for Factory Use Only This pin must be kept not connected for normal operation 10 14 4 Modulator Control These input pins control the mux selection the PGA gain settings and the standby modes of the AD1555 When used with the AD1556 these pins are generally directly tied to the CBO CB4 output pins of the AD1556 2 are generally used to set the PGA gain cause it to enter in the PGA standby mode refer to Table III CB3 and CB4 select the mux input voltage applied to the PGA as described in Table HI 15 MFLG Modulator Error Digital output that is pulsed high if an overrange condition occurs in the modulator 16 DGND Digital Ground 17 MDATA Modulator Output The bitstream generated by the modulator is output in a return to zero data format The data is valid for approximately one half a MCLK cycle Refer to Figure 3 18 MCLK Clock Input The clock input signal nominally 256 kHz provides the necessary clock for the X A modulator When this input is static AD1555 is in the power down mode 19 VL Positive Digital Supply Voltage 5 V Nominal 22 AGND3 Analog Ground Used as the ground reference for the REFIN pin 23 REFCAP1 DAC Reference Filter The reference input is internally divided and available at this pin to provide the reference for the modulator Connect an external 22 uF 5 V min tantalum capacitor from REFCAPI to AGND3 to filter the external reference noise 24 REFCA
23. e is expressed in decibels SIGNAL TO NOISE RATIO SNR SNR is the ratio of the rms value of the full scale signal to the total rms noise in the bandwidth from 3 Hz to the Nyquist fre quency Fo 2 The value for SNR is expressed in decibels TOTAL HARMONIC DISTORTION THD THD is the ratio of the rms sum of all the harmonic components up to Nyquist frequency 2 to the rms value of a full scale input signal The value for THD is expressed in decibels INTERMODULATION DISTORTION IMD IMD is the ratio of the rms sum of two sine wave signals of 30 Hz and 50 Hz which are each 6 dB down from full scale to the rms sum of all intermodulation components within the bandwidth from 1 Hz to the Nyquist frequency 2 The value for IMD is expressed in decibels 212 OFFSET The offset is the difference between the ideal midscale input volt age 0 V and the actual voltage producing the midscale output code code 000000H at the output of the AD1556 The offset specification is referred to the output This offset is intentionally set at a nominal value of 60 mV see Sigma Delta Modulator section The value for offset is expressed in mV OFFSET ERROR DRIFT The change of the offset over temperature It is expressed in mV GAIN ERROR gain error is the ratio of the difference between the actual gain and the ideal gain to the ideal gain The actual gain is the ratio of the output difference obtained with a full scale analog input
24. egister via the Input Shift Register Data is loaded MSB first and must be valid on the falling edge of SCLK Error Flag A logic low output indicates an error condition occurred in the modulator or digital filter When ERROR goes low the ERROR bit in the status register is set high The ERROR output pin has an open drain type buffer with an internal 100 typical pull up that allows wired OR connection of multiple AD1556s Chip Reset A logic high input clears any error condition in the status register and sets the configuration register to the state of the corresponding hardware pins On power up this reset state is entered Power Down Hardware Control A logic high input powers down the filter convolution cycles in the digital filter and the MCLK signal are stopped registers retain their data and the serial data interface remains active The power down mode is entered on the first falling edge of CLKIN after PWRDN is taken high When exiting the power down mode a SYNC must be applied to resume filter convolutions Filter Input Select Selects the source for input to the digital filter A logic high selects the TDATA input a low selects MDATA as the filter input Test Data Input to digital filter for user test data Synchronization Input The SYNC input clears the AD1556 filter in order to synchronize the start of the filter convolutions The SYNC event is initiated on the first CLKIN rising edge after the SYNC pin goes high
25. g Devices Inc 2002 AD1555 AD1556 AD1555 SPECIFICATIONS 41 5 V V 5 V V 5 AGND DGND 0 V MCLK 256 kHz T Tm to Tmax unless otherwise noted AD1555BP AD1555AP Parameter Notes Min Typ Max Min Typ Max Unit PGA Gain Settings 1 2 5 8 5 34 128 AC ACCURACY Dynamic Range PGA Gain of 1 116 5 120 116 120 dB PGA Gain of 2 5 116 119 5 115 5 119 5 dB PGA Gain of 8 5 114 117 5 114 117 5 PGA of 34 104 5 109 5 104 5 109 5 dB PGA Gain of 128 98 98 dB Total Harmonic Distortion PGA Gain of 1 120 111 120 107 dB PGA Gain of 2 5 116 108 116 107 dB PGA Gain of 8 5 116 106 116 105 dB PGA Gain of 34 115 101 115 101 dB PGA Gain of 128 108 108 dB Jitter Tolerance 300 300 ps Intermodulation Distortion PGA Gain of 1 122 122 dB DC ACCURACY Absolute Gain Error PGA Gain of 1 2 5 3 5 3 5 3 5 3 5 8 5 4 5 4 5 4 5 4 5 PGA of 34 10 10 10 10 Gain Stability Over Temperature 15 15 ppm C Offset All PGA Gain 60 60 mV Offset Drift 9 6 6 uV C ANALOG INPUT Full Scale Nondifferential Input MODIN 42 25 2 25 Input Impedance MODIN 20 20 Full Scale Differential Input PGA Gain of 1 2 25 2 25 Other PGA Gain Settings See Table I See Table I Differential Input Impedance AIN TIN Inputs 140 140 MQ Common Mode Range 2 25 2 25 V Common Mode Rejection Ratio Vom 2 25 V 200 Hz PGA Gain of 1 93 101 91 101 dB
26. gives for each filter the pass band frequency the 3 dB frequency the stop band frequency and the group delay The pass band frequency is 37 5 of the output word rate and the 3 dB frequency is approximately 41 of the output word rate The noise generated by the AD1556 even that due to the word truncation has a negligible impact on the dynamic range performance of the AD1555 AD1556 chipset Although dedicated to the AD1555 the AD1556 can also be used as a very efficient and low power low pass digital filter of a bitstream generated by other A modulators Architecture The functional block diagram of the filter portion of the AD 1556 is given in Figure 10 The basic architecture is a two stage filter The second stage has a decimation ratio of 4 for all filters except FIRST STAGE FILTER INPUT DATA STORAGE FIRST STAGE FILTER 29 BIT ACCUMULATOR MODULATOR BITSTREAM 1 1 BIT WIDE AT 256kbits s RAM 1024 BY 1 BIT FIRST STAGE FILTER COEFFICIENTS ROM 1008 BY 26 BITS SECOND STAGE FILTER INPUT DATA STORAGE RAM 364 BY 24 BITS at the output word rate of 250 Hz where the decimation ratio is 8 Each filter is a linear phase equiripple FIR implemented by summing symmetrical pairs of data samples and then convolut ing by multiplication and accumulation The input bitstream at 256 kHz enters the first filter and is multiplied by the 26 bit wide coefficients tallied in Table IV Due to
27. h design techniques Because of the switched capacitor feedback this modulator is much less sensitive to timing jitter than is the usual continuous time design that relies on the duty cycle of the clock to control a switched current feedback DAC Unlike its fully switched capacitor counterparts the modulator input circuitry is nonsampling consisting simply of an internal low temperature coefficient resistor connected to the summing node of the input integrator Among the advantages of this continuous time architecture is a relaxation of requirements for the antialias filter in fact the output of the programmable gain amplifier PGAOUT may be tied directly to the input of the modulator MODIN without any external filter Another advan tage is that the gain may be adjusted to accommodate a higher input range by adding an external series resistor at MODIN The modulator of the AD1555 is fourth order which very effi ciently shapes the quantization noise so that it is pushed toward the higher frequencies above 1 kHz as shown in TPC 3 This high frequency noise is attenuated by the AD1556 digital filter However when the output word rate OWR of the AD1556 is higher than 4 kHz 3 dB frequency is higher than 1634 Hz the efficiency of this filtering is limited and slightly reduces the dynamic range as shown in the Table I Hence when possible an OWR of 2 kHz or lower is generally preferred Sigma delta modulators have the potential
28. h input signals of 30 Hz and 50 Hz each 6 dB down full scale gt This specification is for the AD1555 only and does not include the errors from external components as for instance the external reference 6 offset specification is referred to the modulator output Characterized with a 100 mV p p sine wave applied separately to each supply 5Contact factory for extended temperature range Recommended Reference AD780BR Specified with analog inputs grounded See Table III for configuration conditions Specified with MCLK input grounded Specifications subject to change without notice AD 1 586 5 0 V 2 85 to 5 25 CLKIN 1 024 MHz T to unless otherwise noted AD1556AS Parameter Notes Min Typ Max Unit FILTER PERFORMANCES Pass Band Ripple 0 05 0 05 Stop Band Attenuation All Filters Except Fo 16 kHz 135 dB Fo 16 kHz 86 dB Filters Characteristics See Table II DIGITAL INPUTS OUTPUTS Vir 0 3 0 8 2 0 0 3 V 10 10 10 10 Igwk 2 mA 0 5 2 mA 0 6 POWER SUPPLIES Specified Performance Vr 2 85 5 25 V Quiescent Currents I Vi 4 5 mA Power Dissipation 3 3 V Fo kHz 6 2 8 5 mW In Power Down Mode 70 uW TEMPERATURE RANGE Specified Performance Tmn to Tmax 55 85 Contact factory for extended temperature range Specifications
29. ill not change during power down or RESET REV B ACC bit is set high and the data output is clipped to either FS 0111 or FS 1000 if an underflow or overflow has occurred in the digital filter FLSTL bit indicates the digital filter has settled and the conversion results are an accurate representation of the analog input FLSTL is set low on RESET at power up and upon exiting the power down state FLSTL also goes low when SYNC sets the start of the filter s convolution cycle when changes are made to the device setting with the hardware pins BWO BW2 CSEL and when the status bit is set high When FLSTL is low the OVWR MFLG ACC and DRNG status bits will not change The DRNG bit is used to indicate if the analog input to the AD1555 is outside its specified operating range The DRNG bit is set high whenever the AD1556 digital filter computes four consecutive output samples that are greater than decimal 6 291455 or all less than 6 291456 Layout The AD1555 has very good immunity to noise on the power supplies However care should still be taken with regard to grounding layout The printed circuit board that houses the AD1555 and the AD1556 should be designed so the analog and digital sections are separated and confined to certain areas of the board This facilitates the use of ground planes that can be easily separated Digital and analog ground planes should be joined in onl
30. ly differential inputs AIN and TIN The common mode rejection capability of these inputs generally surpasses the performance of conventional program mable gain amplifiers The very high input impedance typically higher than 140 allows direct connection of the sensor to the AD1555 inputs even through serial resistances Figure 7 illustrates such a configuration The passive filter between the sensor and the AD1555 is shown here as an example Other filter structures could be used depending on the specific require ments of the application Also the Johnson noise TRB of the serial resistance should be taken into consideration For instance a 1 serial resistance reduces by approximately 1 3 dB the dynamic performance of a system using a gain setting of 128 at an output word rate Fo 500 Hz For applications where the sensor inputs must be protected against severe UNUSED AD1555 PINS MUST BE LEFT UNCONNECTED UNUSED AD1556 INPUT PINS MUST BE TIED TO DGND OR Vj CLOCK SOURCE SERIAL DATA M SMS INTERFACE ADSP 21xxx OR pP MFLG MDATA AD1555 SENSOR GEOPHONE HYDROPHONE TO OTHER AD1556s 31 HARDWARE VA AGNDi AGND2 Va 25 CONTROL 3 26 27 4 20 21 5V 5 10 100nF 100nF 10 V 10 11 22 44 12 23 24 34 Figure 7 Typical Operating Circuit 16 AD1555 AD1556 external stresses such as lightning the inputs AIN are specifi cally designe
31. o AGNDI low impedance trace should connect in the following order AGND3 the low side of the reference decoupling capacitor on REFCAP1 the ground of the reference voltage and return to AGND 1 22 Evaluating the AD1555 AD1556 Performance Performances of the AD1555 AD1556 can be evaluated with the evaluation board EVAL AD1555 AD1556EB The evaluation board package includes a fully assembled and tested evaluation board documentation and software for controlling the board from a PC via the PC printer port REV B AD1555 AD1556 OUTLINE DIMENSIONS Dimensions shown in inches and mm 28 Lead PLCC P 28A 0 180 4 57 0 048 1 21 0 165 4 19 0 042 1 07 0 056 1 42 T 0 042 1 07 SEES 0 048 1 21 en yal 0 015 0 38 6 042 1 07 1065 IDENTIFIER 3 0 021 0 53 1 0 013 0 33 TOP VIEW 0 430 10 92 PINS DOWN 0 032 0 81 0 390 9 91 10 026 0 66 0020 0 040 1 01 0507 0466 11 58 a NI lt 0 450 11 43 0 495 12 57 0 110 2 79 0 485 12 32 99 0 085 2 16 44 Lead S 44A 0 530 13 45 0 096 2 45 0 510 12 95 MAX 0 398 10 10 0 041 1 03 0 390 9 90 0 029 0 73 1 1 33 SEATING TOP VIEW 0 315 8 00 PINS DOWN REF 11 23 010 0 2 12 22 0 000 cla 0 005 0 13 0 031 0 80 0 018 0 45 0 083 2 10 BSC 0 012 0 30 0 07
32. sistor Specifications subject to change without notice TO OUTPUT PIN CL 50pF T Figure 2 Load Circuit for Digital Interface Timing REV B b AD1555 AD1556 SYNC MCLK Fs MDATA DRDY Figure 4 AD1556 RESET DRDY and Overwrite Timings REV B AD1555 AD1556 RSEL DOUT SCLK t24 t33 t25 C OC Figure 6 Serial Write Timing REV 7 AD1555 AD1556 ABSOLUTE MAXIMUM RATINGS Analog Inputs Pins 7 8 23 24 25 28 0 3 V to 0 3 V AIN DC Input Current 100 mA AIN 2 us Pulse Input Current t1 5A Supply Voltages BV TO VA voe Rx RV 0 3 14 V 0 3 V to 7 V VatoAGND 7 V to 403 V Vr to DOGNDJ reci 0 3 V to 7 V Ground Voltage Differences DGND AGND1 AGND2 AGND3 Digital Inputs Internal Power Dissipation 0 3 V Junction Temperature 150 C Storage Temperature 65 to 150 C Lead Temperature Range Soldering 10 sec NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indic
33. ternal serial resistance between each AIN input and the PGA inputs nominally 66 Q slightly affects these measurements The total internal serial resistance between each TIN input and the PGA inputs is nominally 1160 When the Sensor Test 2 is selected S1 2 and S2 are closed all the other switches are opened This configuration could be used to test the sensor isolation Power Down Modes of the AD1555 The AD1555 has two power down modes The multiplexer and programmable gain amplifier can be powered down by the 2 setting of 101 The entire chip is powered down either 2 set to 11 or by keeping the clock input MCLK at a fixed level high or low Less shutdown current flows with MCLE low The least power dissipation is achieved when the external reference is shut down eliminating the current through the 30 nominal load at REFIN When in power down the multiplexer is switched to the ground input INTEGRATOR COMPARATOR Figure 9 Sigma Delta Modulator Block Diagram 18 SIGMA DELTA MODULATOR The AD1555 sigma delta modulator achieves its high level of performance notably in dynamic range and distortion through the use of a switched capacitor feedback DAC in an otherwise continuous time design Novel circuitry eliminates the subtle distortion normally encountered when these disparate types are connected together As a result the AD1555 enjoys many of the benefits of bot
34. the symmetry of the filter only half of the coefficients are stored in the internal ROM and each is used twice per con volution Because the multiplication uses a 1 bit input data the convolution for the first stage is implemented with a single accu mulator 29 bits wide to avoid any truncation in the accumulation process The output of the first stage filter is decimated with the ratios given in Table IV and then are stored in an internal RAM which truncates the accumulator result to 24 bits The second stage filter architecture is similar to the first stage The main difference is the use of a true multiplier The multiplier the accumulator and the output register which are respectively 32 bits 35 bits and 24 bits wide introduce some truncation that does not affect the overall dynamic performance of the AD1555 AD1556 chipset Filter Coefficients As indicated before each stage for each filter uses a different set of coefficients These coefficients are provided with the EVAL AD1555 AD1556EB the evaluation board for the AD1555 and the AD1556 SECOND STAGE FILTER 35 BIT ACCUMULATOR MULTIPLIER SECOND STAGE FILTER INPUT COEFFICIENTS ROM 333 BY 26 BITS Figure 10 AD1556 Filter Functional Block Diagram Table IV Filter Definition Output Word Rate Hz Decimation Ratio Number of Coefficients Sampling Rate ms First Stage Second Stage First Stage Second Stage 16000 1 16 ms 4 4 32 1
35. to 1 kHz 4 93 dB Min 101 dB Typical Gain of 1 fy 24 4 2 77 mW Typical Low Power Dissipation 20 SNR 116 7dB Standby Modes 40 ns AD1556 FIR Digital Filter Decimator 27 Serial or Parallel Selection of Configuration T 80 Output Word Rates 250 SPS to 16 kSPS 6 2 mW Low Power Dissipation 5 70 in Standby Mode Reference Design and Evaluation Board with 140 Software Available 160 APPLICATIONS 180 Seismic Data Acquisition Systems Chromatography 0 50 100 150 200 250 300 350 400 450 500 Automatic Test Equipment FREQUENCY Hz GENERAL DESCRIPTION Figure 1 FFT Plot Full Scale AIN Input Gain of 1 The AD1555 is a complete sigma delta modulator combined with a programmable gain amplifier intended for low frequency FUNCTIONAL BLOCK DIAGRAM REFIN REFCAP2 REFCAP1 AGND3 PGAO PGA4 HIS ERROR Ff rer oben O O O O AGND1 PGAOUT MODIN AGND2 REV Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A may result from its use No license is granted by implication or otherwise Tel 781 329 4700 www analog com under any patent or patent rights of Analog Devices Fax 781 326 8703 Analo
36. to generate idle tones that occur for dc inputs close to ground To prevent this unde sirable effect the AD1555 modulator offset is set to about 60 mV In this manner any existing idle tones are moved out of the band of interest and filtered out by the digital filter Also sigma delta modulators may oscillate when the analog input is overranged To avoid any instability the modulator of the AD1555 includes circuitry to detect a string of 16 identical bits 40 or 1 Upon this event the modulator is reset by discharging the integrator and loop filter capacitors and MFLG is forced high After 1 5 MCLK cycles MFLG returns low REV B AD1555 AD1556 DIGITAL FILTERING The AD1556 is a digital finite impulse response FIR linear phase low pass filter and serves as the decimation filter for the AD1555 It takes the output bitstream of the AD1555 filters and decimates it by a user selectable choice of seven different filters associated with seven decimation ratios in power of 2 from 1 16 to 1 1024 With a nominal bit rate of 256 kbits s at the AD1556 input the output word rate the inverse of the sampling rate ranges from 16 kHz 1 16 ms to 250 Hz 4 ms in powers of 2 The AD1556 filter achieves a maximum pass band flatness of 0 05 dB for each decimation ratio and an out of band attenuation of 135 dB maximum for each decimation ratio except 1 16 OWR 16 at which the out of band attenuation is 86 dB maximum Table II
37. ts tied respectively to TIN and TIN inputs and with PGA Gain of 1 Sensor Test 2 Signal inputs TIN and TIN with input tied to TIN input and with PGA Gain of 1 PGA Powered Down Chip Powered Down REV B 17 AD1555 AD1556 When the input is selected 54 and 4 are closed all the other switches are opened and a reference voltage 2 25 V equal to half of the full scale range is sampled In this combina tion the gain setting is forced to be the gain of 1 When the signal input is selected 81 and S1 are closed all the other switches are opened and the differential input signal between AIN and AIN is sampled This is the main path for signal acquisition When the test input is selected S2 and S2 are closed all the other switches are opened and the differential input signal between TIN and TIN is sampled This combination allows acquisition of a test signal or a secondary channel with the same level of performance as with AIN inputs By applying known voltages to these inputs it is also possible to calibrate the gain for each gain setting When the Sensor Test 1 is selected S1 S1 2 and S2 are closed all the other switches are opened and the gain setting is forced to be the gain of 1 In this configuration a source between TIN may be applied to the sensor to determine its impedance or other characteristics The total in
38. y one place preferably underneath the AD1555 or at least as close as possible to the AD1555 If the AD1555 is in a system where multiple devices require analog to digital ground connections the connection should still be made at one point only a star ground point which should be established as close as possible to the AD1555 It is recommended to avoid running digital lines under the device since these will couple noise onto the die The analog ground plane should be allowed to run under the AD1555 to avoid noise coupling Fast switching signals such as MDATA and MCLK should be shielded with digital ground to avoid radiating noise to other sections of the board and should never run near analog signal paths Crossover of digital and analog signals should be avoided Traces on different but close layers of the board should run at right angles to each other This will re duce the effect of feedthrough through the board The power supply lines to the AD1555 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines Good decoupling is also important to lower the supplies impedance resent to the AD1555 and reduce the magnitude of the supply spikes Decou pling ceramic capacitors typically 100 nF should be placed on power supply pins V4 and close to and ideally right up against these pins and their corresponding ground pins Additionally low ESR 10 capa
39. ynamic Performances AD1555AP Only Input and Gain MODIN PGA 1 0dB PGA 2 5 8dB PGA 8 5 19dB 34 31 dB Fo 1 kHz 1 ms 116 116 115 5 114 104 5 Fo 500 Hz 2 ms 119 119 118 5 117 107 5 Fo 250 Hz 4 ms 122 122 121 5 120 110 5 tested in production Guaranteed by design Table Ib Minimum Dynamic Performances AD1555BP Only Input and Gain MODIN 1 0 dB PGA 2 5 8 dB PGA 8 5 19 dB 34 31 dB Fo 1 kHz 1 ms 116 5 116 5 116 114 104 5 Fo 500 Hz 2 ms 119 5 119 5 119 117 107 5 Fo 250 Hz 4 ms 122 5 122 5 121 120 110 5 tested in production Guaranteed by design Table II Filter Characteristics Output Word Rate Fo Pass Band 3 dB Frequency Stop Band Group Delay Sampling Rate in ms Hz Hz Hz ms 16000 Hz 1 16 ms 6000 6480 8000 0 984 8000 Hz 1 8 ms 3000 3267 5 4000 3 4000 Hz 1 4 ms 1500 1634 2000 6 2000 Hz 1 2 ms 750 816 9 1000 12 1000 Hz 1 ms 375 408 5 500 24 500 Hz 2 ms 187 5 204 2 250 48 250 Hz 4 ms 93 75 101 4 125 93 4 AD1555 AD1556 41 5 V 5 5 5 AD1555 V 5 V 5 AD1556 V 2 85 V to 5 25 V TIMING SPECIFICATIONS cikin 1 024 Mhz AGND DGND 0 V 50 pF T Tuy to Tuay unless otherwise noted Symbol Min Typ Max Unit CLKIN Frequency 0 975 1 024 1 075 MHz CLKIN Duty Cycle Error 45 55
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