ANALOG DEVICES AD7654 English products handbook
Contents
1. 100 NORMAL AVDD 10 T E NORMAL DVDD 1 2 2 IMPULSE AVDD 5 IMPULSE DVDD o z 5 ul a 0 001 OVDD 2 7V 0 0001 2 1 10 100 1000 8 SAMPLING RATE kSPS Figure 15 Operating Currents vs Sample Rate OVDD 2 7V 85 C OVDD 2 7V 25 C gt OVDD 5V 85 C 5 gt 5 a OVDD 5V 25 2 50 100 150 200 CL pF 03057 013 Figure 16 Typical Delay vs Load Capacitance C Rev B Page 13 of 28 03057 014 03057 015 03057 016 AD7654 APPLICATION INFORMATION CIRCUIT INFORMATION The AD7654 is a very fast low power single supply precise simultaneous sampling 16 bit ADC The AD7654 provides the user with two on chip track and hold successive approximation ADCs that do not exhibit any pipeline or latency making it ideal for multiple multiplexed channel applications The AD7654 can also be used as a 4 channel ADC with two pairs simultaneously sampled The AD7654 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic It is housed in a 48 lead LQFP or tiny 48 lead LFCSP that combines space savings and allows flexible configurations as either a serial or parallel interface The AD7654 is pin to pin compatible with PulSAR ADCs MODES OF OPERATION The AD7654 features two modes of operation normal and impulse Each of these modes is more suitable for specific2. 102 v SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO 220 VKKD 2 Figure 36 48 Lead Lead Frame Chip Scale Package LFCSP VO 7 7 48 1 Dimensions shown in millimeters Rev B Page 26 of 28 AD7654 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7654ACP 409 to 85 C Lead Frame Chip Scale Package LFCSP_VQ CP 48 1 AD7654ACPRL 409 to 85 C Lead Frame Chip Scale Package LFCSP_VQ CP 48 1 AD7654ACPZ 409 to 85 C Lead Frame Chip Scale Package LFCSP_VQ CP 48 1 AD7654ACPZRL 409 to 85 C Lead Frame Chip Scale Package LFCSP VQ CP 48 1 AD7654AST 40 C to 85 C Low Profile Quad Flat Package LOFP ST 48 AD7654ASTRL 40 C to 85 C Low Profile Quad Flat Package LOFP ST 48 AD7654ASTZ 40 to 85 C Low Profile Quad Flat Package LOFP ST 48 AD7654ASTZRL 40 C to 85 Low Profile Quad Flat Package LOFP ST 48 EVAL AD7654CB Evaluation Board EVAL CONTROL BRD2 EVAL CONTROL BRD3 Controller Board Controller Board 17 Pb free part This board can be used as a standalone evaluation board or in conjunction with the EVAL CONTROL BRD2 EVAL CONTROL BRD3 for evaluation demonstration purposes 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator Rev B Page 27 of 28 AD7654 NOTES 2005 Analog Devices Inc All rights reserved Trademarks a
3. 14 Modes of Operation seen 14 Transfer F ctions s siape aa 14 Typical Connection Diagram 0 2 2 0 16 Analog Inp ts eee tente R 16 Input Channel Multiplexer eee 16 REVISION HISTORY 11 05 Rev A to Rev B Changes to General Description sse 1 Changes to Timing Specifications 5 Changes to Figure lOean ieser ees etier i aiir iasi 13 Changes to Figure 18 ede nto e ee ESI 15 Added Table 8 2 toe een 17 Changes to Figure 24 19 Changes to Figure 29 eiecti eet hene 21 Updated Outline Dimensions seen 26 Changes to Ordering Guide eee 26 Driver Amplifier Choice eene 16 Voltage Reference Input essent 17 Power Supply iode en e oett 17 Power Dissipation sssseseeeeeeenenene nennen 17 Conversion Control sentent 18 Digital Interfaces a EEs 18 Parallel Interface siiicar 18 Serial Interface en R E 20 Master Serial Interface eerte 20 Slave Serial Interface 5 5 cement 22 Microprocessor Interfacing sse 24 SPI Interface ADSP 219x sss 24 Application Hints aere ee etd 25 Layout xe INE RR ERR ERN 25 Evaluating the AD7654 Performance sse 25 Outline Dimensions essent 26 Ordering Guide oe remm ted 27 11 04 Rev 0 t
4. 175 200 225 250 DNL LSB 03057 005 COUNTS 03057 006 SNR dB 03057 007 Rev B Page 12 of 28 3 0 16384 32768 49152 65535 5 CODE 8 Figure 8 Differential Nonlinearity vs Code 7FCO 7FC1 7FC2 7FC3 7FC4 7FC5 7FC6 CODE IN HEX 03057 009 Figure 9 Histogram of 16 384 Conversions of a DC Input at the Code Center TEMPERATURE C Figure 10 SNR THD vs Temperature 03057 010 SNR SINAD dB SNR SINAD dB THD HARMONICS CROSSTALK dB 100 16 0 95 15 5 90 15 0 85 14 5 7 75 13 5 70 13 0 10 100 1000 FREQUENCY kHz Figure 11 SNR SINAD and ENOB vs Frequency 92 TA 88 86 INPUT LEVEL dB Figure 12 SNR and SINAD vs Input Level Referred to Full Scale 115 110 105 100 95 90 85 80 THIRD HARMONIC 75 70 HARMONIC 1 65 60 1 10 100 1000 FREQUENCY kHz Figure 13 THD Harmonics Crosstalk and SFDR vs Frequency AD7654 FULL SCALE ERROR a ENOB Bits LSB 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C 03057 011 Figure 14 Full Scale Error and Zero Error vs Temperature
5. 89 dB Spurious Free Dynamic Range fin 100 kHz 105 dB Total Harmonic Distortion fin 100 kHz 100 dB Signal to Noise and Distortion fin 20 kHz 87 5 90 dB fin 100 kHz 88 5 dB fin 100 kHz 60 dB Input 30 dB Channel to Channel Isolation fin 100 kHz 92 3 dB Input Bandwidth 10 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Delay Matching 30 ps Aperture Jitter 5 ps rms Transient Response Full scale step 250 ns REFERENCE External Reference Voltage Range 2 3 2 5 AVDD 2 External Reference Current Drain 500 kSPS throughput 180 pA DIGITAL INPUTS Logic Levels Vit 0 3 0 8 V Vin 2 0 DVDD 0 3 V 1 1 1 1 yA Rev B Page 3 of 28 AD7654 Parameter Conditions Min Typ Max Unit DIGITAL OUTPUTS Data Format Pipeline Delay Vor Isink 1 6 mA 0 4 V Vou Isource 500 pA OVDD 0 2 V POWER SUPPLIES Specified Performance AVDD 4 75 5 5 25 V DVDD 4 75 5 5 25 V OVDD 27 5 258 V Operating Current 500 kSPS throughput AVDD 15 5 mA DVDD 8 5 mA OVDD 100 uA Power Dissipation 500 kSPS throughput 120 135 mW 10 kSPS throughput 2 6 mW 444 kSPS throughput 114 125 mW TEMPERATURE RANGE Specified Performance Tmn to Tmax 40 85 1 the Analog Inputs section Linearity is tested using endpoints not best fit 3 LSB means least significant bit Within the 0 V to 5 V input range one LSB is 76 294 uV 4 See the Terminology section T
6. AD7654 MICROPROCESSOR INTERFACING The AD7654 is ideally suited for traditional dc measurement applications supporting a microprocessor and for ac signal processing applications interfacing to a digital signal processor The AD7654 is designed to interface with either a parallel 8 bit wide or 16 bit wide interface a general purpose serial port or ports on a microcontroller A variety of external buffers can be used with the AD7654 to prevent digital noise from coupling into the ADC The following section illustrates the use of the AD7654 with an SPI equipped DSP the ADSP 219x SPI INTERFACE ADSP 219x Figure 34 shows an interface diagram between the AD7654 and the SPI equipped ADSP 219x To accommodate the slower speed of the DSP the AD7654 acts as a slave device and data must be read after conversion This mode also allows the daisy chain feature The convert command can be initiated in response to an internal timer interrupt The 32 bit output data is read with two serial peripheral interface SPI 16 bit wide accesses The reading process can be initiated in response to the end of conversion signal BUSY going low using an interrupt line of the DSP By writing to the SPI control register SPICLTx the serial interface SPI on the ADSP 219x is configured for master mode MSTR 1 clock polarity bit CPOL 0 clock phase bit CPHA 1 and SPI interrupt enable TIMOD 00 To meet all timing requirements the SPI clock
7. INA2 INB2 A0 high The part features a very high sampling rate mode normal and for low power applications a reduced power mode impulse where the power is scaled with the throughput Operation is specified from 40 C to 85 Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM AVDD AGND REFGND REFx DVDD DGND sen FAR CONTROL LOGIC AND RD CALIBRATION CIRCUITRY OAB BYTESWAP 03057 001 Figure 1 Table 1 PulSAR Selection Type kSPS 100 to 250 500 to 570 800 to 1000 gt 1000 Pseudo AD7660 AD7650 AD7667 Differential AD7661 AD7652 AD7653 AD7664 AD7666 True Bipolar AD7663 AD7665 AD7671 True Differential AD7675 AD7676 AD7677 AD7621 AD7623 18 Bit AD7678 AD7679 AD7674 AD7641 Multichannel AD7654 AD7655 Simultaneous PRODUCT HIGHLIGHTS 1 Simultaneous Sampling The AD7654 features two sample and hold circuits that allow simultaneous sampling It provides inputs for four channels 2 Fast Throughput
8. both CS and RD are low the data can be read after each conversion or during the following conversion The external clock can be either a continuous or discontinuous clock A discontinuous clock can be either normally high or normally low when inactive Figure 32 and Figure 33 show the detailed timing diagrams of these methods While the AD7654 is performing a bit decision it is important that voltage transients not occur on digital input output pins or degradation of the conversion result could occur This is particularly important during the second half of the conversion phase of each channel because the AD7654 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase For this reason it is recommended that when an external clock is provided it is a discontinuous clock that toggles only when BUSY is low or more importantly that it does not transition during the latter half of EOC high External Discontinuous Clock Data Read After Convert Although the maximum throughput cannot be achieved in this mode it is the most recommended of the serial slave modes Figure 32 shows the detailed timing diagrams of this method After a conversion is complete indicated by BUSY returning low the conversion results can be read while both CS and RD are low Data is shifted out from both channels MSB first with 32 clock pulses and is valid on both rising and falling edges of the
9. bus In parallel mode signal A B allows the choice of reading either the output of Channel A or Channel B whereas in serial mode signal A B controls which channel is output first Figure 23 details the timing when using the RESET input Note the current conversion if any is aborted and the data bus is high impedance while RESET is high to RESET BUSY CNVST 03057 023 Figure 23 Reset Timing PARALLEL INTERFACE The AD7654 is configured to use the parallel interface when SER PAR is held low Master Parallel interface Data can be read continuously by tying CS and RD low thus requiring minimal microprocessor connections However in this mode the data bus is always driven and cannot be used in shared bus applications unless the device is held in RESET Figure 24 details the timing for this mode Rev B Page 18 of 28 CS 0 CNVST BUSY EOC t4 t4 DATA PREVIOUS CHANNEL A PREVIOUS CHANNEL B NEW BUS ORB OR NEWA ORB Figure 24 Master Parallel Data Timing for Continuous Read 03057 024 Slave Parallel Interface In slave parallel reading mode the data can be read either after each conversion which is during the next acquisition phase or during the other channel conversion or during the following conversion as shown in Figure 25 and Figure 26 respectively When the data is read during the conversion however it is recommended that it is read only during the first
10. clock One advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process Another advantage is the ability to read the data at any speed up to 40 MHz which accommodates both a slow digital host interface and the fastest serial reading Finally in this mode only the AD7654 provides a daisy chain feature using the RDC SDIN serial data in input pin for cascading multiple converters together This feature is useful for reducing component count and wiring connections when it is desired as in isolated multiconverter applications An example of the concatenation of two devices is shown in Figure 31 Simultaneous sampling is possible by using a common CNVST signal Note that the RDC SDIN input is latched on the edge of SCLK opposite the one used to shift out the data on SDOUT Therefore the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle The SDIN input should be tied either high or low on the most upstream converter in the chain BUSY BUSY AD7654 1 DOWNSTREAM 2 UPSTREAM RDC SDIN SDOUT RDC SDIN SDOUT CNVST CNVST cs cs SCLK SCLK 03057 031 CNVST IN O Figure 31 Two AD7654s in a Daisy Chain Configuration External Clock Data Read Previous During Convert Figure 33 shows the detailed timing diagrams of this method During a conversion while both CS and RD are
11. half of the conversion phase This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry CURRENT CONVERSION 03057 025 tig 5 gt tig DATA BUS 03057 026 Figure 26 Slave Parallel Data Timing for a Read During Conversion AD7654 8 Bit Interface Master or Slave The BYTESWAP pin allows a glueless interface to an 8 bit bus As shown in Figure 27 the LSB byte is output on D 7 0 and the MSB is output D 15 8 when BYTESWAP is low When BYTESWAP is high the LSB and MSB bytes are swapped the LSB is output on D 15 8 and the MSB is output on D 7 0 By connecting BY TESWAP to an address line the 16 bit data can be read in two bytes on either D 15 8 or D 7 0 BYTESWAP PINS D 15 8 HIGH BYTE LOW BYTE T PINS D 7 0 LOW BYTE HIGH BYTE 5 Figure 27 8 Bit Parallel Interface Channel A B Output The A B input controls which channel s conversion results INAx or INBx are output on the data bus The functionality of A B is detailed in Figure 28 When high the data from Channel A is available on the data bus When low the data from Channel B is available on the bus Note that Channel A can be read immediately after conversion is done EOC while Channel B is still in its converting phase However in any of the serial reading modes Channel A data is updated only after Channel B i
12. should be limited to 17 Mbps which allows it to read an ADC result in less than 1 us When a higher sampling rate is desired use of one of the parallel interface modes is recommended DVDD AD7654 ADSP 219x SER PAR EXT INT PFx SPIxSEL PFx MISOx RD SCKx INVSCLK PFx or TFSx 03057 034 ADDITIONAL PINS OMITTED FOR CLARITY Figure 34 Interfacing the AD7654 to an SPI Interface Rev B Page 24 of 28 AD7654 APPLICATION HINTS LAYOUT The AD7654 has very good immunity to noise on the power supplies However care should still be taken with regard to grounding layout The printed circuit board that houses the AD7654 should be designed so the analog and digital sections are separated and confined to certain areas of the board This facilitates the use of ground planes that can be separated easily Digital and analog ground planes should be joined in only one place preferably underneath the AD7654 or as close as possible to the AD7654 If the AD7654 is in a system where multiple devices require analog to digital ground connections the connection should still be made at only a star ground point established as close as possible to the AD7654 Running digital lines under the device should be avoided because these couple noise onto the die The analog ground plane should be allowed to run under the AD7654 to avoid noise coupling Fast switching signals like CNVST or clocks should be shielded with digital ground to
13. ANALOG DEVICES 16 Bit 500 kSPS PulSAR Dual 2 Channel Simultaneous Sampling ADC AD7654 FEATURES Dual 16 bit 2 channel simultaneous sampling ADC 16 bit resolution with no missing codes Throughput 500 kSPS normal mode 444 kSPS impulse mode INL 3 5 LSB max 0 0053 of full scale SNR 89 dB typ 100 kHz THD 100 dB 100 kHz Analog input voltage range 0 V to5V No pipeline delay Parallel and serial 5 V 3 V interface SPI QSPI MICROWIRE DSP compatible Single 5 V supply operation Power dissipation 120 mW typical 2 6 mW 10 kSPS Packages 48 lead low profile quad flat package LOFP 48 lead lead frame chip scale package LFCSP Low cost APPLICATIONS AC motor control 3 phase power control 4 channel data acquisition Uninterrupted power supplies Communications GENERAL DESCRIPTION The AD7654 is a low cost simultaneous sampling dual channel 16 bit charge redistribution SAR analog to digital converter that operates from a single 5 V power supply It contains two low noise wide bandwidth track and hold amplifiers that allow simultaneous sampling a high speed 16 bit sampling ADC an internal conversion clock error correction circuits and both serial and parallel system interface ports Each track and hold has a multiplexer in front to provide a 4 channel input ADC AO multiplexer control input allows the choice of simultaneously sampling input pairs INA1 INB1 A0 low or
14. High tas 10 ns External SCLK Low t44 10 ns In serial interface modes the SYNC SCLK and SDOUT timings are defined with a maximum load C of 10 pF otherwise is 60 pF maximum In serial master read during convert mode See Table 4 for serial master read after convert mode Table 4 Serial Clock Timings in Master Read After Convert DIVSCLK 1 0 0 1 1 DIVSCLK O Symbol 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum tos 3 17 17 17 ns Internal SCLK Period Minimum t26 25 50 100 200 ns Internal SCLK Period Typical 06 40 70 140 280 ns Internal SCLK High Minimum t27 12 22 50 100 ns Internal SCLK Low Minimum tos 7 21 49 99 ns SDOUT Valid Setup Time Minimum t29 4 18 18 18 ns SDOUT Valid Hold Time Minimum t30 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum 131 1 3 30 80 ns Busy High Width Maximum Normal tas 3 25 4 25 6 25 10 75 us Busy High Width Maximum Impulse t35 3 5 4 5 6 5 11 us Rev B Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Values Analog Inputs INAx INBx REFx INXN AVDD 0 3 V to REFGND AGND 0 3 V Ground Voltage Differences AGND DGND OGND 0 3V Supply Voltages AVDD DVDD OVDD 0 3 V to 7 V AVDD to DVDD AVDD to OVDD 7V DVDD to OVDD 0 3 V to 7 V Digital Inputs 0 3 V to DVDD 0 3 V Internal Power Dissipation 700 mW Internal Power Dissipation 2 5 W Junction Temperature 150 C Storage Temperature Range 65 C to 150 C Lead Temperature R
15. Setup Time ta 250 ns Channel Selection Hold Time tis 30 ns PARALLEL INTERFACE MODES See Figure 24 to Figure 28 CNVST Low to DATA Valid Delay tis 1 75 2 us DATA Valid to BUSY Low Delay ti7 14 ns Bus Access Request to DATA Valid tis 40 ns Bus Relinquish Time tio 5 15 ns A B Low to Data Valid Delay tzo 40 ns MASTER SERIAL INTERFACE MODES see Figure 29 and Figure 30 CS Low to SYNC Valid Delay tai 10 ns CS Low to Internal SCLK Valid Delay t 10 ns CS Low to SDOUT Delay tos 10 ns CNVST Low to SYNC Delay Read During Convert Normal Mode Impulse Mode t24 250 500 ns SYNC Asserted to SCLK First Edge Delay t25 3 ns Internal SCK Period t26 23 40 ns Internal SCLK High t27 12 ns Internal SCLK Low t28 7 ns SDOUT Valid Setup Time t29 4 ns SDOUT Valid Hold Time t30 2 ns SCLK Last Edge to SYNC Delay 1 ns CS High to SYNC HI Z t32 10 ns CS High to Internal SCLK HI Z 10 ns CS High to SDOUT HI Z tsa 10 ns BUSY High in Master Serial Read After Convert 135 See Table 4 CNVST Low to SYNC Asserted Delay Normal Mode Impulse Mode t36 0 75 1 us SYNC Deasserted to BUSY Low Delay t37 25 ns Rev B Page 5 of 28 AD7654 Parameter Symbol Min Typ Max Unit SLAVE SERIAL INTERFACE MODES see Figure 32 and Figure 33 External SCLK Setup Time 5 ns External SCLK Active Edge to SDOUT Delay t39 3 18 ns SDIN Setup Time tao 5 ns SDIN Hold Time ta 5 ns External SCLK Period ta2 25 ns External SCLK
16. The AD7654 is a 500 kSPS charge redistribution 16 bit SAR ADC with internal error correction circuitry 3 Superior INL and No Missing Codes The AD7654 has a maximum integral nonlinearity of 3 5 LSB with no missing 16 bit codes 4 Single Supply Operation The AD7654 operates from a single 5 V supply In impulse mode its power dissipation decreases with throughput 5 Serial or Parallel Interface Versatile parallel or 2 wire serial interface arrangement is compatible with both 3 V and 5 V logic One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved AD7654 TABLE OF CONTENTS Features zc eae eeu p IR 1 AppliCatiOns IA 1 Functional Block Diagram 1 General Descriptions svesessivccstseiswssiwssvecsscevensevssswustvccusctesnsuessevainvtives 1 Product Highlights ette e Ie 1 3 Timing Specifications sees 5 Absolute Maximum Ratings seen 7 ESD Caution z cese eere 7 Pin Configuration and Function 8 11 Typical Performance Characteristics 12 Application Information seen 14 Circuit
17. ange Soldering 10 sec 300 C AD7654 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 1 See Analog Inputs section 2 Specification is for device in free air 48 lead LQFP 91 C W 30 C W 3 Specification is for device in free air 48 lead LFCSP 26 C W ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev B Page 7 of 28 TO OUTPUT PIN c 60pF T IN SERIAL INTERFACE MODES THE SYNC SCLK AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF OTHERWISE THE LOAD IS 60pF MAXIMUM SDOUT SYNC SCLK Outputs C 10 pF WARNI 03057 002 Figure 2 Load Circuit for Digital Interface Timing 03057 003 Figure 3 Voltage Reference Levels f
18. applications Normal mode is the fastest mode 500 kSPS Except when it is powered down PD the power dissipation is almost independent of the sampling rate Impulse mode the lowest power dissipation mode allows power saving between conversions The maximum throughput in this mode is 444 kSPS When operating at 10 kSPS for example it typically consumes only 2 6 mW This feature makes the AD7654 ideal for battery powered applications TRANSFER FUNCTIONS The AD7654 data format is straight binary The ideal transfer characteristic for the AD7654 is shown in Figure 17 and Table 7 The LSB size is 2 Vrex 65536 which is about 76 3 uV 111 111 111 110 5 111 101 8 2 lt 000 010 000 001 000 000 Fs FS 1 LSB 5 1 LSB FS 0 5 LSB FS 1 5 LSB ANALOG INPUT 03057 017 Figure 17 ADC Ideal Transfer Function Table 7 Output Codes and Ideal Input Voltages Description Analog Input Digital Output Code Vrer 2 5 FSR 1 LSB 4 999924 V FSR 2 LSB 4 999847 V OxFFFE Midscale 1 LSB 2 500076 V 0x8001 Midscale 2 5V 0x8000 Midscale 1 LSB 2 499924 V Ox7FFF FSR 1 LSB 76 29 uV 0x0001 FSR OV 0 00002 This is also the code for overrange analog input Vinx above 2 X Vner This is also the code for underrange analog input Vinx below Rev B Pag
19. avoid radiating noise to other sections of the board and should never run near analog signal paths Crossover of digital and analog signals should be avoided Traces on different but close layers of the board should run at right angles to each other This reduces the effect of crosstalk through the board The power supply lines to the AD7654 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines Good decoupling is also important to lower the supply s impedance presented to the AD7654 and to reduce the magnitude of the supply spikes Decoupling ceramic capacitors typically 100 nF should be placed on each power supply pin AVDD DVDD and OVDD close to and ideally right up against these pins and their corresponding ground pins Additionally low ESR 10 uF capacitors should be located near the ADC to further reduce low frequency ripple The DVDD supply of the AD7654 can be a separate supply or can come from the analog supply AVDD or the digital interface supply OVDD When the system digital supply is noisy or when fast switching digital signals are present if no separate supply is available the user should connect DVDD to AVDD through an RC filter see Figure 18 and the system supply to OVDD and the remaining digital circuitry When DVDD is powered from the system supply it is useful to insert a bead to further reduce high frequency spikes The AD7654 has f
20. ce especially the total harmonic distortion The maximum source impedance depends on the amount of total harmonic distortion THD that can be tolerated The THD degrades as the source impedance increases INPUT CHANNEL MULTIPLEXER The AD7654 allows the choice of simultaneously sampling the inputs pairs INA1 INB1 or INA2 INB2 with the AO multiplexer input When 0 is low the input pairs INA1 INB1 are selected and when 0 is high the input pairs INA2 INB2 are selected Note that INAx is always converted before INBx regardless of the state of the digital interface channel selection A B pin Also note that the channel selection control A0 should not be changed during the acquisition phase of the converter Refer to the Conversion Control section and Figure 22 for timing details DRIVER AMPLIFIER CHOICE Although the AD7654 is easy to drive the driver amplifier needs to meet at least the following requirements e For multichannel multiplexed applications the driver amplifier and the AD7654 analog input circuit together must be able to settle for a full scale step of the capacitor array at a 16 bit level 0 001596 In the amplifier s data sheet the settling at 0 196 or 0 0196 is more commonly specified It could significantly differ from the settling time at a 16 bit level and therefore it should be verified prior to the driver selection e The noise generated by the driver amplifier needs to be kept as low as possible to pre
21. e 14 of 28 AD7654 DVDD ANALOG 300 o DIGITAL SUPPLY nu 3 3V OR 5V tL tour 400nF 10pF AD780 DGND DVDD OVDD OGND SERIAL PORT 2 5V REF 1wo 1 REFA SCLK NOTE 1 ANALOG INPUT A10 AD7654 SER PAR DVDD am d 8 cs NOTE 4 ANALOG INPUT 20 Cs RESET gt ee ANALOG INPUT B10 NOTE 4 ANALOG INPUT B2 NOTES 1 SEE VOLTAGE REFERENCE INPUT SECTION 2 WITH THE RECOMMENDED VOLTAGE REFERENCES Crer IS 47 SEE VOLTAGE REFERENCE INPUT SECTION 3 OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION 4 THE AD8021 IS RECOMMENDED SEE DRIVER AMPLIFIER CHOICE SECTION 5 SEE ANALOG INPUTS SECTION z 6 OPTIONAL SEE POWER SUPPLY SECTION 5 7 OPTIONAL LOW JITTER CNVST SEE CONVERSION CONTROL SECTION 8 Figure 18 Typical Connection Diagram Serial Interface Rev B Page 15 of 28 AD7654 TYPICAL CONNECTION DIAGRAM Figure 18 shows a typical connection diagram for the AD7654 Different circuitry shown on this diagram is optional and is discussed in the following sections ANALOG INPUTS Figure 19 shows a simplified analog input section of the AD7654 03057 019 AGND A0 Figure 19 Simplified Analog Input The diodes shown in Figure 19 provide ESD protection for the inputs Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs This causes these diodes to become forward biased and start conducting current These di
22. e as possible to the REF REFGND inputs Also it is recommended that a buffer such as the AD8031 AD8032 be used in this configuration AD7654 Care should be taken with the reference temperature coefficient of the voltage reference which directly affects the full scale accuracy if this parameter is applicable For instance a 15 ppm C tempco of the reference changes the full scale accuracy by 1 LSB C POWER SUPPLY The AD7654 uses three sets of power supply pins an analog 5 V supply AVDD a digital 5 V core supply DVDD and a digital input output interface supply OVDD The OVDD supply allows direct interface with any logic working between 2 7 V and DVDD 0 3 V To reduce the number of supplies needed the digital core DVDD can be supplied through a simple RC filter from the analog supply as shown in Figure 18 The AD7654 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0 3 V and thus free from supply voltage induced latch up Additionally it is very insensitive to power supply variations over a wide frequency range as shown in Figure 20 70 65 60 55 PSRR dB 50 45 1 10 100 1000 10000 FREQUENCY kHz 03057 020 Figure 20 PSRR vs Frequency POWER DISSIPATION In impulse mode the AD7654 automatically reduces its power consumption at the end of each conversion phase During the acquisition phase the operating currents are very low which allows si
23. ete 17 OGND P Input Output Interface Digital Power Ground 18 OVDD P Input Output Interface Digital Power Nominally at the same supply as the supply of the host interface 5 V or3V 19 36 DVDD P Digital Power Nominally at 5 V 21 D 8 DO When SER PAR is LOW this output is used as Bit 8 of the Parallel port data output bus or SDOUT When SER PAR is HIGH this output part of the serial port is used as a serial data output synchronized to SCLK Conversion results are stored in a 32 bit on chip register The AD7654 provides the two conversion results MSB first from its internal shift register The order of channel outputs is controlled by A B In serial mode when EXT INT is LOW SDOUT is valid on both edges of SCLK In Serial Mode when EXT INT is HIGH If INVSCLK is LOW SDOUT is updated on the SCLK rising edge and valid on the next falling edge If INVSCLK is HIGH SDOUT is updated on the SCLK falling edge and valid on the next rising edge 22 D 9 DI O When SER PAR is LOW this output is used as Bit 9 of the Parallel Port Data Output Bus or SCLK When SER PAR is HIGH this pin part of the serial port is used as a serial data clock input or output dependent upon the logic state of the EXT INT pin The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin 23 D 10 DO When SER PAR is LOW this output is used as Bit 10 of the parallel port data output bus or SYNC When SER PAR is HIGH this output part of the se
24. external clock signal connected to the SCLK input 14 D 5 DI O When SER PAR is LOW this output is used as Bit 5 of the parallel port data output bus or INVSYNC When SER PAR is HIGH this input part of the serial port is used to select the active state of the SYNC signal in Master modes When LOW SYNC is active HIGH When HIGH SYNC is active LOW Rev B Page 8 of 28 AD7654 Pin No Mnemonic Type Description 15 D 6 DI O When SER PAR is LOW this output is used as Bit 6 of the parallel port data output bus or INVSCLK When SER PAR is HIGH this input part of the serial port is used to invert the SCLK signal It is active in both master and slave modes 16 D 7 DI O When SER PAR is LOW this output is used as Bit 7 of the parallel port data output bus or RDC SDIN When SER PAR is HIGH this input part of the serial port is used as either an external data input or a read mode selection input depending on the state of EXT INT When EXT INT is HIGH RDC SDIN be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line The digital data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the initiation of the read sequence When EXT INT is LOW RDC SDIN is used to select the read mode When RDC SDIN is HIGH the previous data is output on SDOUT during conversion When RDC SDIN is LOW the data can be output on SDOUT only when the conversion is compl
25. gnificant power savings when the conversion rate is reduced as shown in Figure 21 This feature makes the AD7654 ideal for very low power battery applications Note that the digital interface remains active even during the acquisition phase To reduce the operating digital supply currents even further the digital inputs need to be driven close to the power rails that is DVDD and DGND and OVDD should not exceed DVDD by more than 0 3 V Rev Page 17 of 28 AD7654 1000 100 POWER DISSIPATION mW 100 1000 SAMPLING RATE kSPS 03057 021 Figure 21 Power Dissipation vs Sample Rate CONVERSION CONTROL Figure 22 shows the detailed timing diagrams of the conversion process The AD7654 is controlled by the signal CNVST which initiates conversion Once initiated it cannot be restarted or aborted even by the power down input PD until the conversion is complete The CNVST signal operates independently of the CS and RD signals t le t4 CNVST t44 A0 MODE ACQUIRE CONVERT A CONVERT 03057 022 Figure 22 Basic Conversion Timing Although CNVST is a digital signal it should be designed with special care with fast clean edges and levels and with minimum overshoot and undershoot or ringing For applications where the SNR is critical the CNVST signal should have very low jitter Some solut
26. hese specifications do not include the error contribution from the external reference 5 All specifications in dB are referred to as full scale input FS tested with an input signal at 0 5 dB below full scale unless otherwise specified 6 Parallel or serial 16 bit Conversion results are available immediately after completed conversion The maximum should be the minimum of 5 25 V and DVDD 0 3 V n normal mode tested in parallel reading mode 10 n impulse mode tested in parallel reading mode 11 Consult sales for extended temperature range Rev B Page 4 of 28 AD7654 TIMING SPECIFICATIONS AVDD DVDD 5 V OVDD 2 7 V to 5 25 V all specifications Tum to Tmax unless otherwise noted Table 3 Parameter Symbol Min Typ Max Unit CONVERSION AND RESET See Figure 22 and Figure 23 Convert Pulse Width ti 5 ns Time Between Conversions Normal Mode Impulse Mode t 2 2 25 us CNVST Low to BUSY High Delay 32 ns BUSY High All Modes Except in Master Serial Read After Convert Mode Normal Mode Impulse Mode ta 1 75 2 us Aperture Delay ts 2 ns End of Conversions to BUSY Low Delay te 10 ns Conversion Time Normal Mode Impulse Mode t 1 75 2 us Acquisition Time ts 250 ns RESET Pulse Width to 10 ns CNVST Low to EOC High Delay tio 30 ns EOC High for Channel A Conversion Normal Mode Impulse Mode tu 1 1 25 us EOC Low after Channel A Conversion to 45 ns EOC High for Channel B Conversion 0 0 75 Hs Channel Selection
27. ions to achieve this are to use a dedicated oscillator for CNVST generation or at least to clock it with a high frequency low jitter clock as shown in Figure 18 In impulse mode conversions can be automatically initiated If CNVST is held low when BUSY is low the AD7654 controls the acquisition phase and automatically initiates a new conversion By keeping CNVST low the AD7654 keeps the conversion process running by itself Note that the analog input has to be settled when BUSY goes low Also at power up CNVST should be brought low once to initiate the conversion process In this mode the AD7654 could sometimes run slightly faster than the guaranteed limits of 444 kSPS in impulse mode This feature does not exist in normal mode DIGITAL INTERFACE The AD7654 has a versatile digital interface it can be interfaced with the host system by using either a serial or parallel interface The serial interface is multiplexed on the parallel data bus The AD7654 digital interface accommodates either 3 V or 5 V logic by simply connecting the OVDD supply pin of the AD7654 to the host system interface digital supply The two signals CS and RD control the interface When at least one of these signals is high the interface outputs are in high impedance Usually CS allows the selection of each AD7654 in multicircuit applications and is held low in a single AD7654 design RD is generally used to enable the conversion result on the data
28. ive different ground pins INGND REFGND AGND DGND and OGND INGND is used to sense the analog input signal REFGND senses the reference voltage and because it carries pulsed currents should be a low impedance return to the reference AGND is the ground to which most internal ADC analog signals are referenced it must be connected with the least resistance to the analog ground plane DGND must be tied to the analog or digital ground plane depending on the configuration OGND is connected to the digital system ground EVALUATING THE AD7654 PERFORMANCE recommended layout for the AD7654 is outlined in the documentation of the evaluation board for the EVAL AD7654CB The evaluation board package includes fully assembled and tested evaluation board documentation and software for controlling the board from a PC via the EVAL CONTROL BRD3 Rev B Page 25 of 28 AD7654 OUTLINE DIMENSIONS TOP VIEW PINS DOWN VIEWA 0 50 le 0 27 BSC 0 22 LEAD PITCH 0 1 VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026 BBC Figure 35 48 Lead Low Profile Quad Flat Package LOFP ST 48 Dimensions shown in millimeters 7 00 0 60 MAX __ i t PIN 1 EXPOSED 6 75 PAD BSC SQ BOTTOM VIEW Y 100 42 MAX 0 80 PADDLE CONNECTED AGND 0 85 je 0 65 TYP THIS CONNECTION IS NOT 0 80 0 05 MAX REQUIRED TO MEET THE Xt q 0 02 NOM ELECTRICAL PERFORMANCES E 0 50
29. low the result of the previous conversion can be read The data is shifted out MSB first with 32 clock pulses and is valid on both the rising and falling edges of the clock The 32 bits have to be read before the current conversion is completed otherwise RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading There is no daisy chain feature in this mode and RDC SDIN input should always be tied either high or low To reduce performance degradation due to digital activity a fast discontinuous clock at least 32 MHz in impulse mode and 40 MHz in normal mode is recommended to ensure that all of the bits are read during the first half of each conversion phase high tu It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated This allows the use of a slower clock speed like 26 MHz in impulse mode and 30 MHz in normal mode Rev B Page 22 of 28 AD7654 1 INVSCLK 0 0 1 BUSY SCLK SDOUT VXCHA D15 YCHA YYCHA D15 SDIN 03057 032 Figure 32 Slave Serial Data Timing for Reading Read After Convert EXT INT 1 INVSCLK 0 RD 0 1 CNVST BUSY SCLK SDOUT 03057 033 Figure 33 Slave Serial Data Timing for Reading Read Previous Conversion During Convert Rev B Page 23 of 28
30. nd ANALOG registered trademarks are the property of their respective owners C03057 0 11 05 B DEVICES www analog com Rev B Page 28 of 28
31. o Rev A Ch nges to Figure 7 con EHE RTT 12 Changes to Figure 18 ie ie e este es 15 Changes to Figure 19 isis isisisi entente 16 Changes to Voltage Reference Input 17 Changes to Conversion Control Section sss 18 Changes to Digital Interface Section 18 Updated Outline Dimensions sente 25 11 02 Revision 0 Initial Version Rev B Page 2 of 28 SPECIFICATIONS AVDD DVDD 5 V OVDD 2 7 V to 5 25 V all specifications Tum to Tmax unless otherwise noted AD7654 Table 2 Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range Vinx 0 2 Veer V Common Mode Input Voltage 0 1 40 5 V Analog Input CMRR fin 100 kHz 55 dB Input Current 500 kSPS throughput 45 pA Input Impedance THROUGHPUT SPEED Complete Cycle In normal mode 2 us Throughput Rate In normal mode 0 500 kSPS Complete Cycle In impulse mode 2 25 us Throughput Rate In impulse mode 0 444 kSPS DC ACCURACY Integral Linearity Error 3 5 43 5 LSB No Missing Codes 16 Bits Transition Noise 0 7 LSB Full Scale Error4 to Tmax 0 25 0 5 of FSR Full Scale Error Drift 2 ppm C Unipolar Zero Error Tmn to Tmax 0 25 of FSR Unipolar Zero Error Drift 0 8 ppm C Power Supply Sensitivity AVDD 5 V 5 0 8 LSB AC ACCURACY Signal to Noise fin 20 kHz 88 90 dB fin 100 kHz
32. odes can handle a forward biased current of 120 mA maximum This condition could eventually occur when the input buffers U1 or U2 supplies are different from AVDD In such a case an input buffer with a short circuit current limitation can be used to protect the part This analog input structure allows the sampling of the differential signal between INx and INxN Unlike other converters the INxN is sampled at the same time as the INx input By using these differential inputs small signals common to both inputs are rejected During the acquisition phase for ac signals the AD7654 behaves like a one pole RC filter consisting of the equivalent resistance Ra Rs and Cs The resistors Ra and Rs are typically 500 Q and are a lumped component made up of some serial resistors and the on resistance of the switches The capacitor Cs is typically 32 pF and is mainly the ADC sampling capacitor This one pole filter with a typical 3 dB cutoff frequency of 10 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs Because the input impedance of the AD7654 is very high the AD7654 be driven directly by a low impedance source without gain error To further improve the noise filtering of the AD7654 analog input circuit an external one pole RC filter between the amplifier output and the ADC input as shown in Figure 18 can be used However the source impedance has to be kept low because it affects the ac performan
33. of each channel has been output Note that in this mode the SCLK period changes because the LSBs require more time to settle and the SCLK is derived from the SAR conversion clock Note that in the master read after convert mode unlike in other modes the signal BUSY returns low after the 32 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width One advantage of using this mode is that it can accommodate slow digital hosts because the serial clock can be slowed down by using DIVSCLK 1 0 inputs Refer to Table 4 for the timing details Rev B Page 20 of 28 07694 EXT INT 0 RDC SDIN 0 INVSCLK INVSYNC 0 AIB Cs RD BUSY SYNC SCLK SDOUT CHA CHB CHB 015 D1 03057 029 t 4 Figure 29 Master Serial Data Timing for Reading Read After Conversion EXT INT 0 RDC SDIN 1 INVSCLK INVSYNC 0 1 CS RD 2 0 0 1 eh a a CNVST BUSY SYNC SDOUT 03057 030 Figure 30 Master Serial Data Timing for Reading Read Previous Conversion During Convert Rev B Page 21 of 28 AD7654 SLAVE SERIAL INTERFACE External Clock The AD7654 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT INT pin is held high In this mode several methods can be used to read the data The external serial clock is gated by CS When
34. or Timing em Aa ESD SENSITIVE DEVICE AD7654 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6 Pin Function Descriptions an m 5 48 47 46 45 44 43 42 1 40 39 38 37 AGND 1 36 DVDD AVDD 2 Sms 35 CNVST A0 3 34 PD BYTESWAP 4 33 RESET 5 AD7654 32 cs DGND 6 TOP VIEW 31 RD IMPULSE 7 Not to Scale 30 EOC SER PAR 8 29 BUSY s 28 D15 D1 10 27 D14 D2 DIVSCLK 0 11 26 D13 D3 DIVSCLK 1 12 25 D12 p a o 3 N N E N N N e N D4 EXT INT D5 INVSYNC D6 INVSCLK D7 RDC SDIN OGND OVDD DVDD DGND D8 SDOUT D9 SCLK D10 SYNC 11 RDERROR 03057 004 a Figure 4 48 Lead LQFP ST 48 and 48 Lead LFCSP CP 48 Pin No Mnemonic Type Description 1 47 48 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pin Nominally 5 V 3 0 Multiplexer Select When LOW the analog inputs INA1 INB1 are sampled simultaneously then converted When HIGH the analog inputs INA2 and INB2 are sampled simultaneously then converted 4 BYTESWAP DI Parallel Mode Selection 8 bit 16 bit When LOW the LSB is output on D 7 0 and the MSB is output on D 15 8 When HIGH the LSB is output on D 15 8 and the MSB is output on D 7 0 5 A B DI Data Channel Selection In parallel mode when LOW the data from Channel B is read When HIGH the data from Channel A is read In serial mode when HIGH Channel A is ou
35. put signal and is expressed in decibels Signal to Noise and Distortion Ratio SINAD SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels Spurious Free Dynamic Range SFDR The difference in decibels between the rms amplitude of the input signal and the peak spurious signal Effective Number of Bits ENOB ENOB is a measurement of the resolution with a sine wave input It is related to SINAD and expressed in bits by ENOB SINADas 1 76 6 02 and is expressed in bits Aperture Delay Aperture delay is a measure of acquisition performance and is measured from the falling edge of the CNVST input to when the input signals are held for a conversion Transient Response The time required for the AD7654 to achieve its rated accuracy after a full scale step function is applied to its input Rev B Page 11 of 28 AD7654 COUNTS INL LSB AMPLITUDE dB of Full Scale 16384 32768 CODE 49152 65535 Figure 5 Integral Nonlinearity vs Code CODE IN HEX Figure 6 Histogram of 16 384 Conversions of a DC Input at the 75 Code Transition 100 125 150 FREQUENCY kHz Figure 7 FFT Plot 8192 POINT FFT fs 500kHz fin 100kHz 0 5dB SNR 89 9dB SINAD 89 4dB THD 99 3dB
36. rial port is used as a digital output frame synchronization for use with the internal data clock EXT INT Logic LOW When a read sequence is initiated and INVSYNC is LOW SYNC is driven HIGH and frames SDOUT After the first channel is output SYNC is pulsed LOW When a read sequence is initiated and INVSYNC is HIGH SYNC is driven LOW and remains LOW while SDOUT output is valid After the first channel is output SYNC is pulsed HIGH 24 D 11 DO When SER PAR is LOW this output is used as Bit 11 of the parallel port data output bus or RDERROR When SER PAR is HIGH and EXT INT is HIGH this output part of the serial port is used as an incomplete read error flag In Slave mode when a data read is started and not complete when the following conversion is complete the current data is lost and RDERROR is pulsed HIGH 25 to 28 D 12 15 DO Bit 12 to Bit 15 of the parallel port data output bus When SER PAR is HIGH these outputs are in high impedance 29 BUSY DO Busy Output Transitions HIGH when a conversion is started and remains HIGH until the two conversions are complete and the data is latched into the on chip shift register The falling edge of BUSY can be used as a data ready clock signal 30 EOC DO End of Convert Output Goes LOW at each channel conversion 31 RD DI Read Data When CS and RD are both LOW the interface parallel or serial output bus is enabled 32 cs DI Chip Select When CS and RD are both LOW the interface parallel or serial outp
37. s converted DATA BUS CHANNEL B 03057 028 Figure 28 Channel Reading Rev B Page 19 of 28 AD7654 SERIAL INTERFACE The AD7654 is configured to use the serial interface when the SER PAR is held high The AD7654 outputs 32 bits of data MSB first on the SDOUT pin The order of the channels being output is also controlled by A B When high Channel A is output first when low Channel B is output first This data is synchronized with the 32 clock pulses provided on the SCLK pin MASTER SERIAL INTERFACE Internal Clock The AD7654 is configured to generate and provide the serial data clock SCLK when the EXT INT pin is held low The AD7654 also generates a SYNC signal to indicate to the host when the serial data is valid The serial clock SCLK and the SYNC signal can be inverted if desired The output data is valid on both the rising and falling edge of the data clock Depending on RDC SDIN input the data can be read after each conversion or during the following conversion Figure 29 and Figure 30 show the detailed timing diagrams of these two modes Usually because the AD7654 is used with a fast throughput the master read during convert mode is the most recommended serial mode when it can be used In this mode the serial clock and data toggle at appropriate instants which minimizes potential feedthrough between digital activity and the critical conversion decisions The SYNC signal goes low after the LSB
38. serve the SNR and transition noise performance of the AD7654 The noise coming from the driver is filtered by the AD7654 analog input circuit one pole low pass filter made by R4 Rs and Cs The SNR degradation due to the amplifier is 56 SNR 20 log 56 5 Ney where faa is the 3 dB input bandwidth in MHz of the AD7654 10 MHZ or the cutoff frequency of the input filter if any is used noise factor of the amplifier 1 if in buffer configuration en _ is the equivalent input noise voltage of the op amp in nV VHz For instance a driver like the AD8021 with an equivalent input noise of 2 nV VHz configured as a buffer and thus with a noise gain of 1 degrades the SNR by only 0 06 dB with the filter in Figure 18 and by 0 10 dB without e The driver needs to have a THD performance suitable to that of the AD7654 Rev B Page 16 of 28 AD8021 meets these requirements and is usually appro priate for almost all applications The AD8021 needs an external compensation capacitor of 10 pF This capacitor should have good linearity as an NPO ceramic or mica type The AD8022 could be used where a dual version is needed and a gain of 1 is used The AD829 is another alternative where high frequency above 100 kHz performance is not required In a gain of 1 it requires an 82 pF compensation capacitor The AD8610 is another option where low bias current is needed in low frequency applica
39. tions Refer to Table 8 for some recommended op amps Table 8 Recommended Driver Amplifiers Amplifier Typical Application ADA4841 Very low noise low distortion low power low frequency AD829 Very low noise low frequency AD8021 Very low noise high frequency AD8022 Very low noise high frequency dual AD8655 AD8656 Low noise 5 V single supply low power low frequency single dual AD8610 AD8620 Low bias current low frequency single dual VOLTAGE REFERENCE INPUT The AD7654 requires an external 2 5 V reference The reference input should be applied to REF REFA and REFB The voltage reference input REF of the AD7654 has a dynamic input impedance it should therefore be driven by a low impedance source with an efficient decoupling This decoupling depends on the choice of the voltage reference but usually consists of a 1 ceramic capacitor a low ESR tantalum capacitor connected to the REFA REFB and REFGND inputs with minimum parasitic inductance A value of 47 uF is an appro priate value for the tantalum capacitor when using one of the recommended reference voltages The low noise low temperature drift AD780 AD361 ADR421 and ADR431 voltage reference The low cost AD1582 voltage reference For applications using multiple AD7654s with one voltage reference source it is recommended that the reference source drives each ADC in a star configuration with individual decoupling placed as clos
40. tput first followed by Channel B When LOW Channel B is output first followed by Channel A 6 20 DGND P Digital Power Ground 7 IMPULSE DI Mode Selection When HIGH this input selects a reduced power mode In this mode the power dissipation is approximately proportional to the sampling rate 8 SER PAR DI Serial Parallel Selection Input When LOW the parallel port is selected when HIGH the serial interface mode is selected and some bits of the DATA bus are used as a serial port 9 10 D 0 1 DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus When SER PAR is HIGH these outputs are in high impedance 11 12 D 2 3 or DI O When SER PAR is LOW these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus DIVSCLK 0 1 When SER PAR is HIGH EXT INT is LOW and RDC SDIN is LOW which is the serial master read after convert mode these inputs part of the serial port are used to slow down if desired the internal serial clock that clocks the data output In the other serial modes these inputs are not used 13 D 4 DI O When SER PARis LOW this output is used as Bit 4 of the parallel port data output bus or EXT INT When SER PARis HIGH this input part of the serial port is used as a digital select input for choosing the internal or an external data clock called respectively master and slave mode With EXT INT tied LOW the internal clock is selected on SCLK output With EXT INT set to a logic HIGH output data is synchronized to an
41. ual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs LSB before the first code transition Positive full scale is defined as a level 1 LSB beyond the last code transition The deviation is measured from the middle of each code to the true straight line Differential Nonlinearity Error DNL In an ideal ADC code transitions are 1 LSB apart Differential nonlinearity is the maximum deviation from this ideal value It is often specified in terms of resolution for which no missing codes are guaranteed Full Scale Error The last transition from 111 10 to 111 11 should occur for an analog voltage 1 LSB below the nominal full scale 4 999886 V for the 0 V to 5 V range The full scale error is the deviation of the actual level of the last transition from the ideal level Unipolar Zero Error The first transition should occur at a level LSB above analog ground 76 29 uV for the 0 V to 5 V range The unipolar zero error is the deviation of the actual transition from that point Signal to Noise Ratio SNR SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency excluding harmonics and dc The value for SNR is expressed in decibels AD7654 Total Harmonic Distortion THD THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full scale in
42. ut bus is enabled CS is also used to gate the external serial clock 33 RESET Reset Input When set to a logic HIGH reset the AD7654 Current conversion if any is aborted If not used this pin could be tied to DGND 34 PD Power Down Input When set to a logic HIGH power consumption is reduced and conversions inhibited after the current one is completed Rev B Page 9 of 28 AD7654 Pin No Mnemonic Type Description 35 CNVST Start Conversion A falling edge CNVST puts the internal sample and hold into the hold state initiates a conversion In impulse mode IMPULSE HIGH if CNVST is held LOW when the acquisition phase ts is complete the internal sample and hold is put into the hold state and a conversion is immediately started 37 REF Al This input pin is used to provide a reference to the converter 38 REFGND Al Reference Input Analog Ground 39 41 INB1 INB2 Al Channel B Analog Inputs 40 45 INBN INAN Al Analog Inputs Ground Senses Allow to sense each channel ground independently 42 43 REFB REFA Al These inputs are the references applied to Channel A and Channel B respectively 44 46 INA2 INA1 Al Channel A Analog Inputs 1 Al analog input DI digital input DI O bidirectional digital DO digital output P power Rev B Page 10 of 28 TERMINOLOGY Integral Nonlinearity Error INL Linearity error refers to the deviation of each individ
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ANALOG DEVICES AD7654 English products handbook