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ANALOG DEVICES AD7732 English products handbook

1. 6 144 MHz The conversion time is selected via the channel conversion time register Table 4 Typical Output RMS Noise in pV vs Conversion Time and Input Range with Chopping Enabled FW Conversion Time Conversion Time Output Data Rate 3 dB Frequency RMS Noise Register ps H2 H2 pV 127 FFh 2686 372 200 9 6 46 AEh 999 1001 520 15 5 22 96h 499 2005 1040 22 7 17 91h 395 2534 1300 26 1 8 88h 207 4826 2500 39 2 6 86h 166 6041 3100 46 0 2 82h 82 12166 6300 120 0 Table 5 Typical Effective Resolution in Bits vs Conversion Time and Input Range with Chopping Enabled FW Conversion Time Conversion Time Output Data Rate 3 dB Frequency Input Range Effective Resolution Bits Register us Hz Hz 10V OVto 10V 45V OVto 5V 127 FFh 2686 372 200 21 0 20 0 20 0 19 0 46 AEh 999 1001 520 20 3 19 3 19 3 18 3 22 96h 499 2005 1040 19 7 18 7 18 7 17 7 17 91h 395 2534 1300 19 5 18 5 18 5 17 5 88h 207 4826 2500 19 0 18 0 18 0 17 0 86h 166 6041 3100 18 7 17 7 17 7 16 7 82h 82 12166 6300 17 3 16 3 16 3 15 3 Table 6 Typical Peak to Peak Resolution in Bits vs Conversion Time and Input Range with Chopping Enabled FW Conversion Time Conversion Time Output Data Rate 3 dB Frequency Input Range Peak to Peak Resolution Bits Register ps Hz Hz 10V OVto 10V 5V OVto 5V 127 FFh 2686 372 200 18 1 17 1 17 1 16 1 46 AEh 999 1001 520 17 4 16 4 16 4 15 4 22 96h 499 2005
2. Table 1 40 C to 105 C AVpp 5 V 5 DVpp 2 7 V to 3 6 V or 5 V 5 BIAS all REFIN 2 5 V REFIN AGND RA RB RC RD open circuit AIN Range 10 V fucixin 6 144 MHz unless otherwise noted AD7732 Parameter Min Typ Max Unit Test Conditions Comments ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate 372 12190 Hz Configure via Conv Time Register No Missing Codes 24 Bits FW 6 Conversion Time 165 us Output Noise See Table 4 Resolution See Table 5 and Table 6 Integral Nonlinearity INL gt gt 0 0003 0 0015 of FSR fmcek n 2 5 MHz Vem O V Integral Nonlinearity INL 7 0 0010 0 0030 of FSR fmcik n 6 144 MHz Vem 0 V Offset Error Unipolar Bipolar 13 mV Before Calibration Offset Drift vs Temperature 2 5 yv C Gain Error 0 7 Before Calibration Gain Drift vs Temperature 3 2 ppm of FS C Positive Full Scale Error 0 7 of FSR Before Calibration Positive Full Scale Drift vs Temp 3 ppm of FS C Bipolar Negative Full Scale Error 0 0060 of FSR After Calibration Common Mode Rejection 50 65 dB At DC Power Supply Sensitivity 10 LSBie At DC AIN 7 V AVoo 5 V 4 5 Channel to Channel Isolation 110 dB At DC Maximum 16 5 V AIN Voltage ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate 737 15437 Hz Configure via Conv Time Register No Missing Codes 24 Bits FW 2 8 Conversion Time 117 us Output Noise See Table 7 Resolution See Tabl
3. gt WRITE WRITE WRITE CONVERSION READ READ CONVERSION READ READ COMM MODE COMM ON CHO CHO CHO ON CH1 CH1 CH1 REGISTER REGISTER REGISTER COMPLETE STATUS DATA COMPLETE STATUS DATA Figure 22 Continuous Conversion CHO and CH1 Continuous Read Continuous Read Continuous Conversion Mode and reading the result should always start before the next When the Cont RD bit in the mode register is set the first write oe conversion is completed of 48h to the communications register starts the continuous read mode As shown in Figure 22 subsequent accesses to the part sequentially read the channel status and data registers of the last completed conversion without any further configuration of the communications register being required The AD7732 will stay in continuous read mode as long as the DIN pin is low while the CS pin is low therefore write 0 to the AD7732 while reading in continuous read mode To exit continuous read mode take the DIN pin high for at least 100 ns Note that the continuous conversion bit in the mode register should be set when entering the continuous read mode Note that the continuous read mode is a dump mode reading of the channel status and data registers regardless of the dump bit value Use the channel bits in the channel status register to check recognize that channel data is actually being shifted out Note that the last completed conversion result is being read Therefore the RDYFN bit in the I O port reg
4. AD7732 REGISTER DESCRIPTION Table 11 Register Summary Register Addr Dir Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 hex Default Value Communications 00 W 0 R W 6 Bit Register Address I O Port 01 R W PO P1 PO DIR P1 DIR RDYFN 0 0 SYNC PO Pin P1 Pin 1 1 0 0 0 0 Revision 02 R Chip Revision Code Chip Generic Code x x x x 0 1 0 0 Test 03 R W 24 Bit Manufacturing Test Register ADC Status 04 R RDY1 RDYO 0 0 0 0 0 0 0 0 Checksum 05 R W 16 Bit Checksum Register ADC Zero Scale Calibration 06 R W 24 Bit ADC Zero Scale Calibration Register 800000h ADC Full Scale 07 R W 24 Bit ADC Full Scale Register 800000h Channel Data 08 0A R 16 24 Bit Data Registers 8000h Channel Zero Scale Cal 10 12 R W 24 Bit Channel Zero Scale Calibration Registers 800000h Channel Full Scale Cal 18 1A R W 24 Bit Channel Full Scale Calibration Registers 200000h Channel Status 20 22 R 0 CH1 0 0 PO RDY P1 NOREF SIGN OVR Channel Number 0 0 0 0 0 Channel Setup 28 2A R W 0 0 0 Stat OPT ENABLE 0 RNG1 RNGO 0 0 0 0 0 0 0 0 Channel Conversion Time 30 32 R W CHOP FW 7 Bit Filter Word 1 11h Mode 38 3A R W MD2 MD1 MDO CLKDIS DUMP Cont RD 24 16 BIT CLAMP 0 0 0 0 0 0 0 0 Bit 1 in the communication register specifies the channel number of the register bein
5. Single Conversion and Reading Data cesses 23 D mp Moders E E pti abies bias 24 Continuous Conversion Mode ssssssssssssessssssssssssssreseesssssssss 24 Continuous Read Continuous Conversion Mode 25 Circuit Description s sissi csscsc scdesecesdeseseastsionsssdsiesctevasssnssteseosssoase 26 Analog Front Ende saivscssssesessisessessseesiovasenstnactectiosangeaseastavehaseiseaser 26 Analog Input s Extended Voltage Range uu 27 CHOP Ping sassitssseseasdsussoscdssesssassvanestdssdasnsevatenasesshescaastiavssgusseasesuetys 27 Multiplexer Conversion and Data Output Timing 28 Sigma Delta AD Crisis scssiissusscsssnesssethesndarsseneseeshnecadsthovascoosenstdanies 28 Frequency Response ccsssessssesssseesesesseseeseseeseseesesessesesseseeenees 28 Voltage Reference Inputs cecesesseessesessessessessesessessesseesees 29 Reference Detectan inssin nE Eisi 29 VO Potters 30 Ca lily rat Orns enesenn aa NE 30 ADC Zero Scale Self Calibration csceesessssesseeseeseeses 30 Per Channel System Calibration sssssssssssssssssssrssressssssssesseeee 30 High Common Mode Voltage Application eee 31 Outline Dimensions ssrin arinina ENE 32 Ordering Guid irian Aaa E ie 32 Changes to Figure 22 nenk eaa ae ESE EAEE E ERENS 25 Changes to Ordering Guide ssssessssssessssssreressssrrresssserressseeressss 32 2 03 Revision 0 Initial Version Rev A Page 2 of 32 AD7732 SPECIFICATIONS
6. 1040 16 9 15 9 15 9 14 9 17 91h 395 2534 1300 16 7 15 7 15 7 14 7 8 88h 207 4826 2500 16 2 15 2 15 2 14 2 86h 166 6041 3100 15 8 14 8 14 8 13 8 2 82h 82 12166 6300 15 0 13 4 13 4 12 4 Rev A Page 10 of 32 Chopping Disabled The second mode in which the AD7732 is configured with chopping disabled CHOP 0 provides faster conversion time while still maintaining high resolution Table 7 to Table 9 show the 3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate respectively Table 7 shows the typical output rms noise Table 8 shows the typical effective resolution based on the rms noise Table 9 shows the typical output peak to peak resolution AD7732 representing values for which there will be no code flicker within a 6 sigma limit The peak to peak resolutions are not calculated based on rms noise but on peak to peak noise These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK 6 144 MHz The conversion time is selected via the channel conversion time register Table 7 Typical Output RMS Noise in pV vs Conversion Time and Input Range with Chopping Disabled FW Conversion Time Conversion Time Output Data Rate 3 dB Frequency RMS Noise Register ps Hz Hz pV 127 7Fh 1357 737 670 13 2 92 5Ch 992 1008 920 15 5 44 2Ch 492 2032 1850 22 7 35 23h
7. Figure 2 Read Cycle Timing Diagram tn k tu kK Figure 3 Write Cycle Timing Diagram SCLK tis Igink 8004A AT DVpp 5V 1004A AT DVpp 3V 1 6V Isource 2004A AT DVpp 5V 1004A AT DVpp 3V Figure 4 Load Circuit for Access Time and Bus Relinquish Time Rev A Page 7 of 32 AD7732 ABSOLUTE MAXIMUM RATINGS Table 3 T 25 C unless otherwise noted Parameter Rating AVop to AGND DVop to DGND 0 3 V to 7 V AGND to DGND 0 3 V to 0 3 V AVop to DVpp 5 V to 5 V AIN to AGND 50 V to 50 V RA RB RC RD to AGND 11 V to 25 V BIAS to AGND 0 3 V to AVoo 0 3 V REFIN REFIN to AGND 0 3 V to AVpp 0 3 V PO P1 Voltage to AGND 0 3 V to AVpp 0 3 V PO P1 Current Tmax 70 C 8 mA PO P1 Current Tmax 85 C 5 mA PO P1 Current Tmax 105 C 2 5 MA Digital Input Voltage to DGND 0 3 V to DVoo 0 3 V Digital Output Voltage to DGND 0 3 V to DVoo 0 3 V Operating Temperature Range 40 C to 105 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C TSSOP Package Power Dissipation 660 mW Osa Thermal Impedance 97 9 C W Lead Temperature Soldering Vapor Phase 60 sec 215 C Infrared 15 sec 220 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional
8. The AD7732 automatically returns to this mode after any calibration or after a single conversion 0 0 1 Continuous Conversion Mode The AD7732 performs a conversion on the specified channel After the conversion is complete the relevant channel data register and channel status register are updated the relevant RDY bit in the ADC status register is set and the AD7732 continues converting on the next enabled channel The part will cycle through all enabled channels until it is put into another mode or reset The cycle period will be the sum of all enabled channels conversion times set by the corresponding channel conversion time registers 0 1 0 Single Conversion Mode The AD7732 performs a conversion on the specified channel After the conversion is complete the relevant channel data register and channel status register are updated the relevant RDY bit in the ADC status register is set the RDY pin goes low the MD2 MD0 bits are reset and the AD7732 returns to idle mode Requesting a single conversion ignores the channel setup register enable bits a conversion will be performed even if that channel is disabled 0 1 1 Power Down Standby Mode The ADC and the analog front end internal buffer go into the power down mode The AD7732 digital interface can still be accessed The CLKDIS bit works separately and the MCLKOUT mode is not affected by the power down standby mode 1 0 0 ADC Zero Scale Self Calibration Mode A zero scale self calibration is p
9. The part has an overrange and underrange detection capability and accepts an analog input overvoltage to 16 5 V without degrading the performance of the adjacent channels Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM REFIN REFIN a AINO REFERENCE DETECT 24 BIT AD7732 AIN1 AIN1 CALIBRATION CIRCUITRY PO sync P1 AGND AVpp MCLKOUT MCLKIN DGND DVpp Figure 1 The differential reference input features No Reference detect capability The ADC also supports per channel system calibration options The digital serial interface can be configured for 3 wire operation and is compatible with microcontrollers and digital signal processors All interface inputs are Schmitt triggered The part is specified for operation over the extended industrial temperature range of 40 C to 105 C Other parts in the AD7732 family are the AD7734 and the AD7738 The AD7734 is similar to AD7732 but its analog front end features four single ended input
10. identification and easier operation of the dump mode and continuous read mode 4 0 PO When the status option bit of the corresponding channel setup register is reset to 0 this bit is read as a zero When the status option bit is set to 1 this bit reflects the state of the PO pin whether it is configured as an input or an output 3 RDY P1 When the status option bit of the corresponding channel setup register is reset to 0 this bit reflects the selected channel RDY bit in the ADC status register When the status option bit is set to 1 this bit reflects the state of the P1 pin whether it is configured as an input or an output 2 NOREF This bit indicates the reference input status If the voltage between the REFIN and REFIN pins is less than NOREF the trigger voltage and a conversion is executed then the NOREF bit goes to 1 1 SIGN The voltage polarity at the analog input It will be 0 for a positive voltage and 1 for a negative voltage 0 OVR This bit reflects either the overrange or the underrange on the analog input The bit is set to 1 when the analog input voltage goes over or under the nominal voltage range see the Analog Input s Extended Voltage Range section Rev A Page 18 of 32 AD7732 Channel Setup Registers 8 Bits Read Write Register Address 28h 2Ah Default Value 00h These registers are used to configure the selected channel to configure its input voltage range and to set up the corresponding channel status
11. mA DVoo 3 V Rev A Page 4 of 32 AD7732 Parameter Min Typ Max Unit Test Conditions Comments Power Dissipation Normal Mode 85 100 mW AVoo DVop Current Standby Mode gt 140 yA Power Dissipation Standby Mode 750 uW 1 Specifications are not production tested but guaranteed by design and or characterization data at initial product release See Typical Performance Characteristics 3Vcm Common Mode Voltage 0 V 4 Specifications before calibration Channel system calibration reduces these errors to the order of the noise gt Applies after the zero scale and full scale calibration The negative full scale error represents the remaining error after removing the offset and gain error 6 ADC zero scale self calibration reduces this error to 10 mV Channel zero scale system calibration reduces this error to the order of the noise 7 For specified performance The output data span corresponds to the specified nominal input voltage range The ADC is functional outside the nominal input voltage range but the performance might degrade Outside the nominal input voltage range the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register See the register and circuit descriptions for more details 5 The AIN absolute voltage of 16 5 V applies for a nominal VBIAS voltage of 2 5 V By configuring the BIAS and RA to RD pins differently the
12. only see the Calibration section for more details Channel Status Registers Channel Full Scale Calibration Registers 24 Bits Read Write Registers Address 18h 1Ah Default Value 200000h These registers hold the particular channel full scale calibration coefficients The value in these registers is used in conjunction with the value in the corresponding channel zero scale calibration register the ADC zero scale calibration register and the ADC full scale register to digitally scale the particular channel conversion results The value in this register is updated automatically following the execution of a channel full scale system calibration Writing this register is possible in the idle mode only see the Calibration section for more details 8 Bits Read Only Register Address 20h 22h Default Value 20h x Channel Number These registers contain individual channel status information and some general AD7732 status information Reading the status registers can be associated with reading the data registers in the dump mode Reading the status registers is always associated with reading the data registers in the continuous read mode see the Digital Interface Description section for more details Bi rainy eins ns ana Tes siee Pies To Mnemonic ome je NOREF SIGN OVR Default chomel Number 0 Bit Mnemonic Description 7 5 CH1 These bits reflect the channel number This can be used for current channel
13. operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Rev A Page 8 of 32 NO MISSING CODES FILTER WORD Figure 5 No Missing Codes Performance Chopping Enabled 25 24 23 22 21 NO MISSING CODES FILTER WORD Figure 6 No Missing Codes Performance Chopping Disabled 15 Vom OV INL ppm 0 1 2 3 4 5 6 7 MCLK FREQUENCY MHz Figure 7 Typical INL vs MCLK Frequency 10 V Differential Signal AIN Common Mode Voltage 0 V BIAS BIAS 2 5 V AD7732 MCLK 6 144MHz Vom OV INL ppm 20 15 10 5 0 5 10 15 20 AIN DIFFERENTIAL VOLTAGE V Figure 8 Typical INL vs AIN Differential Voltage AIN Common Mode Voltage 0 V MCLK 6 144 MHz BIAS BIAS 2 5 V 60 MCLK 6 144MHz 50 40 30 INL ppm 20 10 15 10 5 0 5 10 15 AIN COMMON MODE VOLTAGE V Figure 9 Typical INL vs AIN Common Mode Voltage 10 V Differential Signal MCLK 6 144 MHz BIAS BIAS 2 5 V 20 15 10 AVpp DVpp CURRENT mA o N 2 3 4 5 6 MCLK FREQUENCY MHz Figure 10 Typical Supply C
14. read mode see the Digital Interface Description section for more details 1 24 16 BIT The Channel Data Register Data Width Selection Bit When set to 1 the channel data registers will be 24 bits wide When set to 0 the channel data registers will be 16 bits wide 0 CLAMP This bit determines the channel data register s value when the analog input voltage is outside the nominal input voltage range When the CLAMP bit is set to 1 the channel data register will be digitally clamped either to all Os or all 1s when the analog input voltage goes outside the nominal input voltage range When the CLAMP bit is reset to 0 the data registers reflect the analog input voltage even outside the nominal voltage range see the Analog Input s Extended Voltage Range section MD2 MD1 MDO Mode Address Used for Mode Register Write Specifies 0 0 0 Idle Mode 0 0 1 Continuous Conversion Mode The First Channel to Start Converting 0 1 0 Single Conversion Mode Channel to Convert 0 1 1 Power Down Standby Mode 1 0 0 ADC Zero Scale Self Calibration Channel Conversion Time Used for the ADC Self Calibration 1 0 1 For Future Use 1 1 0 Channel Zero Scale System Calibration Channel to Calibrate 1 1 1 Channel Full Scale System Calibration Channel to Calibrate Rev A Page 20 of 32 AD7732 MD2 MD1 MDO Operating Mode 0 0 0 Idle Mode The default mode after power on or reset
15. 398 2511 2290 26 3 16 10h 200 4991 2500 39 0 8 08h 117 8545 7780 57 0 3 03h 65 15398 14000 132 Table 8 Typical Effective Resolution in Bits vs Conversion Time and Input Range with Chopping Disabled FW Conversion Time Conversion Time Output Data Rate 3 dB Frequency Input Range Effective Resolution Bits Register us Hz Hz 10V OVto 10V 5V OVto 5V 127 7Fh 1357 737 670 20 5 19 5 19 5 18 5 92 5Ch 992 1008 920 20 3 19 3 19 3 18 3 44 2Ch 492 2032 1850 19 7 18 7 18 7 17 7 35 23h 398 2511 2290 19 5 18 5 18 5 17 5 16 10h 200 4991 2500 19 0 18 0 18 0 17 0 8 08h 117 8545 7780 18 4 17 4 17 4 16 4 3 03h 65 15398 14000 17 2 16 2 16 2 15 2 Table 9 Typical Peak to Peak Resolution in Bits vs Conversion Time and Input Range with Chopping Disabled Fw Conversion Time Conversion Time Output Data Rate 3 dB Frequency Input Range Peak to Peak Resolution Bits Register us Hz Hz 10V OVto 10V 5V OVto 5V 127 7Fh 1357 737 670 17 6 16 6 16 6 15 6 92 5Ch 992 1008 920 174 16 4 16 4 15 4 44 2Ch 492 2032 1850 16 8 15 8 15 8 14 8 35 23h 398 2511 2290 16 6 15 6 15 6 14 6 16 10h 200 4991 2500 16 1 15 1 15 1 14 1 8 08h 117 8545 7780 15 5 14 5 14 5 13 5 3 03h 65 15398 14000 14 3 13 3 13 3 12 3 Rev A Page 11 of 32 AD7732 PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS REFIN REFIN d BIASO DETECT SCLK 1 28 DGND R
16. A MCLKIN 2 DVpp RBO MCLKOUT 126 DIN ts 4 25 DOUT AINO RESET 5 24 RDY BIASO RC AV AGND ow 6 ap7732 22 46 DG PO 22 REFIN AD7732 AIN1 go zolRD BIAS1 E A D RB 10 19 RC ae des BIAS1 11 18 BIAS1 AIN O CALIBRATION OSscLK AIN1 2 AIN4 ASI JR CIRCUITRY Opin BIASO 14 15 BIASO PO QORESET Figure 11 28 Lead TSSOP SYNC P1 ORDY AGND AVpp MCLKOUT MCLKIN DGND DVpp Figure 12 Block Diagram Table 10 Pin Function Descriptions 28 Lead TSSOP Pin No Mnemonic Description 1 SCLK Serial Clock Schmitt triggered logic input An external serial clock is applied to this input to transfer serial data to or from the AD7732 2 Master Clock Signal for the ADC This can be provided in the form of a crystal resonator or external clock A crystal resonator can be tied across the MCLKIN and MCLKOUT pins Alternatively the MCLKIN pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected MCLKIN 3 When the master clock for the device is a crystal resonator the crystal resonator is MCLKOUT connected between MCLKIN and MCLKOUT If an external clock is applied to the MCLKIN MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption MCLK OUT is capable of driving one CMOS load 4 Chip Select Active low Schmitt triggered logic input with an internal pull up resistor With this input hardwired low the A
17. AGND 200 mV to AVpp 300 mV The AD7732 AIN differential voltage should be within the specified nominal up to 10 V input range otherwise the performance on channel might degrade see the Analog Input s Extended Voltage Range section The AD7732 INL performance varies with the AIN common mode voltage Figure 9 The differential analog input voltage of 10 V with a common mode voltage of 0 V means that the AIN differential voltage is centered around AGND and both AIN and AIN change within 5 V respect to AGND The AD7732 INL also varies with the MCLK frequency Figure 7 If the BIAS pins are in normal configuration the AIN pin absolute voltage up to 16 5 V does not degrade the adjacent channel s performance An AIN absolute voltage over 16 5 V results in current flowing through the internal protection diodes located behind the thin film resistors the adjacent channel can be affected By configuring the BIAS and RA to RD pins differently the part will work with higher AIN absolute voltages as long as the internal voltage seen by the multiplexer and input buffer is within 200 mV to AVpp 300 mV Absolute voltage for the AIN BIAS and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings Note that the OVR bit in the channel status register is generated digitally from the conversion result and indicates the sigma delta modulator nominal overrange The OVR bit DOES NOT indicate exceedin
18. ANALOG DEVICES 2 Channel 10 V Input Range High Throughput 24 Bit A ADC AD7732 FEATURES High resolution ADC 24 bits no missing codes 0 0015 nonlinearity Optimized for fast channel switching 18 bit p p resolution 21 bits effective at 500 Hz 16 bit p p resolution 19 bits effective at 2 kHz 14 bit p p resolution 18 bits effective at 15 kHz On chip per channel system calibration 2 fully differential analog inputs Input ranges 5 V 5 V 10V 10V Overvoltage tolerant Up to 16 5 V not affecting adjacent channel Up to 50 V absolute maximum 3 wire serial interface SPI QSPI MICROWIRE and DSP compatible Schmitt trigger on logic inputs Single supply operation 5 Vanalog supply 3 V or 5 V digital supply Package 28 lead TSSOP APPLICATIONS PLCs DCS Multiplexing applications Process control Industrial instrumentation GENERAL DESCRIPTION The AD7732 is a high precision high throughput analog front end True 16 bit p p resolution is achievable with a total conversion time of 500 us 2 kHz channel switching making it ideally suitable for high resolution multiplexing applications The part can be configured via a simple digital interface which allows users to balance the noise performance against data throughput up to a 15 4 kHz The analog front end features two fully differential input channels with unipolar or true bipolar input ranges to 10 V while operating from a single 5 V analog supply
19. D7732 can operate in its 3 wire interface mode cs using SCLK DIN and DOUT CS can be used to select the device in systems with more than one device on the serial bus It can also be used as an 8 bit frame synchronization signal 5 Schmitt Triggered Logic Input Active low input that resets the control logic interface logic digital filter analog modulator and all on chip registers of the part to power on status Effectively everything on the part except the clock oscillator is reset when the RESET pin is exercised 6 AVbp Analog Positive Supply Voltage 5 V to AGND nominal 7 Digital Input Output The pin direction is determined by the PO DIR bit the digital PO value can be read written as the PO bit in the I O port register The digital voltage is referenced to analog supplies When configured as an input the pin should be tied high or low Rev A Page 12 of 32 AD7732 Pin No Mnemonic Description 8 SYNC Digital Input Digital Output The pin direction is determined by the P1 DIR bit the digital value can be read written as the P1 bit in the I O port register When the SYNC P1 SYNC bit in the I O port register is set to 1 the SYNC P1 pin can be used to synchronize the AD7732 modulator and digital filter with other devices in the system The digital voltage is referenced to analog supplies When configured as an input the pin should be tied
20. V 0 80 ns DVon of 2 7V to3 3V tsa 3 CS Falling Edge to Data Valid Delay 0 60 ns DVop of 4 75 V to 5 25 V 0 80 ns DV of 2 7V to3 3V te 50 ns SCLK High Pulsewidth t7 50 ns SCLK Low Pulsewidth ts 0 ns CS Rising Edge after SCLK Rising Edge Hold Time tof 10 80 ns Bus Relinquish Time after SCLK Rising Edge Write Operation tu 0 ns CS Falling Edge to SCLK Falling Edge Setup t12 30 ns Data Valid to SCLK Rising Edge Setup Time t3 25 ns Data Valid after SCLK Rising Edge Hold Time t14 50 ns SCLK High Pulsewidth tis 50 ns SCLK Low Pulsewidth te 0 ns CS Rising Edge after SCLK Rising Edge Hold Time 1 Sample tested during initial release to ensure compliance All input signals are specified with tr tf 5 ns 10 to 90 of DVpp and timed from a voltage level of 1 6 V See Figure 2 and Figure 3 2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the Vor or Vou limits 3 This specification is relevant only if CS goes low while SCLK is low 4 These numbers are derived from the measured time taken by the data output to change 0 5 V when loaded with the circuit of Figure 4 The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances Rev A Page 6 of 32 AD7732
21. bit in the I O port register is set and the SYNC pin is low the AD7732 does not process any conversion If it is put into single conversion mode continuous conversion mode or any calibration mode the AD7732 waits until the SYNC pin goes high and then starts operation This allows conversion to start from a known point in time i e the rising edge of the SYNC pin The digital PO and P1 voltage is referenced to the analog supplies When configured as inputs the pins should be tied high or low Calibration The AD7732 provides zero scale self calibration and zero and full scale system calibration capability that can effectively reduce the offset error and gain error to the order of the noise After each conversion the ADC conversion result is scaled using the ADC calibration registers and the relevant channel calibration registers before being written to the data register For unipolar ranges Data ADC result ADC ZS Cal reg x ADC FS Reg 200000h Ch ZS Cal reg x Ch FS Cal reg 200000h For bipolar ranges Data ADC result ADC ZS Cal reg x ADC FS Reg 400000h 800000h Ch ZS Cal reg x Ch FS Cal reg 200000h Where the ADC result is in the range of 0 to FFFFFFh Note that the channel zero scale calibration register has the format of a sign bit and a 22 bit channel offset value It is strongly recommended that the user not change the ADC full scale register To start any calibration wri
22. bration Limit 1 05 x FS V Zero Scale Calibration Limit 1 05 x FS V Input Span 0 8 x FS 2 1 x FS V LOGIC INPUTS Input Current 1 yA Input Current CS 10 uA CS DVoo 40 uA CS DGND Internal Pull Up Resistor Input Capacitance 5 pF Vie 1 4 2 V DVow 5 V Vr 0 8 1 4 V DVow 5 V Vr Vr 0 3 0 85 V DVop 5 V Vr 0 95 2 V DVoo 3 V Vr 0 4 1 1 V DVop 3 V Vie Vr 0 3 0 85 V DVoo 3 V MCLK IN ONLY Input Current 10 yA Input Capacitance 5 pF Vint Input Low Voltage 0 8 V DVd 5 V Vinn Input High Voltage 3 5 V DVpp 5 V Vint Input Low Voltage 0 4 V DVoo 3 V Vinn Input High Voltage 2 5 V DVoo 3 V LOGIC OUTPUTS Vo Output Low Voltage 0 4 V Isink 800 pA DVop 5 V Vou Output High Voltage 4 0 V lsource 200 yA DVpp 5 V Vo Output Low Voltage 0 4 V Isink 100 pA DVoo 3 V Vox Output High Voltage DVpp 0 6 V Isource 100 pA DVoo 3 V Floating State Leakage Current 1 yA Floating State Leakage Capacitance 3 pF PO P1 INPUTS OUTPUTS Levels Referenced to Analog Supplies Input Current 10 yA Vint Input Low Voltage 0 8 V AVoo 5V Vinn Input High Voltage 3 5 V AVoo 5V Vo Output Low Voltage 0 4 V Isnk 7 MA See Abs Max Ratings Vox Output High Voltage 4 0 V Isource 200 pA AVoo 5 V POWER REQUIREMENTS AVoo AGND Voltage 4 75 5 25 V DVoo DGND Voltage 4 75 5 25 V 2 70 3 60 V AVoo Current Normal Mode 13 5 15 9 mA AVop 5 V DVoo Current Normal Mode 4 2 8 3 1 mA DVoo 5 V DVoo Current Normal Mode 1 0 1 5
23. ce can be connected to the host device via the serial interface in several different ways The CS pin can be used to select the AD7732 as one of several circuits connected to the host serial interface When CS is high the AD7732 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state When the CS signal is not used connect the CS pin to DGND The RDY pin can be polled for high to low transition or can drive the host device interrupt input to indicate that the AD7732 has finished the selected operation and or new data from the AD7732 is available The host system can also wait a designated time after a given command is written to the device before reading Alternatively the AD7732 status can be polled When the RDY pin is not used in the system it should be left as an open circuit Note that the RDY pin is always an active digital output i e it never goes into a high impedance state DVpp DVpp AD7732 68HC11 DGND Figure 13 AD7732 to Host Device Interface SPI DVpp AD7732 ADSP 2105 Figure 14 AD7732 to Host Device Interface DSP The RESET pin can be used to reset the AD7732 When not used connect this pin to DVpp The AD7732 interface can be reduced to just two wires connecting the DIN and DOUT pins to a single bidirectional data line The second signal in this 2 wire configuration is the SCLK signal The host system should change the data line direction with reference to the AD7732 ti
24. channels The AD7738 analog front end is configurable for four fully differential or eight single ended input channels features 0 625 V to 2 5 V bipolar unipolar input ranges and accepts a common mode input voltage from 200 mV to AVDD 300 mV The AD7738 multiplexer output is pinned out externally allowing the user to implement programmable gain or signal conditioning before being applied to the ADC One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2003 2011 Analog Devices Inc All rights reserved AD7732 TABLE OF CONTENTS AD7732 Specific tion s 3 Timing Specifications cccesessesssesesseessessessessessesseesessessesseeseess 6 Absolute Maximum Ratings cccssseseseseseesseseesseseeseeneeneesenss 8 Typical Performance Characteristics csseessesseesseseeseesesseese 9 Output Noise and Resolution Specification 10 Chopping Enabled eeesesssessesseessessesseessessesssessesseesesseenees 10 Chopping Disabledi2 ccasu tees eee ee ee oe 11 Pin Configurations and Functional Descriptions 12 Register Description cccsssessseessseeseseeseseensseeneseeneseesseeeseeneseens 14 Register Access c5 522s ccesc2assiosdsssinessdsstvecs eseesnsdss tees setine iseinean 15 Communications Register ccccsesesseseeseseeseseeneseeneseeneseeeseens 15 T O POrt REGISCERS c32 csesscetsbesssssseessassteedscosegenscisteessdasieesdeneseesia
25. d Conversion Time us FW x 128 248 MCLK Frequency MHz the FW range is 2 to 127 CHOP 1 continuous conversion with two channels enabled Conversion Time us FW x 128 249 MCLK Frequency MHz the FW range is 2 to 127 CHOP 0 single conversion or continuous conversion with one channel enabled Conversion Time us FW x 64 206 MCLK Frequency MHz the FW range is 3 to 127 CHOP 0 continuous conversion with two channels enabled Conversion Time us FW x 64 207 MCLK Frequency MHz the FW range is 3 to 127 Rev A Page 19 of 32 AD7732 Mode Register 8 Bits Read Write Register Address 38h 3Ah Default Value 00h The mode register configures the part and determines its operating mode Writing to the mode register clears the ADC status register sets the RDY pin to a logic high level exits all current operations and starts the mode specified by the mode bits The AD7732 contains only one mode register Bit 1 of the address is used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MDO bits Only the address 38h must be used for reading from the mode register Bi Ber ene ens era 6R3 om2 em ero Mnemonic MD2 CLKDIS DUMP Cont RD 24 16 BIT CLAMP Default 0 0 0 0 0 0 0 Bit Mnemonic Description 7 5 MD2 MDO Mode Bits These three bits determine the AD7732 operation mode Writing a new value to the mode bits will ex
26. e 8 and Table 9 Integral Nonlinearity INL gt 0 0015 of FSR Offset Error Unipolar Bipolar 10 mV Before Calibration Offset Drift vs Temperature 25 yv C Gain Error 0 5 Before Calibration Gain Drift vs Temperature 5 3 ppm of FS C Positive Full Scale Error 0 5 of FSR Before Calibration Positive Full Scale Drift vs Temp 4 ppm of FS C Bipolar Negative Full Scale Error 0 0060 of FSR After Calibration Common Mode Rejection 55 dB At DC Power Supply Sensitivity LSBie At DC AIN 7V AVoo 5 V 5 Channel to Channel Isolation 110 dB At DC Maximum 16 5 V AIN Voltage ANALOG INPUTS Analog Input Differential Voltage 10 V Range 10 V O V to 10 V Range Oto 10 V 5 V Range V 0 V to 5 V Range Oto 5 V AIN Absolute Voltage 8 16 5 16 5 V BIAS Voltage 0 2 5 AVop V RA RB RC RD Voltage 10 5 20 V AIN Impedance 100 124 kQ AIN Pin Impedance 87 5 108 5 kQ BIAS Pin Impedance 12 5 15 5 kQ Rev A Page 3 of 32 AD7732 Parameter Min Typ Max Unit Test Conditions Comments RA RB RC RD Pin Impedance 25 31 kQ Input Resistor Matching 0 2 Input Resistor Temp Coefficient 30 ppm C REFERENCE INPUTS REFIN to REFIN Voltage 2 475 2 5 2 525 V NOREF Trigger Voltage 0 5 V NOREF Bit in Channel Status Register REFIN REFIN Common Mode Voltage 0 AVop Vv Reference Input DC Current 400 yA SYSTEM CALIBRATION 2 Full Scale Cali
27. e channel status register goes high when the result is updated The RDY bit will return low once the data register reading has begun The RDY pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data If any channel data register read operation is in progress when a new result is updated no update of the data register will occur This avoids having corrupted data Reading the status registers can be associated with reading the data registers in the dump mode Reading the status registers is always associated with reading the data registers in the continuous read mode see the Digital Interface Description section for more details Rev A Page 17 of 32 AD7732 Channel Zero Scale Calibration Registers 24 Bits Read Write Registers Address 10h 12h Default Value 800000h These registers hold the particular channel zero scale calibration coefficients The value in these registers is used in conjunction with the value in the corresponding channel full scale calibration register the ADC zero scale calibration register and the ADC full scale register to digitally scale the particular channel conversion results The value in this register is updated automatically following the execution of a channel zero scale system calibration The format of the channel zero scale calibration register is a sign bit and 22 bits unsigned value Writing this register is possible in the idle mode
28. ed by a channel full scale system calibration The system calibration is affected by the ADC zero scale and full scale calibration registers Therefore if both self calibration and system calibration are used in the system an ADC full scale self calibration should be performed first followed by a system calibration cycle While executing a system calibration the fully settled system zero scale voltage signal or system full scale voltage signal must be connected to the selected channel analog inputs The per channel calibration registers can be read stored or modified and written back to the AD7732 Note that when writing the calibration registers the AD7732 must be in idle mode Note that outside the specified calibration range calibration is possible but the performance may degrade see the System Calibration section in Table 1 Rev A Page 30 of 32 AD7732 AVpp DVpp 0 1uF E 10uF ANALOG L a 4 INPUTS O d MCLKIN 6 144MHz CLOCK 11 5V COMMON GENERATOR MODE VOLTAGE 40y MAX 16 5v DIFFERENTIAL ABSOLUTE VOLTAGE VOLTAGE TO AGND MCLKOUT 33pF T i 33pF BUFFER DIFFERENTIAL VOLTAGE YT AD7732 seral INTERFACE HOST AND Sh CONTROL SYSTEM VIN VOUT 2 5V__REFIN Locic AD780 TEMP Q O 10uF 0 01uF 10uF AGND DGND Vv v xy v Y b Figure 29 Typical Connections for the AD7732 Application High Common Mode Voltage Application Using additional thin film resisto
29. ential can lie REFIN anywhere between AVpp and AGND In normal circuit configuration this pin should be connected to a 2 5 V reference voltage 22 Negative Terminal of the Differential Reference Input REFIN voltage potential can lie REFIN anywhere between AVpp and AGND In normal circuit configuration this pin should be connected to a 0 V reference voltage 23 AGND Ground Reference Point for Analog Circuitry 24 Logic Output Used as a status output in both conversion mode and calibration mode In conversion mode a falling edge on this output indicates that either any channel or all RDY channels have unread data available according to the RDYFN bit in the I O port register In calibration mode a falling edge on this output indicates that calibration is complete see the Digital Interface Description section for more details 25 Serial data output with serial data being read from the output shift register on the part DOUT This output shift register can contain information from any AD7732 register depending on the address bits of the communications register 26 Serial data input Schmitt triggered with serial data being written to the input shift DIN register on the part Data from this input shift register is transferred to any AD7732 register depending on the address bits of the communications register 27 DVpp Digital Supply Voltage 3 V or 5 V Nominal 28 DGND Ground Reference Point for Digital Circuitry Rev A Page 13 of 32
30. erformed on internally shorted ADC inputs After the calibration is complete the contents of the ADC zero scale calibration register are updated all RDY bits in the ADC status register are set the RDY pin goes low the MD2 MD0 bits are reset and the AD7732 returns to idle mode 1 0 1 For Future Use 1 1 0 Channel Zero Scale System Calibration Mode A zero scale system calibration is performed on the selected channel An external system zero scale voltage should be provided at the AD7732 analog input and should remain stable for the duration of the calibration After the calibration is complete the contents of the corresponding channel zero scale calibration register are updated all RDY bits in the ADC status register are set the RDY pin goes low the MD2 MD0 bits are reset and the AD7732 returns to idle mode Channel Full Scale System Calibration Mode A full scale system calibration is performed on the selected channel An external system full scale voltage should be provided at the AD7732 analog input and this voltage should remain stable for the duration of the calibration After the calibration is complete the contents of the corresponding channel full scale calibration register are updated all RDY bits in the ADC status register are set the RDY pin goes low the MD2 MD0O bits are reset and the AD7732 returns to idle mode Rev A Page 21 of 32 AD7732 DIGITAL INTERFACE DESCRIPTION Hardware The AD7732 serial interfa
31. es converting on the next enabled channel The part will cycle through all enabled channels until put into another mode or reset The cycle period will be the sum of all enabled channels conversion times set by the corresponding channel conversion time registers The RDY bit is reset when the relevant channel data register is being read The behavior of the RDY pin depends on the RDYEN bit in the I O port register When the RDYEN bit is 0 the RDY pin goes low when any channel has unread data When the RDYEN bit is set to 1 the RDY pin will only go low if all enabled channels have unread data Ifan ADC conversion result has not been read before a new ADC conversion is completed the new result will overwrite the previous one The relevant RDY bit goes low and the RDY pin goes high for at least 163 MCLK cycles 26 5 us indicating when the data register is updated and the previous conversion data is lost If the data register is being read as an ADC conversion completes the data register will not be updated with the new result to avoid data corruption and the new conversion data is lost Figure 19 shows the digital interface signal s sequence for the continuous conversion mode with Channels 0 and 1 enabled and the RDYEN bit set to 0 The RDY pin goes low and the data register is read after each conversion Figure 20 shows a similar sequence but with the RDYEN bit set to 1 The RDY pin goes low and all data registers are read after al
32. f is 20 dB dec up to the Nyquist frequency If chopping is enabled the input signal is resampled by chopping Therefore the overall frequency response features notches close to the frequency of 1 channel conversion time The top envelope is again the ADC response of 20 dB dec The typical frequency response plots are given in Figure 27 and Figure 28 The plots are normalized to 1 channel conversion time 0 10 CHOP 1 GAIN dB b o 40 50 60 0 1 1 0 10 0 NORMALIZED INPUT FREQUENCY INPUT FREQUENCY x CONVERSION TIME Figure 27 Typical ADC Frequency Response Chopping Enabled CHOP 0 20 GAIN dB b o 40 50 60 0 1 1 0 10 0 100 0 1000 0 NORMALIZED INPUT FREQUENCY INPUT FREQUENCY x CONVERSION TIME Figure 28 Typical ADC Frequency Response Chopping Disabled AD7732 Voltage Reference Inputs The AD7732 has a differential reference input REF IN and REF IN The common mode range for these inputs is from AGND to AVpp The nominal differential reference voltage for specified operation is 2 5 V Both reference inputs feature dynamic load Therefore the reference inputs should be connected to a low impedance reference voltage source External resistance capacitance combinations may result in gain errors on the part The output n
33. g accessed There is only one mode register although the mode register can be accessed in one of two address locations The address used to write the mode register specifies the ADC channel on which the mode will be applied Only address 38h must be used for reading from the mode register Table 12 Operational Mode Summary Table 13 Input Range Summary MD2 MD1 MDO Mode RNG1 RNGO Nominal Input Voltage Range Idle Mode 0 0 10V Continuous Conversion Mode 0 1 O0Vto 10V Single Conversion Mode 1 0 5V Power Down Standby Mode 1 1 OVto 5V For Future Use OOOO A E e A a e E E o A r 0O 0 oO O O ADC Zero Scale Self Calibration Channel Zero Scale System Calibration Channel Full Scale System Calibration Rev A Page 14 of 32 Register Access The AD7732 is configurable through a series of registers Some of them configure and control general AD7732 features while others are specific to each channel The register data widths vary from 8 bits to 24 bits All registers are accessed through the communications register i e any communication to the AD7732 must start with a write to the communications register specifying which register will be subsequently read or written Communications Register 8 Bits Write Only Register Address 00h All communications to the part must start with a write operation to the communications register The data written to AD7732 the communication
34. g the AIN pin absolute common mode voltage limits Figure 23 shows the AD7732 analog input internal structure PROTECTION AVpp DIODES AIN 10V BUFFER 2 1875V 1 25V v v AGND Figure 23 Simplified Analog Input Internal Structure Rev A Page 26 of 32 Analog Input s Extended Voltage Range The AD7732 output data code span corresponds to the nominal input voltage range The ADC is functional outside the nominal input voltage range but the performance might degrade The sigma delta modulator was designed to fully cover a 11 6 V differential input voltage outside this range the performance might degrade more rapidly The adjacent channels are not affected by up to 16 5 V absolute analog input voltage Figure 8 When the CLAMP bit in the mode register is set to 1 the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range As shown in Table 16 and Table 17 when CLAMP 0 the data reflects the analog input voltage outside the nominal voltage range In this case the SIGN and OVR bits in the channel status register should be considered along with the data register value to decode the actual conversion result Note that the OVR bit in the channel status register is generated digitally from the conversion result and indicates the sigma delta modulator nominal overrange The OVR bit DOES NOT indicate exceeding t
35. he AIN pin s absolute voltage limits Table 16 Extended Input Voltage Range Nominal Voltage Range 10 V 16 Bits CLAMP 0 Input V Data hex SIGN OVR 11 60039 10 00061 10 00031 10 00000 0 00031 0 00000 0 00031 10 00000 10 00031 10 00061 11 60040 343 4 343 e A o E o A e E e e M m E a E a E a a AIN O MULTIPLEXER BUFFER 5 OD Z A osol 2 vonuraror ve BIAS O AIN O Lf ob BISBO CHOP fmeLK 2 fmeLK 2 SCALING POEA ARITHMETIC INTERFACE CALIBRATIONS AD7732 Table 17 Extended Input Voltage Range Nominal Voltage Range 0 V to 10 V 16 Bits CLAMP 0 Input V Data hex SIGN OVR 11 60006 10 00031 10 00015 10 00000 0 00015 0 00000 0 00015 D O 00 0 O0O00 R Chopping With chopping enabled the multiplexer repeatedly reverses the ADC inputs Every output data result is then calculated as an average of two conversions the first with the positive and the second with the negative offset term included This effectively removes any offset error of the input buffer and sigma delta modulator However chopping is applied only behind the input resistor divider stage therefore chopping does not eliminate the offset error and drifts caused by the resistors Figure 24 shows the channel signal chain with chopping enabled OUTPUT DATA AT THE SELECTED DATA RATE CHOP Figure 24 Channel Signal Chain Diagram with Chopping Enabled Re
36. high or low 9 RA RA in association with RB and BIASO can be used to level shift the positive analog input 0 In normal circuit configuration this pin is left open circuit 10 RB RB in association with RA and BIASO can be used to level shift the positive analog input 0 In normal circuit configuration this pin is left open circuit 11 This input is used to level shift the positive analog input 1 This signal is used to ensure BIAS1 that the differential signal seen by the internal buffer amplifier is within its common mode range BIAS pins will normally be connected to 2 5 V 12 AIN1 Positive Analog Input Channel 1 13 AINO Positive Analog Input Channel 0 14 BIASO Voltage Bias for Positive Analog Input 0 This pin has the same function as BIAS1 15 BIASO Voltage Bias for Negative Analog Input 0 This pin has the same function as BIAS1 16 AINO Negative Analog Input Channel 0 17 AIN1 Negative Analog Input Channel 1 18 BIAS1 Voltage Bias for Negative Analog Input 1 This pin has the same function as BIAS1 19 RC RC in association with RD and BIASO can be used to level shift the negative analog input 0 In normal circuit configuration this pin is left open circuit 20 RD RD in association with RC and BIASO can be used to level shift the negative analog input 0 In normal circuit configuration this pin is left open circuit 21 Positive Terminal of the Differential Reference Input REFIN voltage pot
37. ifferential input 1 Bit Mnemonic Default Checksum Register 16 Bits Read Write Register Address 05h This register is described in the Using the AD7732 AD7734 AD7738 AD7739 Checksum Register application note www analog com AN 626 ADC Zero Scale Calibration Register 24 Bits Read Write Register Address 06h Default Value 800000h The register holds the ADC zero scale calibration coefficient The value in this register is used in conjunction with the value in the ADC full scale calibration register and the corresponding channel zero scale and channel full scale calibration registers to scale digitally all channels conversion results The value in this register is updated automatically following the execution of an ADC zero scale self calibration Writing this register is possible in the idle mode only see the Calibration section for more details ADC Full Scale Register 24 Bits Read Write Register Address 07h Default Value 800000h This register holds the ADC full scale coefficient The user is advised not to change the default configuration of this register Channel Data Registers 16 Bit 24 Bit Read Only Registers Address 08h 0Ah Default Width 16 Bits Default Value 8000h These registers contain the most up to date conversion results corresponding to each analog input channel The 16 bit or 24 bit data width can be configured by setting the 16 bit 24 bit in the mode register The relevant RDY bit in th
38. ister should be 0 after a read is complete Write 80h to the AD7732 to exit continuous reading Taking the DIN pin high does not change the Cont RD bit in the mode register Therefore the next write of 48h starts the continuous read mode again To completely stop the continuous read mode write to the mode register to clear the Cont RD bit Rev A Page 25 of 32 AD7732 CIRCUIT DESCRIPTION The AD7732 is a sigma delta ADC that is intended for the measurement of wide dynamic range low frequency signals in industrial process control instrumentation and PLC systems It contains thin film resistor dividers a multiplexer an input buffer a sigma delta or charge balancing ADC a digital filter a clock oscillator a digital I O port and a serial communications interface Analog Front End The AD7732 features two fully differential analog inputs The on chip thin film resistor dividers allow 10 V 5 V 0 V to 10 V and 0 V to 5 V input signals to be connected directly to the analog input pins The resistor divider input stage is followed by the multiplexer and then by a wide bandwidth fast settling time differential input buffer capable of driving the dynamic load of a high speed sigma delta modulator In normal circuit configuration the BIAS pins are connected to the 2 5 V reference voltage source This ensures that the differential signal seen by the internal input buffer is within its absolute common mode range of
39. it the part from the mode in which it has been operating and place it in the newly requested mode immediately The function of the mode bits is described in more detail below 4 CLKDIS Master Clock Output Disable When this bit is set to 1 the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state This allows turning off the MCLKOUT as a power saving feature When using an external clock on MCLKIN the AD7732 continues to have internal clocks and will convert normally regardless of the CLKDIS bit state When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins the AD7732 clock is stopped and no conversions can take place when the CLKDIS bit is active The AD7732 digital interface can still be accessed using the SCLK pin 3 DUMP DUMP Mode When this bit is reset to 0 the channel status register and channel data register will be addressed and read separately When the DUMP bit is set to 1 the channel status register will be followed immediately by a read of the channel data register regardless of whether the status or data register has been addressed through the communication register The continuous read mode will always be dump mode reading of the channel status and data register regardless of the dump bit value see the Digital Interface Description section for more details 2 Cont RD When this bit is set to 1 the AD7732 will operate in the continuous
40. l conversions are completed Figure 21 shows the RDY pin when no data are read from the AD7732 cs l j l SCLK Wu WU I I A A DIN lt 38h _ gt lt 48h gt DOUT lt 48h gt 00h 00h 00h STATUS DATA DATA RDY Y a a a gt a lt gt lt I WRITE WRITE CONVERSION TIME COMMUNICATIONS MODE REGISTER REGISTER WRITE READ READ DATA COMMUNICATIONS CHANNEL REGISTER REGISTER STATUS Figure 18 Serial Interface Signals Single Conversion Command 16 Bits Data Reading Dump Mode START CONTINUOUS DATA CONVERSION OHO READ READ READ DATA DATA DATA CH1 CHO CH1 SERIAL O O O O O INTERFACE RDY Y J J l CHO CONVERSION CH1 CONVERSION CHO CONVERSION CH1 CONVERSION CHO CONVERSION Figure 19 Continuous Conversion CHO and CH1 RDYFN 0 Rev A Page 24 of 32 AD7732 CONTINUOUS READ READ READ READ CONVERSION DATA DATA DATA DATA CHO CH1 CHO CH1 SERIAL INTERFACE RY OOZ OO LT n CHO CONVERSION CH1 CONVERSION CHO CONVERSION CH1 CONVERSION CHO CONVERSION Figure 20 Continuous Conversion CHO and CH1 RDYFN 1 START CONTINUOUS CONVERSION SERIAL lt gt INTERFACE RDY X CHO CONVERSION CH1 CONVERSION CHO CONVERSION CH1 CONVERSION CHO CONVERSION Figure 21 Continuous Conversion CHO and CH1 No Data Read cs l l J l J DIN lt 38h gt lt 24h gt lt 48h__ gt 00h 00h 00h 00h 00h 00h DOUT STATUS DATA DATA STATUS DATA DATA RDY yY J I lt lt lt gt lt _ _ re A gt _ q4
41. le 14 Bit 2 Bit 1 Bit 0 Channel Input 0 0 0 0 AINO AINO 0 1 0 1 AIN1 AIN1 Rev A Page 15 of 32 AD7732 I O Port Register 8 Bits Read Write Register Address 01h Default Value 30h Digital Input Value x 40h The bits in this register are used to configure and access the digital I O port on the AD7732 Bit Mnemonic Default Bit Mnemonic Description 7 6 PO P1 When the PO and P1 pins are configured as outputs the PO and P1 bits determine the pins output level When the PO and P1 pins are configured as inputs the PO and P1 bits reflect the current input level on the pins 5 4 PO DIR P1 DIR These bits determine whether the PO and P1 pins are configured as inputs or outputs When set to 1 the corresponding pin will be an input when reset to 0 the corresponding pin will be an output 3 RDYFN This bit is used to control the function of the RDY pin on the AD7732 When this bit is reset to 0 the RDY pin goes low when any channel has unread data When this bit is set to 1 the RDY pin will only go low if all enabled channels have unread data 2 1 0 These bits must be 0 for proper operation SYNC This bit enables the SYNC pin function By default this bit is O and SYNC P1 can be used as a digital I O pin When the SYNC bit is set to 1 the SYNC pin can be used to synchronize the AD7732 modulator and digital filter with other devices in the system Revision Regi
42. ming specification see the Bus Relinquish Time in Table 2 The AD7732 cannot operate in the continuous read mode in 2 wire serial interface configuration All the digital interface inputs are Schmitt Triggered therefore the AD7732 interface features higher noise immunity and can be easily isolated from the host system via optocouplers Figure 13 Figure 14 and Figure 15 outline some of the possible host device interfaces SPI without using the CS signal Figure 13 a DSP interface Figure 14 and a 2 wire configuration Figure 15 AD7732 C P3 1 TXD C P3 0 RXD DGND Figure 15 AD7732 to Host Device Interface 2 Wire Configuration Rev A Page 22 of 32 Reset The AD7732 can be reset by the RESET pin or by writing a reset sequence to the AD7732 serial interface The reset sequence is N x 0 32 x 1 which could be the data sequence 00h FFh FFh FFh FFh in a byte oriented interface The AD7732 also features a power on reset with a trip point of 2 V and goes to the defined default state after power on It is the system designer s responsibility to prevent an unwanted write operation to the AD7732 The unwanted write operation could happen when a spurious clock appears on the SCLK while the CS pin is low It should be noted that on system power on if the AD7732 interface signals are floating or undefined the part can be inadvertently configured into an unknown state This could be easily overcome by initia
43. nss 16 Re Vision R gister icses 5 scsascsssssescssaseadebeasosdtscessacecasssesccsessasenstsets 16 West RESister AE ETTET T TEET 16 ADG Stats RESISte ry iiss 5 dcssccsscissstasclessssdescubssietssebeseceseastecestss 17 ChecksummResisterssasccccssssssassssssesesdassucsscsatnnnsssssnectaosieenssesiesssaves 17 ADC Zero Scale Calibration Register teseeeeeeeeeeees 17 ADC Full Scale Register sitv scisiodiessiorssseseosagsprcsepnmecsnneniess 17 Channel Data Registers ecsssessessesessesessesteseeseeseeneeseenesses 17 Channel Zero Scale Calibration Registers 18 Channel Full Scale Calibration Registers 18 Channel Status Registers sssesesessesseseeseeseeseeseeneeneesesses 18 Channel Setup Registers essessesessestesseseesteseeseeseeneenesses 19 Channel Conversion Time Registers 00 19 Mode Registe asyr E E N 20 REVISION HISTORY 6 11 Rev 0 to Rev A Changes to ADC Performance Chopping Enabled Offset Error Unipolar Bipolar Parameter Offset Drift vs Temperature Parameter Positive Full Scale Drift vs Temp Parameter and Channel to Channel Isolation Parameter in Table 1 0 0 0 3 Change to ADC Performance Chopping Disabled Channel to Channel Isolation Parameter in Table 1 o ceeeeseseseseseeeeeesees 3 Digital Interface Description 0 ccecssssessesssessessesssessesseessesseenes 22 Ar WATE E emanates 22 Reset iei i treer aone E E R 23 Access the AD7732 Registers csssessessessesesssesesseesessessees 23
44. oise performance outlined in Table 4 through Table 9 is for an analog input of 0 V and is unaffected by noise on the reference To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7732 If the reference noise in the bandwidth of interest is excessive it will degrade the performance of the AD7732 Recommended reference voltage sources for the AD7732 include the AD780 ADR421 REF43 and REF192 Note that in a typical connection the voltage reference must be capable of sinking current flowing out of the BIAS pins through the internal resistors if a positive voltage is applied to the analog input The AD780 meets this requirement If the voltage reference used in an application is not capable of sinking current an external resistor 5 kQ should be connected in parallel to the REFIN pins Reference Detect The AD7732 includes on chip circuitry to detect if the part has a valid reference for conversions If the voltage between the REFIN and REFIN pins goes below the NOREF trigger voltage 0 5 V typ and the AD7732 is performing a conversion the NOREF bit in the channel status register is set Rev A Page 29 of 32 AD7732 1 O Port The AD7732 PO pin can be used as a general purpose digital T O pin The P1 pin SYNC P1 can be used as a general purpose digital I O pin or to synchronize the AD7732 with other devices in the system When the SYNC
45. part will work with higher AIN absolute voltages as long as the internal voltage seen by the multiplexer and the input buffer is within 200 mV to AVop 300 mV Absolute voltage for the AIN BIAS and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings Pin impedance is from the pin to the internal node In normal circuit configuration the analog input total impedance is typically 108 5 kQ 15 5 KQ 124 kQ 10 For specified performance Part is functional with lower Veer Dynamic current charging the sigma delta modulator input switching capacitor Outside the specified calibration range calibration is possible but the performance may degrade These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load With external MCLK MCLKOUT is disabled the CLKDIS bit is set in the mode register 15 External MCLKIN 0 V or DVpp Digital Inputs 0 V or DVpp and PO and P1 0 V or AVop Rev A Page 5 of 32 AD7732 TIMING SPECIFICATIONS Table 2 AVpp 5 V 5 DV pp 2 7 V to 3 6 V or 5 V 5 Input Logic 0 0 V Logic 1 DVpp unless otherwise noted Parameter Min Typ Max Unit Test Conditions Comments Master Clock Range 1 6 144 MHz ti 50 ns SYNC Pulsewidth t2 500 ns RESET Pulsewidth Read Operation t4 0 ns CS Falling Edge to SCLK Falling Edge Setup Time ts SCLK Falling Edge to Data Valid Delay 0 60 ns DVop of 4 75 V to 5 25
46. property of their respective companies www ana l 0 g om Printed in the U S A D03070 0 6 11 A DEVICES Rev A Page 32 of 32
47. register Bi B7 eke ens ona 6R3 om2 om ewo Mnemonic Stat OPT ENABLE RNG1 RNGO Default 0 0 0 0 Bit Mnemonic Description 7 5 0 These bits must be 0 for proper operation 4 Stat OPT Status Option When this bit is set to 1 the PO and P1 bits in the channel status register will reflect the state of the PO and P1 pins When this bit is reset to 0 the RDY bit in the channel status register will reflect the channel corresponding to the RDY bit in the ADC status register 3 ENABLE Channel Enable Set this bit to 1 to enable the channel in the continuous conversion mode A single conversion will take place regardless of this bit s value 2 0 This bit must be 0 for proper operation 1 0 RNG1 RNGO This is the channel input voltage range see Table 15 Nominal Input Voltage Range 10V OVto 10V 5V OVto 5V Channel Conversion Time Registers 8 Bits Read Write Register Address 30h 32h Default Value 91h The conversion time registers enable or disable chopping and configure the digital filter for a particular channel This register value affects the conversion time frequency response and noise performance of the ADC Mnemonic FW 7 Bit Filter Word Default 11h Bit Mnemonic Description 7 CHOP Chopping Enable Bit Set to 1 to apply chopping mode for a particular channel 6 0 FW CHOP 1 single conversion or continuous conversion with one channel enable
48. rs on AINO and an external operational amplifier with a 15 V power supply the AD7732 AINO can easily be configured to accept high common mode voltages AVpp DVpp 0 1uF J a 10uF MCLKIN 6 144MHz ANALOG g INPUTS Co 37V COMMON MODE VOLTAGE 10y MCLKOUT DIFFERENTIAL 33pF 42V ABSOLUTE MAX VOLTAGE VOLTAGE TO AGND I ISV Biaso ro Vv BUFFER AD7732 SERIAL INTERFACE HOST AND a CONTROL SYSTEM VOUT 2 5V__REFIN LOGIC Figure 30 High Common Mode Voltage Application Rev A Page 31 of 32 AD7732 OUTLINE DIMENSIONS Ordering Guide Model AD7732BRU AD7732BRUZ AD7732BRUZ REEL AD7732BRUZ REEL7 EVAL AD7732EBZ 6 40 BSC 1 20 MAX PLANE 0 09 0 45 si COMPLIANT TO JEDEC STANDARDS MO 153 AE Figure 31 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 Dimensions shown in millimeters Temperature Range Package Description Package Option 40 C to 4 40 C to 4 40 C to 4 105 C 105 C 105 C 40 C to 4 105 C 1 Z RoHS Compliant Part RU 28 RU 28 RU 28 RU 28 28 Lead Thin Shrink Small Outline Package TSSOP 28 Lead Thin Shrink Small Outline Package TSSOP 28 Lead Thin Shrink Small Outline Package TSSOP 28 Lead Thin Shrink Small Outline Package TSSOP Evaluation Board 2003 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the
49. s l l DIN lt __38h__ lt 40h _ gt DOUT DATA DATA RDY Y J lt gt lt t _ gt gt lt gt a WRITE WRITE COMMUNICATIONS MODE REGISTER REGISTER CONVERSION TIME WRITE READ DATA REGISTER COMMUNICATIONS REGISTER Figure 17 Serial Interface Signals Single Conversion Command and 16 Bits Data Reading Rev A Page 23 of 32 AD7732 Dump Mode When the DUMP bit in the mode register is set to 1 the channel status register will be read immediately by a read of the channel data register regardless of whether the status or the data register has been addressed through the communications register The DIN pin should not be high while reading 24 bit data in dump mode otherwise the AD7732 will be reset Figure 18 shows the digital interface signals executing a single conversion on Channel 0 waiting for the RDY pin to go low and reading the Channel 0 status register and data register in the dump mode Continuous Conversion Mode When the mode register is being written the ADC status byte is cleared and the RDY pin goes high regardless of its previous state When the continuous conversion command is written to the mode register the ADC starts conversion on the channel selected by the address of the mode register After the conversion is complete the relevant channel data register and channel status register are updated the relevant RDY bit in the ADC status register is set and the AD7732 continu
50. s register determines whether the subsequent operation will be a read or write and to which register this operation will be directed The digital interface defaults to expect write operation to the communications register after power on after reset or after the subsequent read or write operation to the selected register is complete If the interface sequence is lost the part can be reset by writing at least 32 serial clock cycles with DIN high and CS low Note that all of the parts including the modulator filter interface and all registers are reset in this case Remember to keep DIN low while reading 32 bits or more either in continuous read mode or with the DUMP bit and 24 16 bit in the mode register set Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic 0 R W 6 Bit Register Address Bit Mnemonic Description 7 0 This bit must be 0 for proper operation 6 RW A Oin this bit indicates that the next operation will be a write to a specified register A 1 in this bit indicates that the next operation will be a read from a specified register 5 0 Address specifying to which register the read or write operation will be directed For channel specific registers Address Bit 1 specifies the channel number When the subsequent operation writes to the Mode register Bit 1 specifies the channel selected for operation determined by the mode register value see Table 14 Tab
51. ster 8 Bits Read Only Register Address 02h Default Value 04h Chip Revision x 10h Mnemonic Default Bit Mnemonic Description 7 4 Chip Revision Code 4 Bit Factory Chip Revision Code 3 0 Chip Generic Code On the AD7732 these bits will read back as 04h Test Register 24 Bits Read Write Register Address 03h This register is used for testing the part in the manufacturing process The user must not change the default configuration of this register Rev A Page 16 of 32 ADC Status Register 8 Bits Read Only Register Address 04h Default Value 00h AD7732 In conversion modes the register bits reflect the individual channel status When a conversion is complete the corresponding channel data register is updated and the corresponding RDY bit is set to 1 When the channel data register is read the corresponding bit is reset to 0 The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the channel data register Writing to the mode register resets all the bits to 0 In calibration modes all the register bits are reset to 0 while a calibration is in progress all the register bits are set to 1 when the calibration is complete The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I O port register The RDY0 bit corresponds to the differential input 0 and the RDY1 bit corresponds to the d
52. te the relevant mode bits to the AD7732 mode register After the calibration is complete the contents of the corresponding calibration registers are updated all RDY bits in the ADC status register are set the RDY pin goes low and the AD7732 reverts to idle mode The calibration duration is the same as the conversion time configured on the selected channel A longer conversion time gives less noise and yields a more exact calibration therefore use at least the default conversion time to initiate any calibration ADC Zero Scale Self Calibration The ADC zero scale self calibration can reduce the offset error in the chopping disabled mode If repeated after a temperature change it can also reduce the offset drift error in the chopping disabled mode The zero scale self calibration is performed on internally shorted ADC inputs The negative analog input terminal on the selected channel is used to set the ADC zero scale calibration common mode Therefore either the negative terminal of the selected differential pair or the AINCOM on the single ended channel configuration should be driven to a proper common mode voltage It is strongly recommended that the ADC zero scale calibration register should only be updated as part of a zero scale self calibration Per Channel System Calibration If the per channel system calibrations are used these should be initiated in the following order a channel zero scale system calibration follow
53. ting either a hardware reset event or a 32 ones reset sequence as the first step in the system configuration Access the AD7732 Registers All communications to the part start with a write operation to the communications register followed by either reading or writing the addressed register In a simultaneous read write interface such as SPI write 0 to the AD7732 while reading data Figure 16 shows the AD7732 interface read sequence for the ADC status register AD7732 e Lo T Lo T sc MNM Nnn on L S lea re pour _ f t lt WRITE READ COMMUNICATIONS ADC STATUS REGISTER REGISTER Figure 16 Serial Interface Signals Registers Access Single Conversion and Reading Data When the mode register is being written the ADC status byte is cleared and the RDY pin goes high regardless of its previous state When the single conversion command is written to the mode register the ADC starts the conversion on the channel selected by the address of the mode register After the conversion is completed the data register is updated the mode register is changed to idle mode the relevant RDY bit is set and the RDY pin goes low The RDY bit is reset and the RDY pin returns high when the relevant channel data register is being read Figure 17 shows the digital interface signals executing a single conversion on Channel 0 waiting for the RDY pin to go low and reading the Channel 0 data register c
54. urrent vs MCLK Frequency Normal Operation Converting Rev A Page 9 of 32 AD7732 OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7732 can be operated with chopping enabled or disabled allowing the ADC to be programmed to either optimize the throughput rate and channel switching time or to optimize the offset drift performance Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times The AD7732 noise performance depends on the selected chopping mode the filter word FW value and the selected analog input range The AD7732 noise will not vary significantly with MCLK frequency Chopping Enabled The first mode in which the AD7732 is configured with chopping enabled CHOP 1 provides very low noise with lower output rates Table 4 to Table 6 show the 3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate respectively Table 4 shows the typical output rms noise Table 5 shows the typical effective resolution based on rms noise Table 6 shows the typical output peak to peak resolution representing values for which there will be no code flicker within a 6 sigma limit The peak to peak resolutions are not calculated based on rms noise but on peak to peak noise These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK
55. v A Page 27 of 32 AD7732 Multiplexer Conversion and Data Output Timing The specified conversion time includes one or two settling and sampling periods and a scaling time With chopping enabled Figure 25 a conversion cycle starts with a settling time of 43 MCLK cycles or 44 MCLK cycles 7 us with a 6 144 MHz MCLK to allow the circuits following the multiplexer to settle The sigma delta modulator then samples the analog signals and the digital filter processes the digital data stream The sampling time depends on FW i e on the channel conversion time register contents After another settling of 42 MCLK cycles 6 8 us the sampling time is repeated with a reversed chopped analog input signal Then during the scaling time of 163 MCLK cycles 26 5 us the two results from the digital filter are averaged scaled using the calibration registers and written into the channel data register With chopping disabled Figure 26 there is only one sampling time preceded by a settling time of 43 MCLK cycles or 44 MCLK cycles and followed by a scaling time of 163 MCLK cycles MULTIPLEXER The RDY pin goes high during the scaling time regardless of its previous state The relevant RDY bit is set in the ADC status register and in the channel status register and the RDY pin goes low when the channel data register is updated and the channel conversion cycle is finished If in continuous conversion mode the part will automaticall
56. y continue with a conversion cycle on the next enabled channel Note that every channel can be configured independently for conversion time and chopping mode The overall cycle and effective per channel data rates depend on all enabled channel settings Sigma Delta ADC The AD7732 core consists of a charge balancing sigma delta modulator and a digital filter The architecture is optimized for fast fully settled conversion This allows for fast channel to channel switching while maintaining inherently excellent linearity high resolution and low noise CHANNEL 0 CHANNEL 1 CHANNEL 1 RDY SETTLING SAMPLING SETTLING TIME TIME SAMPLING SCALING TIME TIME CONVERSION TIME _ yYg aaa Ss Figure 25 Multiplexer and Conversion Timing Continuous Conversion on Several Channels with Chopping Enabled MULTIPLEXER CHANNEL 0 CHANNEL 1 RDY Pj _ See SETTLING SAMPLING SCALING TIME TIME CONVERSION TIME Figure 26 Multiplexer and Conversion Timing Continuous Conversion on Several Channels with Chopping Disabled Rev A Page 28 of 32 Frequency Response The sigma delta modulator runs at the MCLK frequency which is effectively the sampling frequency Therefore the Nyquist frequency is the MCLK frequency The digital filter in association with the modulator features the frequency response of a first order low pass filter The 3 dB point is close to the frequency of 1 channel conversion time The roll of

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