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ANALOG DEVICES AD9865 English products handbook

1. S Z m a Q o 2 ii o 2 E 6 0 12 18 24 30 36 42 48 RxPGA GAIN dB Figure 12 SINAD ENOB vs RxPGA Gain and Frequency 55 60 65 o a 2 70 a I E 75 5MHz 10MHz 80 15MHz 20MHz 30MHz S 85 n 6 12 18 24 42 48 RxPGA GAIN dB Figure 13 THD vs RxPGA Gain and Frequency 62 40 SINAD 25 C SINAD Q 85 C 59 JF SINCE SINAD 40 C 45 ANS Oe d NSN 56 E 50 THD 25 C o V s3 THDO 85 C 55 oo S THD 40 C m a 2 a 50 60 E Z Y f VoL IN NN E FA X K AT ING a 7 65 M l Y KY N 3 44 N x 70 B E 4 75 6 0 12 18 24 36 42 48 RxPGA GAIN dB Figure 14 SINAD THD Performance vs RxPGA Gain and Temperature Rev A Page 13 of 48 fiv 10 MHz AD9865 61 0 52 SNR 3 13V Ka 68 5 Lll RR SNR 3 3V 54 59 5 SNR Q 3 47V 0 0 ina Ra 59 0 SNR 3 13V Tp SNR 3 3V 59 5 58 5 THD Q 3 13V 5857 SNR 3 46V m 590 THD 3 3V 60 gt F 58 0 i THD 3 47V o u S 58 5 eee 62 S 57 5 E ss 2 T THD 3 13V 6 58 0 Z 64 E amp 57 0 THD 3 3V eee Sal K hE THD Q 3 46V 57 5 E uL 66 56 5 T 57 0 68 56 0 56 5 m 3 55 5 56 0 72 2 55 0 6 0 6 12 18 24 30 36 42 48 20 INPUT FREQUENCY MHz INPUT FREQUENCY MHz
2. THD 40 C 12 18 24 42 RxPGA GAIN dB 30 36 Figure 8 SINAD THD Performance vs RxPGA Gain and Temperature fiv 5 MHz ENOB Bits 04493 0 043 THD dBc 04493 0 045 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD CLKVDD DVDD DRVDD 3 3 V foscm fanc 80 MSPS low pass filter s f 3 as 30 MHz AIN 1 dBFS RIN 50 Q half or full duplex interface default power bias settings INPUT REFERRED SPECTRUM dBm Figure 10 Spectral Plot with 4k FFT of 111 Carrier DMT Signal with FUND 1dBFS SINAD 59 3dBFS ENOB 9 56 BITS SNR 59 8dBFS THD 69 1dBFS SFDR 70 3dBc THIRD HARMONIC RBW 19 53kHz 04493 0 046 0 10 20 30 40 FREQUENCY MHz Figure 9 Spectral Plot with 4k FFT of Input Sinusoid with RxPGA 0 dB and P 9 dBm 10 20 30 FREQUENCY MHz 4 04493 0 047 eo PAR 11 dB Pin 33 7 dBm LPF f 3 a8 32 MHz and RxPGA 36 dB SINAD dBFS SINAD 3 14V SINAD 3 3V SINAD 3 46V THD 3 14V THD Q 3 3V THD 3 46V INPUT AMPLITUDE dBFS OdBFS 2V p p Figure 11 SINAD and THD vs Input Amplitude and Supply fin 8 MHz LPF f 3as 26 MHz RxPGA 0 dB 5MHz 10MHz 15MHz 20MHz 30MHz AD9865
3. 40 C to 85 C 40 C to 85 C 40 C to 85 C Z Pb free part CP 64 3 Dimensions shown in millimeters Temperature Range Package Description 64 Lead LFCSP 64 Lead LFCSP 64 Lead LFCSP 64 Lead LFCSP DIE Evaluation Board Rev A Page 47 of 48 0 25 MIN Package Option CP 64 3 CP 64 3 CP 64 3 CP 64 3 AD9865 NOTES 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com suu La DEVICES Rev A Page 48 of 48
4. Default setting is for all functional blocks powered down except PLL MODE CONFIG 1 Setting has PLL powered down with OSCIN input routed to RXCLK output Default setting is for TXEN input to control power on off of Tx Rx path Tx driver delayed by 31 1 foata clock cycles 0x04 5 DutyCycleEnable 1 o X Default setting is Duty Cycle ea E eR G2 PlLDivideN 2 oo multiplier x 2 setting 09 PiMw pierM 2 for HEI 0x05 Wim MO Full duplex RXCLK normally Fo iwere 1 9 at nibble rate g Tasse cR 1 0 Exception on power up 0x06 7 6 CLKOUT2Divide 2 o Default setting is CLKOUT2 5 aKUmmen 9 _ and CLKOUT enabled with amp axoumpsee o i Ades Gz aoui ovde 2 o disabled o CLKOUT1 Disable 1 Rx PATH CONTROL 0x07 Default setting has LPF ON L4 ise p fo Rev A Page 19 of 48 1T fand Rx path at nominal ES i bias setting Rx path to low power AD9865 Power Up Default Value MODE 1 Full Duplex Bit Address Break MODE 0 Half Duplex Hex down Description CONFIG lt 0 0x08 7 0 Rx Filter Tuning 8 Cut off Frequency 0x80 Tx Rx PATH GAIN CONTROL 9x99 6 __ Use SPI Gain _ e gaa seems th SUR Les renee fo Tx AND Rx zm CONTROL O08 9 PGACodeforTx o PGACodeforRx 1 i jFexeGANsmobe 1 O0 S ee E wa Tx DIGITAL FILTER AND INTERFACE Ox0
5. I 100 production tested at 25 C and guaranteed by design and characterization at specified temperatures Ill Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI 100 production tested at 25 C and guaranteed by design and characterization for industrial temperature range Rev A Page 8 of 48 ABSOLUTE MAXIMUM RATINGS Table 8 Parameter Rating ELECTRICAL AVDD CLKVDD Voltage DVDD DRVDD Voltage RX RX REFT REFB IOUTP IOUTP IOUTN IOUTN IOUTG IOUTG OSCIN XTAL REFIO REFADJ Digital Input and Output Voltage Digital Output Current 3 9 V maximum 3 9 V maximum 0 3 V to AVDD 0 3 V 1 5 V to AVDD 0 3 V 0 3 V to 7 V 0 3 V to CLVDD 0 3 V 0 3 V to AVDD 0 3 V 0 3 V to DRVDD 0 3 V 5 mA maximum ENVIRONMENTAL Operating Temperature Range Ambient Maximum Junction Temperature Lead Temperature Soldering 10 s Storage Temperature Range Ambient ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or lo
6. 0x10 7 Enable current mirror gain settings 6 4 Secondary path first stage gain of 0 to4withA 1 Not used 2 0 Primary path NMOS gain of 0 to 4 with A 1 0x11 Don t care 6 4 Secondary path second stage gain of Oto 1 5 with A 0 25 3 Not used 2 0 Secondary path third stage gain of 0 to 5 withA 1 0x12 IOFF2 secondary path standing current IOFF1 primary path standing current Tx PROGRAMMABLE GAIN CONTROL TxPGA functionality is also available to set the peak output current from the TxDAC or IAMP The TxDAC and IAMP are digitally programmable via the PGA 5 0 port or SPI over a 0 dB to 7 5 dB and 0 dB to 19 5 dB range respectively in 0 5 dB increments The TxPGA can be considered as two cascaded attenuators with the TxDAC providing 7 5 dB range in 0 5 dB increments and the IAMP providing 12 dB range in 6 dB increments As a result the IAMP s composite 19 5 dB span is valid only if Register 0x10 remains at its default setting of 0x44 Modifying this register setting corrupts the LUT and results in an invalid gain mapping TxDAC OUTPUT OPERATION The differential current output of the TxDAC is available at the IOUTP and IOUTP pins and the IAMP should be disabled by setting Bit 0 of Register OxOE Any load connected to these pins must be ground referenced to provide a dc path for the current sources Figure 63 shows the outputs of the TxDAC driving a doubly terminated 1 1 transformer with its center tap t
7. 50 Q half or full duplex interface default power bias settings 512 352 288 384 256 uy 320 u 224 a a 8 S 256 192 160 192 128 128 3 96 E 64 64 0 80 160 240 320 400 480 560 640 720 0 80 160 240 320 400 480 560 640 720 TIME ns TIME ns Figure 21 RxPGA Settling Time 12 dB to 48 dB Transition for DC Input Figure 24 RxPGA Settling Time for 0 dB to 5 dB Transition for DC Input faoc 50 MSPS LPF Disabled faoc 50 MSPS LPF Disabled 0 6dB GAIN 0dB GAIN 6dB GAIN 3 a s g a 7 5 o S j u z 18dB GAIN a a 30dB GAIN B z 42dB GAIN 5 12 gt a lt 15 2 g a 0 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY MHz INPUT FREQUENCY MHz Figure 22 Rx Low Pass Filter Amplitude Response vs Supply Figure 25 Rx Low Pass Filter Amplitude Response vs RXPGA Gain faoc 50 MSPS f 3 a8 33 MHz RXPGA 0 dB LPF s Laas 33 MHz 140 420 130 410 TxDAC ISOLATION 0dB 120 S 400 T B 390 T S 110 g e u 380 W g 2 amp 100 amp 370 G Lc E o o z 90 o 360 amp Im Im 3 S E S d 350 IAMP ISOLATION 0dB 340 70 g S 3 330 Z 3 0 5 10 15 20 25 30 35 Ea 5 15 25 35 45 55 65 75 85 95
8. CLKVDD DRVDD 3 3 V 10 fosc 50 MHz fpac 200 MHz Rser 2 0 KQ unless otherwise noted Table 1 Parameter TxDAC DC CHARACTERISTICS Resolution Update Rate Full Scale Output Current IOUTP_FS Gain Error Offset Error Voltage Compliance Range TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy Gain Range Error TxDAC AC CHARACTERISTICS Fundamental Signal to Noise and Distortion SINAD Signal to Noise Ratio SNR Total Harmonic Distortion THD Spurious Free Dynamic Range SFDR IAMP DC CHARACTERISTICS IOUTN Full Scale Current IOUTN IOUTN IOUTG Full Scale Current IOUTG IOUTG AC Voltage Compliance Range ll IV V V V V IV V IV IV IV IV 7 5 0 0 5 Monotonic 2 IAMPN AC CHARACTERISTICS Fundamental IOUTN SFDR Third Harmonic IAMP GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy IOUTN Gain Range Error REFERENCE Internal Reference Voltage Reference Error Reference Drift Tx DIGITAL FILTER CHARACTERISTICS 2x Interpolation Latency Relative to 1 foac 0 2 dB Bandwidth 3 dB Bandwidth Stop Band Rejection 0 289 fpc to 0 711 fpac 19 5 0 0 5 Monotonic 0 5 25 C 1 23 V Full V 0 7 34 96 Full V 30 ppm C Full V 43 Cycles Full V 0 2187 fout foac Full V 0 2405 four fpac Full V 50 dB Rev A Page 3 of 48 AD9865 Tx DIGITAL FILTER CHARACTERISTICS Ax In
9. tez Full IV 2 ns HALF DUPLEX DATA INTERFACE ADIO PORT TIMING SPECIFICATIONS AVDD 3 3 V 596 DVDD CLKVDD DRVDD 3 3 V 10 unless otherwise noted Table 6 Parameter READ OPERATION See Figure 50 Output Data Rate Three State Output Enable Time tes Three State Output Disable Time teiz Rx Data Valid Time tvr Rx Data Output Delay top WRITE OPERATION See Figure 49 Input Data Rate 1x Interpolation Input Data Rate 2x Interpolation Input Data Rate 4x Interpolation Tx Data Setup Time tps Tx Data Hold Time ton Latch Enable Time ten Latch Disable Time tois Coup 5 pF for digital data outputs Rev A Page 7 of 48 Unit MSPS ns ns ns ns MSPS MSPS MSPS ns ns ns ns AD9865 FULL DUPLEX DATA INTERFACE Tx AND Rx PORT TIMING SPECIFICATIONS AVDD 3 3 V 5 DVDD CLKVDD DRVDD 3 3 V 10 unless otherwise noted Table 7 Parameter Temp Test Level Min Typ Max Unit Tx PATH INTERFACE See Figure 53 Input Nibble Rate 2x Interpolation Full ll 20 160 MSPS Input Nibble Rate 4x Interpolation Full ll 10 100 MSPS Tx Data Setup Time tos Full II 2 5 ns Tx Data Hold Time ton Full Hl 1 5 ns Rx PATH INTERFACE See Figure 54 Output Nibble Rate Full Il 10 160 MSPS Rx Data Valid Time tov Full Hl 3 ns Rx Data Hold Time rou Full Hl 0 ns Coup 5 pF for digital data outputs EXPLANATION OF TEST LEVELS 100 production tested
10. the ADIO port can still be placed onto a shared bus by disabling its input latch via the control signal and disabling the output driver via the SPI register The clock timing can be independently changed on the transmit and receive paths by selecting either the rising or falling clock edge as the validating sampling edge of the clock Lastly the output driver s strength can be reduced for lower data rate applications Table 13 SPI Registers for Half Duplex Interface Address Hex 0x0C Description Invert TXEN TXCLK negative edge Twos complement Rx port three state Invert RXEN RXCLK negative edge Twos complement Low digital drive strength OxOD OxOE The half duplex interface can be configured to act as a slave or a master to the digital ASIC An example of a slave configuration is shown in Figure 51 In this example the AD9865 accepts all the clock and control signals from the digital ASIC Because the sampling clocks for the DAC and ADC are derived internally from the OSCIN signal the TXCLK and RXCLK signals must be at exactly the same frequency as the OSCIN signal The phase relationships among the TXCLK RXCLK and OSCIN signals can be arbitrary If the digital ASIC cannot provide a low jitter clock source to OSCIN use the AD9865 to generate the clock for its DAC and ADC and to pass the desired clock signal to the digital ASIC via CLKOUTI or CLKOUT2 Rev A Page 23 of 48 AD9865 DIGITAL ASIC Ke P AD986
11. 8 dB resolution The RxPGA is comprised of two sections a continuous time PGA CPGA for course gain and a switched capacitor PGA SPGA for fine gain resolution The CPGA consists of two cascaded gain stages providing a gain range from 12 dB to 42 dB with 6 dB resolution The first stage features a low noise preamplifier 3 0 nV rtHz thereby eliminating the need for an external preamplifier The SPGA provides a gain range from 0 dB to 6 dB with 1 dB resolution A look up table LUT is used to select the appropriate gain setting for each stage The nominal differential input impedance of the RxPGA input appearing at the device RX and RX input pins is 400 O 4 pF 20 and remains relatively independent of gain setting The PGA input is self biased at a 1 3 V common mode level allowing maximum input voltage swings of 1 5 V at RX and RX AC coupling the input signal to this stage via coupling capacitors 0 1 uF is recommended to ensure that any external dc offset 4493 0 024 AD9865 does not get amplified with high RxPGA gain settings potentially exceeding the ADC input range To limit the RxPGAs self induced input offset an offset cancellation loop is included This cancellation loop is auto matically performed upon power up and can also be initiated via SPI During calibration the RxPGAs first stage is internally shorted and each gain stage set to a high gain setting A digital servo loop slaves a calibration DAC wh
12. Data Interface ADIO Port Timing Specifications aiis eaaeo renia isna aeai Sana arietes 7 Full Duplex Data Interface Tx and Rx Port Timing Specifications gud 8 Explanation of Test Levels sse 8 Absolute Maximum Ratings sss 9 Thermal Characteristics essent 9 ESD Caution esie nen HER ttis 9 Pin Configuration and Function Descriptions 10 Typical Performance Characteristics sss 12 Rx Path Typical Performance Characteristics 12 TxDAC Path Typical Performance Characteristics 16 IAMP Path Typical Performance Characteristics 18 Serial POLE erra r a pep EHUCOEUEPESCDESCDESGOEERDENSEME 19 Register Map Description sse 21 Serial Port Interface SPI sese 21 Digital Interface ient ter iaia 23 Halft Duplex Mode irt ere oe EP SURG 23 Full Duplex Mode E 24 RXPGA Gontro leire rear Rie et d RIT 25 TIPGA Control inr 27 Transmit Patb ertet eee a RE a 28 Digital Interpolation Filters see 28 REVISION HISTORY 11 04 Data Sheet Changed from Rev 0 to Rev A Changes to Specifications Tables sss 3 Changes to Serial Table 3 19 Changes to Full Duplex Mode section 24 Change to TxDAC and IAMP Architecture section 29 TxDAC and IAMP Architecture see 28 Tx Programmab
13. Figure 15 SNR and THD vs Input Frequency and Supply LPF f 3as 26 MHz RxPGA 0 dB AD9865 25 C AD9865 85 C AD9865 40 C INTEGRATED NOISE uV rms NOISE SPECTRAL DENSITY nVA Hz 04493 0 053 0 12 18 24 48 RxPGA GAIN dB 30 36 42 Figure 16 Input Referred Integrated Noise and Noise Spectral Density vs RxPGA Gain LPF f 3 ag 26 MHz DC OFFSET of full scale GAIN STEP ERROR dB DEVICE 4 04493 0 054 18 24 GAIN dB 30 36 42 48 Figure 17 Rx DC Offset vs RXPGA Gain Rev A Page 14 of 48 SNR dBc Figure 18 SNR and THD vs Sample Rate and Supply LPF Disabled RxPGA 0 dB fin 8 MHz 10 20 30 40 50 CUTOFF FREQUENCY MHz 60 70 80 Figure 19 SNR vs Filter Cutoff Frequency 50 MSPS fn 5 MHz AIN 1 dB RXPGA 48 dB Le M 0 1 eo AD9865 GAIN STEP ERROR 25 C AD9865 GAIN STEP ERROR 85 C AD9865 GAIN STEP ERROR 40 C 12 18 24 RxPGA GAIN dB 30 36 42 48 Figure 20 RXxPGA Gain Step Error vs Gain fiw 10 MHz 04493 0 056 04493 0 057 THD dBc 04493 0 055 AD9865 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD CLKVDD DVDD DRVDD 3 3 V foscm fanc 50 MSPS low pass filter disabled RxPGA 0 dB AIN 1 dBFS RIN
14. IAMP Settings of 4 25 mA N2 0 G 6 IAMP Settings of 10 mA N 2 4 G 0 VCM 4 8 V 2 1 Transformer into 75 Q Load PAR 11 4 RMS 9 8dBm RBW 10kHz PAR 11 4 RMS 10 4dBm dBm 04493 0 086 04493 0 089 0 5 10 15 20 25 FREQUENCY MHz FREQUENCY MHz Figure 41 Spectral Plot of 84 Carrier OFDM Test Vector Using IAMP in Figure 44 Spectral Plot of 84 Carrier OFDM Test Vector Using IAMP in Voltage Mode Configuration with AVDD 5 V Voltage Mode Configuration with AVDD 3 3 V PBR951 Transistors IAMP Settings of lt 6 mA N 2 G 6 PBR951 Transistors IAMP Settings of 6 mA N 2 G 6 Rev A Page 18 of 48 SERIAL PORT Table 10 SPI Register Mapping Address Hex Bit Break MODE 0 Half Duplex MODE 1 Full Duplex down Description CONFIG 0 0 SPI PORT CONFIGURATION AND SOFTWARE uet 0x00 m ewes h 9 6 um h 9 S swese 9 POWER CONTROL REGISTERS via PWR DWN pin 0x01 m deksm p fp 6 oe 1 i ro wow o oo m c p 1 m passe fr 1 Fo sess E ES HALF DUPLEX POWER CONTROL 0x03 U3 morbew s o mmm po PLL CLOCK MULTIPLIER SYNTHESIZER CONTROL Power Up Default Value CONFIG 1 CONFIG O CONFIG 1 AD9865 Comments Default SPI configuration is 3 wire MSB first PWR DWN 0 Default setting is for all blocks powered on PWR DWN 1
15. TXEN pin is high the RXEN pin is low and a clock is present on the TXCLK pin as shown in Figure 49 RXEN 4493 0 007 Figure 49 Transmit Data Input Timing Diagram The Tx interpolation filter s following the ADIO port can be flushed with zeros if the clock signal into the TXCLK pin is present for 33 clock cycles after TXEN goes low Note that the data on the ADIO bus is irrelevant over this interval The output from the receive path is driven onto the ADIO bus when the RXEN pin is high and a clock is present on the RXCLK pin While the output latch is enabled by RXEN valid data AD9865 appears on the bus after a 6 clock cycle delay due to the internal FIFO delay Note that Rx data is not latched back into the Tx path if TXEN is high during this interval with TXCLK present The ADIO bus becomes three stated once the RXEN pin returns low Figure 50 shows the receive path output timing xek UO L L L L L L RXEN sd Co ES Figure 50 Receive Data Output Timing Diagram ES LET ADIO 9 0 4493 0 008 To add flexibility to the digital interface port several program ming options are available in the SPI registers These options are listed in Table 13 The default Tx and Rx data input formats are straight binary but can be changed to twos complement The default TXEN and RXEN settings are active high but can be set to opposite polarities thus allowing them to share the same control In this case
16. and Rx 5 0 for simultaneous Tx and Rx operations In this mode data is transferred between the ASIC and AD9865 in 6 bit or 5 bit nibbles The AD9865 also features a flexible digital interface for updating the RxPGA and TxPGA gain registers via a 6 bit PGA port or Tx 5 0 port for fast updates or via the SPI port for slower updates See the RxPGA Control section for more information HALF DUPLEX MODE The half duplex mode functions as follows when the MODE pin is tied low The bidirectional ADIO port is typically shared in burst fashion between the transmit path and receive path Two control signals TXEN and RXEN from a DSP or digital ASIC control the bus direction by enabling the ADIO port s input latch and output driver respectively Two clock signals are also used TXCLK to latch the Tx input data and RXCLK to clock the Rx output data The ADIO port can also be disabled by setting TXEN and RXEN low default setting thus allowing it to be connected to a shared bus Internally the ADIO port consists of an input latch for the Tx path in parallel with an output latch with three state outputs for the Rx path TXEN is used to enable the input latch RXEN is used to three state the output latch A five sample deep FIFO is used on the Tx and Rx paths to absorb any phase difference be tween the AD98655 internal clocks and the externally supplied clocks TXCLK RXCLK The ADIO bus accepts input data words into the transmit path when the
17. be calculated given a programmed cutoff frequency using the following equation Actual GDT Normalized GDT 2 45 x Laan 7 5 0 5 L S GAIN dB I a N e 0 0 5 1 0 1 5 2 0 2 5 3 0 FREQUENCY 4493 0 025 Figure 70 LPF s Normalized Wideband Gain Response 0 25 1 30 0 1 25 NORMALIZED GAIN RESPONSE 0 25 1 20 0 50 1 15 E 0 75 140 8 a 00 1 05 5 u Q 1 25 1 00 Z oOo Z 1 50 0 95 a q ul 0 9 475 0 90 Nx U 2 00 085 or 2 25 0 80 9 _2 50 NORMALIZED GROUP DELAY ozs 2 75 0 70 3 00 0 65 g 0 01 02 03 04 05 06 07 08 09 10 3 NORMALIZED FREQUENCY 8 Figure 71 LPF s Normalized Pass Band Gain and Group Delay Responses The 3 dB cut off frequency f s as is programmable by writing an 8 bit word referred to as the target to Register 0x08 The cutoff frequency is a function of the ADC sample rate fanc and to a lesser extent the RxPGA gain setting in dB Figure 72 shows how the frequency response f s as varies as a function of the RxPGA gain setting 3 6dB GAIN 0dB GAIN 6dB GAIN N 18dB GAIN UN 30dB GAIN E M 42dB GAIN _ AN a ON Z T Z N 6 in MS z G z 3 K a wv z N P 12 S A SIs 15 R K 18 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY MHz 4493 0 027 Figure 72 Effects of RXxPGA Gain on LPF Frequency Response
18. bit with logic high indicating a read operation The next two bits N1 and NO specify the number of bytes one to four bytes to be transferred during the data transfer cycle The remaining five bits specify the address bits to be accessed during the data transfer portion The data bits immediately follow the instruction header for both read and write operations Table 12 Instruction Header Information MSB 17 16 R W N1 The AD9865 serial port can support both MSB most significant bit first and LSB least significant bit first data formats Figure 45 illustrates how the serial port words are built for the MSB first and LSB first modes The bit order is con trolled by the SPI LSB first bit Register 0 Bit 6 The default value is 0 MSB first Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the last address to be accessed The AD9865 automatically decrements the address for each succes sive byte required for the multibyte communication cycle Rev A Page 21 of 48 AD9865 SEN 71 INSTRUCTION CYCLE DATA TRANSFER CYCLE sex STULL soara EG DH EE eme a EO SEN 71 INSTRUCTION CYCLE DATA TRANSFER CYCLE se LLL sparA e we s Te T Tev es P TSS EN Figure 45 SPI Timing MSB First Upper and LSB First Lower 4493 0 003 When the SPI LSB first bit is set high the serial port interprets both instruction and data bytes LSB first Mu
19. differential dc offset thus preventing spectral splatter due to an impulse transient Applications using a half duplex interface MODE 0 can benefit from an additional power savings feature made available in Register 0x03 This register is effective only for a half duplex interface Besides providing power savings for half duplex applications this feature allows the AD9865 to be used in applications that need only its Rx or Tx path functionality through pin strapping making a serial port interface SPT optional This feature also allows the PWRDWN pin to retain its default function as a master power control as defined in Table 10 The default settings for Register 0x03 provide fast power control of the functional blocks in the Tx and Rx signal paths outlined above using the TXEN pin The TxDAC still remains powered on in this mode while the IAMP is powered down Significant current savings are typically realized when the IAMP is powered down For a Tx burst the falling edge of TXEN is used to generate an internal delayed signal for powering down the Tx circuitry Upon receipt of this signal power down of the Tx circuitry Rev A Page 39 of 48 AD9865 occurs within 100 ns The user programmable delay for the Tx path power down is meant to match the pipeline delay of the last Tx burst sample such that power down of the TxDAC and IAMP does not impact its transmission A 5 bit field in Register 0x03 sets the delay from 0 to 3
20. ee ZSS SER L TROD D oO O O O O O l x c aa X amp amp amp amp a lx o z 6 Figure 2 Pin Configuration Table 9 Pin Function Descriptions Pin No 2to5 Mnemonic L Mode Description ADIO9 HD MSB of ADIO Buffer ADIO8 to 5 HD Bits 8 to 5 of ADIO Buffer m e Bits 4 to 1 of Tx Nibble Input ADIO4 Bit 4 of ADIO Buffer ADIO3 Bit 3 of ADIO Buffer MSB of Rx Nibble Output ius 1 Bits 2 to 1 of ADIO Buffer E Bits 4 to 3 of Rx Nibble Output ADIO LSB of ADIO Buffer No Connect Bit 1 of Rx Nibble Output Rx 1 3 HD No Connect EN ADIO Buffer Control Input NN Rx Data Synchronization Output TXEN Tx Path Enable Input TXSYNC FD Tx Data Synchronization Input 4493 0 002 Rev A Page 10 of 48 AD9865 Pin No Mnemonic Modd Description 15 TXCLK ADIO Sample Clock Input TXQUIET Fast TXDAC IAMP Power Down 16 RXCLK ADIO Request Clock Input FD Rx and Tx Clock Output at 2 x fapc 17 64 DRVDD Digital Output Driver Supply Input 18 63 DRSS Digital Output Driver Supply Return 19 CLKOUT1 fapc N Clock Output L 1 2 4 or 8 20 Iso tw SY Serial Port Data Input Output 21 so Serial Port Data Output 22 seak do 1 Serial Port Clock Input 23 SEN Serial Port Enable Input 24 RT FD Tx Data Port Tx 5 0 Mode Select MSB of PGA Input Data Port 25 to 29 Bits 4 to 0 of PGA Input Data Port 30 i Reset Input Active Low 31 34 36 39 44 47 48 AVSS Analog Ground 32 33 R
21. f 3 ag 32 MHz 0 dB and fapc 80 MSPS The following formula can be used to estimate f 3 as for a RxPGA gain setting of 0 dB Laan oan 128 target x fapc 80 X fapc 30 t 23 83 f 8 Figure 73 compares the measured and calculated f s a using this formula 1 Empirically derived for a f 5as range of 15 MHz to 35 MHz and fanc of 40 MSPS to 80 MSPS with an RxPGA 0 dB Rev A Page 34 of 48 80 MSPS MEASURED CALCULATED FREQUENCY MHz 0 028 48 64 80 96 112 128 144 160 176 192 208 224 TARGET DECIMAL EQUIVALENT 4493 Figure 73 Measured and Calculated f_3 as vs Target Value for fapc 50 MSPS and 80 MSPS The following scaling factor can be applied to the previous formula to compensate for the RxPGA gain setting on f s as Scale Factor 1 RxPGA in dB 382 9 This scaling factor reduces the calculated f 3 as as the RxPGA is increased Applications that need to maintain a minimum cut off frequency f 5as ws for all RxPGA gain settings should first determine the scaling factor for the highest RxPGA gain setting to be used Next the f 5a uix should be divided by this scale factor to normalize to the 0 dB RxPGA gain setting f 5as oas Equation 8 can then be used to calculate the target value The LPF frequency response shows a slight sensitivity to temperature as shown in Figure 74 Applications sensitive to temperature drift can recalibrate the LP
22. interpolation filter relaxes the Tx analog filtering requirements by simultaneously reducing the images from the DAC reconstruction process while increasing the analog filter s transition band The digital interpolation filter can also be bypassed resulting in lower digital current consumption ADIO 11 6 Tx 5 0 0 TO 7 5dB 0 TO 12dB ADIO 11 6 Rx 5 0 AD9865 AD9866 TXEN SYNC D TXCLK D 44930017 Figure 59 Functional Block Diagram of Tx Path DIGITAL INTERPOLATION FILTERS The input data from the Tx port can be fed into a selectable 2x 4x interpolation filter or directly into the TxDAC for a half duplex only The interpolation factor for the digital filter is set via SPI Register 0x0C with the settings shown in Table 18 The maximum input word rate fpara into the interpolation filter is 80 MSPS the maximum DAC update rate is 200 MSPS There fore applications with input word rates at or below 50 MSPS can benefit from 4x interpolation while applications with input word rates between 50 MSPS and 80 MSPS can benefit from 2x interpolation Table 18 Interpolation Factor Set via SPI Register 0x0C Bits 7 6 Interpolation Factor 00 4 01 2 10 1 half duplex only 11 Do not use The interpolation filter consists of two cascaded half band filter stages with each stage providing 2x interpolation The first stage filter consists of 43 taps The second stage filter operating at the higher data rate consists
23. npn transistors capable of delivering in excess of 23 dBm peak signal power Tx power can be digitally controlled over a 19 5 dB range in 0 5 dB steps The receive path consists of a programmable amplifier RxPGA a tunable low pass filter LPF and a 10 bit ADC The low noise RxPGA has a programmable gain range of 12 dB to 48 dB in 1 dB steps Its input referred noise is less than 3 nV rtHz for gain settings beyond 36 dB The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or simply bypassed The 10 bit ADC achieves excellent dynamic performance over a 5 MSPS to 80 MSPS span Both the RxPGA and the ADC offer scalable power consumption allowing power performance optimization The AD9865 provides a highly integrated solution for many broadband modems It is available in a space saving 64 pin chip scale package and is specified over the commercial 40 C to 85 C temperature range One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved AD9865 TABLE OF CONTENTS Specificatii ONS cete tt teria ette ate e t eben 3 Tx Path Specifications iiit dett 3 Rx Path Specifications ccssssssssecvsossssnessssssvesoscsonwsssssevesasseasesotieses 4 Power Supply Specifications sse 5 Digital Specifications ssis 6 Serial Port Timing Specifications sss 7 Half Duplex
24. to Pin 16 have the highest potential of generating problematic high frequency noise A ground serration that contains these currents should reduce the effects of this potential noise source The ground plane directly underneath the MxFE should be continuous and uniform The 64 lead LFCSP package is designed to provide excellent thermal conductivity This is partly achieved by incorporating an exposed die paddle on the bottom surface of the package However to take full advantage of this feature the PCB must have features to effectively conduct heat away from the package This can be achieved by incorporating thermal pad and thermal vias on the PCB While a thermal pad provides a solderable surface on the top surface of the PCB to solder the package die paddle on the board thermal vias are needed to provide a thermal path to inner and or bottom layers of the PCB to remove the heat Lastly all ground connections should be made as short as possible This results in the lowest impedance return paths and the quietest ground connections SIGNAL ROUTING The digital Rx and Tx signal paths should be kept as short as possible Also the impedance of these traces should have a controlled characteristic impedance of about 50 Q This prevents poor signal integrity and the high currents that can Rev A Page 44 of 48 occur during undershoot or overshoot caused by ringing If the signal traces cannot be kept shorter than about 1 5 inches serie
25. with IOUTN Only Default IAMP Settings Rev A Page 32 of 48 RECEIVE PATH The receive path block diagram for the AD9865 or AD9866 is shown in Figure 68 The receive signal path consists of a 3 stage RxPGA a 3 pole programmable LPE and a 10 bit or 12 bit ADC Note that the additional two bits of resolution offered by the AD9866 result in a 3 dB to 5 dB lower noise floor depending on the RxPGA gain setting and LPF cutoff frequency Also working in conjunction with the receive path is an offset correction circuit These blocks are discussed in detail in the following sections Note that the power consumption ofthe RxPGA can be modified via Register 0x13 as discussed in the Power Control and Dissipation section ADIO 11 6 Tx 5 0 35 O CLKOUT 1 I O CLKOUT 2 OSCIN ADIO 11 6 5 Rx 5 0 O XTAL A 1dB A 6dB A 6dB G EE REGISTER SPORT O conTROL AD9865 AD9866 Figure 68 Functional Block Diagram of Rx Path RX PROGRAMMABLE GAIN AMPLIFIER The RxPGA has a digitally programmable gain range from 12 dB to 48 dB with 1 dB resolution via a 6 bit word Its purpose is to extend the dynamic range of the Rx path such that the input of the ADC is presented with a signal that scales within its fixed 2 V input span There are multiple ways of setting the RxPGAS gain as discussed in the RxPGA Control section as well as an alternative 3 bit gain mapping having a range of 12 dB to 36 dB with
26. 0 Q 4 0 pF Input Bandwidth with RxLPF Disabled RxPGA 0 dB 53 MHz Input Voltage Noise Density RxPGA Gain 36 dB f 3 ase 26 MHz 3 0 nV rtHz Input Voltage Noise Density RxPGA Gain 48 dB f 3 asc 26 MHz 2 4 nV rtHz RxPGA CHARACTERISTICS Minimum Gain 12 dB Maximum Gain 48 dB Gain Step Size 1 dB Gain Step Accuracy Monotonic dB Gain Range Error 0 5 dB RxLPF CHARACTERISTICS Cutoff Frequency f 3 asr Range 15 35 MHz Attenuation at 55 2 MHz with f 3 asr 21 MHz 20 dB Pass Band Ripple 1 dB Settling Time to 5 dB RxPGA Gain Step fapc 50 MSPS 20 ns Settling Time to 60 dB RxPGA Gain Step fapc 50 MSPS 100 ns ADC DC CHARACTERISTICS Resolution NA NA 10 Bits Conversion Rate Full I 5 80 MSPS Rev A Page 4 of 48 AD9865 Parameter Rx PATH LATENCY Full Duplex Interface Half Duplex Interface Rx PATH COMPOSITE AC PERFORMANCE Q fanc 50 MSPS RxPGA Gain 48 dB Full Scale 8 0 mV p p Signal to Noise and Distortion SNR Total Harmonic Distortion THD RxPGA Gain 24 dB Full Scale 2126 mV p p 25 C 25 C Signal to Noise SNR 25 C I 59 dBc Total Harmonic Distortion THD 25 C Il 67 2 dBc RxPGA Gain 0 dB Full Scale 2 0 V p p Signal to Noise and Distortion SINAD Full IV Total Harmonic Distortion THD Full 62 9 ju Rx PATH COMPOSITE AC PERFORMANCE Q fapc 80 MSPS RxPGA Gain 48 dB Full Scale 8 0 mV p p Signal to Noise SNR 25 C I 41 8 dBc Total Harmonic Dist
27. 1 TXCLK clock cycles with the default being 31 0 62 us with frxcix 50 MSPS The digital interpolation filter is automatically flushed with midscale samples prior to power down if the clock signal into the TXCLK pin is present for 33 additional clock cycles after TXEN returns low For an Rx burst the rising edge of TXEN is used to generate an internal signal with no delay that powers up the Tx circuitry within 0 5 us The Rx path power on power off can be controlled by either TXEN or RXEN by setting Bit 2 of Register 0x03 In the default setting the falling edge of TXEN powers up the Rx circuitry within 2 us while the rising edge of TXEN powers down the Rx circuitry within 0 5 us If RXEN is selected as the control signal then its rising edge powers up the Rx circuitry and the falling edge powers it down To disable the fast power down of the Tx and or Rx circuitry set Bit 1 and or Bit 0 to 0 POWER REDUCTION OPTIONS The power consumption of the AD9865 can be significantly reduced from its default setting by optimizing the power consumption versus performance of the various functional blocks in the Tx and Rx signal path On the Tx path minimum power consumption is realized when the TxDAC output is used directly and its standing current I is reduced to as low as 1 mA Although a slight degradation in THD performance results at reduced standing currents it often remains adequate for most applications because the op amp driver typic
28. 105 FREQUENCY MHz FREQUENCY MHz Figure 23 Rx to Tx Full Duplex Isolation 0 RxPGA Setting Figure 26 Rx Input Impedance vs Frequency Note ATTEN erxrca xag ATTEN rxpca ods RXPGA Gain Rev A Page 15 of 48 AD9865 TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD CLKVDD DVDD DRVDD 3 3 V fosc 50 MSPS and 80 MSPS RSET 1 96 KQO 2 1 transformer coupled output see Figure 63 into 50 Q load half or full duplex interface default power bias settings 10 0 10 20 E 30 m gt _40 50 60 70 80 CAm 0 5 10 15 20 30 FREQUENCY MHz Figure 27 Dual Tone Spectral Plot of TXDAC s Output foata 50 MSPS 4x Interpolation 10 dBm Peak Power F1 17 MHz F2 18 MHz 65 amp z nee D a ae ER z E 0 25 50 7 5 100 125 150 175 20 2 TONE CENTER FREQUENCY MHz Figure 28 2 Tone IMD Frequency Sweep vs Peak Power With foata 50 MSPS 4x Interpolation A R H x tc Oo Fu E f E 7 5 2 TONE CENTER FREQUENCY MHz 10 0 125 15 0 N e Figure 29 2 Tone Worst Spur Frequency Sweep vs Peak Power With fpara 50 MSPS 4x Interpolation 04493 0 072 4493 0 073 04493 0 074 04493 0 076 10 0 10 20 E 30 m gt 40 50 60 go c ee gt petet rou S i 0 5 10 15 20 25 35 FREQUENCY MHz Figure 30 Dual Tone Spe
29. 3 ce Zt 65 a a 24 21 18 15 12 9 6 3 0 AOUT dBFS AOUT dBFS Figure 35 SNR and SFDR vs Pour Figure 38 SNR and SFDR vs Pour four 12 55 MHz foara 50 MSPS 4x Interpolation four 20 MHz foata 80 MSPS 2x Interpolation Rev A Page 17 of 48 AD9865 IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD CLKVDD DVDD DRVDD 3 3 V fosc 50 MSPS Rser 1 58 KQ 1 1 transformer coupled output see Figure 64 and Figure 65 into 50 Q load half or full duplex interface default power bias settings 48 2 5MHz 46 Z H 5MHz 44 zt N 2 7 42 ka amp 40 d 4 4 2 10MHz 38 P4 e vu 15MHz 20MHz 4 36 7 9 l w 34 A r 7 LA 32 e E pde MU UMS Jo v UH PW E E peser mee i i 0 5 10 15 20 25 N 3 5 4 0 4 5 5 0 FREQUENCY MHz VCM V Figure 39 Dual Tone Spectral Plot of IAMPN Output Figure 42 IOUTN Third Order Intercept vs Common Mode Voltage IAMP Settings of 12 5 mA N2 4 G 0 IAMP Settings of 12 5 mA N 2 4 G 0 2 1 2 1 Transformer into 75 Q Loader VCM 4 8 V Transformer into 75 Q Load PAR 11 4 RMS 10 3dBm tf g E a o S 3 0 3 5 4 0 45 50 FREQUENCY MHz VCM V Figure 40 Spectral Plot of 84 Carrier OFDM Test Vector Using IAMPN in Figure 43 IOUTG Third Order Intercept vs Common Mode Voltage Current Mode Configuration
30. 5 TO Tx DIGITAL Tx Rx FILTER Data 9 0 10 FROM 7 Rx ADC RXEN TXEN DAC_CLK ADC_CLK CLKOUT 4493 0 009 Figure 51 Example of a Half Duplex Digital Interface with AD9865 Serving as the Slave Figure 52 shows a half duplex interface with the AD9865 acting as the master generating all the required clocks CLKOUT1 provides a clock equal to the bus data rate that is fed to the ASIC as well as back to the TXCLK and RXCLK inputs This interface has the advantage of reducing the digital ASIC s pin count by three The ASIC needs only to generate a bus control signal that controls the data flow on the bidirectional bus n n DIGITAL ASIC AD9865 10 To Tx DIGITAL Tx Rx FILTER Data 9 0 10 FROM 7 Rx ADC RXEN BUS CTH TXEN TXCLK RXCLK CLKIN CLKOUT1 OSCIN di FROM CRYSTAL OR MASTER CLK 4493 0 010 Figure 52 Example of a Half Duplex Digital Interface with AD9865 Serving as the Master FULL DUPLEX MODE The full duplex mode interface is selected when the MODE pin is tied high It can be used for full or half duplex applications The digital interface port is divided into two 6 bit ports called Tx 5 0 and Rx 5 0 allowing simultaneous Tx and Rx opera tions for full duplex applications In half duplex applications the Tx 5 0 port can also be used to provide a fast update of the RxPGA AD9875 backward compatible during an Rx opera tion This feature is enabled by default and can be used to reduce the required pin c
31. ANALOG DEVICES Broadband Modem Mixed Signal Front End AD9865 FUNCTIONAL BLOCK DIAGRAM FEATURES Low cost 3 3 V CMOS MxFE for broadband modems 10 bit D A converter 2x 4x interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19 5 dB gain control 10 bit 80 MSPS A D converter 12 dB to 48 dB low noise RxPGA 3 0 nV rtHz Third order programmable low pass filter Flexible digital data path interface Half and full duplex operation Backward compatible with AD9975 and AD9875 Various power down reduction modes Internal clock multiplier PLL 2 auxiliary programmable clock outputs Available in 64 lead chip scale package or bare die APPLICATIONS Powerline networking VDSL and HPNA GENERAL DESCRIPTION The AD9865 is a mixed signal front end MxFE IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS Its flexible digital interface power saving modes and high Tx to Rx isolation make it well suited for half and full duplex applications The digital inter face is extremely flexible allowing simple interfaces to digital back ends that support half or full duplex data transfers thus often allowing the AD9865 to replace discrete ADC and DAC solutions Power saving modes include the ability to reduce power consumption of individual functional blocks or to power down unused blocks in half duplex applications A serial port interface SPI allows software p
32. AVDD 2 The outputs of the differential reference amplifier are available at the REFT and REFB pins and must be properly decoupled for optimum performance The REFT and REFB pins are conven iently situated at the corners of the CSP package such that Cl 0603 type can be placed directly across its pins C3 and C4 can be placed underneath C1 and C2 10 uF tantalum can be placed furthest from the package Table 21 SPI Registers for Rx ADC Address Hex Description 0x04 Duty cycle restore circuit 4 ADC clock from PLL 0x07 4 ADC low power mode 0x13 2 0 ADC power bias adjust AGCTIMING CONSIDERATIONS When implementing a digital AGC timing loop it is important to consider the Rx path latency and settling time of the Rx path in response to a change in gain setting Figure 21 and Figure 24 show the RxPGAs settling response to a 60 dB and 5 dB change in gain setting when using the Tx 5 0 or PGA 5 0 port While the RxPGA settling time may also show a slight dependency on the LPF s cut off frequency the ADCS pipeline delay along with the ADIO bus interface presents a more significant delay The amount of delay or latency is dependent on whether a half or full duplex is selected An impulse response at the RXPGAS input can be observed after 10 0 ADC clock cycles 1 fapc in the case of a half duplex interface and 10 5 ADC clock cycles in the case of a full duplex interface This latency along with the RxPGA settling time should b
33. Both sets of mirrors sink current because they originate from NMOS devices Therefore each output pin requires a dc current path to a positive supply Although the voltage output of each output pin can swing between 0 5 V and 7 V optimum ac per formance is typically achieved by limiting the ac voltage swing with a dc bias voltage set between 4 to 5 V Lastly both the standing current I and the ac current Als from the TxDAC are amplified by the gain factor N and G with the total standing current drawn from the positive supply being equal to 2x N 2G xI Programmable current sources Ior and Ior via Register 0x12 can be used to improve the primary and secondary path mirrors linearity performance under certain conditions by increasing their signal to standing current ratio This feature provides a marginal improvement in distortion performance under large signal conditions when the peak ac current of the reconstructed waveform frequently approaches the dc standing current within the TxDAC 0 to 1 dBFS sine wave causing the internal mirrors to turn off However the improvement in distortion performance diminishes as the crest factor peak to rms ratio of the ac signal increases Most applications can disable these current sources set to 0 mA via Register 0x12 to reduce the IAMP s current consumption Rev A Page 29 of 48 AD9865 Table 19 SPI Registers for TxDAC and LAMP Address Hex Bit Description OxOE TxDAC output
34. C 7 6 Interpolation 2 Factor 4 Invert 1 TXEN TXSYNC m teciKneg edge 9 Twos complement 1 o Rx INTERFACE AND ANALOG DIGITAL LOOPBACK Uy Analog loopback i 9 LG og i fo Rx Port 3 State LM 00 NU LN RXEN RXSYNC aj RXikmegedge 1 fo o weempenek T To Low Drive Strength Lo woxc onset M fe Gn RvibNumbe 9 Comments Refer to Low Pass Filter section Default setting is for hardware Rx gain code via PGA or Tx data port Default setting is for Tx gain code via SPI control Default setting is RxPGA control active Tx port with GAIN strobe AD9875 AD9876 compatible 3 bit RxPGA gain map AD9975 compatible Default setting is 2x interpolation with LPF response Data format is straight binary for half duplex and twos complement for full duplex interface Full duplex only Data format is straight binary for half duplex and twos complement for full duplex interface Analog loopback ADC Rx data fed back to TxDAC Digital loopback Tx input data to Rx output port Full duplex only Default setting is for high drive strength and IAMP enabled Secondary path G1 3 4 Primary path N 0 1 2 3 4 0 1 2 Secondary path stages G2 0to 1 50 in 0 25 steps and G3 0 to 6 Stand _Primary Rev A Page 20 of 48 Standing current of primary and secondary path Bit Br
35. EFBRET Gs ADC Reference Decoupling Nodes 35 40 43 AVDD Analog Power Supply Input 37 38 RX RX Receive Path and Analog Inputs 41 READ TxDAC Full Scale Current Adjust 42 REO TxDAC Reference Input Output 45 OUT G Tx Amp Current Output Sink 46 IOUTN Tx Mirror Current Output Sink 49 IOUT G L Tx Amp Current Output_Sink 50 IOUTN Tx Mirror Current Output Sink 51 iout P TxDAC Current Output Source 52 OUT P TxDAC Current Output Source 53 ped Digital Interface Mode Select Input LOW HD HIGH FD 54 cCoNIG Power Up SPI Register Default Setting Input 55 cKvs Clock Oscillator Synthesizer Supply Return 56 XN eT Crystal Oscillator Inverter Output 57 OSIN Crystal Oscillator Inverter Input 58 CIKVDD Clock Oscillator Synthesizer Supply 59 Dvss Digital Supply Return 60 DVDD Digital Supply Input 61 cLKOUT2 fosaw L Clock Output L 1 2 or 4 62 PWRDWN Power Down Input 1 HD half duplex mode FD full duplex mode Rev A Page 11 of 48 AD9865 TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD CLKVDD DVDD DRVDD 3 3 V fosa fanc 50 MSPS low pass filter s La as 22 MHz AIN 1 dBFS RIN 50 Q half or full duplex interface default power bias settings dBm INPUT RE
36. F by rewriting the target value to Register 0x08 35 30 F Fa Four ACTUAL 80MHz AND 40 C 5 NV 2 25 NN Four ACTUAL 80MHz AND 25 C o W tc Lu N eo NY NS Four ACTUAL 80MHz AND 85 C M INS 96 112 128 144 160 176 192 208 224 240 TARGET DECIMAL EQUIVALENT 15 4493 0 029 Figure 74 Temperature Drift of f 3 as for faoc 80 MSPS and RxPGA 0 dB AD9865 ANALOG TO DIGITAL CONVERTER ADC The AD9865 features a 10 bit analog to digital converter ADC capable of up to 80 MSPS Referring to Figure 68 the ADC is driven by the SPGA stage which performs both the sample and hold and the fine gain adjust functions A buffer amplifier not shown isolates the last CPGA gain stage from the dynamic load presented by the SPGA stage The full scale input span of the ADC is 2 V p p and depending on the PGA gain setting the full scale input span into the SPGA is adjustable from 1 V to 2 V in 1 dB increments A pipelined multistage ADC architecture is used to achieve high sample rates while consuming low power The ADC distributes the conversion over several smaller A D subblocks refining the conversion with progressively higher accuracy as it passes the results from stage to stage on each clock edge The ADC typi cally performs best when driven internally by a 50 duty cycle clock This is especially the case when operating the ADC at high sample rate 55 MSPS to 80 MSPS and or lower internal bia
37. FERRED SPECTRUM FUND 1dBFS SINAD 59 1dBFS ENOB 9 53 BITS SNR 60 2dBFS THD 65 2dBFS SFDR 64 9dBc THIRD HARMONIC RBW 12 21kHz FREQUENCY MHz Figure 3 Spectral Plot with 4 k FFT of Input Sinusoid with RxPGA 0 dB and Pw 9dBm RBW lt 12 2kHz 100 110 120 130 0 5 10 15 20 2 FREQUENCY MHz SINAD dBFS Figure 4 Spectral Plot with 4 k FFT of 84 Carrier DMT Signal with PAR 10 2 dB Pw 33 7 dBm and RxPGA 36 dB 66 50 63 56 60 x aa L 57 7 68 7 7 54 E x 74 4 51 be i o d 80 48 SINAD 3 14V THD 3 14V 86 SINAD 3 3V THD 3 3V SINAD 3 46V THD 3 46V 45 92 21 18 15 12 9 6 3 0 INPUT AMPLITUDE dBFS OdBFS 2V p p Figure 5 SINAD and THD vs Input Amplitude and Supply fiw 8 MHz LPF f 3as 26 MHz Rx PGA 0 dB 04493 0 040 eo e 04493 0 041 a THD dBFS 04493 0 042 SINAD dBFS SINAD dBFS Rev A Page 12 of 48 THD dBFC 12 18 24 RxPGA GAIN dB 30 36 42 Figure 6 SINAD ENOB vs RXPGA Gain and Frequency 04493 0 044 12 18 24 42 48 RxPGA GAIN dB 30 36 Figure 7 THD vs RxPGA Gain and Frequency SINAD 25 C SINAD 85 C SINAD 40 C THD 25 C THD 85 C
38. ION dBFS 1 IAMPs IOUTN AND IOUTG ___ OUTPUTS HAS 19 5dB RANGE 04493 0 063 0 8 16 24 32 40 48 56 64 6 BIT DIGITAL CODE Decimal Equivalent Figure 58 Digital Gain Mapping of TxPGA AD9865 The TxPGA register can be updated via the PGA 5 0 port or SPI port The first method should be considered for fast updates of the TxPGA register Its operation is similar to the description in the RxPGA Control section The SPI port allows direct up date and readback of the TxPGA register via Register 0x0A with an update rate limited to 1 6 MSPS SCLK 32 MHz Bit 6 of Register Ox0A must be set for a read or write operation Table 17 lists the SPI registers pertaining to the TxPGA The TxPGA control register default setting is for minimum attenuation 0 dBFS with the PGA 5 0 port disabled for Tx gain control Table 17 SPI Registers TxPGA Control Address Hex Description Ox0A Enable TxPGA update via SPI TxPGA gain code 0x0B Select TxPGA via PGA 5 0 Select RxPGA via PGA 5 0 OxOE TxDAC output IAMP disabled Rev A Page 27 of 48 AD9865 TRANSMIT PATH The AD9865 or AD9866 transmit path consists of a selectable digital 2x 4x interpolation filter a 10 bit or 12 bit TxDAC and a current output amplifier LAMP as shown in Figure 59 Note that the additional two bits of resolution offered by the AD9866 result in a 10 dB to 12 dB reduction in the pass band noise floor The digital
39. MODE OPERATION The IAMP can be configured for the current mode operation as shown in Figure 64 for loads remaining relatively constant In this mode the primary path mirrors should be used to deliver the signal dependent current to the load via a center tapped transformer because it provides the best linearity performance Because the mirrors exhibit a high output impedance they can be easily back terminated if required For peak signal currents IOUT x up to 50 mA only the primary path mirror gain should be used for optimum distortion performance and power efficiency The primary paths gain should be set to 4 with the secondary path s gain stages set to 0 Register 0x10 0x84 The TxDAC s standing current I can be set between 2 5 mA and 12 5 mA with the IOUTP outputs left open The IOUTN outputs should be connected to the transformer with the IOUTG and IOUTP Rev A Page 30 of 48 outputs left open for optimum linearity performance The transformer should be specified to handle the dc standing current Iss drawn by the IAMP Also because Isias remains signal independent a series resistor not shown can be inserted between AVDD and the transformers center tap to reduce the IAMP s common mode voltage V cv and reduce the power dissipation on the IC The Vem bias should not exceed 5 0 V and the power dissipated in the IAMP alone is as follows Puup 2 x N G x Ix Vem 2 e 0 TO 7 5dB 0 TO 12dB IOUT
40. N IOUTG 4493 0 022 IOUTpk N G x 1 P_OUTpx IOUTpp x T2 x R Figure 64 Current Mode Operation A step down transformer with a turn ratio T can be used to increase the output power P_OUT delivered to the load This causes the output load Ri to be reflected back to the IAMP s differential output by T resulting in a larger differential voltage swing seen at the IAMP s output For example the IAMP can deliver 24 dBm of peak power to a 50 Q load ifa 1 41 1 step down transformer is used This results in 5 V p p voltage swings appearing at IOUTN and IOUTN pins Figure 42 shows how the third order intercept point OIP3 of the IAMP varies as a function of common mode voltage over a 2 5 MHz to 20 0 MHz span with a 2 tone signal having a peak power of approximately 24 dBm with IOUT 50 mA For applications requiring an IOUT exceeding 50 mA set the secondary s path to deliver the additional current to the load IOUTG and IOUTN should be shorted as well as IOUTG and IOUTN If IOUT represents the peak current to be delivered to the load then the current gain in the secondary path G can be set by the following equation G IOUT x 12 5 4 3 The linearity performance becomes limited by the secondary mirror path s distortion The B6080 and BX6090 transformers from Pulse Engineering are worthy of consideration for current and voltage modes AD9865 IAMP VOLTAGE MODE OPERATION The volt
41. N pin with TXSYNC low programs the PGA setting on either the rising edge or falling edge of RXCLK as shown in Figure 57 The GAIN pin must be held high TXSYNC must be held low and GAIN data must be stable for one or more clock cycles to update the RxPGA gain setting A low level on the GAIN pin enables data to be fed to the digital interpolation filter This interface should be considered when upgrading existing designs from the AD9875 AD9876 MxFE products or half duplex applications trying to minimize an ASIC s pin count tsu RXCLK Tx SYNC tao Tx 5 0 q ean p GAIN S Figure 57 Updating RxPGA via Tx 5 0 in Full Duplex Mode Updating the RxPGA or TxPGA via the PGA 5 0 port is an option for both the half duplex and full duplex interface The PGA port consists of an input buffer that passes the 6 bit data appearing at its input directly to the RxPGA or TxPGA gain register with no gating signal required Bit 5 or Bit 6 of Register OxOB is used to select whether the data updates the RxPGA or TxPGA gain register In applications that switch between RxPGA and TxPGA gain control via PGA 5 0 be careful that the RxPGA or TxPGA is not inadvertently loaded with the wrong data during a transition In the case of an RxPGA to TxPGA transition first deselect the RxPGA gain register update the PGA 5 0 port with the desired TxPGA gain setting and then select the TxPGA gain register The RxPGA also offers an a
42. TION CONSIDERATIONS The Tx paths analog current consumption is an important consideration when determining its contribution to the overall on chip power dissipation This is especially the case in full duplex applications where the power dissipation can exceed the maximum limit of 1 66 W if the IAMP s IOUT is set to high The analog current consumption includes the TxDAC analog supply Pin 43 along with the standing current from the IAMP s outputs Equation 2 and Equation 5 can be used to calculate the power dissipated in the IAMP for the current and voltage mode configuration Figure 66 shows the current consumption for the TxDAC and IAMP as a function of the TxDAC s standing current I when only the IOUTN outputs are used Figure 67 shows the current consumption for the TxDAC and IAMP as a function of the TxDAC standing current I when the IOUTN and IOUTG outputs are used Both figures are with the default current mirror gain settings of N 4 and G 12 IsuppLy mA 04493 0 064 1 mA Figure 66 Current Consumption of TxDAC and IAMP in Current Mode Operation with IOUTN Only Default IAMP Settings 150 140 130 120 110 100 90 80 70 60 50 40 30 IOUTG OUTPUT H IsuppLy mA 04493 0 065 1 10 15 20 25 3 0 3 5 40 45 50 55 60 65 7 0 1 mA Figure 67 Current Consumption of TxDAC and IAMP in Current Mode Operation
43. ace on the evaluation board provides a full analog front end reference design for power line applications It includes a power line socket line transformer protection diodes and passive filtering components An auxiliary path allows independent monitoring of the ac power line The evaluation board allows complete optimization of power line reference designs based around the AD9865 or AD9866 Alternatively the evaluation board allows independent evalua tion of the TxDAC IAMP and Rx paths via SMA connectors The IAMP can be easily configured for a voltage or current mode interface via jumper settings The TxDAC s performance can be evaluated directly or via an optional dual op amp driver stage The Rx path includes a transformer and termination resistor allowing a calibrated differential input signal to be injected into its front end The Analog Devices Inc website offers more information on the AD9865 AD9866 evaluation board Rev A Page 46 of 48 OUTLINE DIMENSIONS ORDERING GUIDE Model AD9865BCP AD9865BCPRL AD9865BCPZ AD9865BCPZRL AD9865CHIPS AD9865 EB 00 12 MAX Tare 0 80 MAX 0 65 TYP AD9865 PIN 1 INDICATOR EXPOSED PAD BOTTOM VIEW 0 05 MAX 0 02 NOM 0 50 Bsc E 0 20 REF COMPLIANT TO JEDEC STANDARDS MO 220 VMMD EXCEPT FOR EXPOSED PAD DIMENSION SEATING PLANE Figure 85 64 Lead Lead Frame Chip Scale Package LFCSP 40 C to 85 C
44. age mode configuration is shown in Figure 65 This configuration is suited for applications having a poorly defined load that can vary over a considerable range A low impedance voltage driver can be realized with the addition of two external RF bipolar npn transistors Phillips PBR951 and resistors In this configuration the current mirrors in the primary path IOUTN outputs feed into scaling resistors R generating a differential voltage into the bases of the npn transistors These transistors are configured as source followers with the secon dary path current mirrors appearing at IOUTG and IOUTG providing a signal dependent bias current Note that the IOUTP outputs must remain open for proper operation O 1uF Raer XVBE 1 R n DUAL NPN o 2 a IOUTN PHILLIPS PBR951 fiw E C R uu 2 s O 1uF coc o IOUTG4T isl 4 am O AVDD E TO LOAD 0 TO 7 5dB 0 TO 12dB H Iouras Rs 0 1uF 8 Figure 65 Voltage Mode Operation The peak differential voltage signal developed across the npn s bases is as follows VOUT lt Rx Nx I 4 where N is the gain setting of the primary mirror Tis the standing current of the TxDAC defined in Equation 1 The common mode bias voltage seen at IOUTN and IOUTN is approximately AVDD VOUT while the common mode voltage seen at IOUTG and IOUTG is approximately the npns Vap drop below this level AVDD VOUT 0 65 In the voltage mode configur
45. ally limits the overall linearity performance of the Tx path The load resistors used at the TxDAC outputs IOUTP and IOUTP can be increased to generate an adequate differential voltage that can be further amplified via a power efficient op amp based driver solution Figure 78 shows how the supply current for the TxDAC Pin 43 is reduced from 55 mA to 14 mA as the standing current is reduced from 12 5mA to 1 25 mA Further Tx power savings can be achieved by bypassing or reducing the interpolation factor of the digital filter as shown in Figure 79 55 50 45 40 35 30 IAVDDrxpac mA 25 20 15 04493 0 068 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 stanpine MA Figure 78 Reduction in TxDAC s Supply Current vs Standing Current Ipvpp mA 04493 0 069 INPUT DATA RATE MSPS Figure 79 Digital Supply Current Consumption vs Input Data Rate DVDD DRVDD 3 3 V and four foata 10 Power consumption on the Rx path can be achieved by reduc ing the bias levels of the various amplifiers contained within the RxPGA and ADC As previously noted the RxPGA consists of two CPGA amplifiers and one SPGA amplifier The bias levels of each of these amplifiers along with the ADC can be con trolled via Register 0x13 as shown in Table 24 The default setting for 0x13 is 0x00 Table 24 SPI Register for RxPGA and ADC Biasing Address Hex De
46. ar away from each other as possible To best manage the return currents pure digital circuits that generate high switching currents should be closest to the power supply entry This keeps the highest frequency return current paths short and prevents them from traveling over the sensitive MxFE and analog portions of the ground plane Also these circuits should be generously bypassed at each device which further reduces the high frequency ground currents The MxFE should be placed adjacent to the digital circuits such that the ground return currents from the digital sections do not flow in the ground plane under the MxFE The AD9865 has several pins that are used to decouple sensitive internal nodes These pins are REFIO REFB and REFT The decoupling capacitors connected to these points should have low ESR and ESL These capacitors should be placed as close to the MxFE as possible see Figure 75 and be connected directly to the analog ground plane The resistor connected to the REFADJ pin should also be placed close to the device and connected directly to the analog ground plane POWER PLANES AND DECOUPLING While the AD9865 evaluation board demonstrates a very good power supply distribution and decoupling strategy it can be further simplified for many applications The board has four layers two signal layers one ground plane and one power plane While the power plane on the evaluation board is split into multiple analog and digital s
47. aring on the Tx 5 0 port is routed back to the Rx 5 0 port thereby confirming proper bus operation The Rx port can also be three stated for half and full duplex interfaces Table 26 SPI Registers for Test Modes Address Hex OxOD Description Analog loop back Digital loop back Rx port three state Rev A Page 43 of 48 AD9865 PCB DESIGN CONSIDERATIONS Although the AD9865 is a mixed signal device the part should be treated as an analog component The on chip digital circuitry has been specially designed to minimize the impact of its digital switching noise on the MxFE s analog performance To achieve the best performance the power grounding and layout recommendations in this section should be followed Assembly instructions for the micro lead frame package can be found in an application note from Amkor at http www amkor com products notes_papers MLF_AppNote _0902 pdf COMPONENT PLACEMENT If the three following guidelines of component placement are followed chances for getting the best performance from the MxFE are greatly increased First manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the MxFE or analog circuits Second keep noisy digital signal paths and sensitive receive signal paths as short as possible Third keep digital noise generating and analog noise susceptible circuits as f
48. ation the total power dissipated within the IAMP is as follows Pume 2 x Ix AVDD VOUT x N AVDD VOUT 0 65 x G 5 The emitters of the npn transistors are ac coupled to the trans former via a 0 1 uF blocking capacitor and series resistor of 1 Q to 2 Q Note that protection diodes are not shown for clarity purposes but should be considered if interfacing to a power or phone line The amount of standing and signal dependent current used to bias the npn transistors depends on the peak current IOUT x required by the load If the load is variable determine the worst case IOUT x and add 3 mA of margin to ensure that the npn transistors remain in the active region during peak load Rev A Page 31 of 48 AD9865 currents The gain of the secondary path G and the TxDAC s standing current I can be set using the following equation TOUT L 3 mA GxI 6 The voltage output driver exhibits a high output impedance if the bias currents for the npn transistors are removed This feature is advantageous in half duplex applications for example power lines in which the Tx output driver must go into a high impedance state while in Rx mode If the AD9865 is configured for the half duplex mode MODE 0 the IAMB TxDAC and interpolation filter are automatically powered down after a Tx burst via TXEN thus placing the Tx driver into a high impedance state while reducing its power consumption IAMP CURRENT CONSUMP
49. ault setting without impacting the devices overall performance Rev A Page 41 of 48 AD9865 220 101 OR 111 000 001 010 lavpp mA o 011 100 101 04493 0 071 20 30 40 50 60 70 80 SAMPLE RATE MSPS Figure 83 AVDD Current vs ADC Bias Setting and Sample Rate THD 000 THD 001 THD 010 THD 011 THD 100 THD 101 SNR dBc THD dBc SNR 011 SNR 100 04493 0 092 SAMPLE RATE MSPS Figure 84 SNR and THD Performance vs fapc and ADC Bias Setting with RxPGA 0 dB fw 10 MHz and AIN 1 dBFS A sine wave input is a standard and convenient method of analyzing the performance of a system However the amount of power reduction that is possible is application dependent based on the nature of the input waveform such as frequency content peak to rms ratio the minimum ADC sample and the mini mum acceptable level of performance Thus it is advisable that power sensitive applications optimize the power bias setting of the Rx path using an input waveform that is representative of the application POWER DISSIPATION The power dissipation of the AD9865 can become quite high in full duplex applications in which the Tx and Rx paths are si multaneously operating with nominal power bias settings In fact some applications that use the IAMP may need to either reduce its peak power capabilities or reduce the power con sumpt
50. c 50 MSPS 04493 0 092 SAMPLE RATE MSPS Figure 82 SNR and THD Performance vs faoc and SPGA Bias Setting with RxPGA 0 dB fin 10 MHz LPF set to 26 MHz and AIN 1 dBFS THD dBc The ADC is based on a pipeline architecture with each stage consisting of a switched capacitor amplifier Therefore its per formance vs bias level is mostly dependent on the sample rate Figure 83 shows how the typical current consumption seen at AVDD Pins 35 and 40 varies as a function of Bits 2 0 and sample rate while the remaining bits are maintained at the default setting of 0 Setting Bit 4 or Register 0x07 corresponds to the 011 setting and the settings of 101 and 111 result in higher current consumption Figure 84 shows how the SNR and THD performance are affected for a 10 MHz sine wave input for the lower power settings as the ADC sample rate is swept 04493 0 091 therefore its performance vs bias level is mostly dependent on from 20 MHz to 80 MHz the sample rate Figure 81 shows how the typical current consumption seen at AVDD Pin 35 and Pin 40 varies as a function of Bits 4 3 and sample rate while the remaining bits are maintained at the default setting of 0 Figure 82 shows how the SNR and THD performance is affected for a 10 MHz sine wave input as the ADC sample rate is swept from 20 MHz to 80 MHz The SNR and THD performance remains relatively stable suggesting that the SPGA bias can often be reduced from its de f
51. ctral Plot of TXDAC s Output fna 80 MSPS 2x Interpolation 10 dBm Peak Power F12 27 1 MHz F2 28 7 MHz F LS H ar z gt z E E 0 5 10 15 20 25 30 2 TONE CENTER FREQUENCY MHz Figure 31 2 Tone IMD Frequency Sweep vs Peak Power With foara 80 MSPS 2x Interpolation F P a ur S o py OF q u E Rev A Page 16 of 48 2 TONE CENTER FREQUENCY MHz Figure 32 2 Tone Worst Spur Frequency Sweep vs Peak Power with fpara 80 MSPS 2x Interpolation 04493 0 077 AD9865 PAR 11 4 RMS 1 4dBm PAR 11 4 RMS 1 4dBm dBm dBm 04493 0 078 04493 0 081 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 FREQUENCY MHz FREQUENCY MHz Figure 33 Spectral Plot of 84 Carrier OFDM Test Vector Figure 36 Spectral Plot of 111 Carrier OFDM Test Vector foara 50 MSPS 4x Interpolation foara 80 MSPS 2x Interpolation PAR 11 4 RMS 1 4dBm PAR 11 4 RMS 1 4dBm dBm dBm 0 0 FREQUENCY MHz FREQUENCY MHz Figure 34 Wideband Spectral Plot of 88 Subcarrier OFDM Test Vector Figure 37 Wideband Spectral Plot of 111 Carrier OFDM Test Vector foata 50 MSPS 4x Interpolation foara 80 MSPS 2x Interpolation 95 2 TONE IMD 90 a a Le Loe 85 KE Si o o 2 ay ud W 2 Za Za 75 Be Be N N o ag 70 Zea Za lt a lt
52. e considered to ensure stability of the AGC loop Rev A Page 36 of 48 CLOCK SYNTHESIZER The AD9865 generates all its internal sampling clocks as well as two user programmable clock outputs appearing at CLKOUT1 and CLKOUT2 from a single reference source as shown in Figure 76 The reference source can be either a fundamental frequency or an overtone quartz crystal connected between OSCIN and XTAL with the parallel resonant load components as specified by the crystal manufacturer It can also be a TTL level clock applied to OSCIN with XTAL left unconnected The data rate foara for the Tx and Rx data paths must always be equal Therefore the ADC s sample rate fanc is always equal to foara while the TxDAC update rate is a factor of 1 2 or 4 of foara depending on the interpolation factor selected The data rate refers to the word rate and should not be confused with the nibble rate in full duplex interface TO ADC TO TxDAC CLKOUT1 Figure 76 Clock Oscillator and Synthesizer The 2 CLK multiplier contains a PLL with integrated loop filter and VCO capable of generating an output frequency that is a multiple of 1 2 4 or 8 of its input reference frequency foscm appearing at OSCIN The input frequency range of fosc is between 20 MHz and 80 MHz while the VCO can operate over a 40 MHz to 200 MHz span For the best phase noise jitter characteristics it is advisable to operate the VCO with a fre quency betw
53. eak Address Power Up Default Value MODE 0 Half Duplex AD9865 MODE 1 Full Duplex Hex 0x13 down Description 7 5 CPGA Bias Adjust 43 SPGA Bias Adjust ADC Bias Adjust CONFIG 0 CONFIG 1 Comments Current bias setting for Rx path s functional blocks Refer to page 41 CONFIG 0 CONFIG 1 Bits that are undefined should always be assigned a 0 REGISTER MAP DESCRIPTION The AD9865 contains a set of programmable registers described in Table 10 that are used to optimize its numerous features interface options and performance parameters from its default register settings Registers pertaining to similar functions have been grouped together and assigned adjacent addresses to minimize the update time when using the multibyte serial port interface SPI read write feature Bits that are undefined within a register should be assigned a 0 when writing to that register The default register settings were intended to allow some applications to operate without the use of an SPI The AD9865 can be configured to support a half or full duplex digital interface via the MODE pin with each interface having two possible default register settings determined by the setting of the CONFIG pin For instance applications that need to use only the Tx or Rx path functionality of the AD9865 can configure it for a half duplex interface MODE 0 and use the TXEN pin to
54. een 100 MHz and 200 MHz The VCO output drives the TxDAC directly such that its update rate fpac is related to foscm by the following equation foac 2 x fosa 10 where M 0 1 2 or 3 M is the PLLs multiplication factor set in Register 0x04 The value of M is determined by the Tx path s word rate foara and digital interpolation factor F as shown in the following equation M log Fx foata foscm 11 Note if the reference frequency appearing at OSCIN is chosen to be equal to the AD9865 s Tx and Rx paths word rate then M is simply equal to log F The clock source for the ADC can be selected in Register 0x04 as a buffered version of the reference frequency appearing at OSCIN default setting or a divided version of the VCO output 04493 0 030 AD9865 fpac The first option is the default setting and most desirable if fosc is equal to the ADC sample rate fanc This option typically results in the best jitter phase noise performance for the ADC sampling clock The second option is suitable in cases where foscmis a factor of 2 or 4 less than the fanc In this case the divider ratio N is chosen such that the divided down VCO output is equal to the ADC sample rate as shown in the following equation fanc foac 2N 12 where N 0 1 or 2 Figure 77 shows the degradation in phase noise performance imparted onto the ADC s sampling clock for different VCO output frequencies In this case a 25 MHz 1 V p p si
55. f SCLK A read operation occurs if the read not write indicator is set high After the address bits of the instruction header are read the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles If a multibyte communication cycle is specified in the instruction header a similar process as previously described for a multibyte SPI write operation applies The SDO pin remains three stated in a 3 wire read operation M ts lack SEN o g o gt lt aly zz z RF 4493 0 005 Figure 47 SPI 3 Wire Read Operation Timing Figure 48 illustrates the timing for a 4 wire read operation to the SPI port The timing is similar to the 3 wire read operation with the exception that data appears at the SDO pin while the SDIO pin remains high impedance throughout the operation The SDO pin is an active output only during the data transfer phase and remains three stated at all other times SDIO 4493 0 006 SDO Figure 48 SPI 4 Wire Read Operation Timing Rev A Page 22 of 48 DIGITAL INTERFACE The digital interface port is configurable for half duplex or full duplex operation by pin strapping the MODE pin low or high respectively In half duplex mode the digital interface port becomes a 10 bit bidirectional bus called the ADIO port In full duplex mode the digital interface port is divided into two 6 bit ports called Tx 5 0
56. gister 0x01 has all blocks powered on all bits 0 while Register 0x02 has all blocks powered down excluding the PLL such that the clock signal remains available at CLKOUTI and CLKOUT2 When the PWRDWN pin is low the functional blocks corresponding to the bits in Register 0x01 are powered down When the PWRDWN is high the functional blocks corresponding to the bits in Register 0x02 are powered down PWRDWN immediately affects the designated functional blocks with minimum digital delay Table 23 SPI Registers Associated with Power Down and Half Duplex Power Savings Address Hex Bit Description Comments 0x01 PLL PWRDWN 0 TxDAC IAMP TX Digital Default setting is all REF functional blocks powered on ADC CML ADC PGA BIAS RxPGA 0x02 7 PLL PWRDWN 1 6 TxDAC IAMP 5 TX Digital Default setting is all functional blocks 4 REF 4 powered off 3 ADC CML excluding PLL 2 ADC 1 PGA BIAS 0 RxPGA 0x03 3 Tx OFF Delay Half duplex power RxPWRDWN Savings via TXEN Enable Tx PWRDWN Enable Rx PWRDWN With MODE 1 and CONFIG 1 Reg 0x02 default settings are with all blocks powered off with RXCLK providing a buffered version of the signal appearing at OSCIN This setting results in the lowest power consumption upon power up while still allowing AD9865 to generate the system clock via a crystal AD9865 HALF DUPLEX POWER SAVINGS Significant power savings can be realized in applicat
57. gure 61 Frequency Response of 4x Interpolation Filter Normalized to foara TxDAC AND IAMP ARCHITECTURE The Tx path contains a TxDAC with a current amplifier LAMP The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to an external load or fed into the IAMP for further amplification The TxDAC s and IAMPS s peak current outputs are digitally programmable over a 0 to 7 5 dB and 0 to 19 5 dB range respectively in 0 5 dB increments Note that this assumes default register settings for Register 0x10 and Register 0x11 Rev A Page 28 of 48 Applications demanding the highest spectral performance and or lowest power consumption can use the TxDAC output directly The TxDAC is capable of delivering a peak signal power up to 10 dBm while maintaining respectable linearity performance as shown in Figure 27 through Figure 38 For power sensitive applications requiring the highest Tx power efficiency the TxDAC s full scale current output can be reduced to as low as 2 mA and its load resistors sized to provide a suitable voltage swing that can be amplified by a low power op amp based driver Most applications requiring higher peak signal powers up to 23 dBm should consider using the IAMP The IAMP can be configured as a current source for loads having a well defined impedance 50 Q or 75 Q systems or a voltage source with the addition of a pair of npn trans
58. ich forces the Rx input offset to be within 32 LSB for this particular high gain setting Although the offset varies for other gain settings the offset is typically limited to 5 of the ADC s 2 V input span Note that the offset cancellation circuitry is intended to reduce the voltage offset attributed to only the RxPGA s input stage not any dc offsets attributed to an external source The gain of the RxPGA should be set to minimize clipping of the ADC while utilizing most of its dynamic range The maxi mum peak to peak differential voltage that does not result in clipping of the ADC is shown in Figure 69 While the graph suggests that maximum input signal for a gain setting of 12 dB is 8 0 V p p the maximum input voltage into the PGA should be limited to less than 6 V p p to prevent turning on ESD protec tion diodes For applications having higher maximum input signals consider adding an external resistive attenuator network While the input sensitivity of the Rx path is degraded by the amount of attenuation on a dB to dB basis the low noise characteristics of the RxPGA provide some design margin such that the external line noise remains the dominant source 8 0000 4 0000 2 0000 1 0000 0 5000 0 2500 0 1250 0 0625 0 0312 FULL SCALE PEAK TO PEAK INPUT SPAN V 0 0156 0 0100 12 6 0 6 12 18 24 30 36 142 48 GAIN dB 04493 0 031 Figure 69 Maximum Pea
59. ied to ground The peak to peak voltage V p p across Ri and IOUT to IOUT is equal to 2 x I x R Rs With I 10 mA and Ri Rs 50 Q V p p is equal to 0 5 V with 1 dBm of peak power being delivered to Rand 1 dBm being dissipated in Rs 0 TO 7 5dB 0 TO 12dB 4493 0 021 Figure 63 TxDAC Output Directly via Center Tap Transformer The TxDAC is capable of delivering up to 10 dBm peak power to a load Ri To increase the peak power for a fixed standing current one must increase V p p across IOUTP and IOUTP by increasing one or more of the following parameters Rs Ru if possible and or the turns ratio N of transformer For exam ple the removal of Rs and the use of a 2 1 impedance ratio transformer in the previous example results in 10 dBm of peak power capabilities to the load Note that increasing the power output capabilities of the TxDAC reduces the distortion per formance due to the higher voltage swings seen at IOUTP and IOUTP See Figure 27 through Figure 38 for performance plots on the TxDAC s ac performance Optimum distortion performance can typically be achieved by e Limiting the peak positive Viourp and Viourr_to 0 8 V to avoid onset of TxDAC s output compression TxDAC s voltage compliance is around 1 2 V e Limiting V p p seen at IOUTP and IOUTP to less than 1 6 V Applications demanding higher output voltage swings and power drive capabilities can benefit from using the IAMP IAMP CURRENT
60. igh level as the least significant nibble Rev A Page 24 of 48 RXCLK RXSYNC 4493 0 012 Rx 5 0 Rx0LSB Rx3LSB Figure 54 Full Duplex Rx Port Timing To add flexibility to the full duplex digital interface port several programming options are available in the SPI registers These options are listed in Table 14 The timing for the Tx 5 0 and or Rx 5 0 ports can be independently changed by selecting either the rising or falling clock edge as the sampling validating edge of the clock Inverting RXCLK via Bit 1 or Register 0x05 affects both the Rx and Tx interface because they both use RXCLK Table 14 SPI Registers for Full Duplex Interface Address Hex 0x05 Description OSCIN to RXCLK Invert RXCLK Disable RXCLK Rx gain on Tx port Invert TXSYNC Tx 5 5 nibble LS nibble first TXCLK negative edge Twos complement Rx port three state Invert RXSYNC Rx 5 5 nibble LS nibble first RXCLK negative edge Twos complement Low drive strength OxOB OxOC OxOD OxOE The default Tx and Rx data input formats are twos complement but can be changed to straight binary The default TXSYNC and RXSYNC settings can be changed such that the first nibble of the word appears while TXSYNC RXSYNC or both are high Also the least significant nibble can be selected as the first nibble of the word LS nibble first The output driver strength can also be reduced for lower data rate applications AD9865 For
61. in The first set of current mirrors is designated as the primary path providing a gain factor of N that is programmable from 0 to 4 in steps of 1 via Bits 2 0 of Register 0x10 with a default setting of N 4 Bit 7 of this register must be set to overwrite the default settings of this register This differential path exhibits the best linearity performance see Figure 42 and is available at the IOUTN and IOUTN pins The maximum peak current per output is 100 mA and occurs when the TxDAC standing current I is set for 12 5 mA IOUTFS 25 mA The second set of current mirrors is designated as the secon dary path providing a gain factor of G that is programmable from 0 to 36 via Bits 6 4 of Register 0x10 and Bits 6 0 of Register Ox11 with a default setting of G 12 This differential path is intended to be used in the voltage mode configuration to bias the external npn transistors because it exhibits degraded linearity performance see Figure 43 relative to the primary path It is capable of sinking up to 180 mA of peak current into either its IOUTG or IOUTG pins The secondary path actually consists of three gain stages G1 G2 and G3 which are individually programmable as shown in Table 19 While many permutations may exist to provide a fixed gain of G the linearity performance of a secondary path remains relatively independent of the various individual gain settings that are possible to achieve a particular overall gain factor
62. ion of the Rx path so that the devices maximum allowable power consumption Pmax is not exceeded Pmax is specified at 1 66 W to ensure that the die temperature does not exceed 125 C at an ambient temperature of 85 C This specification is based on the 64 pin LFSCP having a thermal resistance Oja of 24 C W with its heat slug soldered The Oja is 30 8 C W if the heat slug remains unsoldered If a particular applications maximum ambient temperature Ta falls below 85 C the maximum allowable power dissipation can be deter mined by the following equation Puax 1 66 85 T4 24 13 Assuming the IAMP s common mode bias voltage is operating off the same analog supply as the AD9865 the following equa tion can be used to calculate the maximum total current consumption Imax of the IC Imax Pmax Piaup 3 47 14 With an ambient temperature of up to 85 C Imax is 478 mA If the IAMP is operating off a different supply or in the voltage mode configuration first calculate the power dissipated in the IAMP Pw using Equation 2 or Equation 5 and then recalculate Imax using Equation 14 Figure 78 Figure 79 Figure 81 and Figure 83 can be used to calculate the current consumption of the Rx and Tx paths for a given setting MODE SELECT UPON POWER UP AND RESET The AD9865 power up state is determined by the logic levels appearing at the MODE and CONFIG pins The MODE pin is used to select a half or full duplex i
63. ions having a half duplex protocol allowing only the Rx or Tx path to be operational at any instance The power savings method depends on whether the AD9865 is configured for a full or half duplex interface Functional blocks having fast power on off times for the Tx and Rx path are controlled by the following bits TxDAC IAMP TX Digital ADC and RxPGA In the case of a full duplex digital interface MODE 1 one can set Register 0x01 to 0x60 and Register 0x02 to Register 0x05 or vice versa such that the AD9865 s Tx and Rx path are never powered on simultaneously The PWRDWN pin can then be used to control which path is powered on depending on the burst type During a Tx burst the Rx paths PGA and ADC blocks can typically be powered down within 100 ns while the Tx paths DAC IAMP and digital filter blocks are powered up within 0 5 us For an Rx burst the Tx path s can be powered down within 100 ns while the Rx circuitry is powered up within 2 us Setting the TXQUIET pin low allows it to be used with the full duplex interface to quickly power down the IAMP and disable the interpolation filter This is meant to maintain backward compatibility with the AD9875 AD9876 MxFEs with the excep tion that the TxDAC remains powered if its IOUTP outputs are used In most applications the interpolation filter needs to be flushed with 0s before or after being powered down This ensures that upon power up the TxDAC and IAMP have a negligible
64. istors for poorly defined loads having varying impedance such as power lines Figure 62 shows the equivalent schematic of the TxDAC and IAMP The TxDAC provides a differential current output appearing at IOUTP and IOUTP It can be modeled as a differential current source generating a signal dependent ac current when Als has a peak current of I along with two dc current sources sourcing a standing current equal to I The full scale output current IOUTFS is equal to the sum of these standing current sources IOUTFS 2 x I N x I Al N x I Al G x UAH G x I AI 4493 0 020 Figure 62 Equivalent Schematic of TxDAC and IAMP The value of I is determined by the Rszr value at the REFADJ pin along with the Tx paths digital attenuation setting With 0 dB attenuation the value of I is T 16 x 1 23 Rser 1 For example an Rser value of 1 96 kQ results in I equal to 10 0 mA with IOUTFS equal to 20 0 mA Note that the REFIO pin provides a nominal band gap reference voltage of 1 23 V and should be decoupled to analog ground via a 0 1 uF capacitor The differential current output of the TxDAC is always con nected to the IOUTP pins but can be directed to the AMP by AD9865 clearing Bit 0 of Register OxOE As a result the IOUTP pins must remain completely open if the IAMP is to be used The IAMP contains two sets of current mirrors that are used to replicate the TxDAC s current output with a selectable ga
65. k to Peak Input vs RxPGA Gain Setting that Does Not Result in ADC Clipping Rev A Page 33 of 48 AD9865 LOW PASS FILTER The low pass filter LPF provides a third order response with a cutoff frequency that is typically programmable over a 15 MHz to 35 MHz span Figure 68 shows that the first real pole is im plemented within the first CPGA gain stage and the complex pole pair is implemented in the second CPGA gain stage Capacitor arrays are used to vary the different R C time con stants within these two stages in a manner that changes the cutoff frequency while preserving the normalized frequency response Because absolute resistor and capacitor values are process dependent a calibration routine lasting less than 100 us automatically occurs each time the target cutoff frequency register Register 0x08 is updated ensuring a repeatable cutoff frequency from device to device Although the default setting specifies that the LPF be active it can also be bypassed providing a nominal f 3 as of 55 MHz Table 20 shows the SPI registers pertaining to the LPF Table 20 SPI Registers for Rx Low Pass Filter Address Hex Description 0x07 Enable Rx LPF 0x08 Target value The normalized wideband gain response is shown in Figure 70 The normalized pass band gain and group delay responses are shown in Figure 71 The normalized cutoff frequency f 3 as results in 3 dB attenuation Also the actual group delay time GDT response can
66. le Gain Control sss 30 TxDAC Output Operation essere 30 IAMP Current Mode Operation sse 30 IAMP Voltage Mode Operation see 31 IAMP Current Consumption Considerations 32 R c eive Pathi ep epp EE 33 Rx Programmable Gain Amplifier sss 33 LowzPass Filter iit ettet 34 Analog to Digital Converter ADC ses 35 AGC Timing Considerations sse 36 Clock Synthesizer auiem ite dioere tpe ied 37 Power Control and Dissipation s 39 POWER DOWN iip ce IRR RERO 39 Half Duplex Power Savings sse 39 Power Reduction Options sse 40 Power Dissipation sse 42 Mode Select upon Power Up and Reset sss 42 Analog and Digital Loop Back Test Modes 43 PCB Design Considerations eerte 44 Component Placement 44 Power Planes and Decoupling ses 44 Ground Planes nte ee RR ids 44 Signal Routing sss eee 44 Evaluation Board oer ue 46 Outline Dimensions diete eee tiic iore itin 47 Ordering Guilde te ettet eio 47 Change to TxDAC Output Operation section eee 30 Insert equation eene tenete emittenti Change to Figure 84 caption 11 03 Revision 0 Initial Version Rev A Page 2 of 48 SPECIFICATIONS Tx PATH SPECIFICATIONS AD9865 AVDD 3 3 V 5 DVDD
67. lternative 3 bit word gain mapping option that provides a 12 dB to 36 dB span in 8 dB increments as shown in Table 16 The 3 bit word is directed to PGA 5 3 with PGA 5 being the MSB This feature is backward compatible with the AD9975 MxFE and allows direct interfacing to the CX11647 or INT5130 HomePlug 1 0 PHYs Table 16 PGA Timing for AD9975 Backward Compatible Mode Digital Gain Setting PGA 5 3 Decimal Gain dB 000 0 12 001 1 12 010 2 4 011 3 4 100 4 12 101 5 20 110 6 28 111 7 36 Default setting for full duplex mode MODE 1 The GAIN strobe can also be set in software via Reg OxOB Bit 3 for continuous updating This eliminates the requirement for external GAIN signal reducing the ASIC pin count by 1 Default setting for half duplex mode MODE 0 Default setting for MODE 0 and CONFIG 1 Rev A Page 26 of 48 TXPGA CONTROL The AD9865 also contains a digital PGA in the Tx path distri buted between the TxDAC and IAMP The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7 5 dB and 19 5 dB span respectively with 0 5 dB resolution A 6 bit word is used to set the TxPGA attenuation according to the mapping shown in Figure 58 The TxDAC gain mapping is applicable only when Bit 0 of Register OxOE is set and only the four LSBs of the 6 bit gain word are relevant Cs IOUTP OUTPUT HAS 7 5dB RANGE Tx ATTENUAT
68. ltibyte data trans fers in LSB format can be completed by writing an instruction byte that includes the register address of the first address to be accessed The AD9865 automatically increments the address for each successive byte required for the multibyte communication cycle Figure 46 illustrates the timing requirements for a write opera tion to the SPI port After the serial port enable SEN signal goes low data SDIO pertaining to the instruction header is read on the rising edges of the clock SCLK To initiate a write operation the read not write bit is set low After the instruction header is read the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles If a multibyte communication cycle is specified the destination address is decremented MSB first and shifts in another eight bits of data This process repeats until all the bytes specified in the instruction header N1 NO bits are shifted into the SDIO pin SEN must remain low during the data transfer operation only going high after the last bit is shifted into the SDIO pin ts SEN SCLK fsck ty w t s EAS ENA STS qos w X Figure 46 SPI Write Operation Timing SDIO 4493 0 004 Figure 47 illustrates the timing for a 3 wire read operation to the SPI port After SEN goes low data SDIO pertaining to the instruction header is read on the rising edges o
69. meter Temp Test Level Min Typ Max Unit POWER CONSUMPTION Half Duplex Operation with foara 50 MSPS Tx Mode lavop lcikvop 25 C IV 112 130 mA lovop Iprvop 25 C IV 46 49 5 mA Rx Mode lavop laikvop 25 C IV 225 253 mA lovop Iprvop 25 C IV 36 5 39 mA POWER CONSUMPTION OF FUNCTIONAL BLOCKS lavop lcikvob RxPGA and LPF 25 C I 87 mA ADC 25 C Ill 108 mA TxDAC 25 C I 38 mA IAMP Programmable 25 C I 10 120 mA Reference 25 C IH 170 mA CLK PLL and Synthesizer 25 C Il 107 mA MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1 66 Ww STANDBY POWER CONSUMPTION IS_TOTAL Total Supply Current Full 13 mA POWER DOWN DELAY USING PWR_DWN PIN RxPGA and LPF 25 C lll 440 ns ADC 25 C lll 12 ns TxDAC 25 C I 20 ns IAMP 25 C Ill 20 ns CLK PLL and synthesizer 25 C Il 27 ns POWER UP DELAY USING PWR DWN PIN RxPGA and LPF 25 C lll 78 us ADC 25 C lll 88 ns TxDAC 25 C Ill 13 us IAMP 25 C Ill 20 ns CLK PLL and Synthesizer 25 C Il 20 US Default power up settings for MODE HIGH and CONFIG LOW IOUTP FS 20 mA does not include IAMP s current consumption which is application dependent Default power up settings for MODE LOW and CONFIG LOW DIGITAL SPECIFICATIONS AVDD 3 3 V 5 DVDD CLKVDD DRVDD 3 3 V 1096 Rser 2 kQ unless otherwise noted Table 4 Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS High Level Input Voltage Full VI DRVDD 0 7 V Low Level In
70. ne wave was used to drive OSCIN and the PLUs M and N factors were selected to provide an fanc of 50 MHz for VCO operating frequencies of 50 100 and 200 MHz The RxPGA input was driven with a near full scale 12 5 MHz input signal with a gain setting of 0 dB Operating the VCO at the highest possible frequency results in the best narrow and wideband phase noise characteristics For comparison purposes the clock source for the ADC was taken directly from OSCIN when driven by a 50 MHz square wave DIRECT VCO 50MHz VCO 100MHz VCO 200MHz dBFS M 04493 0 067 25 45 65 85 10 12 5 145 16 5 18 5 20 5 22 FREQUENCY MHz Figure 77 Comparison of Phase Noise Performance when ADC Clock Source is Derived from Different VCO Output Frequencies The CLK synthesizer also has two clock outputs appearing at CLKOUT1 and CLKOUT2 They are programmable via Register 0x06 Both outputs can be inverted or disabled The voltage levels appearing at these outputs are relative to DRVDD and remain active during a hardware or software reset Table 22 shows the SPI registers pertaining to the clock synthesizer CLKOUT1 is a divided version of the VCO output and can be set to be a submultiple integer of fpac foac 2 where R 0 1 2 or 3 Because this clock is actually derived from the same set of dividers used within the PLL core it is phase locked to them such that its phase relationship relative
71. nterface by pin strapping it low or high respectively The CONFIG pin is used in conjunc tion with the MODE pin to determine the default settings for the SPI registers as outlined in Table 10 The intent of these particular default settings is to allow some applications to avoid using the SPI disabled by pin strapping SEN high thereby reducing implementation costs For example setting MODE low and CONFIG high configures the AD9865 to be backward compatible with the AD9975 while setting MODE high and CONFIG low makes it backward compatible with the AD9875 Other applications must use the SPI to configure the device A hardware RESET pin or software Bit 5 of Register 0x00 reset can be used to place the AD9865 into a known state of operation as determined by the state of the MODE and CONFIG pins A dc offset calibration and filter tuning routine is also initiated upon a hardware reset but not with a software reset Neither reset method flushes the digital interpolation filters in the Tx path Refer to the Half Duplex Mode and Full Duplex Mode sections for information on flushing the digital filters A hardware reset can be triggered by pulsing the RESET pin low for a minimum of 50 ns The SPI registers are instantly reset to their default settings upon RESET going low while the dc offset Rev A Page 42 of 48 calibration and filter tuning routine is initiated upon RESET returning high To ensure sufficient power on time of the
72. of 11 taps The normalized wideband and pass band filter responses relative fparA for the 2x and 4x low pass interpolation filters are shown in Figure 60 and Figure 61 respectively These responses also include the inherent sinc x from the TxDAC reconstruction process and can be used to estimate any post analog filtering requirements The pipeline delays of the 2x and 4x filter responses are 21 5 and 24 clock cycles respectively relative to fpara The filter delay is also taken into consideration for applications configured for a half duplex interface with the half duplex power down mode enabled This feature allows the user to set a programmable delay that powers down the TxDAC and IAMP only after the last Tx input sample has propagated through the digital filter See the Power Control and Dissipation section for more details WIDE BAND RESPONSE dB o PASS BAND RESPONSE dB 2 5 0 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 NORMALIZED FREQUENCY Relative to fpata 4493 0 018 Figure 60 Frequency Response of 2x Interpolation Filter Normalized to foarta 10 2 5 WIDE BAND 0 2 0 10 1 5 a a kJ S 20 10 qq U eo o z S 30 05 9 g PASS BAND I f 40 of c a 9 50 1 0dB 0 45 fDATA 0 5 Z Ei m a w 60 1 0 g a lt 70 1 5 80 20 90 2 5 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 NORMALIZED FREQUENCY Relative to fpata 4493 0 019 Fi
73. ortion THD 25 C Il 67 dBc RxPGA Gain 24 dB Full Scale 126 mV p p Signal to Noise SNR 25 C I 58 6 dBc Total Harmonic Distortion THD 25 C Il 62 9 dBc RxPGA Gain 0 dB Full Scale 2 0 V p p Signal to Noise SNR 25 C II 58 9 59 6 dBc Total Harmonic Distortion THD 25 C ll 69 7 59 8 dBc Rx to Tx PATH FULL DUPLEX ISOLATION 1 V p p 10 MHz Sine Wave Tx Output RxPGA Gain 40 dB IOUTP Pins to RX Pins 25 C IH 83 dBc IOUTG Pins to RX Pins 25 C IH 37 dBc RxPGA Gain 0 dB IOUTP Pins to RX Pins 25 C IH 123 dBc IOUTG Pins to RX Pins 25 C I 77 dBc 1 Includes RxPGA ADC pipeline and ADIO bus delay relative to fanc fin 5 MHz AIN 1 0 dBFS LPF cutoff frequency set to 15 5 MHz with Reg 0x08 0x80 3 hu 5 MHz AIN 1 0 dBFS LPF cutoff frequency set to 26 MHz with Reg 0x08 0x80 POWER SUPPLY SPECIFICATIONS AVDD 3 3 V DVDD CLKVDD DRVDD 3 3 V Rser 2 KO full duplex operation with foara 80 MSPS unless otherwise noted Table 3 Parameter Temp TestLevel Min Typ Max Unit SUPPLY VOLTAGES AVDD Full V 3 135 33 3 465 V CLKVDD Full V 3 0 33 3 6 V DVDD Full V 3 0 33 3 6 V DRVDD Full V 3 0 33 3 6 V IS TOTAL Total Supply Current Full II 406 475 mA POWER CONSUMPTION Iavop lakvop Analog Supply Current IV 311 342 mA Ipvop Ipavop Digital Supply Current Full IV 95 133 mA Rev A Page 5 of 48 AD9865 Para
74. ount of the ASIC refer to RxPGA Control section for details In either application Tx and Rx data are transferred between the ASIC and AD9865 in 6 bit or 5 bit nibbles at twice the internal input output word rates of the Tx interpolation filter and ADC Note that the TxDAC update rate must not be less than the nibble rate Therefore the 2x or 4x interpolation filter must be used with a full duplex interface The AD9865 acts as the master providing RXCLK as an output clock that is used for the timing of both the Tx 5 0 and Rx 5 0 ports RXCLK always runs at the nibble rate and can be inverted or disabled via an SPI register Because RXCLK is derived from the clock synthesizer it remains active provided that this func tional block remains powered on A buffered version of the signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05 This feature allows the AD9865 to be completely powered down including the clock synthesizer while serving as the master The Tx 5 0 port operates in the following manner with the SPI register default settings Two consecutive nibbles of the Tx data are multiplexed together to form a 10 bit data word in twos complement format The clock appearing on the RXCLK pin is a buffered version of the internal clock used by the Tx 5 0 ports input latch with a frequency that is always twice the ADC sample rate 2 x fanc Data from the Tx 5 0 port is read on the rising edge of
75. put Voltage Full VI 0 4 V Input Leakage Current 12 uA Input Capacitance Full VI 3 pF CMOS LOGIC OUTPUTS Cioap 5 pF High Level Output Voltage lou 1 mA Full VI DRVDD 0 7 V Low Level Output Voltage lou 1 mA Full VI 0 4 V Output Rise Fall Time High Strength Mode and Cioap 15 pF Full VI 1 5 2 3 ns Output Rise Fall Time Low Strength Mode and Cioap 15 pF Full VI 1 9 2 7 ns Output Rise Fall Time High Strength Mode and Cioap 5 pF Full VI 0 7 0 7 ns Output Rise Fall Time Low Strength Mode and Coup 5 pF Full VI 1 0 1 0 ns RESET Minimum Low Pulse Width Relative to faoc 1 Clock cycles Rev A Page 6 of 48 SERIAL PORT TIMING SPECIFICATIONS AVDD 3 3 V 596 DVDD CLKVDD DRVDD 3 3 V 10 unless otherwise noted AD9865 Table 5 Parameter Temp Test Level Min Typ Max Unit WRITE OPERATION See Figure 46 SCLK Clock Rate fsax Full IV 32 MHz SCLK Clock High tu Full IV 14 ns SCLK Clock Low trow Full IV 14 ns SDIO to SCLK Setup Time tps Full IV 14 ns SCLK to SDIO Hold Time ton Full IV 0 ns SEN to SCLK Setup Time ts Full IV 14 ns SCLK to SEN Hold Time tx Full IV 0 ns READ OPERATION See Figure 47 and Figure 48 SCLK Clock Rate fsax Full IV 32 MHz SCLK Clock High tu Full IV 14 ns SCLK Clock Low trow Full IV 14 ns SDIO to SCLK Setup Time tps Full IV 14 ns SCLK to SDIO Hold Time ton Full IV 0 ns SCLK to SDIO or SDO Data Valid Time tov Full IV 14 ns SEN to SDIO Output Valid to Hi Z
76. rogramming of the various functional blocks An on chip PLL clock multiplier and synthesizer provide all the required internal clocks as well as two external clocks from a single crystal or clock source The Tx signal path consists of a bypassable 2x 4x low pass interpolation filter a 10 bit TxDAC and a line driver The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS The TxDAC provides differential current outputs that can be steered directly to an external load Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners AD9865 ae Q OUT G PWR DWN C 2 4XN C IOUT Na MODE IOUT N 9739 IOUT G TXEN SYNC O TXCLK C 10 CLK CLKOUT 1 ADIO 9 4 SYN Q CLKOUT 2 Tx 5 0 P xax mio OSCIN L XTAL ADIO 3 0 Rx 5 0 10 C RX RXE SYNC Q ADC j AGC 5 0 O Ja pR CONTROL SPI 04493 0 001 Figure 1 or to an internal low distortion current amplifier The current amplifier IAMP can be configured as a current or voltage mode line driver with two external
77. s termination resistors 33 O to 47 Q should be placed close to all digital signal sources It is a good idea to series terminate all clock signals at their source regardless of trace length The receive RX and RX signals are the most sensitive signals on the entire board Careful routing of these signals is essential for good receive path performance The RX and RX signals AD9865 form a differential pair and should be routed together as a pair By keeping the traces adjacent to each other noise coupled onto the signals appears as common mode and is largely rejected by the MxFE receive input Keeping the driving point impedance of the receive signal low and placing any low pass filtering of the signals close to the MxFE further reduces the possibility of noise corrupting these signals Rev A Page 45 of 48 AD9865 EVALUATION BOARD An evaluation board is available for the AD9865 and AD9866 The digital interface to the evaluation board can be configured for a half or full duplex interface Two 40 pin and one 26 pin male right angle headers 0 100 inches provide easy interfacing to test equipment such as digital data capture boards pattern generators or custom digital evaluation boards FPGA DSP or ASIC The reference clock source can originate from an exter nal generator crystal oscillator or crystal Software and an interface cable are included to allow for programming of the SPI registers via a PC The analog interf
78. s levels which adversely affect interstage settling time requirements The ADC sampling clock path also includes a duty cycle restorer circuit which ensures that the ADC gets a near 50 duty cycle clock even when presented with a clock source with poor symmetry 35 65 This circuit should be enabled if the ADC sampling clock is a buffered version of the reference signal appearing at OSCIN see the Clock Synthesizer section and if this reference signal is derived from an oscillator or crystal whose specified symmetry cannot be guaranteed to be within 45 55 or 55 45 This circuit can remain disabled if the ADC sampling clock is derived from a divided down version of the clock synthesizer s VCO because this clock is near 50 The ADC s power consumption can be reduced by 25 mA with minimal effect on its performance by setting Bit 4 of Register 0x07 Alternative power bias settings are also available via Register 0x13 as discussed in the Power Control and Dissipation section Lastly the ADC can be completely powered down for half duplex operation further reducing the AD9865 s peak power consumption Rev A Page 35 of 48 AD9865 04493 0 066 Figure 75 ADC Reference and Decoupling The ADC has an internal voltage reference and reference ampli fier as shown in Figure 75 The internal band gap reference generates a stable 1 V reference level that is converted to a dif ferential 1 V reference centered about mid supply
79. scription 0x07 ADC low power 0x13 7 5 CPGA bias adjust 4 3 SPGA bias adjust 2 0 ADC power bias adjust Rev A Page 40 of 48 Because the CPGA processes signals in the continuous time domain its performance vs bias setting remains mostly independent of the sample rate Table 25 shows how the typical current consumption seen at AVDD Pins 35 and 40 varies as a function of Bits 7 5 while the remaining bits are maintained at their default settings of 0 Only four of the possible settings result in any reduction in current consumption relative to the default setting Reducing the bias level typically results in a degradation in the THD vs frequency performance as shown in Figure 80 This is due to a reduction of the amplifiers unity gain bandwidth while the SNR performance remains relatively AD9865 lavpp mA 04493 0 070 unaffected Table 25 Analog Supply Current vs CPGA Bias Settings at ADC SAMPLE RATE MSPS fanc 65 MSPS t Figure 81 AVDD Current vs SPGA Bias Setting and Sample Rate Bit 7 Bit 6 Bit 5 A mA 0 0 0 0 0 0 1 27 0 1 0 42 0 1 1 51 1 0 0 55 1 0 1 27 1 1 0 69 Z Sz a a 1 1 1 27 E SNR dBFS The SPGA is implemented as a switched capacitor amplifier puer BIAS Sie BITS T Figure 80 THD vs fw Performance and RxPGA Bias Settings 000 001 010 100 with RxPGA 0 and 36 dB and AIN 1 dBFS LPF set to 26 MHz and fap
80. select between the Tx or Rx signal path with the unused path remaining in a reduced power state The CONFIG pin can be used to select the default interpolation ratio of the Tx path and RxPGA gain mapping SERIAL PORT INTERFACE SPI The serial port of the AD9865 has 3 or 4 wire SPI capability allowing read write access to all registers that configure the devices internal parameters Registers pertaining to the SPI are listed in Table 11 The default 3 wire serial communication port consists of a clock SCLK serial port enable SEN and a bi directional data SDIO signal SEN is an active low control gating read and write cycle When SEN is high SDO and SDIO are three stated The inputs to SCLK SEN and SDIO contain a Schmitt trigger with a nominal hysteresis of 0 4 V centered about VDDH 2 The SDO pin remains three stated in a 3 wire SPI interface Table 11 SPI Registers Pertaining to SPI Options Address Hex Description 0x00 Enable 4 wire SPI Enable SPI LSB first A 4 wire SPI can be enabled by setting the 4 wire SPI bit high causing the output data to appear on the SDO pin instead of on the SDIO pin The SDIO pin serves as an input only throughout the read operation Note that the SDO pin is active only during the transmission of data and remains three stated at any other time An 8 bit instruction header must accompany each read and write operation The instruction header is shown in Table 12 The MSB is an R W indicator
81. ss of functionality 40 C to 85 C 125 C 150 C 65 C to 150 C AD9865 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL CHARACTERISTICS Thermal Resistance 64 lead LFCSP 4 layer board Oya 24 C W paddle soldered to ground plane 0 LPM air Oya 30 8 C W paddle not soldered to ground plane 0 LPM air Ea ESD SENSITIVE DEVICE Rev A Page 9 of 48 AD9865 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OSCIN a XTAL a MODE 2 DRVSS g PWR_DWN 2 CLKoUT2 8 DvD a pvss a CLKVDD a CLKVSS CONFIG a a gt tc a 64 ADIO9 Tx S 1 laal AVSS ADIO8 Tx 4 2 ee AVSS ADIO7 Tx 3 3 IDENTIFIER IOUT N ADIO6 Tx 2 4 ADIO5 Tx 1 5 44 AVSS ADIO4 Tx 0 6 AVDD ADIO3 Rx 5 AD9865 42 REFIO ADIO2 Rx 4 e music n REFADJ ADIO1 Rx 3 9 40 AVDD ADIO0 Rx 2 10 AVSS Nc Rx 1 11 ss RX Nc Rx 0 12 RX RXEN RXSYNC 13 Iss AVSS TXEN TXSYNC 14 35 AVDD TXCLK TXQUIET 15 la avss RXCLK ss ss REFT m Ro uoc IU rem pem Ei ra Em S
82. t word is fed into a LUT that is used to distribute the desired gain over three amplification stages within the Rx path Upon power up the RxPGA gain register is set to its minimum gain of 12 dB The RxPGA gain mapping is shown in Figure 56 Table 15 lists the SPI registers pertaining to the RxPGA Rev A Page 25 of 48 AD9865 48 GAIN dB 0 6 12 18 24 30 36 42 48 54 60 66 6 BIT DIGITAL WORD DECIMAL EQUIVALENT 4493 0 014 Figure 56 Digital Gain Mapping of RxPGA Table 15 SPI Registers RxPGA Control Address Hex Description 0x09 Enable RxPGA update via SPI RxPGA gain code 0x0B 6 Select TxPGA via PGA 5 0 5 Select RxPGA via PGA 5 0 Enable RxPGA update via Tx 5 0 Full duplex Enable software GAIN strobe Full duplex 3 bit RxPGA gain mapping Half duplex The RxPGA gain register can be updated via the Tx 5 0 port the PGA 5 0 port or the SPI port The first two methods allow fast updates of the RxPGA gain register and should be considered for digital AGC functions requiring a fast closed loop response The SPI port allows direct update and readback of the RxPGA gain register via Register 0x09 with an update rate limited to 1 6 MSPS with SCLK 32 MHz Note that Bit 6 of Register 0x09 must be set for a read or write operation Updating the RxPGA via the Tx 5 0 port is an option only in full duplex mode In this case a high level on the GAI
83. terpolation Latency Relative to 1 Foac Cycles 0 2 dB Bandwidth fout foac 3 dB Bandwidth four foac Stop Band Rejection 0 289 fosaw to 0 711 foscn dB PLL CLK MULTIPLIER OSCIN Frequency Range 80 MHz Internal VCO Frequency Range MHz Duty Cycle 60 OSCIN Impedance 100 3 MO pF CLKOUT1 Jitter 12 ps rms CLKOUT2 Jitter 6 ps rms CLKOUT1 and CLKOUT2 Duty Cycle 96 1 Gain error and gain temperature coefficients are based on the ADC only with a fixed 1 23 V external reference and a 1 V p p differential analog input TxDAC IOUTFS 20 mA differential output with 1 1 transformer with source and load termination of 50 O Four 5 MHz 4x interpolation 3 IOUN full scale current 80 mA foscin 80 MHz fpc 2160 MHz 2x interpolation Use external amplifier to drive additional load 5 Internal VCO operates at 200 MHz set to divide by 1 Because CLKOUT2 is a divided down version of OSCIN its jitter is typically equal to OSCIN 7 CLKOUT2 is an inverted replica of OSCIN if set to divide by 1 Rx PATH SPECIFICATIONS AVDD 3 3 V 5 DVDD CLKVDD DRVDD 3 3 V 1096 half or full duplex operation with CONFIG 0 default power bias settings unless otherwise noted Table 2 Parameter Temp TestLevel Min Typ Max Rx INPUT CHARACTERISTICS Input Voltage Span RxPGA Gain 10 dB 6 33 V p p Input Voltage Span RxPGA Gain 48 dB 8 mV p p Input Common Mode Voltage 1 3 V Differential Input Impedance 40
84. the AD9865 the most significant nibble defaults to 6 bits and the least significant nibble defaults to 4 bits This can be changed so that the least significant nibble and most significant nibble have 5 bits each To accomplish this set the 5 5 nibble bit in Register 0x0C and Register 0x0D and use data pins Tx 5 1 and Rx 5 1 Figure 55 shows a possible digital interface between an ASIC and the AD9865 The AD9865 serves as the master generating the required clocks for the ASIC This interface requires that the ASIC reserve 16 pins for the interface assuming a 6 bit nibble width and the use of the Tx port for RxPGA gain control Note that the ASIC pin allocation can be reduced by 3 if a 5 bit nibble width is used and the gain or gain strobe of the RxPGA is controlled via the SPI port DIGITAL ASIC AD9865 AD9866 OPTIONAL T 6 To S GAIN RxPGA Tx 5 0 x 1012 To Tx Data 5 0 Tx DIGITAL a FILTER Rx Data 5 0 Rx 5 0 x 1012 FROM E 2 ranc RX SYNC RXSYNC TX SYNC TXSYNC CLKIN RXCLK CLKOUT1 CLKOUT2 OSCIN FROM CRYSTAL OR MASTER CLK 4493 0 013 Figure 55 Example of a Full Duplex Digital Interface with Optional RxPGA Gain Control via Tx 5 0 RxPGA CONTROL The AD9865 contains a digital PGA in the Rx path that is used to extend the dynamic range The RxPGA can be programmed over 12 dB to 48 dB with 1 dB resolution using a 6 bit word and with a 0 dB setting corresponding to a 2 V p p input signal The 6 bi
85. this sampling clock as illustrated in the timing diagram shown in Figure 53 Note TXQUIET must remain high for the reconstructed Tx data to appear as an analog signal at the output of the TxDAC or IAMP tos RXCLK ET a tox TXSYNC 0 011 4493 mnn Figure 53 Tx 5 0 Port Full Duplex Timing Diagram The TXSYNC signal is used to indicate to which word a nibble belongs While TXSYNC is low the first nibble of every word is read as the most significant nibble The second nibble of that same word is read on the following TXSYNC high level as the least significant nibble If TXSYNC is low for more than one clock cycle the last transmit data is read continuously until TXSYNC is brought high for the second nibble of a new trans mit word This feature can be used to flush the interpolator filters with zeros Note that the GAIN signal must be kept low during a Tx operation The Rx 5 0 port operates in the following manner with the SPI register default settings Two consecutive nibbles of the Rx data are multiplexed together to form a 10 bit data word in twos complement format The Rx data is valid on the rising edge of RXCLK as illustrated in the timing diagram shown in Figure 54 The RXSYNC signal is used to indicate to which word a nibble belongs While RXSYNC is low the first nibble of every word is transmitted as the most significant nibble The second nibble of that same word is transmitted on the following RXSYNC h
86. to the signal appearing Rev A Page 37 of 48 AD9865 at OSCIN or RXCLK can be determined upon power up Also this clock has near 50 duty cycle because it is derived from the VCO As a result CLKOUT1 should be selected before CLKOUT2 as the primary source for system clock distribution CLKOUT2 is a divided version of the reference frequency foscin and can be set to be a submultiple integer of fosen foscin 2 where L 0 1 or 2 With L set to 0 the output of CLKOUT2 is a delayed version of the signal appearing at OSCIN exhibiting the same duty cycle characteristics With L set to 1 or 2 the output of CLKOUT is a divided version of the OSCIN signal exhibiting a near 50 duty cycle but without having a determi nistic phase relationship relative to CLKOUT1 or RXCLK Table 22 SPI Registers for CLK Synthesizer Address Hex Description 0x04 ADC CLK from PLL PLL divide factor P PLL multiplication factor M 0x06 CLKOUT2 divide number CLKOUT2 invert CLKOUT2 disable 3 2 CLKOUT1 divide number 1 CLKOUT1 invert 0 CLKOUT1 disable Pa a ES ee rr Sle o Rev A Page 38 of 48 POWER CONTROL AND DISSIPATION POWER DOWN The AD9865 provides the ability to control the power on state of various functional blocks The state of the PWRDWN pin along with the contents of Register 0x01 and Register 0x02 allow two user defined power settings that are pin selectable The default settings are such that Re
87. ubsections a permissible alternative would be to have AVDD and CLKVDD share the same analog 3 3 V power plane A separate analog plane supply may be allocated to the IAMP if its supply voltage differs from the 3 3 V required by AVDD and CLKVDD On the digital side DVDD and DRVDD can share the same 3 3 V digital power plane This digital power plane brings the current used to power the digital portion of the MxFE and its output drivers This digital plane should be kept from going underneath the analog components The analog and digital power planes allocated to the MxFE may be fed from the same low noise voltage source however they should be decoupled from each other to prevent the noise generated in the digital portion of the MxFE from corrupting the AVDD supply This can be done by using ferrite beads be tween the voltage source and the respective analog and digital power planes with a low ESR bulk decoupling capacitor on the MxFE side of the ferrite Each of the MxFE supply pins AVDD CLKVDD DVDD and DRVDD should also have dedicated low ESR ESL decoupling capacitors The decoupling capacitors should be placed as close to the MxFE supply pins as possible GROUND PLANES The AD9865 evaluation board uses a single serrated ground plane to help prevent any high frequency digital ground currents from coupling over to the analog portion of the ground plane The digital currents affiliated with the high speed data bus interface Pin 1
88. various functional blocks RESET returning high should occur no less than 10 ms upon power up If a digital reset signal from a microprocessor reset circuit such as ADM1818 is not available a simple R C network referenced to DVDD can be used to hold RESET low for approximately 10 ms upon power up ANALOG AND DIGITAL LOOP BACK TEST MODES The AD9865 features analog and digital loop back capabilities that can assist in system debug and final test Analog loop back routes the digital output of the ADC back into the Tx data path prior to the interpolation filters such that the Rx input signal can be monitored at the output of the TxDAC or IAMP As a result the analog loop back feature can be used for a half or full duplex interface to allow testing of the functionality of the entire IC excluding the digital data interface For example the user can configure the AD9865 with similar settings as the target system inject an input signal sinusoidal AD9865 waveform into the Rx input and monitor the quality of the reconstructed output from the TxDAC or IAMP to ensure a minimum level of performance In this test the user can exercise the RxPGA as well as validate the attenuation char acteristics of the RxLPF Note that the RxPGA gain setting should be selected such that the input does not result in clipping of the ADC Digital loop back can be used to test the full duplex digital interface of the AD9865 In this test data appe

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