ANALOG DEVICES AD9481 English products handbook
Contents
1. 2004 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05045 0 10 04 0 Temperature Range 40 to 85 C Evaluation board shipped with AD9481BSUZ 250 installed Package Descriptio 44 Lead Thin Plastic Evaluation Board ANALOG DEVICES Rev 0 Page 28 of 28 Package Option SU 44 n Quad Flat Package TOFP www analog com2. EXPLANATION OF TEST LEVELS Table 5 Table 6 Min Max Level Description Parameter Rating Rating 10096 production tested ELECTRICAL 10096 production tested at 25 and guaranteed by AVDD With respect to AGND 0 5V 4 0V design and characterization at specified temperatures DRVDD 0 5 4 0V Sample tested only With respect to DRGND IV Parameter is guaranteed by design and characterization AGND With respect to DRGND 0 5 V 0 5 V testing Digital 1 0 0 V DRVDD 0 5 Parameter is a typical value only With respect to DRGND VI 10096 production tested at 25 and guaranteed by Analog Inputs 0 5V AVDD 0 5V design and characterization for industrial temperature With respect to AGND range ENVIRONMENTAL Operating Temperature 40 85 Junction Temperature 150 Storage Temperature 150 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although th
3. 622 B r3 fe T mca VCTRL AVDD 28 oo 8 CT 1 82 g 2 cms qe R53 AVOD R35 C48 0 vcr E26 5 38 DR w a i 08500 zee nw T 69 amar SB ENSE DEVICES VCTRL AVDD DRVDD VDL AD9481 CMOS Customer Board Rev A Serial Number August 3 2004 USA http www onalog com fastades Figure 41 PCB Top Side Silkscreen Figure 42 PCB Top Side Copper Routing Rev 0 Page 26 of 28 05045 042 05045 043 Figure 44 PCB Split Power Plane 05045 044 05045 045 AD9481 29 Se 053 mo eo 5 v c3 os Col GJ g 653 6455 5 8 Figure 45 PCB Bottom Side Copper Routing Figure 46 PCB Bottom Side Silkscreen Rev 0 Page 27 of 28 AD9481 OUTLINE DIMENSIONS TOP VIEW PINS DOWN 1 20 MAX ic 0 75 0 60 45 1 05 0 MIN 0 2 1 00 AF asg 95 iz 0 15 ve 005 crane 0 08 MAX COPLANARITY VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026ACB Figure 47 44 Lead Thin Plastic Quad Flat Package TQFP SU 44 Dimensions shown in millimeters ORDERING GUIDE Model AD9481BSUZ 250 AD9481 PCB 17 Pb free part
4. Out of Range Recovery Time This is the time it takes for the ADC to reacquire the analog input after a transient from 1096 above positive full scale to 1096 above negative full scale or from 1096 below negative full scale to 1096 below positive full scale Rev 0 Page 11 of 28 AD9481 TYPICAL PERFORMANCE CHARACTERISTICS AVDD DRVDD 3 3 V T 25 C Am differential drive FS 1 internal reference mode unless otherwise noted SNR 45 8dB H2 65 2dBc 63 2dBc SFDR 63 2dBc B AA m mm ema ew REPRE II ae 0 4 2 tod at eti a ial h sat a m 1 1 0 20 40 60 80 100 120 MHz Figure 4 FFT fs 250 MSPS An 10 3 MHz 1 dBFS SNR 45 8dB H2 68 5dBc 63 5dBc SFDR 63 8dBc 90 al heer ey T 0 20 40 60 80 100 120 MHz Figure 5 FFT fs 250 MSPS Aw 70 MHz 1 dBFS SNR 45 9dB H2 66 6dBc 70 1dBc SFDR 65 9dBc B 0 20 40 60 MHz Figure 6 FFT fs 250 MSPS An 70 MHz 1 dBFS Single Ended Input 05045 004 05045 005 05045 006 dB dB dB Rev 0 Page 12 of 28 90 85 80 75 70 65 60 55 50 45 40 SNR 45 6dB H2 72 9dBc 65 2086 SFDR 59 6dBc n mar nw mmn Farm LUDERE D E d LT ion d 20 40 60 80 100 MHz Figure 7 FFT fs 250 MSPS Aw 170 MHz 1 dBFS 05045
5. Second The ratio of the rms signal amplitude to the rms value of the second harmonic component reported in dBc Harmonic Distortion Third The ratio of the rms signal amplitude to the rms value of the third harmonic component reported in dBc Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit Maximum Conversion Rate The encode rate at which parametric testing is performed Output Propagation Delay The delay between a differential crossing of CLK and CLK and the time when all output data bits are within valid logic levels Noise for Any Range within the ADC This value includes both thermal and quantization noise oise x0 001x10 Fae SNRag ES Signal gprs 10 V n where Zis the input impedance FS is the full scale of the device for the frequency in question SNR is the value for the particular input level Signal is the signal level within the ADC reported in dB below full scale Rev 0 Page 10 of 28 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage Signal to Noise and Distortion SINAD The ratio of the rms signal amplitude set 1 dB below ful
6. 007 120 50 100 150 200 250 300 350 Ain MHz Figure 8 Analog Input Frequency Sweep Am 1 dBFS FS 1 V fs 250 MSPS 05045 008 H3 SFDR SNR SINAD 50 100 150 200 250 300 350 Ain MHz Figure 9 Analog Input Frequency Sweep 05045 009 gt e 1 dBFS FS 0 75 V fs 250 MSPS External VREF Mode dB dB 05045 010 lt 0 50 100 150 200 250 SAMPLE CLOCK MHz Figure 10 SNR SINAD SFDR vs Sample Clock Frequency An 70 MHz Q 1 SFDR dBFS CURRENT mA AD9481 05045 013 0 50 100 150 200 250 300 SAMPLE CLOCK MSPS Figure 13 lavon and vs Clock Rate Coan 5 pF Ain 70 MHz Q 1 dBFS 5 SFDR dBc 60dB REFERENCE LINE gt 70 60 50 40 30 20 10 0 20 30 40 50 60 70 80 ANALOG INPUT DRIVE LEVEL dBFS CLOCK POSITIVE DUTY CYCLE 96 Figure 11 SFDR vs Aw Input Level Aw 70 MHz 250 MSPS Figure 14 SNR SINAD vs Clock Pulse Width High An 70 MHz 1 dBFS 250 MSPS DCS On Off 50 0 F1 F2 7dBFS 2F2 F1 65 9dBc 2F1 F2 64 9dBc 47 5 5 a 45 0 o c z 5 42 5 E 40 0 Figure 12 Two Tone Intermodulation Distort
7. LON XX X X 31 40 ATIVINHON LON X X x x 053 gt 5 9 312 1nodWv no THLOA x y 19 998 Ha 1nodWv X X 29 QNO 653 WOOA OF 19580 X aNd 00t OX X ein 075 n 159 ano and STVLX 1VNOILdO 683 3 tea OL mH LH 853 553 VAL 063 aaay x bu 55 Sry 6 4 OAL 1 153 053 THLOA 953 553 55 Avior eeu 89 5 aN Lairo L 301 ua T 1 veo an anro L amiro L amiro 31101 53 ano an9 x 3101 miro 3 0 L amiro L amiro 31101 xi 1889 ZO AdINVA X Sy en Figure 40 PCB Schematic 2 of 2 Rev 0 Page 25 of 28 AD9481 PCB LAYERS PU m GND 3 Z82229 Q 2 5 5 55585 5 5 s SENSE PWON cs ws D mom 9 o 2 53 2008 M oR H E ce 0 2 e r 90 Hz Active som vo VANP REF 65 0 70 8 Output Clocks 46 9530 8 624 w 2 0020 0e 08 m ww R22 AN 14 DS 3 q wa gg ia UU amp
8. at power on reset Rev 0 Page 19 of 28 AD9481 Table 9 51 Voltage Levels Duty Cycle S1 Voltage Data Format Stabilizer 0 9 x AVDD AVDD Offset binary Disabled 2 3 x AVDD 0 1 x AVDD Offset binary Enabled 1 3 x AVDD 0 1 x AVDD Twos complement Enabled AGND 0 1 x AVDD Twos complement Disabled DIGITAL OUTPUTS The CMOS digital outputs are TTL CMOS compatible for lower power consumption The outputs are biased from a separate supply DRVDD allowing easy interface to external logic The outputs are CMOS devices that swing from ground to DRVDD with no dc load It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short lt 2 inch for a total lt 5 pF When operating in CMOS mode it is also recommended to place low value series damping resistors on the data lines close to the ADC to reduce switching transient effects on performance Table 10 Output Coding FS 1 V Code VIN VIN Offset Binary Twos Complement 255 gt 0 512 11111111 01111111 255 0 512 V 11111111 01111111 254 0 508 V 11111110 01111110 129 0 004 V 1000 0001 0000 0001 128 10 0 V 1000 0000 0000 0000 127 0 004 V 0111 1111 1111 1111 2 0 504 V 0000 0010 1000 0010 1 0 508 V 0000 0001 1000 0001 0 0 512 V 0000 0000 1000 0000 0 lt 0 512 V 0000 0000 1000 0000 INTERLEAVING TWO AD9481s Instrumentation appli
9. jitter on the clock is combined with the desired signal at the A D output Considerable care has been taken in the design of the CLOCK input of the AD9481 and the user is advised to give commensurate thought to the clock source The AD9481 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLOCK and optimizes timing internally for sample rates between 100 MSPS and 250 MSPS This allows for a wide range of input duty cycles at the input without degrading performance Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit The duty cycle control loop does not function for clock rates less than 70 MHz nominally The loop has a time constant associated with it that needs to be considered in applications where the clock rate can AD9481 change dynamically requiring a wait time of 5 us after a dynamic clock frequency increase before valid data is available The clock duty cycle stabilizer can be disabled at Pin 28 S1 The clock inputs are internally biased to 1 5 V nominal and support either differential or single ended signals For best dynamic performance a differential signal is recommended An MCIOOLVELI6 performs well in the circuit to drive the clock inputs ac coupling is optional If the clock buffer is greater than two inches from the ADC a standard LVPECL termination may be required instead of the simple pull down terminat
10. wideband RF transformer that provides the single ended to differential conversion allowing the ADC to be driven differentially minimizing even order harmonics An optional transformer 14 can be placed if desired remove T1 as shown in Figure 39 and Figure 40 The analog signal can be low pass filtered by R21 C8 and R28 C9 at the ADC input GAIN Full scale is set by the sense jumper This jumper applies a bias to the SENSE pin to vary the full scale range the default position is SENSE ground setting the full scale to 1 V p p OPTIONAL OPERATIONAL AMPLIFIER The PCB has been designed to accommodate an optional AD8351 op amp that can serve as a convenient solution for dc coupled applications To use the AD8351 op amp remove R29 R31 and C3 Populate R12 R17 and R36 with 25 resistors and populate C1 C21 C23 C31 C39 and C30 with 0 1 uF capacitors Populate R54 R10 and R11 with 10 resistors and R34 and R32 with 1 resistors Populate R15 with a 1 2 resistor and R14 with 100 resistor Populate R37 with a 10 kQ resistor CLOCK The clock input is terminated to ground through 50 at SMA Connector J1 The input is ac coupled to a high speed differential receiver LVEL16 that provides the required low jitter fast edge rates needed for best performance J1 input should gt 0 5 V Power to the LVEL16 is set to default or AVDD by jumper placement at the device OPTIONAL
11. 9 ONISSVdAd Hl 35 ro NS d 3 9413 803 80 914 63 3 tld and I L 1013 ZL HSWHOJSNVHITVNOHdO EZH 59 2083 ND 813 aiio 724 83 917347004 53 19 XU f miro 99A u is ir 93 93 THLOA 5 1 VOEL LEY ANY 3AOW3H apo Oa eg wadav 9 uo NOILVHNDISNOD dNY dO 1 Q m o nam m gt 9293 S 5550 ae ah on S 2 235 SOTINY E 2 14 112 ano a amp DO gt S00 X X 839555 69 82 08 006 GND 29591 623 823 93 598 gripo 9 8 5 0 1nOdWv 870 A 5 sa zsa 5 I S 55 55 5 no Ris ane ix 0 5 P NIA Vo sa NIA c QNO vr 0 5 708 199 81 aaay avo 1 1 310 airo LH zaa 92 j 53 FT 19 SSH 553 80 7 aca 085 Uoor 29922 83525 gpvmua X T 5889220 0208 O dWYA fez vz sz sz z ez Joc 1s ze 1 925 Olsuav or 6393 vad 9130 SOND saa 2 oa 980 5 586 ous 79 ela zoo 18a AD9481 GND 03433135 dasn 34 04
12. ANALOG DEVICES 8 Bit 250 MSPS 3 3 V A D Converter 09481 FUNCTIONAL BLOCK DIAGRAM VREF SENSE AGND DRGND DRVDD AVDD FEATURES DNL 0 35 LSB INL 0 26 LSB Single 3 3 V supply operation 3 0 V to 3 6 V Power dissipation of 439 mW at 250 MSPS 1 V p p analog input range Internal 1 0 V reference Single ended or differential analog inputs De multiplexed CMOS outputs Power down mode Clock duty cycle stabilizer APPLICATIONS Digital oscilloscopes Instrumentation and measurement Communications Point to point radios Digital predistortion loops GENERAL DESCRIPTION The AD9481 is an 8 bit monolithic analog to digital converter ADC optimized for high speed and low power consumption Small in size and easy to use the product operates at a 250 MSPS conversion rate with excellent linearity and dynamic performance over its full operating range To minimize system cost and power dissipation the AD9481 includes an internal reference and track and hold circuit The user only provides a 3 3 V power supply and a differential encode clock No external reference or driver components are required for many applications The digital outputs are TTL CMOS compatible with an option of twos complement or binary output format The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture Rev 0 Information furnished by Analog Devices is believed to be accurate and relia
13. CLOCK BUFFER The PCB has been designed to accommodate the SNLVDSI line driver The SNLVDSI is used as a high speed LVDS level optional encode clock To use this clock please remove C2 C5 and C6 Place 0 1 uF capacitors on C34 C35 and C26 Place 10 resistor on R48 and place 100 resistor on R6 Place a 0 Q resistor on both R49 and R53 For best results using the line driver J1 input should be gt 2 5 V p p DS The DS inputs are available on the PCB at J2 and JA If driving DS externally place a 0 resistor at C48 and remove R53 Rev 0 Page 21 of 28 AD9481 OPTIONAL XTAL The PCB has been designed to accommodate an optional crystal oscillator that can serve as a convenient clock source The footprint can accept both through hole and surface mount devices including Vectron XO 400 and Vectron VCC6 family oscillators T vec OUT GND umm 05045 038 Figure 38 XTAL Footprint To use either crystal populate C38 and C40 with 0 1 capaci tors Populate R48 and R49 with 0 resistors Place R50 R51 R59 and R60 with 1 resistors Remove and C5 If the Vectron VCC6 family crystal is being used populate R57 with a 10 resistor If using the XO 400 crystal place jumper E21 or E22 to E23 VOLTAGE REFERENCE The AD9481 has an internal 1 V reference mode The ADC uses the internal 1 V reference as the default when sense is set to ground An optional on board external 1 0 V referen
14. D9481 EVALUATION BOARD The AD9481 evaluation board offers an easy way to test the device It requires a clock source an analog input signal and a 3 3 V power supply The clock source is buffered on the board to provide the clocks for the ADC and a data ready signal The digital outputs and output clocks are available at an 80 pin output connector P3 P23 Note that P3 P23 are represented schematically as two 40 pin connectors and this connector is implemented as one 80 pin connector on the PCB The board has several different modes of operation and is shipped in the following configuration e Offset binary e Internal voltage reference POWER CONNECTOR Power is supplied to the board via two detachable 4 pin power strips Table 11 Power Connector Terminal Comments VDL 3 3 V Output supply for external latches and data ready clock buffer 30 mA AVDD 3 3 V Analog supply for ADC 140 mA DRVDD 3 3 V Output supply for ADC 30 mA VCTRL 3 3 V Supply for support clock circuitry 60 mA Op amp ext ref Optional supply for op amp and ADR510 reference 1 AVDD DRVDD VDL and VCTRL are the minimum required power connections AD9481 ANALOG INPUTS The evaluation board accepts a 700 mV p p analog input signal centered at ground at SMB Connector J3 This signal is terminated to ground through 50 by R22 The input can be alternatively terminated at the T1 transformer secondary by R21 and R28 T1 is a
15. HANGE ps 40 20 0 20 40 60 8 TEMPERATURE Figure 22 Propagation Delay Sensitivity vs Temperature 05045 048 Rev 0 Page 15 of 28 AD9481 AD9481 EQUIVALENT CIRCUITS O AVDD AVDD O VIN PDWN 30ko 05045 023 05045 026 Figure 23 Analog Inputs AVDD DRVDD 05045 027 Figure 27 Data DCO Outputs 05045 024 O VDD Pm E Figure 25 S1 Input 05045 025 Rev 0 Page 16 of 28 APPLICATIONS The AD9481 uses a 1 5 bit per stage architecture The analog inputs drive an integrated high bandwidth track and hold circuit that samples the signal prior to quantization by the 8 bit core For ease of use the part includes an on board reference and input logic that accepts TTL CMOS or LVPECL levels The digital output logic levels are CMOS compatible ANALOG INPUTS The analog input to the AD9481 is a differential buffer For best dynamic performance impedances at VIN and VIN should match Optimal performance is obtained when the analog inputs are driven differentially SNR and SINAD performance can degrade if the analog input is driven with a single ended signal The analog inputs self bias to approximately 1 9 V this common mode voltage can be externally overdriven by approximately 300 mV if required A wideband transformer such as the Mini Circuits ADT1 1WT can provide the differential analog inputs for applications that require a single en
16. MSPS Clock Pulse Width High te Full IV 1 2 2 ns Clock Pulse Width Low ta Full IV 1 2 2 ns DS Input Setup Time tsps Full IV 0 5 ns DS Input Hold Time tups Full IV 0 5 ns OUTPUT PARAMETERS Valid Time tv Full VI 2 5 ns Propagation Delay trp Full VI 4 5 4 ns Rise Time tr 1096 to 90 Full V 670 ps Fall Time tr 10 to 9096 Full V 360 ps DCO Propagation Delay tcro Full VI 2 5 3 9 5 3 ns Data to DCO Skew tpp tcpp Full VI 0 5 0 5 ns A Port Data to DCO Rising tska Full IV 4 ns B Port Data to DCO Rising tske Full IV 4 ns Pipeline Latency A B Full IV 8 Cycles APERTURE Aperture Delay t4 25 V 1 5 ns Aperture Uncertainty Jitter 25 V 0 25 ps rms OUT OF RANGE RECOVERY TIME 25 V 1 Cycle 1 Cio equals 5 pF maximum for all output switching specifications Valid time is approximately equal to minimum tro 3 Te equals clock rising edge to DCO or rising edge delay Data changing to DCO or DCO rising edge delay 5 Tska are both clock rate dependent delays equal to Tcycie Data to DCO skew Rev 0 Page 6 of 28 AD9481 TIMING DIAGRAM VIN 8 CYCLES 1 CLK CLK INTERLEAVED DATA OUT PORTA D7A TO DOA STATIC PORT B D7B TO DOB STATIC DCO DCO STATIC y N Figure 2 Timing Diagram 05045 002 Rev 0 Page 7 of 28 AD9481 ABSOLUTE MAXIMUM RATINGS Thermal impedance 46 4 C W 4 layer
17. al reference or provide an external reference for greater accuracy and flexibility Figure 32 shows the typical reference variation with temperature Table 8 summarizes the available reference configurations 05045 032 Figure 31 Internal Reference Equivalent Circuit Rev 0 Page 17 of 28 AD9481 Fixed Reference The internal reference can be configured for a differential span of 1 V see Figure 34 It is recommended to place a 0 1 uF capacitor as close as possible to the VREF pin a 10 uF capacitor is also required see the PCB layout for guidance If the internal reference of the AD9481 is used to drive multiple converters to improve gain matching the loading of the reference by the other converters must be considered Figure 34 depicts how the internal reference voltage is affected by loading 1 0085 1 0080 1 0075 1 0070 1 0065 gt 1 0060 tc 71 0055 1 0050 1 0045 1 0040 1 0035 40 Figure 32 05045 033 20 0 20 40 60 80 TEMPERATURE Typical Reference Variation with Temperature Table 8 Reference Configurations CHANGE IN VREF VOLTAGE 104F 05045 034 Figure 33 Internal Fixed Reference 1 V p p 05045 035 0 5 1 0 1 5 2 0 2 5 IREF mA Figure 34 Internal VREF vs Load Current SENSE Voltage Resulting VREF Reference Differential Span AVDD N A external reference in
18. ble However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners OD7A TO DOA 8 BIT ADC PIPELINE CORE TO Opco QODco 05045 001 Figure 1 The AD9481 is available in a Pb free 44 lead surface mount package TQFP 44 specified over the industrial temperature range 40 to 85 PRODUCT HIGHLIGHTS 1 Superior linearity A DNL of 0 35 makes the AD9481 suitable for many instrumentation and measurement applications 2 Power down mode A power down function may be exercised to bring total consumption down to 15 mW 3 De multiplexed CMOS outputs allow for easy interfacing with low cost FPGAs and standard logic One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved AD9481 TABLE OF CONTENTS DC Speeifications o Am HEN 3 Data Clock Out eR 20 18 1 41 18 1 1 19 18 12 1 19 4 1 51 0 198 1 99898 20 AC SpecificatioDs 5 AD9481 Evaluation Board see 21 Switching Specif
19. cations may prefer to interleave or ping pong two AD9481s to achieve twice the sample rate or 500 MSPS In these applications it is important to match the gain and offset of the two ADCs Varying the reference voltage allows the gain of the ADCs to be adjusted external dc offset compensation can be used to reduce offset mismatch between two ADCs The sampling phase offset between the two ADCs is extremely important as well and requires very low skew between clock signals driving the ADCs lt 2 ps clock skew for a 100 MHz analog input frequency DATA CLOCK OUT data clock is available at DCO and DCO These clocks can facilitate latching off chip providing a low skew clocking solution The on chip delay of the DCO clocks tracks with the on chip delay of the data bits under similar loading such that the variation between tep and tcen is minimized It is recommended to keep the trace lengths on the data and DCO pins matched and 2 inches maximum A series damping resistor at the clock outputs is also recommended The DCO outputs can be disabled and placed in a high impedance state by tying S3 to ground tie to AVDD for DCO active Switching both into and out of high impedance is accomplished in 4 ns from 53 switching POWER DOWN INPUT The ADC can be placed into a low power state by setting the PDWN pin to AVDD Time to go into or come out of power down equals 30 ns typically from PDWN switching Rev 0 Page 20 of 28 A
20. ce ADR510 can be used by setting the sense jumper to AVDD by placing a jumper on E5 to E3 and by placing a 0 resistor on R55 When using an external programmable reference R20 R30 remove the sense jumper DATA OUTPUTS The ADC outputs are buffered on the PCB by LVT574 latches on the data outputs The latch outputs have series terminating resistors at the output pins to minimize reflections Rev 0 Page 22 of 28 EVALUATION BOARD BILL OF MATERIALS BOM AD9481 Table 12 No Quantity Reference Designator Device Package Value 1 24 C1 to C6 C10 to C12 C14 to C15 Capacitors 0402 0 1 uF C17 to C19 C22 to C29 C31 C48 to C49 2 1 C13 Capacitor Tantalum 3528 10 uF 3 5 C32 to C36 Capacitors Tantalum 6032 10 uF 4 4 J1 to J4 SMA SMA Degrees 5 3 P1 P12 to P13 4 pin power connectors Post 5 531 3425 0 6 3 P1 P12 to P13 4 pin power connectors Detachable connector 25 602 5453 0 7 2 P3 P23 80 pin connectors Connector TSW 140 08 L D RA 8 7 R1 R5 R19 R22 R27 R35 R53 Resistors 0603 500 9 8 R2 to R4 R6 to R9 R18 R14 Resistors 0603 100 0 10 7 R13 R42 to R45 R32 R34 Resistors 0603 1 0 11 2 R16 R52 Resistors 0603 130 0 12 2 R23 R24 Resistors 0603 5100 13 2 R25 R26 Resistors 0603 820 14 2 R29 R31 Resistors 0603 000 15 2 R33 R37 Resistors 0603 10 kQ 16 1 R46 Resistor 0603 2 kQ 17 3 R12 R17 R36 Resistors 0603 250 18 1 R15 Resistor 0603 1 2 19 3 R54 R10 to R11 Resistor
21. ded to differential conversion Note that the filter and center tap capacitor on the secondary side is optional and dependent on application requirements An RC filter at the secondary side helps reduce any wideband noise getting aliased by the ADC R C OPTIONAL 49 90 05045 029 Figure 28 Driving the ADC with an RF Transformer For dc coupled applications the AD8138 AD8139 or AD8351 can serve as a convenient ADC driver depending on requirements Figure 29 shows an example with the AD8138 The AD9481 PCB has an optional AD8351 on board as shown in Figure 39 and Figure 40 The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz The AD9481 s linearity and SFDR start to degrade at higher analog frequencies see the Typical Performance Characteristics section For higher frequency applications the AD9480 with LVDS outputs and superior AC performance should be considered AD9481 AGND 05045 030 Figure 29 Driving the ADC with the AD8138 The AD9481 can be easily configured for different full scale ranges See the Voltage Reference section for more information Optimal performance is achieved with a 1 V p p analog input 500mV 2 0V 2 0V DIGITALOUT ALL 1s DIGITALOUT ALL 0s 05045 031 Figure 30 Analog Input Full Scale VOLTAGE REFERENCE A stable and accurate 1 0 V reference is built into the AD9481 Users can choose this intern
22. ge 2 of 28 DC SPECIFICATIONS AD9481 AVDD 3 3 V DRVDD 3 3 V Tui 40 C Tmax 85 C Ax 1 full scale 1 0 V internal reference differential analog and clock inputs unless otherwise noted Table 1 AD9481 250 Parameter Temp Test Level Min Typ Max Unit RESOLUTION 8 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error 25 C 40 40 mV Gain Error 25 6 0 6 0 96 FS Differential Nonlinearity DNL Full VI 0 85 0 35 0 85 LSB Integral Nonlinearity INL Full VI 0 9 0 26 0 9 LSB TEMPERATURE DRIFT Offset Error Full V 30 Gain Error Full V 0 03 96 FS C Reference Full V 0 025 mV C REFERENCE Internal Reference Voltage Full VI 0 97 1 0 1 03 V Output Current 25 IV 1 5 mA Ivrer Input Current 25 C 100 Isense Input Current 25 10 ANALOG INPUTS VIN VIN Differential Input Voltage Range Full V 1 V p p Common Mode Voltage Full VI 1 6 1 9 2 1 V Input Resistance Full VI 84 10 11 2 Input Capacitance 25 V 4 pF Analog Bandwidth Full Power 25 V 750 MHz POWER SUPPLY AVDD Full IV 3 0 3 3 3 6 V DRVDD Full IV 3 0 3 3 3 6 V Supply Currents IAVDD Full VI 133 145 mA IDRVDD Full VI 39 42 5 mA Power Dissipation 25 C V 439 mW Power Down Dissipation 25 V 15 37 mW Power Supply Rejection Ratio PSRR 25 V 4 2 mV V 1 Gain error and gain temperature coefficients are based on the ADC only wit
23. h a fixed 1 V external reference and 1 V input range Internal reference mode SENSE AGND External reference mode VREF driven by external 1 0 V reference SENSE AVDD FS 1 V both analog inputs are 500 mV and out of phase with each other Supply current measured with rated encode and a 20 MHz analog input Power dissipation measured with dc input see the Terminology section for power vs clock rate Rev 0 Page 3 of 28 AD9481 DIGITAL SPECIFICATIONS AVDD 3 3 V DRVDD 3 3 V Tuis 40 Tmax 85 C Ax 1 full scale 1 0 V internal reference differential analog and clock inputs unless otherwise noted Table 2 AD9481 250 Parameter Temp Test Level Min Typ Max Unit CLOCK AND DS INPUTS CLK CLK DS DS Differential Input Full IV 200 mV p p Common Mode Voltage Full VI 1 38 1 5 1 68 V Input Resistance Full VI 4 2 5 5 6 0 Input Capacitance 25 V 4 pF LOGIC INPUTS PDWN S1 Logic 1 Voltage Full IV 2 0 V Logic 0 Voltage Full IV 0 8 V Logic 1 Input Current Full VI 160 Logic 0 input Current Full VI 10 Input Resistance 25 V 30 Input Capacitance 25 V 4 pF DIGITAL OUTPUTS Logic 1 Voltage Full VI DRVDD 0 05 mV Logic 0 Voltage Full VI 0 05 V Output Coding Full IV Twos complement or binary common mode for CLOCK inputs can be externally set such that 0 9 V lt lt 2 6 V Capac
24. ications seen 6 Power Connector ERA 21 Timing Diagram 7 Arialog Inputs tete tee epe 21 Absolute Maximum Ratings esent 8 M 21 Explanation of Test Levels see 8 Optional Operational Amplifier sss 21 ESD C a tion nene ue edente 8 hr m 21 Pin Configuration and Function 5 9 Optional Clock Buffer tree tette 21 Terminology vite eet Pda itus 10 21 Typical Performance Characteristics sss 12 Optional X EAT s oit tette to ae 22 Equivalent eive rH Hd renda 16 Voltage Reference ere eb tbe 22 Applications inei RH eH 17 Data tp ts i iet titre 22 Analog Inputs ete tie eerte 17 Evaluation Board Bill of Materials BOM 23 Voltage Reference icti ies 17 PCB Sch niatics 24 Clocking 948 neret eerte 19 PCB Vayers 26 5 3 19 Outline Dimensions 3599 28 Digital Outputsz 20 Ordering Guide 28 11 11 91 1 9111 32 88 1 20 REVISION HISTORY 10 04 Revision 0 Initial Version Rev 0 Pa
25. ion 69 3 MHz and 70 3 MHz fs 250 MSPS Rev 0 Page 13 of 28 0 5 0 7 0 9 1 1 1 3 1 5 1 7 1 9 EXTERNAL VREF VOLTAGE V 70 MHz 1 dBFS 250 MSPS SFDR dBc 05045 015 Figure 15 SNR SINAD and SFDR vs VREF in External Reference Mode Ain AD9481 2 0 1 5 FS 1V EXTERNAL REFERENCE 1 0 a GAIN ERROR 0 5 1 0 FS 1 E INTERNAL REFERENCE 2 0 40 20 0 20 40 60 80 TEMPERATURE Figure 16 Full Scale Gain Error vs Temperature An 70 3 MHz 0 5 dBFS 250 MSPS 70 65 SFDR 60 5 55 50 SINAD 45 40 40 20 0 20 40 60 80 TEMPERATURE Figure 17 SINAD SFDR vs Temperature 70 MHz 1 dBFS 250 MSPS 0 10 0 05 8 0 gt z 8 2 05 o 0 10 0 15 27 28 29 30 31 32 33 34 35 36 AVDD V Figure 18 VREF Sensitivity to AVDD 05045 016 05045 017 05045 018 70 65 60 dB 55 50 Figure 19 SNR SINAD and SFDR vs Supply Voltage 70 3 MHz 1 dBFS 250 MSPS LSB o 0 50 100 150 CODE 200 Figure 20 Typical DNL Plot 10 3 MHz 0 5 dBFS 250 MSPS 250 0 50 100 150 CODE Figure 21 Typical INL Plot 10 3 MHz 0 5 dBFS 250 MSPS Rev 0 Page 14 of 28 250 05045 019 05045 020 05045 021 DELAY C
26. ion shown in Figure 37 AD9481 05045 028 Figure 37 Clocking the AD9481 DS INPUTS The data sync inputs DS DS can be used in applications which require that a given sample appear at a specific output port A or B relative to a given external timing signal The DS inputs can also be used to synchronize two or more in a system to maintain phasing between Ports A and B on separate ADCs in effect synchronizing multiple DCO outputs The DS inputs are internally biased to 1 5 V nominal and support either differential or single ended signals When DS is held high DS low the ADC data outputs and DCO outputs do not switch and are held static Synchronization is accomplished by the assertion falling edge of DS within the timing constraints tsps and tups relative to a clock rising edge On initial synchronization tus is not relevant If DS falls within the required setup time tsps before a given clock rising edge N the analog value at that point in time is digitized and available at Port A eight cycles later in interleaved mode The next sample N 1 is sampled by the next rising clock edge and available at Port B eight cycles after that clock edge Driving each ADC s DS inputs by the same sync signal accomplishes synchronization between multiple ADCs In applications which require synchronization one shot synchronization is recommended An easy way to accomplish synchronization is by a one time sync
27. is product features WARNING proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Spr tate electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev 0 Page 8 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND 8 AVDD AD9481 TOP VIEW Not to Scale Table 7 Pin Function Descriptions Figure 3 Pin Configuration AD9481 05045 003 Pin Pin No Name Description No Name Description 1 CLK Input Clock True 25 D6B Data Output Bit 6 Channel B 2 CLK Input Clock Complement 26 D7B Data Output Bit 7 B MSB 3 AVDD 3 3 V Analog Supply 27 DRGND Digital Ground 4 AGND Analog Ground 28 S1 Data Format Select and Duty Cycle Stabilizer 5 DRVDD 3 3 V Digital Output Supply Select 6 DRGND Digital Ground 29 PDWN Power Down Selection 7 D7A Data Output Bit 7 Channel A MSB 30 AVDD 3 3 V Analog Supply 8 D6A Data Output Bit 6 Channel A 31 AVDD 3 3 V Analog Supply 9 D5A Data Output Bit 5 Channel A 32 AGND Analog Ground 10 D4A Data Output Bit 4 Channel A 33 SENSE Reference Mode Selection 11 D3A Data Output Bit 3 Channel A 34 VREF Voltage Reference Input Output 12 D2A Data Output Bit 2 Channel A 35 AGND Analog Ground 13 DIA Data Output Bit 1 Channel A 36 AVDD 3 3 V Analog Supply 14 DOA Data O
28. itive loading only Rev 0 Page 4 of 28 AD9481 AC SPECIFICATIONS AVDD 3 3 V DRVDD 3 3 V Tuis 40 C Tmax 85 C Ax 1 full scale 1 0 V internal reference differential analog and clock inputs unless otherwise noted Table 3 AD9481 250 Parameter Temp Test Level Min Typ Max Unit SIGNAL TO NOISE RATIO SNR fin 19 7 MHz 25 V 46 dB fin 70 1 MHz 25 C 44 5 45 7 dB SIGNAL TO NOISE AND DISTORTION SINAD fin 19 7 MHz 25 C V 45 9 dB fin 70 1 MHz 25 444 45 7 dB EFFECTIVE NUMBER OF BITS ENOB fin 19 7 MHz 25 C V 7 5 Bits fin 70 1 MHz 25 7 2 7 5 Bits WORST SECOND OR THIRD HARMONIC DISTORTION fin 19 7 MHz 25 V 64 8 dBc fin 70 1 MHz 25 64 8 54 dBc WORST OTHER fin 19 7 MHz 25 V 68 dBc fin 70 1 MHz 25 65 8 56 dBc SPURIOUS FREE DYNAMIC RANGE SFDR fin 19 7 MHz 25 V 64 8 dBc fin 70 1 MHz 25 64 8 54 dBc TWO TONE INTERMODULATION DISTORTION IMD 69 3 fi 70 3 MHz 25 V 64 9 dBc DC and Nyquist bin energy ignored Rev 0 Page 5 of 28 AD9481 SWITCHING SPECIFICATIONS AVDD 3 3 V DRVDD 3 3 V differential encode input duty cycle stabilizer enabled unless otherwise noted Table 4 AD9481 250 Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Conversion Rate Full VI 250 MSPS Minimum Conversion Rate Full IV 20
29. l scale to the rms value of the sum of all other spectral components including harmonics but excluding dc Signal to Noise Ratio without Harmonics The ratio of the rms signal amplitude set at 1 dB below full scale to the rms value of the sum of all other spectral components excluding the first five harmonics and dc Spurious Free Dynamic Range SFDR The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component The peak spurious component may or may not be a harmonic It also may be reported in dBc degrades as signal level is lowered or dBFS always related back to converter full scale Two Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product in dBc AD9481 Two Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component The peak spurious component may or may not be an IMD product It also may be reported in dBc degrades as signal level is lowered or in dBFS always relates back to converter full scale Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component excluding the second and third harmonic reported in dBc Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10 above negative full scale to 1096 below positive full scale
30. put External 1 x external reference voltage 0 5 V Self Biased 0 5 x 1 RT R2 V Programmable 1 x VREF 0 75 V p p to 1 5 V p p AGND to 0 2 V 1 0V Internal fixed 1Vp p Rev 0 Page 18 of 28 External Reference An external reference can be used for greater accuracy and temperature stability when required The gain of the AD9481 can also be varied using this configuration A voltage output DAC can be used to set VREE providing for a means to digitally adjust the full scale voltage VREF can be externally set to voltages from 0 75 V to 1 5 V optimum performance is typically obtained at VREF 1 V See the Typical Performance Characteristics section MAY REQUIRE RC FILTER EXTERNAL REFERENCE OR DAC INPUT 05045 036 Figure 35 External Reference Programmable Reference The programmable reference can be used to set a differential input span anywhere between 0 75 V p p and 1 5 V p p by using an external resistor divider The SENSE pin self biases to 0 5 V and the resulting VREF is equal to 0 5 x 1 R1 R2 It is recommended to keep the sum of R1 R2 gt 10 to limit VREF loading for VREF 1 5 V set R1 equal to 7 and R2 equal to 3 5 05045 037 Figure 36 Programmable Reference CLOCKING THE AD9481 Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user A track and hold circuit is essentially a mixer and any noise distortion or timing
31. s 0603 100 20 2 RP1 to RP2 Resistor Pack 100 O Res Array 742C163100JTR 21 4 U3 U5 to U6 U8 Resistor Pack 100 100 O Res Array EXB 38V101JV 22 2 U4 U7 74LVT574 5020 74LVT574WM 23 1 T1 Transformer CD542 ADT1 1WT 24 1 U1 AD8351 MSOP 10 Op Amp 25 1 U2 74VCX86 SO 14 XOR 26 1 U10 ADR510 SOT 23 Voltage Regulator 27 1 U9 VCC6PECL6 VCC6 QAB 250M000 Vectron Crystal 28 1 U12 AD9481 TOFP 44 ADC 29 1 U11 MC100 LVEL16D SO8NB Clock Buffer 30 1 T2 ETC1 1 13 1 1 TX M A COM ETC 1 1 13 31 11 C1 C7 to C9 C16 C20 C30 C31 C38 to C40 Capacitors 0402 x 32 18 R20 to R21 R28 R30 R38 to R41 Resistors 0603 x R48 to R51 R55 to R60 33 16 E98 to E102 E73 to E84 Jumpers Not placed Rev 0 Page 23 of 28 AD9481 PCB SCHEMATICS 00 99090 xova xiva xova xeva xeva xsva xpva xvva xsvd xeva xova xiva xeva ano xiva ud aN5 xova HOLO3NNOO indino ONS YOLOANNOO Nid 08 INO SV 31 3 314 YOLOANNOOD LNdLNO Nid OF 310 aNd xoga xoga xiaa xzaa xead xeaa 8 xeaa xsaa xvaa 80 xsaa aNd xoaa 1 ano YOLOANNOO indino ONS 1115 90 so vo to 55 oo 073 8 73 8 O 13 3193135 835 1 LON XX 31 3404 ATIVIWHON LON X 0 0 11 235 0 911
32. sstalk Coupling onto one channel being driven by a low level 40 dBFS signal when the adjacent interfering channel 15 driven by a full scale signal Differential Analog Input Resistance Differential Analog Input Capacitance and Differential Analog Input Impedance The real and complex impedances measured at each analog input port The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer Differential Analog Input Voltage Range The peak to peak differential voltage that must be applied to the converter to generate a full scale response Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin which is 180 out of phase Peak to peak differential is computed by rotating the inputs phase 180 and taking the peak measurement again The difference is then computed between both peak measurements Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step Effective Number of Bits ENOB ENOB is calculated from the measured SINAD based on the equation assuming full scale input 6 02 ENOB Full Scale Input Power Expressed in dBm Computed using the following equation 2 V FULLSCALE rms ZINPUT Powerguttscate 10 log 0 001 Gain Error Gain error is the difference between the measured and ideal full scale input voltage range of the ADC Harmonic Distortion
33. utput Bit O Channel A LSB 37 AGND Analog Ground 15 DRGND Digital Ground 38 VIN Analog Input Complement 16 DCO Data Clock Output Complement 39 VIN Analog Input True 17 DCO Data Clock Output True 40 AGND Analog Ground 18 DRVDD 3 3VDigital Output Supply 4i AVDD 3 3 V Analog Supply 19 DOB Data Output Bit 0O Channel LSB 42 S3 DCO Enable Select Tie to AVDD for DCO 20 D1B Data Output Bit 1 Channel Active 21 D2B Data Output Bit 2 Channel B 43 DS DOE Complement If Unused Tie to s pua x Hed 44 DS Data Sync True If Unused Tie to DGND 24 D5B Data Output Bit 5 Channel B Rev 0 Page 9 of 28 AD9481 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency as determined by the FFT analysis is reduced by 3 dB Aperture Delay The delay between the 5096 point of the rising edge of the encode command and the instant the analog input is sampled Aperture Uncertainty Jitter The sample to sample variation in aperture delay Clock Pulse Width Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance pulse width low is the minimum time clock pulse should be left in a low state See timing implications of changing ten in the Clocking the AD9481 section At a given clock rate these specifications define an acceptable clock duty cycle Cro
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