ANALOG DEVICES AD7688 English products handbook
Contents
1. CNV I tconv ACQUISITION CONVERSION ACQUISITION tsspicnv 4 SDI CS1 tuspicnv SDI CS2 tsckL SCK 3 1 4 tsckH ten gt j j tospo Figure 39 CS Mode 4 Wire No BUSY Indicator Serial Interface Timing 02973 038 Rev A Page 19 of 28 AD7688 CS MODE 4 WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7688 is connected to an SPI compatible digital host which has an interrupt input and it is desired to keep CNV which is used to sample the analog input independent of the signal used to select the data reading This requirement is particularly important in applications where low jitter on CNV is desired The connection diagram is shown in Figure 40 and the corresponding timing is given in Figure 41 With SDI high a rising edge on CNV initiates a conversion selects the CS mode and forces SDO to high impedance In this mode CNV must be held high during the conversion phase and the subsequent data readback if SDI and CNV are low SDO is driven low Prior to the minimum conversion time SDI could be used to select other SPI devices such as analog multiplexers but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator When the conversion is complete SDO goes from high impedance to low With a pull up on the SDO line this2. eerte 24 Changes to Ordering Guide sse 25 4 05 Revision 0 Initial Version Driver Amplifier Choice etre E 15 Single to Differential Driver sse 15 Voltage Reference Input seen 15 Power Supply ied tt epa p DO Re Rav 15 Supplying the ADC from the Reference sss 16 Digital Interface cote E mete 16 CS MODE 3 Wire No BUSY Indicator 17 CS Mode 3 Wire with BUSY Indicator 18 CS Mode 4 Wire No BUSY Indicator 19 CS Mode 4 Wire with BUSY Indicator 20 Chain Mode No BUSY Indicator sse 21 Chain Mode with BUSY Indicator ses 22 Application Hints ire ntis 23 i r 23 Evaluating the AD7688 s 23 Outline Dimensions ertet tree teta 24 Ordering Guide csset tectae tete ea 25 Rev A Page 2 of 28 SPECIFICATIONS VDD 4 5 V to 5 5 V VIO 2 3 V to VDD Vre VDD Ta 40 C to 85 C unless otherwise noted AD7688 Table 2 Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range IN IN V REF Vrer V Absolute Input Voltage IN IN 0 1 Veer 0 1 V Common Mode Input Range IN IN 0 Vrer 2 Vrer 2 0 1 V Analog Input CMRR fin 250 kHz 65 dB Leakage Current at 25 C Acquisition phase 1 nA Input Impedance See the Analog Input section ACC
3. 12V IF VIO ABOVE 2 5V VIO 0 5V IF VIO BELOW 2 5V 20 8V IF VIO ABOVE 2 5V 0 5V IF VIO BELOW 2 5V 02973 004 Figure 4 Voltage Levels for Timing Rev A Page 6 of 28 AD7688 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5 10 Lead MSOP Pin Configuration AD7688 IN 3 TOP VIEW Not to Scale 02973 005 NOTES 1 FOR THE LFCSP PACKAGE ONLY THE EXPOSED PADDLE MUST BE CONNECTED TO GND Figure 6 10 Lead QFN LFCSP Pin Configuration 02973 006 Table 7 Pin Function Descriptions Pin No Mnemonic Type Function 1 REF Al Reference Input Voltage The REF range is from 0 5 V to VDD It is referred to the GND pin This pin should be decoupled closely to the pin with a 10 uF capacitor 2 VDD P Power Supply 3 IN Al Differential Positive Analog Input 4 IN Al Differential Negative Analog Input 5 GND P Power Supply Ground 6 CNV DI Convert Input This input has multiple functions On its leading edge it initiates the conversions and selects the interface mode chain or CS In CS mode it enables the SDO pin when low In chain mode the data should be read when CNV is high 7 SDO DO Serial Data Output The conversion result is output on this pin It is synchronized to SCK 8 SCK DI Serial Data Clock Input When the part is selected the conversion result is shifted out by this clock 9 SDI DI Serial Data Input This input provides multiple features It selects the interface mode
4. Table 3 Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0 5 VDD 0 3 V Load Current 500 kSPS REF 5V 100 uA SAMPLING DYNAMICS 3 dB Input Bandwidth 9 MHz Aperture Delay VDD 5V 2 5 ns DIGITAL INPUTS Logic Levels Vit 0 3 0 3 x VIO V 0 7 x VIO VIO 0 3 V li 1 1 lin 1 1 DIGITAL OUTPUTS Data Format Serial 16 bits twos complement Pipeline Delay Conversion results available immediately after completed conversion VoL Isink 500 pA 0 4 V Vou Isource 500 pA VIO 0 3 V POWER SUPPLIES VDD Specified performance 4 5 5 5 V VIO Specified performance 23 VDD 0 3 V VIO Range 1 8 VDD 0 3 V Standby Current VDD and VIO 5 V 25 C 1 50 nA Power Dissipation VDD 5V 100 SPS throughput 3 75 uW VDD 5 V 100 kSPS throughput 3 75 4 3 mW VDD 5 V 500 kSPS throughput 21 5 mW TEMPERATURE RANGE Specified Performance Tmn to Tmax 40 185 C 1 With all digital inputs forced to VIO or GND as required During acquisition phase 3 Contact sales for extended temperature range Rev A Page 4 of 28 TIMING SPECIFICATIONS AD7688 40 C to 85 C VDD 4 5 V to 5 5 V VIO 2 3 V to 5 5 V or VDD 0 3 V whichever is the lowest unless otherwise stated See Figure 3 and Figure 4 for load conditions Table 4 Parameter Symbol Min Typ Max Unit Conversion Time CNV Rising Edge to Data Available tconv 0 5 1 6 Hs Acquisition Time taco 400 ns Time Between Conversions
5. has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins as explained in the Layout section When REF is driven by a very low impedance source for example a reference buffer using the AD8031 or the AD8605 a 10 X5R 0805 size ceramic chip capacitor is appropriate for optimum performance If an unbuffered reference voltage is used the decoupling value depends on the reference used For instance a 22 uF X5R 1206 size ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference If desired smaller reference decoupling capacitor values down to 2 2 can be used with a minimal impact on performance especially DNL Regardless there is no need for an additional lower value ceramic decoupling capacitor for example 100 nF between the REF and GND pins POWER SUPPLY The AD7688 is specified at 4 5 V to 5 5 V It has unlike other low voltage converters a low enough noise to design a 16 bit resolution system with low supply and respectable performance It uses two power supply pins a core supply VDD and a digital input output interface supply VIO VIO allows direct interface with any logic between 1 8 V and VDD To reduce the supplies needed the VIO and VDD can be tied together The AD7688 is independent of power supply sequencing between VIO and VDD Additionally it is very insensitive t
6. Page 21 of 28 AD7688 CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy chain multiple AD7688s on a 3 wire serial interface while providing a BUSY indicator This feature is useful for reducing component count and wiring connections for example in isolated multiconverter applications or for systems with a limited interfacing capacity Data readback is analogous to clocking a shift register A connection diagram example using three AD7688s is shown in Figure 44 and the corresponding timing is given in Figure 45 When SDI and CNV are low SDO is driven low With SCK high a rising edge on CNV initiates a conversion selects the chain mode and enables the BUSY indicator feature In this mode CNV is held high during the conversion phase and the subsequent data readback When all ADCs in the chain have completed their conversions the nearend ADC ADC C in Figure 44 SDO is driven high This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host The AD7688 then enters the acquisition phase and powers down The data bits stored in the internal shift register are then clocked out MSB first by subsequent SCK falling edges For each ADC SDI feeds the input of the internal shift register and is clocked by the SCK falling edge Each ADC in the chain outputs its data MSB first and 16 x N 1 clocks are required to readback the N ADCs Although the rising edge can b
7. high until the maximum conversion time to avoid the generation of the BUSY signal indicator When the conversion is complete the AD7688 enters the acquisition phase and powers down Each ADC result can be read by This mode is usually used when multiple AD7688s are connected to an SPI compatible digital host A connection diagram example using two AD7688s is shown in bringing low its SDI input which consequently outputs the MSB Figure 38 and the corresponding timing is given in Figure 39 onto SDO The remaining data bits are then clocked by With SDI high a rising edge on CNV initiates a conversion subsequent SCK falling edges The data is valid on both SCK selects the CS mode and forces SDO to high impedance In this edges Although the rising edge can be used to capture the data mode CNV must be held high during the conversion phase and a digital host using the SCK falling edge allows a faster reading the subsequent data readback if SDI and CNV are low SDO is rate provided it has an acceptable hold time After the 16th SCK falling edge or when SDI goes high whichever is earlier SDO driven low Prior to the minimum conversion time SDI could returns to high impedance and another AD7688 can be read be used to select other SPI devices such as analog multiplexers but SDI must be returned high before the minimum conversion DIGITAL HOST 02973 037 Figure 38 CS Mode 4 Wire No BUSY Indicator Connection Diagram
8. in Figure 33 VDD AD7688 02973 032 1OPTIONAL REFERENCE BUFFER AND FILTER Figure 33 Example of Application Circuit DIGITAL INTERFACE Though the AD7688 has a reduced number of pins it offers flexibility in its serial interface modes The AD7688 when in CS mode is compatible with SPI QSPI digital hosts and DSPs e g Blackfin ADSP BF53x or ADSP 219x This interface can use either 3 wire or 4 wire A 3 wire interface using the CNV SCK and SDO signals minimizes wiring connections useful for instance in isolated applications A 4 wire interface using the SDI CNV SCK and SDO signals allows CNV which initiates the conversions to be independent of the readback timing SDI This is useful in low jitter sampling or simultaneous sampling applications The AD7688 when in chain mode provides a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register The mode in which the part operates depends on the SDI level when the CNV rising edge occurs The CS mode is selected if SDI is high and the chain mode is selected if SDI is low The SDI hold time is such that when SDI and CNV are connected together the chain mode is always selected In either mode the AD7688 offers the flexibility to optionally force a start bit in front of the data bits This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigg
9. phase and powers down When CNV goes low the MSB is output onto SDO The remaining data bits are then clocked by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used 02973 033 Figure 34 CS Mode 3 Wire No BUSY Indicator Connection Diagram SDI High SDI 1 ra gt 39 j CNV taca ACQUISITION CONVERSION SCK tois tuspo tsckH tEN tpspo Figure 35 CS Mode 3 Wire No BUSY Indicator Serial Interface Timing SDI High 02973 034 Rev A Page 17 of 28 AD7688 cs MODE 3 WIRE WITH BUSY INDICATOR a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time After the optional 17th SCK falling edge or when CNV goes high whichever is earlier SDO returns to high impedance This mode is usually used when a single AD7688 is connected to an SPI compatible digital host having an interrupt input The connection diagram is shown in Figure 36 and the Inc Mr ARI RR If multiple AD7688s are selected at the same time the SDO corresponding timing is given in Figure 37 output pin handles this contention without damage or induced With SDI tied to VIO a rising edge on CNV initiates a latch up Meanwhile it is recommended to keep this contention conversion selects the CS mode and forces SDO to high as short as p
10. the EVAL CO Rev A Page 25 of 28 TROL BRDx for evaluation demonstration purposes 3 The EVAL CONTROL BRD2 and EVAL CONTROL BRD3 allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators AD7688 NOTES Rev A Page 26 of 28 AD7688 NOTES Rev A Page 27 of 28 AD7688 NOTES 2007 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D02973 0 2 11 A DEVICES www analo g com Rev A Page 28 of 28
11. transition can be used as an interrupt signal to initiate the data readback controlled by the digital host The AD7688 then enters the acquisition phase and powers down The data bits are then clocked out MSB first by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used to capture the data a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time After the optional 17th SCK falling edge or SDI going high whichever is earlier the SDO returns to high impedance 02973 039 CNV a tconv 1 4 taca gt ACQUISITION CONVERSION ACQUISITION tsspicnv SDI tuspicnv gt SCK tuspo tpspo tois ten tsck n 02973 040 Figure 41 CS Mode 4 Wire with BUSY Indicator Serial Interface Timing Rev A Page 20 of 28 CHAIN MODE NO BUSY INDICATOR This mode can be used to daisy chain multiple AD7688s on a 3 wire serial interface This feature is useful for reducing component count and wiring connections for example in isolated multiconverter applications or for systems with a limited interfacing capacity Data readback is analogous to clocking a shift register A connection diagram example using two AD7688s is shown in Figure 42 and the corresponding timing is given in Figure 43 When SDI and CNV are low SDO is driven low With SC
12. 0 000 samples per second 500 kSPS and powers down between conversions When operating at 100 SPS for example it consumes 3 75 yW typically ideal for battery powered applications The AD7688 provides the user with an on chip track and hold and does not exhibit any pipeline delay or latency making it ideal for multiple multiplexed channel applications The AD7688 is specified from 4 5 V to 5 5 V and can be interfaced to any of the 1 8 V to 5 V digital logic family It is housed in a 10 lead MSOP or a tiny 10 lead QFN LFCSP that combines space savings and allows flexible configurations It is pin for pin compatible with the AD7685 AD7686 and AD7687 CONVERTER OPERATION The AD7688 is a successive approximation ADC based on a charge redistribution DAC Figure 24 shows the simplified schematic of the ADC The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors which are connected to the two comparator inputs During the acquisition phase terminals of the array tied to the comparator s input are connected to GND via SW and SW All independent switches are connected to the analog inputs Thus the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN and IN inputs When the acquisition phase is complete and the CNV input goes high a conversion phase is initiated When the conversion phase begins SW and SW are opened first The two capacitor arrays are then disconn
13. ANALOG DEVICES 16 Bit 1 5 LSB INL 500 kSPS PulSAR Differential ADC in MSOP QFN AD7688 APPLICATION DIAGRAM 0 5V TO5V 5V FEATURES 16 bit resolution with no missing codes Throughput 500 kSPS INL 0 4 LSB typ 1 5 LSB max 23 ppm of FSR Dynamic range 96 5 dB SNR 95 5 dB 20 kHz THD 118 dB 20 kHz True differential analog input range Vrer OV to Vrer with Vrer up to VDD on both inputs No pipeline delay Single supply 5 V operation with 1 8 V 2 5 V 3 V 5 V logic interface Serial interface SPI QSPI MICROWIRE DSP compatible Daisy chain multiple ADCs and BUSY indicator Power dissipation 3 75 mW 5 V 100 kSPS 3 75 pW 5 V 100 SPS Standby current 1 nA 10 lead MSOP MSOP 8 size and 3mm x 3 mm QFN LFCSP SOT 23 size Pin for pin compatible with AD7685 AD7686 and AD7687 APPLICATIONS Battery powered equipment Data acquisitions Instrumentation Medical instruments Process controls 1 5 POSITIVE INL 0 31LSB NEGATIVE INL 0 39LSB a o d a z 0 16384 32768 49152 65535 CODE Figure 1 Integral Nonlinearity vs Code Rev Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or oth
14. B 2nd HARM 125dB 80 3rd HARM 119dB a 5 100 5 o 120 140 160 8 180 8 0 25 50 75 100 125 150 175 200 225 25 FREQUENCY kHz Figure 9 FFT Plot Rev A Page 9 of 28 AD7688 POSITIVE DNL 0 37LSB NEGATIVE DNL 0 21LSB 16384 32768 CODE 49152 Figure 10 Differential Nonlinearity vs Code 2973 009 6553 CODE IN HEX 02973 010 Figure 11 Histogram of a DC Input at the Code Transition 100 INPUT LEVEL dB Figure 12 SNR vs Input Level 02973 011 AD7688 SNR S N D dB SNR dB S N D dB NNNM HENN 70 2 3 2 7 3 1 3 5 3 9 90 85 4 3 4 7 5 1 REFERENCE VOLTAGE V T ao m 5 2 5 o _ 2 7 a E 14 0 5 S 13 0 Figure 13 SNR S N D and ENOB vs Reference Voltage 4 7 REFERENCE VOLTAGE V Figure 16 THD SFDR vs Reference Voltage bd a TEMPERATURE C Figure 14 SNR vs Temperature THD dB 130 02973 013 90 VREF 5V 100 110 ID 5 35 15 5 25 45 65 85 105 TEMPERATURE C Figure 17 THD vs Temperature 12 VREF 5V 1dB 100 60 VREF 5V 10dB 95 70 90 80 y 85 x 5 90 a VREF 5V 1dB E 80 100 75 110 70 EE 3 120 0 50 100 150 200 0 FREQUENCY kHz F
15. Figure 48 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters 3 10 H 3 00 SQ 2 90 0 50 BSC PIN 1 INDEX 1 74 AREA 1 64 1 49 N 1 TOP VIEW 4 BOTTOM VIEW INDICATOR FOR PROPER CONNECTION OF 0 05 MAX THE EXPOSED PAD REFER TO 0 80 0 75 002 NOM THE PIN CONFIGURATION AND 0 70 d t FUNCTION DESCRIPTIONS SEATING 0 30 PLANE 4 0 20 REF Figure 49 10 Lead Lead Frame Chip Scale Package QFN 1 WD 3mm x 3 mm Body Very Very Thin Dual Lead CP 10 9 Dimensions shown in millimeters Rev A Page 24 of 28 SECTION OF THIS DATA SHEET 121009 A AD7688 ORDERING GUIDE Integral Transport Media Package Package Model 2 3 Nonlinearity Temperature Range Quantity Description Option Branding AD7688BRMZ 1 5 LSB max 40 C to 85 C Tube 50 10 Lead MSOP RM 10 C3K AD7688BRMZRL7 1 5 LSB max 40 C to 85 C Reel 1 000 10 Lead MSOP RM 10 C3K AD7688BCPZRL 1 5 LSB max 40 C to 85 C Reel 5 000 10 Lead QFN LFCSP_WD CP 10 9 C04 AD7688BCPZRL7 1 5 LSB max 40 C to 85 C Reel 1 500 10 Lead QFN LFCSP_WD CP 10 9 04 EVAL AD7688CBZ Evaluation Board EVAL CONTROL BRD2Z EVAL CONTROL BRD3Z Controller Board Controller Board 1 Z RoHS Compliant Part denotes RoHS compliant product may be top or bottom marked 2 The EVAL AD7688CB be used as a standalone evaluation board or in conjunction with
16. K low a rising edge on CNV initiates a conversion selects the chain mode and disables the BUSY indicator In this mode CNV is held high during the conversion phase and the subsequent data readback When the conversion is complete the MSB is output CNV 8014 0 CNV AD7688 onto SDO and the AD7688 enters the acquisition phase and powers down The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges For each ADC SDI feeds the input of the internal shift register and is clocked by the SCK falling edge Each ADC in the chain outputs its data MSB first and 16 x N clocks are required to readback the N ADCs The data is valid on both SCK edges Although the rising edge can be used to capture the data a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7688s in the chain provided the digital host has an acceptable hold time The maximum conversion rate may be reduced due to the total readback time For instance with a 3 ns digital host set up time and 3 V interface up to four AD7688s running at a conversion rate of 360 kSPS can be daisy chained on a 3 wire port CONVERT DIGITAL HOST DATA IN 02973 041 ACQUISITION SDO SDlg ACQUISITION o gt L D gt gt Aa 02973 042 Figure 43 Chain Mode No BUSY Indicator Serial Interface Timing Rev A
17. URACY No Missing Codes 16 Bits Differential Linearity Error 1 0 4 1 LSB Integral Linearity Error 1 5 0 4 41 5 LSB Transition Noise REF VDD 5V 0 4 LSB Gain Error Tmn to Tmax 2 6 LSB Gain Error Temperature Drift 0 3 ppm C Zero Error Tmn to Tmax 0 1 1 6 mV Zero Temperature Drift 0 3 ppm C Power Supply Sensitivity VDD 5V 5 0 05 LSB THROUGHPUT Conversion Rate 0 500 kSPS Transient Response Full scale step 400 ns AC ACCURACY Dynamic Range Veer 5 95 8 96 5 dB Signal to Noise fin 20 kHz Veer 5 V 94 95 5 dB fin 20 kHz Vrer 5 V 92 5 dB Spurious Free Dynamic Range fin 20 kHz 118 dB Total Harmonic Distortion fin 20 kHz 118 dB Signal to Noise Distortion fin 20 kHz Vae 5 V 93 5 95 dB fin 20 kHz Veer 5 V 60 dB input 36 5 dB Intermodulation Distortion 115 dB LSB means least significant bit With the 5 V input range one LSB is 152 6 uV See the Terminology section These specifications do include full temperature range variation but do not include the error contribution from the external reference 3All specifications in dB are referred to a full scale input FS Tested with an input signal at 0 5 dB below full scale unless otherwise specified 4 fini 21 4 kHz fio 18 9 kHz each tone at 7 dB below full scale Rev A Page 3 of 28 AD7688 VDD 4 5 V to 5 5 V VIO 2 3 V to VDD Vre VDD Ta 40 C to 85 C unless otherwise noted
18. an be used to protect the part 02973 026 Figure 27 Equivalent Analog Input Circuit The analog input structure allows the sampling of the true differential signal between IN and IN By using these differential inputs signals common to both inputs are rejected as shown in Figure 28 which represents the typical CMRR over frequency 80 VDD 5V v tc o 60 1 10 100 1000 10000 FREQUENCY kHz Figure 28 Analog Input CMRR vs Frequency During the acquisition phase the impedance of the analog inputs IN or IN can be modeled as a parallel combination of capacitor Crm and the network formed by the series connection of and Cm is primarily the pin capacitance Rw is typically 600 and is a lumped component made up of some serial resistors and the on resistance of the switches Cin is typically 30 pF and is mainly the ADC sampling capacitor During the conversion phase where the switches are opened the input impedance is limited to Ri and Cis make 1 pole low pass filter that reduces undesirable aliasing effects and limits the noise When the source impedance of the driving circuit is low the AD7688 can be driven directly Large source impedances significantly affect the ac performance especially total harmonic distortion THD The dc performances are less sensitive to the input impedance The maximum s
19. applications the driver should have a THD performance commensurate with the AD7688 Figure 18 shows the THD vs frequency that the driver should exceed e For multichannel multiplexed applications the driver amplifier and the AD7688 analog input circuit must settle for a full scale step onto the capacitor array at a 16 bit level 0 001596 15 ppm In the amplifier s data sheet settling at 0 196 to 0 0196 is more commonly specified This could differ significantly from the settling time at a 16 bit level and should be verified prior to driver selection Table 9 Recommended Driver Amplifiers Amplifier Typical Application AD8021 Very low noise and high frequency AD8022 Low noise and high frequency OP184 Low power low noise and low frequency AD8605 AD8615 5Vsingle supply low power AD8519 Small low power and low frequency AD8031 High frequency and low power AD7688 SINGLE TO DIFFERENTIAL DRIVER For applications using a single ended analog signal either bipolar or unipolar a single ended to differential driver allows for a differential input into the part The schematic is shown in Figure 30 When provided a single ended input signal this configuration produces a differential Vrer with midscale at Vrer 2 ANALOG INPUT o 10V 5V VREF REF AD7688 02973 029 Figure 30 Single Ended to Differential Driver Circuit VOLTAGE REFERENCE INPUT The AD7688 voltage reference input
20. ast one ground plane should be used It could be common or split between the digital and analog sections In the latter case the planes should be joined underneath the AD7688s 02973 045 The AD7688 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances This is done by placing the reference decoupling ceramic capacitor close to and ideally right up against the REF and GND pins and connecting it with wide low impedance traces Finally the power supplies VDD and VIO of the AD7688 should be decoupled with ceramic capacitors typically 100 nF placed close to the AD7688 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines An example of layout following these rules is shown in Figure 46 and Figure 47 EVALUATING THE AD7688 S PERFORMANCE Other recommended layouts for the AD7688 are outlined in the documentation of the evaluation board for the AD7688 EVAL AD7688 The evaluation board package includes a fully assembled and tested evaluation board documentation CREF CUDD CUIO Figure 47 Example of Layout of the AD7688 Bottom Layer 02973 046 and software for controlling the board from a PC via the EVAL CONTROL BRD3 Rev A Page 23 of 28 AD7688 OUTLINE DIMENSIONS gt LA 13 0 40 091709 COMPLIANT TO JEDEC STANDARDS 187
21. e FSR 1 LSB 4 999847 V 7FFF Midscale 1 LSB 152 6 uV 0001 Midscale 0v 0000 Midscale 1 LSB 152 6 uV FFFF FSR 1 LSB 4 999847 V 8001 FSR 5V 8000 t This is also the code for an overranged analog input Vi Vin above Veer Vann 2 This is also the code for an underranged analog input V Vin below VreF VREFO VREF TO 00 O 1 8V TO VDD REF VDD VIO 3 OR 4 WIRE INTERFACES 1SEE REFERENCE SECTION FOR REFERENCE SELECTION 2Crer IS USUALLY A 10 CERAMIC CAPACITOR X5R 3SEE DRIVER AMPLIFIER CHOICE SECTION 4OPTIONAL FILTER SEE ANALOG INPUT SECTION 5SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE 02973 025 Figure 26 Typical Application Diagram with Multiple Supplies Rev A Page 13 of 28 AD7688 ANALOG INPUT Figure 27 shows an equivalent circuit of the input structure of the AD7688 The two diodes D1 and D2 provide ESD protection for the analog inputs IN and IN Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0 3 V because this causes these diodes to begin to forward bias and start conducting current These diodes can handle a forward biased current of 130 mA maximum For instance these conditions could eventually occur when the input buffer s U1 supplies are different from VDD In such a case an input buffer with a short circuit current limitation c
22. e Ratio SNR SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency excluding harmonics and dc The value for SNR is expressed in dB Signal to Noise Distortion Ratio S N D S N D is the ratio of rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for S N D is expressed in dB Aperture Delay Aperature delay is the measure of the acquisition performance It is the time between the rising edge of the CNV input and when the input signal is held for a conversion Transient Response It is the time required for the ADC to accurately acquire its input after a full scale step function was applied Rev A Page 8 of 28 TYPICAL PERFORMANCE CHARACTERISTICS INL LSB COUNTS AMPLITUDE dB of Full Scale 1 5 POSITIVE INL 0 31LSB NEGATIVE INL 0 39LSB y 7 z a 0 16384 32768 49152 65535 CODE Figure 7 Integral Nonlinearity vs Code 300000 VDD REF 5V 250000 200000 2 150000 z 5 100000 50000 0 S 6F 70 71 72 73 74 75 CODE IN HEX Figure 8 Histogram of a DC Input at the Code Center 0 16384 POINT FFT 20 VDD REF 5V 500KSPS Fiy 2kHz Ex SNR 95 6dB THD 117 7dB 60 SFDR 117 9d
23. e used to capture the data a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7688s in the chain provided the digital host has an acceptable hold time For instance with a 3 ns digital host setup time and 3 V interface up to four AD7688s running at a conversion rate of 360 kSPS can be daisy chained to a single 3 wire port CONVERT DIGITAL HOST DATA IN 02973 043 Figure 44 Chain Mode with BUSY Indicator Connection Diagram teye CNV 5014 ACQUISITION SDO SDlg SDOg SDlc lpspospi gt ipspospi I ACQUISITION tpspospi tpspospi 02973 044 Figure 45 Chain Mode with BUSY Indicator Serial Interface Timing Rev A Page 22 of 28 AD7688 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7688 should be designed so that the analog and digital sections are separated and confined to certain areas of the board The pinout of the AD7688 with all its analog signals on the left side and all its digital signals on the right side eases this task Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7688 is used as a shield Fast switching signals such as CNV or clocks should never run near analog signal paths Crossover of digital and analog signals should be avoided At le
24. ead MSOP or a 10 lead QFN LFCSP with operation specified from 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 2007 2011 Analog Devices Inc All rights reserved www analog com AD7688 TABLE OF CONTENTS Features ore eoe LL uer 1 Applications Lunae dei en e eri eR CURIE 1 Application Dia gran seekers itte edente eerte 1 General Description iiras aK r a 1 Revision HIStory eese REISEN a E R E cues 2 Specifications ieii epit te rt rere 3 Timing Specifications scas ccssss cssssiereissssneesiosseonsssitenesserinecdssnionnsessbes 5 Absolute Maximum Ratings essent 6 Thermal Resistance seen 6 ESD Cautiori iiy ERREUR ERE 6 Pin Configuration and Function 7 Terminology 3i eee inepti piter inler ese les ette 8 Typical Performance Characteristics sss 9 Circuit 4 12 Converter Operation sse tees 12 Typical Connection Diagram seseeeeeeee 13 Amalog Input itti tiet 14 REVISION HISTORY 2 11 Rev 0 to Rev A Deleted QFN in Development Throughout Changes to Table 5 6 Added Thermal Resistance Section and Table 6 6 Changes to Figure 6 and Table 7 sse 7 Updated Outline Dimensions
25. ected from the inputs and connected to the GND input Therefore the differential voltage between the inputs IN and IN captured at the end of the acquisition phase is applied to the comparator inputs causing the comparator to become unbalanced By switching each element of the capacitor array between GND and REF the comparator input varies by binary weighted voltage steps Vrer 2 Vrer 4 Vrer 65536 The control logic toggles these switches starting with the MSB in order to bring the comparator back into a balanced condition After the completion of this process the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator Because the AD7688 has an on board conversion clock the serial clock SCK is not required for the conversion process Rev A Page 12 of 28 Transfer Functions AD7688 TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7688 is shown in Figure 26 shows an example of the recommended connection Figure 25 and Table 8 011 111 011 110 011 101 ADC CODE TWOS COMPLEMENT 100 010 100 001 100 000 FSR FSR 1 LSB FSR 0 5 LSB ANALOG INPUT diagram for the AD7688 when multiple supplies are available FSR 1 LSB FSR 1 5 LSB 02973 024 Figure 25 ADC Ideal Transfer Function Table 8 Output Codes and Ideal Input Voltages Analog Input Description Vrer 5 Digital Output Cod
26. er the data reading Otherwise without a BUSY indicator the user must time out the maximum conversion time prior to readback The BUSY indicator feature is enabled as In the CS mode if CNV or SDI is low when the ADC conversion ends Figure 37 and Figure 41 Inthe chain mode if SCK is high during the CNV rising edge Figure 45 Rev A Page 16 of 28 AD7688 CS MODE 3 WIRE NO BUSY INDICATOR to capture the data a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time After the 16th SCK falling edge or when CNV goes high whichever is earlier SDO returns to high impedance This mode is usually used when a single AD7688 is connected to an SPI compatible digital host The connection diagram is shown in Figure 34 and the corresponding timing is given in Figure 35 CONVERT With SDI tied to VIO a rising edge on CNV initiates a conversion selects the CS mode and forces SDO to high DIGITAL HOST impedance Once a conversion is initiated it continues to VIO completion irrespective of the state of CNV For instance it QsD AD7688 sDoQ DATA IN could be useful to bring CNV low to select other SPI devices such as analog multiplexers but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator When the conversion is complete the AD7688 enters the acquisition
27. erwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 1 8V TO VDD 3 OR 4 WIRE INTERFACE SPI DAISY CHAIN CS 02973 002 Figure 2 Table 1 MSOP QFN LFCSP SOT 23 16 Bit PulSAR ADC Type 100 kSPS 250 kSPS 500 kSPS True Differential AD7684 AD7687 AD7688 Pseudo AD7683 AD7685 AD7686 Differential Unipolar AD7694 Unipolar AD7680 GENERAL DESCRIPTION The AD7688 is a 16 bit charge redistribution successive approximation analog to digital converter ADC that operates from a single 5 V power supply VDD It contains a low power high speed 16 bit sampling ADC with no missing codes an internal conversion clock and a versatile serial interface port The part also contains a low noise wide bandwidth short aperture delay track and hold circuit On the CNV rising edge it samples the voltage difference between IN and IN pins The voltages on these pins usually swing in opposite phase between 0 V and REE The reference voltage REF is applied externally and can be set up to the supply voltage Its power scales linearly with throughput The SPI compatible serial interface also features the ability using the SDI input to daisy chain several ADCs on a single 3 wire bus and provides an optional BUSY indicator It is compatible with 1 8 V 2 5 V 3 V or 5 V logic using the separate supply VIO The AD7688 is housed in a 10 l
28. igure 15 S N D vs Frequency Rev A Page 10 of 28 VREF 5V 1 50 100 150 FREQUENCY kHz Figure 18 THD vs Frequency 20 02973 015 02973 016 02973 017 OPERATING CURRENT uA POWER DOWN CURRENT nA OPERATING CURRENT uA AD7688 1000 750 500 250 OFFSET GAIN ERROR LSB 02973 018 55 35 15 5 25 45 65 85 105 SUPPLY V TEMPERATURE C Figure 19 Operating Currents vs Supply Figure 22 Offset and Gain Error vs Temperature 1000 750 T amp V 85 C 500 i i Q o a eo a 250 0 8 5 55 35 15 5 25 45 65 85 105 12 TEMPERATURE C SDO CAPACITIVE LOAD pF Figure 23 tpspo Delay vs Capacitance Load and Suppl Figure 20 Power Down Currents vs Temperature 9 ee id 1000 750 500 250 02973 020 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 21 Operating Currents vs Temperature Rev A Page 11 of 28 02973 021 02973 022 AD7688 IN 32 768C 16 384C 4c 32 768C 16 3846 REF GND SWITCHES CONTROL BUSY CONTROL Losie 4 OUTPUT CODE SW 02973 023 Figure 24 ADC Simplified Schematic CIRCUIT INFORMATION The AD7688 is a fast low power single supply precise 16 bit ADC using a successive approximation architecture The AD7688 is capable of converting 50
29. n terms of resolution for which no missing codes are guaranteed Zero Error It is the difference between the ideal midscale voltage that is 0 V from the actual voltage producing the midscale output code that is 0 LSB Gain Error The first transition from 100 00 to 100 01 should occur at a level LSB above nominal negative full scale 4 999924 V for the 5 V range The last transition from 011 10 to 011 11 should occur for an analog voltage 1 LSB below the nominal full scale 4 999771 V for the 5 V range The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels Spurious Free Dynamic Range SFDR SFDR is the difference in decibels dB between the rms amplitude of the input signal and the peak spurious signal Effective Number of Bits ENOB ENOB is a measurement of the resolution with a sine wave input It is related to S N D by the following formula ENOB S N D as 1 76 6 02 and is expressed in bits Total Harmonic Distortion THD THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full scale input signal and is expressed in dB Dynamic Range It is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together The value for dynamic range is expressed in dB Signal to Nois
30. o power supply variations over a wide frequency range as shown in Figure 31 which represents PSRR over frequency Rev A Page 15 of 28 AD7688 PSRR dB 02973 030 1 10 100 1000 FREQUENCY kHz Figure 31 PSRR vs Frequency The AD7688 powers down automatically at the end of each conversion phase and therefore the power scales linearly with the sampling rate as shown in Figure 32 This makes the part ideal for low sampling rate even a few Hz and low battery powered applications 1000 VDD T 10 2 o o VIO z lt q fi 01 o 0 001 a 10 100 1000 10000 100000 1000000 SAMPLING RATE SPS Figure 32 Operating Currents vs Sampling Rate SUPPLYING THE ADC FROM THE REFERENCE For simplified applications the AD7688 with its low operating current can be supplied directly using the reference circuit shown in Figure 33 The reference line can be driven by either e The system power supply directly e reference voltage with enough current output capability such as the ADR43x e reference buffer such as the AD8031 which can also filter the system power supply as shown
31. of the ADC as follows Chain mode is selected if SDI is low during the CNV rising edge In this mode SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line The digital data level on SDI is output on SDO with a delay of 16 SCK cycles CS mode is selected if SDI is high during the CNV rising edge In this mode either SDI or CNV can enable the serial output signals when low and if SDI or CNV is low when the conversion is complete the BUSY indicator feature is enabled 10 VIO P Input Output Interface Digital Power Nominally at the same supply as the host interface 1 8 V 2 5 V 3 V or5V EPAD N A For the LFCSP package only the exposed paddle must be connected to GND Analog Input DI Digital Input DO Digital Output P Power and N A not applicable Rev A Page 7 of 28 AD7688 TERMINOLOGY Integral Nonlinearity Error INL It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs LSB before the first code transition Positive full scale is defined as a level 1 LSB beyond the last code transition The deviation is measured from the middle of each code to the true straight line Figure 25 Differential Nonlinearity Error DNL In an ideal ADC code transitions are 1 LSB apart DNL is the maximum deviation from this ideal value It is often specified i
32. ossible to limit extra power dissipation impedance SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV CONVERT Prior to the minimum conversion time CNV could be used to select other SPI devices such as analog multiplexers but CNV DIGITAL HOST must be returned low before the minimum conversion time and VIO held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator When the conversion Ospi AD7688 sDoO P DATA IN is complete SDO goes from high impedance to low With a IRQ pull up on the SDO line this transition can be used as an interrupt signal to initiate the data reading controlled by the CLK digital host The AD7688 then enters the acquisition phase and powers down The data bits are then clocked out MSB first by subsequent SCK falling edges The data is valid on both SCK edges Although the rising edge can be used to capture the data 02973 035 Figure 36 CS Mode 3 Wire with BUSY Indicator Connection Diagram SDI High SDI 1 tcvc 1 CNV F taca gt ACQUISITION 4 CONVERSION ACQUISITION tsck SCK 1 2 15 16 tuspo tsckH tpis o g o 02973 036 Figure 37 CS Mode 3 Wire with BUSY Indicator Serial Interface Timing SDI High Rev A Page 18 of 28 AD7688 CS MODE 4 WIRE NO BUSY INDICATOR time and held
33. ource impedance depends on the amount of THD that can be tolerated The THD degrades as a function of the source impedance and the maximum input frequency as shown in Figure 29 THD dB 100 02973 028 0 25 50 75 FREQUENCY kHz E Figure 29 THD vs Analog Input Frequency and Source Resistance Rev A Page 14 of 28 DRIVER AMPLIFIER CHOICE Although the AD7688 is easy to drive the driver amplifier needs to meet the following requirements e The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7688 Note that the AD7688 has a noise much lower than most of the other 16 bit ADCs and therefore can be driven by a noisier op amp while preserving the same or better system perform ance The noise coming from the driver is filtered by the AD7688 analog input circuit 1 pole low pass filter made by Rw and Cw by the external filter if one is used Because the typical noise of the AD7688 is 53 uV rms the SNR degradation due to the amplifier is 53 53 7 7 New y where fas is the input bandwidth in MHz of AD7688 9 MHz or the cutoff frequency of the input filter if one is used oss 20log N is the noise gain of the amplifier for example 1 in buffer configuration en is the equivalent input noise voltage of the op amp in nV VHz e For ac
34. tcvc 2 us CNV Pulse Width CS Mode tenva 10 ns SCK Period CS Mode tsck 15 ns SCK Period Chain Mode tsck VIO Above 4 5 V 17 ns VIO Above 3 V 18 ns VIO Above 2 7 V 19 ns VIO Above 2 3 V 20 ns SCK Low Time 7 ns SCK High Time 7 ns SCK Falling Edge to Data Remains Valid tuspo 5 ns SCK Falling Edge to Data Valid Delay tpspo VIO Above 4 5 V 14 ns VIO Above 3V 15 ns VIO Above 2 7 V 16 ns VIO Above 2 3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid CS Mode ten VIO Above 4 5 V 15 ns VIO Above 2 7 V 18 ns VIO Above 2 3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance CS Mode tois 25 ns SDI Valid Setup Time from CNV Rising Edge CS Mode tsspicNv 15 ns SDI Valid Hold Time from CNV Rising Edge CS Mode tuspicnv 0 ns SCK Valid Setup Time from CNV Rising Edge Chain Mode tssckcNv 5 ns SCK Valid Hold Time from CNV Rising Edge Chain Mode tHscKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge Chain Mode tsspisck 3 ns SDI Valid Hold Time from SCK Falling Edge Chain Mode tuspisck 4 ns SDI High to SDO High Chain Mode with BUSY indicator tosposp VIO Above 4 5 V 15 ns VIO Above 2 3 V 26 ns Rev A Page 5 of 28 AD7688 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating Analog Inputs IN IN GND 0 3 V to VDD 0 3 V or 130 mA REF GND 0 3 V to VDD 0 3 V Supply Voltages VDD VIO to GND 0 3 V to 7 V VDD to VIO 7V Digital Inputs to GND 0 3 V to VIO 0 3 V Digital Outpu
35. ts to GND 0 3 V to VIO 0 3 V Storage Temperature Range 65 C to 150 C Junction Temperature 150 C Lead Temperature Range JEDEC J STD 20 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 6 Thermal Resistance Package Type Unit 10 Lead QFN LFCSP 48 7 2 96 C 10 Lead MSOP 200 44 C 1 See the Analog Input section TO SDO ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy 4 may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality 1 4V 02973 003 Figure 3 Load Circuit for Digital Interface Timing 30 VIO toELay T 2V OR VIO 0 5V1 g 2V OR VIO 0 5V1 0 8V OR 0 5V2 0 8V 0 5V2 70
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