ANALOG DEVICES AD7322 English products handbook
Contents
1. The power consumption of the AD7322 varies with throughput rate The static power consumed by the AD7322 is very low and a significant power savings can be achieved as the throughput ur SGK rate is reduced Figure 48 and Figure 49 shows the power vs throughput rate for the AD7322 at a Vcc of 3 V and 5 V M Ww respectively Both plots clearly show that the average power s consumed by the AD7322 is greatly reduced as the sample vi frequency is reduced This is true whether a fixed SCLK value is E used or if it is scaled with the sampling frequency Figure 48 and gt Figure 49 show the power consumption when operating in Voc 5V normal mode for a fixed 20 MHz SCLK and a variable SCLK Voo Vas V that scales with the sampling frequency INTERNAL REFERENCE 43 0 100 200 300 400 500 600 700 800 900 1000 2 THROUGHPUT RATE kHz 3 i Figure 49 Power vs Throughput Rate with 5 V Vcc 20MHz SCLK x VARIABLE SCLK Ww z 9 e Ww B a a 2 Voc 3V VpplVss 12V Ta 25 C INTERNAL REFERENCE 0 0 100 200 300 400 500 600 700 800 900 1000 1100 THROUGHPUT RATE kSPS Figure 48 Power vs Throughput Rate with 3 V Vcc 04863 052 Rev A Page 29 of 36 AD7322 SERIAL INTERFACE Figure 50 shows the timing diagram for the serial interface of the AD7322 The serial clock applied to the SCLK pin provides the conversion clock and controls the transfer of2. 2fa fb fa 2fb and fa 2fb The AD7322 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used In this case the second order terms are usually distanced in frequency from the original sine waves whereas the third order terms are usually at a frequency close to the input frequencies As a result the second and third order terms are specified separately The calculation of the intermodulation distortion is per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels PSR Power Supply Rejection Variations in power supply affect the full scale transition but not the linearity of the converter Power supply rejection is the maximum change in the full scale transition point due to a change in power supply voltage from the nominal value see the Typical Performance Characteristics section CMRR Common Mode Rejection Ratio CMRR is defined as the ratio of the power in the ADC output at full scale frequency f to the power of a 100 mV sine wave applied to the common mode voltage of the Vint and Vm frequency fs as CMRR dB 10 log Pf Pf where Pf is the power at frequency f in the ADC output and Pfs is the power at frequency fs in the ADC output see Figure 17 Rev A Page 14 of 36 THEORY OF OPERATION CIRCUIT INFORMATION The AD732
3. O Vino Voo Vcc AD73221 Vss V 04863 026 ADDITIONAL PINS OMITTED FOR CLARITY Figure 33 Single Ended Mode Typical Connection Diagram True Differential Mode The AD7322 can have a total of one true differential analog input pair Differential signals have some benefits over single ended signals including better noise immunity based on the devices common mode rejection and improvements in distortion performance Figure 34 defines the configuration of the true differential analog inputs of the AD7322 NOTES 1 Viy REFERS TO Vin AND Viy REFERS TO Vi TADDITIONAL PINS OMITTED FOR CLARITY 04863 027 Figure 34 True Differential Inputs The amplitude of the differential signal is the difference between the signals applied to the Vm and Vm inputs in each differential pair Vint Vis Vi and Vm should be simultaneously driven by two signals of equal amplitude dependent on the input range selected that are 180 out of phase Assuming the 4 x Vrer mode the amplitude of the differential signal is 20 V to 20 V p p 2 x 4 x Vrer regardless of the common mode The common mode is the average of the two signals Vint Vw 2 and is therefore the voltage on which the two input signals are centered This voltage is set up externally and its range varies with reference voltage As the reference voltage increases the common mode range decreases When driving the differential inputs with an amplifier
4. A dc input is applied to the Vm input The voltage applied to this input provides an offset for the Vin input from ground or a pseudo ground Pseudo differential inputs separate the analog input signal ground from the ADC ground allowing cancellation of dc common mode voltages Figure 39 shows the AD7322 configured in pseudo differential mode When a conversion takes place the pseudo ground corresponds to Code 4096 and the maximum amplitude corresponds to Code 4095 AD7322 Vss O Vin O Y NOTES 1 Vint REFERS TO VjyO AND Vn REFERS TO Va TADDITIONAL PINS OMITTED FOR CLARITY 04863 028 Figure 39 Pseudo Differential Inputs Figure 40 and Figure 41 show the typical voltage range on the Vn input for the different analog input ranges when configured in the pseudo differential mode For example when the AD7322 is configured to operate in pseudo differential mode and the 5 V range is selected with 16 5 V Vpp Vss supplies and 5 V Vcc the voltage on the Vm input can vary from 6 5 V to 6 5 V Rev A Page 19 of 36 AD7322 5V RANGE 5V RANGE 2 5V RANGE PSEUDO INPUT VOLTAGE RANGE V OV TO 10V OV TO 10V Ver 5V RANGE RANGE cc Vrer 2 5V 04863 039 16 5V Vpp Vss W 12V Vpp Vss Figure 40 Pseudo Input Range with Vcc 5 V 5V RANGE 5V RANGE 2 5V 10V RANGE RANGE OV TO 10V OV TO 10V RANGE RANGE PSEUDO I
5. The data stream consists of two leading zero bits a channel identification bit the sign bit and 12 bits of conversion data The data is provided MSB first see the Serial Interface section 14 SCLK Serial Clock Logic Input A serial clock input provides the SCLK used for accessing the data from the AD7322 This clock is also used as the clock source for the conversion process Rev A Page 8 of 36 TYPICAL PERFORMANCE CHARACTERISTICS SNR dB DNL ERROR LSB 20 4096 POINT FFT Vcc Vprive 5V Vpp Vss 15V Ta 25 C INT EXT 2 5V REFERENCE 10V RANGE fin 50kHz SNR 77 30dB SINAD 76 85dB THD 86 96dB SFDR 88 22dB 150 200 250 300 FREQUENCY kHz Figure 4 FFT True Differential Mode 350 400 450 4096 POINT FFT Vcc Vpnive 5V Vpp Vss 15V Ta 25 C INT EXT 2 5V REFERENCE 10V RANGE fin 50kHz SNR 74 67dB SINAD 74 03dB THD 82 68dB SFDR 85 40dB 500 150 200 250 300 FREQUENCY kHz Figure 5 FFT Single Ended Mode 350 400 450 500 di nd TPT Vcc Vprive 5V Ta 25 C Vpp Vss 15V 512 INT EXT 2 5V REFERENCE 10V RANGE DNL 0 72LSB DNL 0 22LSB 1024 2048 3072 4096 5120 6144 7168 1536 2560 3584 4608 5632 6656 7680 CODE Figure 6 Typical DNL True Differential Mode WON YA du dan Lali 8192 04863 004 04863 00
6. see Figure 44 This sequence begins by converting on Channel 0 and ends with a final channel selected by Bit ADDO in the control register To operate the AD7322 in this mode set Seq1 to 1 and Seq2 to 0 and then select the final channel in the sequence by programming Bit ADDO in the control register POWER ON DIN WRITE TO RANGE REGISTER TO SELECT THE RANGE FOR THE ANALOG INPUT CHANNELS DOUT CONVERSION RESULT FROM CHANNEL 0 10V RANGE SINGLE ENDED MODE AD7322 When the control register is configured to operate the AD7322 in this mode the DIN line can be held low or the write bit can be set to 0 To return to traditional multichannel operation a write to the control register to set Seq1 to 0 and Seg2 to 0 is necessary When Seq1 and Seq2 are both set to 0 or when both are set to 1 the AD7322 is configured to operate in traditional multichannel mode where a write to Channel Address Bit ADDO in the control register selects the next channel for conversion DIN WRITE TO CONTROL REGISTER TO SELECT THE FINAL CHANNEL IN THE CONSECUTIVE SEQUENCE SET Seg1 1 AND Seq2 0 SELECT OUTPUT CODING FOR SEQUENCE DOUT CONVERSION RESULT FROM CHANNEL 0 RANGE SELECTED IN RANGE REGISTER 1 SINGLE ENDED MODE DIN WRITE BIT 0 OR DIN LINE HELD LOWTO CONTINUE TO CONVERT THROUGH THE SEQUENCE OF DIN WRITE TO CONTROL REGISTER TO STOP THE SEQUENCE Seg1 0 Seq2 0 DOUT CONVERSION RESULT FROM CHANNEL I
7. ADDO bit in the control register selects the next channel for conversion Rev A Page 23 of 36 AD7322 RANGE REGISTER The range register is used to select one analog input range per analog input channel This register is a 6 bit write only register with two dedicated range bits for each of the analog input channels Channel 0 and Channel 1 There are four analog input ranges 10 V 5 V 2 5 V and 0 V to 10 V A write to the register select bit to 1 After the initial write to the range register occurs each time an analog input is selected the AD7322 automatically configures the analog input to the appropriate range as indicated by the range register The 10 V input range is selected by default on each analog input channel see Table 13 range register is selected by setting the write bit to 1 and the MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Zero Register Select VinOA VinOB 0 0 VinlA Vin1B o 0 0 0 0 o 0 Table 13 Range Selection VinxA VinxB Description 0 0 This combination selects the 10 V input range on Vinx 0 1 This combination selects the 5 V input range on Vinx 1 0 This combination selects the 2 5 V input range on Vinx 1 1 This combination selects the 0 V to 10 V input range on Vinx Rev A Page 24 of 36 SEQUENCER OPERATION The AD7322 can be configured to convert a sequence of consecutive channels
8. Register 10 V Voo 10 V min Vss 10 V min Vcc 2 7 V to 5 25 V 5 V Voo 5 V min Vss 5 V min Vcc 2 7 V to 5 25 V 2 5 V Voo 5 V min Vss 5 V min Vcc 2 7 V to 5 25 V Oto 10 V Voo 10 V min Vss AGND min Vcc 2 7 V to 5 25 V Pseudo Differential Vin Input Voo 16 5 V Vss 16 5 V Vcc 5 V see Figure 40 Range and Figure 41 3 5 V Reference 2 5 V range 10 V t6 V Reference 2 5 V range 5 V 5 V Reference 2 5 V range 2 5 V 3 5 V Reference 2 5 V range 0 V to 10 V DC Leakage Current 80 nA Vin Voo or Vss 3 nA Per channel Vin Voo or Vss Input Capacitance 13 5 pF When in track 10 V range 16 5 pF When in track 5 V and 0 V to 10 V range 21 5 pF When in track 2 5 V range 3 pF When in hold all ranges REFERENCE INPUT OUTPUT Input Voltage Range 2 5 3 V Input DC Leakage Current 1 uA Input Capacitance 10 pF Reference Output Voltage 2 5 V Reference Output Voltage Error at 5 mV 25 C Reference Output Voltage 10 mV Tmn to Tmax Reference Temperature Coefficient 3 25 ppm C Reference Output Impedance 7 Q Rev A Page 4 of 36 AD7322 B Version Parameter Min Typ Max Unit Test Conditions Comments LOGIC INPUTS Input High Voltage Vin 24 V Input Low Voltage Viu 0 8 V Vcc 4 75 V to 5 25 V 0 4 V Vcc 27 V to 3 6 V Input Current lin 1 uA Vin 0 V or Vorve Input Capacitance Cn 10 pF LOGIC OUTPUTS Output High Voltage Von Vorve 0 2 V
9. Structure 16 Typical Connection Diagram sese 18 AnalosInput tier ppt ERE HERES 18 Driver Amplifier Choice sse 20 hang mn 21 Addressing Registers seen 21 REVISION HISTORY 1 10 Rev 0 to Rev A Changes to Power Requirements Normal Mode Operational Icc and Ipr ve Parameter and Power Dissipation Normal Mode Parameter Table 2 Changes to Endnote 1 Table 4 Changes to Table Gisa ia eniti ett ChangestoFigure25andFigure26 16 Changes to Figure 30 and Figure 31 sss 17 Changes to Figure 33 and Figure 34 sss 18 Changes to Figure 39 a 19 Control Register Sim ln oS teri 22 Range R gister ioe eere e e le 24 Sequencer Operation sse 25 Reference ia seken anan eli 26 Mom 26 Modes of Operation essere 27 Normal Mode PMI PM0 0 eee 27 Full SbutdownaMode PMI PM0 1 27 AutoshutdownMode PMI 1 PM0 90 28 AutostandbyMode PM10 PM0 11 28 Power vs Throughput Rate sse 29 Serial Interface enegenvdie eene nene eli li 30 Microprocessor Interfacing esee 31 AD7322 to ADSP 2 XX iiie nude nee ee Heber Ee 31 AD7322 to ADSP BE53x nu s 31 Application Hints nene tertiis 32 LayoutandGrounding eer
10. THD performance is maintained Vcc Vporive 5V INTERNAL REFERENCE Ta 25 C fin 10kHz 5V RANGE SE MODE THD dB 500kSPS 04863 051 Vpp Vss SUPPLIES V Figure 31 THD vs Vop Vss Supply Voltage at 500 kSPS 750 kSPS and 1 MSPS Unlike other bipolar ADCs the AD7322 does not have a resistive analog input structure On the AD7322 the bipolar analog signal is sampled directly onto the sampling capacitor This gives the AD7322 high analog input impedance An approximation for the analog input impedance can be calculated from the following formula Z fs x Cs where fs is the sampling frequency and Cs is the sampling capacitor value Cs depends on the analog input range chosen see the Specifications section When operating at 1 MSPS the analog input impedance is typically 75 kO for the 10 V range As the sampling frequency is reduced the analog input impedance further increases As the analog input impedance increases the current required to drive the analog input therefore decreases Rev A Page 17 of 36 AD7322 TYPICAL CONNECTION DIAGRAM Figure 32 shows a typical connection diagram for the AD7322 In this configuration the AGND pin is connected to the analog ground plane of the system and the DGND pin is connected to the digital ground plane of the system The analog inputs on the AD7322 can be configured to operate in single ended true differential or pseudo diff
11. Vcc 0 3 V 10mA 40 C to 85 C 65 C to 150 C 150 C 113 5 C W 30 C W 260 0 C 2 5 kV AD7322 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality 1 If the analog inputs are driven from alternative Voo and Vss supply circuitry Schottky diodes should be placed in series with the AD7322 s Vno and Vss supplies See the Power Supply Configuration section 2 Transient currents of up to 100 mA do not cause SCR latch up Rev A Page 7 of 36 AD7322 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS cs L 14 SCLK DIN 2 13 DGND DGND s AD7322 12 DOUT eee Net to Sesle VpRIVE REFIN OUT 5 10 vec Vss e e Vo Vino 8 Vint z 3 Figure 3 Pin Configuration Table 5 Pin Function De
12. Vs and Ve are the rms amplitudes of the second through the sixth harmonics Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum up to fs 2 excluding dc to the rms value of the fundamental Normally the value of this specification is deter mined by the largest harmonic in the spectrum but for ADCs where the harmonics are buried in the noise floor the largest harmonic can be a noise peak Rev A Page 13 of 36 AD7322 Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between any two channels It is measured by applying a full scale 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal Figure 14 shows the worst case across all eight channels for the AD7322 The analog input range is programmed to be the same on all channels Intermodulation Distortion With inputs consisting of sine waves at two frequencies fa and fb any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa nfb where m n 0 1 2 3 and so on Intermodulation distortion terms are those for which neither m nor n are equal to 0 For example the second order terms include fa fb and fa fb whereas the third order terms include 2fa fb
13. W m 4 2 3 x 8 E INL 1MSPS o u uL c fe ui INL 750kSPS x z W m 2 5V RANGE INL 1MSPS Fe Voc Vorive 5V INTERNAL REFERENCE SINGLE ENDED MODE 5 7 9 11 13 15 17 19 8 CODE S Vpp Vss SUPPLY VOLTAGE V 8 Figure 16 Histogram of Codes Single Ended Mode Figure 19 INL Error vs Supply Voltage at 500 kSPS 750 kSPS and 1 MSPS 50 100mV p p SINE WAVE ON EACH SUPPLY 55 NO DECOUPLING SINGLE ENDED MODE go l fs 1MSPS Vcc 5V 65 m g 70 Vcc 3V kJ kJ 4 E E Vpp 12V o 8 us DD DIFFERENTIAL MODE 85 fin 50kHz Vss 12V Vpp Vss 12V 90 fs 1MSPS Ta 25 C 95 A 100 z 0 200 400 600 800 1000 1200 8 0 200 400 600 800 1000 1200 RIPPLE FREGUENCY kHz 3 SUPPLY RIPPLE FREQUENCY kHz Figure 17 CMRR vs Common Mode Ripple Frequency Figure 20 PSRR vs Supply Ripple Frequency Without Supply Decoupling Vcc Vpnive SV Vpp Vss 12V Ta 25 C INTERNAL REFERENCE DNL 750kSPS DNL 500kSPS RANGE 10V AND 2 5V 7 a Qoa a a T Rin 10009 10V RANG 9 S a Ei E u E z a DNL 500kSPS 5V RANGE Voc Vpnive 5V INTERNAL REFERENCE SINGLE ENDED MODE 42 5V RANGE 5 7 9 11 13 15 17 19 3 z Vpp Vss SUPPLY VOLTAGE V 8 ANALOG INPUT FREQUENCY kHz 3 Figure 18 DNL Error vs Supply Voltage at 500 kSPS 750 kSPS and 1 M
14. dB Differential mode 2 5 V and 5 V ranges 82 dB Differential mode 0 V to 10 Vand 10 V ranges 77 dB Single ended pseudo differential mode 2 5 Vand 5 V ranges 80 dB Single ended pseudo differential mode OV to 10 V and 10 V ranges Peak Harmonic or Spurious Noise 80 dB Differential mode 2 5 V and 5 V ranges SFDR 82 dB Differential mode 0 V to 10 V and 10 V ranges 78 dB Single ended pseudo differential mode 2 5 Vand 5 V ranges 79 dB Single ended pseudo differential mode OV to 10 V and 10 V ranges Intermodulation Distortion IMD fa 50 kHz fb 30 kHz Second Order Terms 88 dB Third Order Terms 90 dB Aperture Delay 7 ns Aperture Jitter 50 ps Common Mode Rejection Ratio 79 dB Up to 100 kHz ripple frequency see Figure 17 CMRR Channel to Channel Isolation 72 dB fn on unselected channels up to 100 kHz see Figure 14 Full Power Bandwidth 22 MHz At 3 dB 5 MHz At 0 1 dB DC ACCURACY All dc accuracy specifications are typical for 0 V to 10 V mode Single ended pseudo differential mode 1 LSB FSR 4096 unless otherwise noted Differential mode 1 LSB FSR 8192 unless otherwise noted Resolution 13 Bits No Missing Codes 12 bit plus Bits Differential mode sign 13 bits 11 bit plus Bits Single ended pseudo differential mode sign 12 bits Integral Nonlinearity 1 1 LSB Differential mode 1 LSB Single ended pseudo differential mode 0 7 41 2 LSB Single ended pseudo differential mode
15. gt ANALOG 2 Channel Software Selectable True DEVICES Bipolar Input 1 MSPS 12 Bit Plus Sign ADC AD7322 FEATURES 12 bit plus sign SAR ADC True bipolar input ranges Software selectable input ranges 10V 45V 2 5V OVto 10V 1 MSPS throughput rate Two analog input channels with channel sequencer Single ended true differential and pseudo differential analog input capability High analog input impedance Low power 21 mW Full power signal bandwidth 22 MHz Internal 2 5 V reference High speed serial interface Power down modes 14 lead TSSOP package iCMOS process technology GENERAL DESCRIPTION The AD7322 is a 2 channel 12 bit plus sign successive approx imation analog to digital converter ADC designed on the iCMOS industrial CMOS process iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies It enables the develop ment of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve Unlike analog ICs using conventional CMOS processes iCMOS components can accept bipolar input signals while providing increased performance dramatically reduced power consumption and reduced package size The AD7322 can accept true bipolar analog input signals The AD7322 has four software selectable input ranges 10 V 5 V 2 5 V and 0 V to 10 V Each analog input channel can be
16. independently programmed to one of the four input ranges The analog input channels on the AD7322 can be programmed to be single ended true differential or pseudo differential The ADC contains a 2 5 V internal reference The AD7322 also allows for external reference operation If a 3 V reference is applied to the REFIN OUT pin the AD7322 can accept a true bipolar 12 V analog input Minimum 12 V Vpn and Vss supplies are required for the 12 V input range The ADC hasa high speed serial interface that can operate at throughput rates up to 1 MSPS Protected by U S Patent No 6 731 232 Rev A Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM Vpp REFIN IOUT Vcc 13 BIT SUCCESSIVE APPROXIMATION ADC CONTROL LOGIC AND REGISTERS CHANNEL SEQUENCER 04863 001 AGND Vss DGND Figure 1 PRODUCT HIGHLIGHTS 1 The AD7322 can accept true bipolar analog input signals 10 V 5 V and 2 5 V and 0 V to 10 V unipolar signals 2 Thetwo analog inputs can be configured as
17. information to and from the AD7322 during a conversion The CS signal initiates the data transfer and the conversion process The falling edge of cs puts the track and hold into hold mode and takes the bus out of three state Then the analog input signal is sampled Once the conversion is initiated it requires 16 SCLK cycles to complete The track and hold goes back into track mode on the 14 SCLK rising edge On the 16 SCLK falling edge the DOUT line returns to three state If the rising edge of CS occurs before 16 SCLK cydes have elapsed the conversion is terminated and the DOUT line returns to three state Depending on where the CS signal is brought high the addressed register may be updated DOUT DIN Data is clocked into the AD7322 on the SCLK falling edge The three MSBs on the DIN line are decoded to select which register is addressed The control register is a 12 bit register If the control register is addressed by the three MSBs the data on the DIN line is loaded into the control on the 15 SCLK rising edge If the range register is addressed the data on the DIN line is loaded into the addressed register on the 11 SCLK falling edge Conversion data is clocked out of the AD7322 on each SCLK falling edge Data on the DOUT line consists of two leading zero bits a channel identifier bit a sign bit and a 12 bit conversion result The channel identifier bit is used to indicate which channel corresponds to the conversion
18. single ended mode Figure 30 shows the equivalent analog input structure in differential mode The two diodes provide ESD protection for the analog inputs Vpp D R1 c2 VinO o m k I D Vss 3 Figure 29 Equivalent Analog Input Circuit Single Ended Rev A Page 16 of 36 Vpp D R1 c2 Vint o w a C1 D Vss Vpp D R1 c2 Vin o w F I C1 D Vss 04863 024 NOTES 1 Vint REFERS TO V y0 AND Vy REFERS TO V y1 Figure 30 Equivalent Analog Input Circuit Differential Care should be taken to ensure that the analog input does not exceed the Vpn and Vss supply rails by more than 300 mV Exceeding this value causes the diodes to become forward biased and to start conducting into either the Vp supply rail or Vss supply rail These diodes can conduct up to 10 mA without causing irreversible damage to the part In Figure 29 and Figure 30 Capacitor C1 is typically 4 pF and can primarily be attributed to pin capacitance Resistor RI is a lumped component made up of the on resistance of the input multiplexer and the track and hold switch Capacitor C2 is the sampling capacitor its capacitance varies depending on the analog input range selected see the Specifications section Track and Hold Section The track and hold on the analog input of the AD7322 allows the ADC to accurately convert an input sine wave of full scale amplitude to 13 bit accuracy The input bandwidth of the track and hold is greater than t
19. technique is generally best All AGND pins on the AD7322 should be connected to the AGND plane Digital and analog ground pins should be joined in only one place If the AD7322 is in a system where multiple devices require an AGND and DGND connection the connection should still be made at only one point A star point should be established as close as possible to the ground pins on the AD7322 Good connections should be made to the power and ground planes This can be done with a single via or multiple vias for each supply and ground pin Avoid running digital lines under the AD7322 device because this couples noise onto the die However the analog ground plane should be allowed to run under the AD7322 to avoid noise coupling The power supply lines to the AD7322 device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line To avoid radiating noise to other sections of the board com ponents with fast switching signals such as clocks should be shielded with digital ground and never run near the analog inputs Avoid crossover of digital and analog signals To reduce the effects of feedthrough within the board traces should be run at right angles to each other A microstrip technique is the best method but its use may not be possible with a double sided board In this technique the component side of the board is dedicated to ground planes and signals are placed on
20. the other side Good decoupling is also important All analog supplies should be decoupled with 10 uF tantalum capacitors in parallel with 0 1 uF capacitors to AGND To achieve the best results from these decoupling components they must be placed as close as possible to the device ideally right up against the device The 0 1 uF capacitors should have a low effective series resistance ESR and low effective series inductance ESI such as is typical of common ceramic and surface mount types of capacitors These low ESR low ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching POWER SUPPLY CONFIGURATION If the supply voltage for the analog input circuitry is different from that of the AD7322 Vpp and Vs supplies or if the analog input can be applied to the AD7322 before Vpp and Vss are established then it is recommended that Schottky diodes be placed in series with the AD7322 Von and Vss supply signals Figure 53 shows this Schottky diode configuration BAT43 Schottky diodes are used 04863 056 TADDITIONAL PINS OMITTED FOR CLARITY Figure 53 Schottky Diode Connection In an application where nonsymmetrical Vpp and Vss supplies are being used adhere to the following guidelines Table 16 outlines the Vss supply range that can be used for particular Vpn voltages when nonsymmetrical supplies are required When operating the AD7322 with low Vpn and Vss
21. 10V 20V 2 441 mV 5V 10V 1 22 mV 2 5 V 5V 0 61 mV OVto 10V 10V 1 22 mV The ideal transfer characteristic for the AD7322 when twos complement coding is selected is shown in Figure 27 The ideal transfer characteristic for the AD7322 when straight binary coding is selected is shown in Figure 28 011 111 011 110 H 000 001 000 000 T 111 111 ADC CODE 100 010 100 001 100 000 1 gt FSR 2 1LSB AGND 1LSB 4FsR 2 1LSB BIPOLAR RANGES AGND 1LSB FSR 1LSB UNIPOLAR RANGE 04863 021 ANALOG INPUT Figure 27 Twos Complement Transfer Characteristic Bipolar Ranges 111 111 111 110 111 000 011 111 000 010 000 001 000 000 a a gt SR 2 1LSB FSR 2 1LSB BIPOLAR RANGES AGND 1LSB FSR 1LSB UNIPOLAR RANGE ANALOG INPUT ADC CODE 04863 022 Figure 28 Straight Binary Transfer Characteristic Bipolar Ranges ANALOG INPUT STRUCTURE The analog inputs of the AD7322 can be configured as single ended true differential or pseudo differential via the control register mode bits see Table 10 The AD7322 can accept true bipolar input signals On power up the analog inputs operate as two single ended analog input channels If true differential or pseudo differential is required a write to the control register is necessary after power up to change this configuration Figure 29 shows the equivalent analog input circuit of the AD7322 in
22. 2 is a fast 2 channel 12 bit plus sign bipolar input serial ADC The AD7322 can accept bipolar input ranges that include 10 V 5 V and 2 5 V it can also accept a 0 V to 10 V unipolar input range A different analog input range can be programmed on each analog input channel via the on chip registers The AD7322 has a high speed serial interface that can operate at throughput rates up to 1 MSPS The AD7322 requires Vpp and Vss dual supplies for the high voltage analog input structures These supplies must be equal to or greater than the analog input range See Table 6 for the requirements of these supplies for each analog input range The AD7322 requires a low voltage 2 7 V to 5 25 V Vcc supply to power the ADC core Table 6 Reference and Supply Requirements for Each Analog Input Range Selected Full Scale Analog Input Reference Input Minimum Range V Voltage V Range V Vcc V Voo Vss V 10 2 5 10 3 5 10 3 0 12 3 5 12 5 2 5 Tp 3 5 5 3 0 6 3 5 6 2 5 2 5 2 5 3 5 5 3 0 3 3 5 5 Oto 10 2 5 Oto 10 3 5 10 AGND 3 0 Oto 12 3 5 12 AGND To meet the specified performance when the AD7322 is confi gured with the minimum Vpp and Vss supplies for a chosen analog input range the throughput rate should be decreased from the maximum throughput range see the Typical Performance Characteristics section Figure 18 and Figure 19 show the change in INL and DNL as the Vpp and Vs voltages are v
23. 21 Rev A Page 20 of 36 REG STERS The AD7322 has two programmable registers the control register and the range register These registers are write only registers ADDRESSING REGISTERS A serial transfer on the AD7322 consists of 16 SCLK cycles The three MSBs on the DIN line during the 16 SCLK transfer are decoded to determine which register is addressed The three AD7322 MSBs consist of the write bit zero bit and register select bit The register select bit is used to determine which of the two on board registers is selected The write bit determines if the data on the DIN line following the register select bit loads into the addressed register If the write bit is 1 the bits are loaded into the register addressed by the register select bits If the write bit is 0 the data on the DIN line does not load into any register The zero bit must always be set to 0 Table 8 Decoding Register Select Bit and Write Bit Write Zero Register Select Comment 0 0 X Data on the DIN line during this serial transfer is ignored Register contents remain unchanged 1 0 0 This combination selects the control register The subsequent 12 bits are loaded into the control register 1 0 1 This combination selects the range register The subsequent six bits are loaded into the range register Rev A Page 21 of 36 AD7322 CONTROL REGISTER The control register is used to select the analog input channel register
24. 25 uW Voo 16 5 V Vss 16 5 V Vcc 5 25 V 1 Temperature range is 40 C to 85 C 2 See the Terminology section 3 Sample tested during initial release to ensure compliance Unipolar O V to 10 V range with straight binary output coding 5 Bipolar range with twos complement output coding Rev A Page 5 of 36 AD7322 TIMING SPECIFICATIONS Unless otherwise noted Vpp 12 V to 16 5 V Vss 12 V to 16 5 V Voc 2 7 V to 5 25 V Vorive 2 7 V to 5 25 Vprive Vco Vrer 2 5 V to 3 0 V internal external Ta Tmax to Twin Table 3 Limit at Tmn Tmax Parameter Vcc lt 4 75V Vcc24 75Vto5 25V Unit Description fsck 50 50 kHz min 14 20 MHz max tconvert 16 X tsc k 16 X tsc k ns max tsak 1 fscik touieT 75 60 ns min Minimum time between end of serial read and next falling edge of CS t 12 5 ns min Minimum CS pulse width t 25 20 ns min CS to SCLK setup time bipolar input ranges 10 V 5 V 2 5 V 45 35 ns min Unipolar input range 0 V to 10 V ts 26 14 ns max Delay from CS until DOUT three state disabled ta 57 43 ns max Data access time after SCLK falling edge ts 0 4 x tsc k 0 4 x tsc k ns min SCLK low pulse width te 0 4 X tsak 0 4 x tsc k ns min SCLK high pulse width t 13 8 ns min SCLK to data valid hold time ts 40 22 ns max SCLK falling edge to DOUT high impedance 10 9 ns min SCLK falling edge to DOUT high impedance to 4 4 ns min DIN setup time prior to SCLK falling e
25. 5 04863 006 INL ERROR LSB DNL ERROR LSB INL ERROR LSB Rev A Page 9 of 36 INT EXT 2 5V REFERENCE 10V RANGE Vcc Vpnive 5V AD7322 Ta 25 C Vpp Vss 7 15V INL 0 55LSB INL 0 68LSB NI 1024 2048 3072 4096 5120 6144 1536 2560 3584 4608 5632 6656 CODE 512 Figure 7 Typical INL True Differential Mode 7168 8192 7680 NA A I Atc LI 10V RANGE Vcc Vpnive SV Ta 25 C Vpp Vss 15V INT EXT 2 5V REFERENCE DNL 0 79LSB DNL 0 38LSB 0 1024 2048 3072 4096 5120 6144 512 1536 2560 3584 4608 5632 6656 CODE Figure 8 Typical DNL Single Ended Mode 7168 8192 7680 Voc Vorive SV Ta 25 C Vpn Vss 15V 10V RANGE INT EXT 2 5V REFER INL 0 87LSB INL 0 49LSB 1024 2048 3072 4096 5120 6144 512 1536 2560 3584 4608 5632 6656 CODE Figure 9 Typical INL Single Ended Mode 7168 8192 7680 04863 007 04863 043 04863 044 AD7322 X10V DIFF Ta 25 C fs 1MSPS X2 5V DIFF I V SE THD dB SINAD dB OV TO 10V DI Vec 3V Vpp Vss 12V Ta 25 C fs 1MSPS 10 100 1000 10 100 1000 5 ANALOG INPU
26. 7322 remains in full shutdown mode until the power management bits Bit PM1 and Bit PMO in the control register are changed A write to the control register with PM1 1 and PMO 1 places the part into full shutdown mode The AD7322 enters full shut down mode on the 15 SCLK rising edge when the control register is updated If a write to the control register occurs while the part is in full shutdown mode with the power management bits Bit PM1 and Bit PMO set to 0 normal mode the part begins to power up on the 15 SCLK rising edge when the control register is updated Figure 46 shows how the AD7322 is configured to exit full shutdown mode To ensure the AD7322 is fully powered up trower up for full shutdown mode should elapse before the next CS falling edge THE PART IS FULLY POWERED UP ONCE tpower up HAS ELAPSED SDATA INVALID DATA CHANNEL IDENTIFIER BITS CONVERSION RESULT DIN DATA INTO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS PM1 0 PMO 0 DATA INTO CONTROL REGISTER TO KEEP THE PART IN NORMAL MODE LOAD PM1 PMO 0 IN CONTROL REGISTER 04863 041 Figure 46 Exiting Full Shutdown Mode Rev A Page 27 of 36 AD7322 AUTOSHUTDOWN MODE PM1 1 PMO 0 Once the autoshutdown mode is selected the AD7322 auto matically enters shutdown on the 15 SCLK rising edge In autoshutdown mode all internal circuitry is powered down The AD7322 retains information in the registers during a
27. AL MODE PM1 PMO 0 This mode is intended for the fastest throughput rate perfor mance with the AD7322 being fully powered up at all times Figure 45 shows the general operation of the AD7322 in normal mode The conversion is initiated on the falling edge of CS and the track and hold enters hold mode as described in the Serial Interface section Data on the DIN line during the 16 SCLK transfer is loaded into one of the on chip registers if the write bit is set The register is selected by programming the register select bits see Figure 45 SCLK DOUT 2 LEADING ZEROS CHANNEL I D BIT SIGN BIT CONVERSION RESULT DIN DATA INTO CONTROL RANGE REGISTER Figure 45 Normal Mode 04863 035 PART IS IN FULL SHUTDOWN PART BEGINS TO POWER UP ON THE 15TH 7 SCLK RISING EDGE AS PM1 PM0 0 cs j 1 16 wn mm SCLK i1 ia E u AD7322 The AD7322 remains fully powered up at the end of the conversion if both PM1 and PMO contain 0 in the control register To complete the conversion and access the conversion result 16 serial clock cycles are required At the end of the conversion CS can idle either high or low until the next conversion When the data transfer is complete another conversion can be initiated after the quiet time touer has elapsed FULL SHUTDOWN MODE PM1 PMO 1 In this mode all internal circuitry on the AD7322 is powered down The part retains information in the registers during full shutdown The AD
28. Isource 200 MA Output Low Voltage Vo 0 4 V Isink 200 pA Floating State Leakage Current 1 uA Floating State Output Capacitance 5 pF Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE Conversion Time 800 ns 16 SCLK cycles with SCLK 20 MHz Track and Hold Acquisition Time 305 ns Full scale step input see the Terminology section Throughput Rate 1 MSPS See the Serial Interface section Vcc 4 75 V to 5 25 V 770 kSPS Vcc lt 4 75 V POWER REQUIREMENTS Digital inputs 0 V or Vpawe Voo 12 16 5 V See Table 6 Vss 12 16 5 V See Table 6 Vcc 24 5 25 V See Table 6 typical specifications for Vcc lt 4 75 V Vorive 2 7 5 25 V Normal Mode Static 0 9 mA Vov Vss 16 5 V Vec Vorive 5 25 V Normal Mode Operational fs 1 MSPS lop 360 uA Voo 16 5 V Iss 410 uA Vss 16 5 V Icc and Iprive 3 4 mA Vcc Vorive 5 25 V Autostandby Mode Dynamic fs 250 kSPS lop 200 uA Voo 16 5 V Iss 210 uA Vss 16 5 V Icc and prive 1 3 mA Vcc Vorive 5 25 V Autoshutdown Mode Static SCLK on or off lbo 1 uA Voo 16 5 V Iss 1 uA Vss 16 5 V Icc and Iprive 1 uA Vcc Vorive 5 25 V Full Shutdown Mode SCLK on or off lop 1 uA Voo 16 5 V Iss 1 uA Vss 16 5 V Icc and Iprive 1 uA Vcc Vorive 5 25 V POWER DISSIPATION Normal Mode 31 mW Voo 16 5 V Vss 16 5 V Vcc 5 25 V 21 mW Voo 12V Vss 12V Vc 5 V Full Shutdown Mode 38
29. LSB FSR 8192 Rev A Page 3 of 36 AD7322 B Version Parameter Min Typ Max Unit Test Conditions Comments Differential Nonlinearity 0 9 41 5 LSB Differential mode guaranteed no missing codes to 13 bits 0 9 LSB Single ended mode guaranteed no missing codes to 12 bits 0 7 41 LSB Single ended pseudo differential mode LSB FSR 8192 Offset Error 4 49 LSB Single ended pseudo differential mode 7 410 LSB Differential mode Offset Error Match 0 6 LSB Single ended pseudo differential mode 0 5 LSB Differential mode Gain Error gt 8 LSB Single ended pseudo differential mode 14 LSB Differential mode Gain Error Match 4 0 5 LSB Single ended pseudo differential mode 0 5 LSB Differential mode Positive Full Scale Error gt 4 LSB Single ended pseudo differential mode 7 LSB Differential mode Positive Full Scale Error Match 0 5 LSB Single ended pseudo differential mode 0 5 LSB Differential mode Bipolar Zero Error 8 5 LSB Single ended pseudo differential mode 7 5 LSB Differential mode Bipolar Zero Error Match 0 5 LSB Single ended pseudo differential mode 0 5 LSB Differential mode Negative Full Scale Error gt 4 LSB Single ended pseudo differential mode 6 LSB Differential mode Negative Full Scale Error Match 0 5 LSB Single ended pseudo differential mode 0 5 LSB Differential mode ANALOG INPUT Input Voltage Ranges Reference 2 5 V see Table 6 Programmed via Range
30. N SEQUENCE Figure 44 Flowchart for Consecutive Sequence of Channels CONSECUTIVE CHANNELS DOUT CONVERSION RESULT FROM CHANNEL 0 RANGE AS SELECTED IN RANGE REGISTER DIN WRITE BIT 0 OR DIN LINE HELD LOWTO CONTINUE THROUGH SEQUENCE OF CONSECUTIVE CHANNELS DOUT CONVERSION RESULT FROM CHANNEL1 RANGE AS SELECTED IN RANGE REGISTER STOPPING A SEQUENCE DIN TIED LOW WRITE BIT 0 CONTINUOUSLY CONVERT ON CONSECUTIVE SEQUENCE OF CHANNELS 04863 032 Rev A Page 25 of 36 AD7322 REFERENCE The AD7322 can operate with either the internal 2 5 V on chip reference or an externally applied reference The internal reference is selected by setting the Ref bit in the control register to 1 On power up the Ref bit is 0 resulting in the selection of the external reference for the AD7322 conversion Suitable reference sources for the AD7322 include AD780 AD1582 ADR431 REF193 and ADR391 The internal reference circuitry consists of a 2 5 V band gap reference and a reference buffer When operating the AD7322 in internal reference mode the 2 5 V internal reference is available at the REFIN OUT pin which should be decoupled to AGND using a 680 nF capacitor It is recommended that the internal reference be buffered before applying it elsewhere in the system The internal reference is capable of sourcing up to 90 uA On power up if the internal reference operation is required for the ADC conversion a wri
31. NPUT VOLTAGE RANGE V Voc 3V Veer 2 5V 04863 040 16 5V Vpp Vss O 12V Vpp Vss Figure 41 Pseudo Input Range with Vcc 3V DRIVER AMPLIFIER CHOICE In applications where the harmonic distortion and signal to noise ratio are critical specifications the analog input of the AD7322 should be driven from a low impedance source Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier When no amplifier is used to drive the analog input the source impedance should be limited to low values The maximum source impedance depends on the amount of THD that can be tolerated in the application The THD increases as the source impedance increases and performance degrades Figure 21 and Figure 22 show graphs of the THD vs the analog input frequency for various source impedances Depending on the input range and analog input configuration selected the AD7322 can handle source impedances of up to 4 7 kQ before the THD starts to degrade Due to the programmable nature of the analog inputs on the AD7322 the choice of op amp used to drive the inputs is a function of the particular application and depends on the input configuration and the analog input voltage ranges selected The driver amplifier must be able to settle for a full scale step to a 13 bit level 0 0122 in less than the specified acquisition time of the AD7322 An op amp such as the AD8021 meets thi
32. SPS Figure 21 THD vs Analog Input Frequency for Various Source Impedances True Differential Mode Rev A Page 11 of 36 AD7322 50 Vcc Vprive 5V 55 Vop Vss 12V 55 rA 25 C INTERNAL REFERENCE 60 RANGE 10V AND 2 5V R y 1000 65 Ri 20000 10V RANGE 10V RANGE E a a a Ras 00 79 L Rin 10000 10V RANGE J 10 PN 10V RANGE 9 75 Rin 20000 42 5V RANGE 80 Ri 10000 42 5V RANGE 85 Rin 1000 42 5V RANGE 90 Riy 500 42 5V RANGE 95 10 100 1000 04863 016 INPUT FREGUENCY kHz Figure 22 THD vs Analog Input Frequency for Various Source Impedances Single Ended Mode Rev A Page 12 of 36 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function The endpoints of the transfer function are zero scale a point 1 LSB below the first code transition and full scale a point 1 LSB above the last code transition Offset Code Error This applies to straight binary output coding It is the deviation of the first code transition 00 000 to 00 001 from the ideal that is AGND 1 LSB Offset Error Match This is the difference in offset error between any two input channels Gain Error
33. T FREQUENCY kHz ANALOG INPUT FREQUENCY kHz 2 Figure 10 THD vs Analog Input Frequency for Single Ended SE and True Figure 13 SINAD vs Analog Input Frequency for Single Ended SE and Differential Mode Diff at 5 V Vcc Differential Mode Diff at 3 V Vcc OV TO 10V THD dB Vpp Vss 12V SINGLE ENDED MODE fs 1MSPS TA 25 C 50kHz ON SELECTED CHANNEL CHANNEL TO CHANNEL ISOLATION dB 2 5V DIFF 0 100 200 300 400 500 600 FREQUENCY OF INPUT NOISE kHz 10 100 1000 ANALOG INPUT FREQUENCY kHz 04863 009 04863 012 Figure 11 THD vs Analog Input Frequency for Single Ended SE and True Figure 14 Channel to Channel Isolation Differential Mode Diff at 3 V Vcc 10V DIFF Voc 5V Vpp Vss 12V RANGE 10V gt 10k SAMPLES W o z ul amp 3 a 3 z ov O n ul m z 2 Voc 5V z Vpp Vss 12V Ta 25 C fs 1MSPS 10 100 1000 amp 5 ANALOG INPUT FREGUENCY kHz CODE 3 Figure 12 SINAD vs Analog Input Frequency for Single Ended SE and Figure 15 Histogram of Codes True Differential Mode Differential Mode Diff at 5 V Vcc Rev A Page 10 of 36 AD7322 7600 Voc 5V Vpp Vss 12V AMPLE INL 500kSPS 10k SAMPLES 4 50kSPS ul 25 i Ta 25 C B
34. This applies to straight binary output coding It is the deviation of the last code transition 111 110 to 111 111 from the ideal that is 4 x Vrer 1 LSB 2 x Vrer 1 LSB Vrer 1 LSB after adjusting for the offset error Gain Error Match This is the difference in gain error between any two input channels Bipolar Zero Code Error This applies when using twos complement output coding and a bipolar analog input It is the deviation of the midscale transi tion all 1s to all 0s from the ideal input voltage that is AGND 1 LSB Bipolar Zero Code Error Match This refers to the difference in bipolar zero code error between any two input channels Positive Full Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges It is the deviation of the last code transition 011 110 to 011 111 from the ideal 4 x Vrer 1 LSB 2 x Vrer 1 LSB Vrer 1 LSB after adjust ing for the bipolar zero code error Positive Full Scale Error Match This is the difference in positive full scale error between any two input channels AD7322 Negative Full Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges This is the deviation of the first code transition 10 000 to 10 001 from the ideal that is 4 x Vrer 1 LSB 2 x Vrer 1 LSB Vrer 1 LSB after adjusting for the bipolar zero code error Neg
35. after the range register has been initialized The bit functions of the control register are shown in Table 9 the power up status of all bits is 0 analog input configuration reference coding and power mode The control register is a write only 12 bit register Data loaded on the DIN line corresponds to the AD7322 configuration for the next conversion Data should be loaded into the control The two analog input channels can be configured as one pseudo differential analog input one true differential input or two single ended analog inputs see Table 10 MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Zero Register Select Zero Zero ADDO Model ModeO PMI PMO Coding Ref Seg Seg2 Zero 0 Table 9 Control Register Details Bit Mnemonic Description 12 11 1 Zero These bits should contain 0 during each write to the control register 10 ADDO This channel address bit is used to select the analog input channel for the next conversion if the sequencer is not being used If the sequencer is being used this channel address bit is used to select the final channel in the consecutive sequence see Table 10 9 8 Mode 1 These two mode bits are used to select the configuration of the two analog input pins VO and Vin1 Mode 0 These bits are used in conjunction with the channel address bit On the AD7322 the analog inputs can be configured as single ended inp
36. allow power saving between conversions The power down modes are selected by programming the on chip control register as described in the Modes of Operation section CONVERTER OPERATION The AD7322 is a successive approximation ADC built around two capacitive DACs Figure 23 and Figure 24 show simplified schematics of the ADC in single ended mode during the acquisition and conversion phases respectively Figure 25 and Figure 26 show simplified schematics of the ADC in differential mode during acquisition and conversion phase respectively The ADC is composed of control logic a SAR and capacitive DACs In Figure 23 the acquisition phase SW2 is closed and SW1 is in Position A the comparator is held in a balanced condition and the sampling capacitor array acquires the signal on the input CAPACITIVE DAC Vino O o o if A sw CONTROL LOGIC Figure 23 ADC Acquisition Phase Single Ended 04863 017 When the ADC starts a conversion see Figure 24 SW2 opens and SW1 moves to Position B causing the comparator to become unbalanced The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the capacitive DAC to bring the comparator back into a balanced condition When the comparator is rebalanced the conversion is complete The control logic generates the ADC output code CAPACITIVE DAC B a Lf Vin9 O o Aswi CONTROL LOGIC 04863 018 Figure 24 ADC Co
37. aried When operating at the maximum throughput rate as the Vpn and Vs supply voltages are reduced the INL and DNL error increases However as the throughput rate is reduced with the minimum Vpp and Vss supplies the INL and DNL error is reduced Figure 31 shows the change in THD as the Vpp and Vss supplies are reduced At the maximum throughput rate the THD degrades significantly as Vp and Vss are reduced It is therefore necessary to reduce the throughput rate when using minimum Vpp and Vss supplies so that there is less degradation of THD and the specified performance can be maintained The degradation is due to an increase in the on resistance of the input multiplexer when the Vpp and Vss supplies are reduced The analog inputs can be configured as two single ended inputs one true differential input or one pseudo differential input Selection can be made by programming the mode bits Mode 0 and Mode 1 in the control register AD7322 The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC The AD7322 has an on chip 2 5 V reference However the AD7322 can also work with an external reference On power up the exter nal reference operation is the default option If the internal reference is the preferred option the user must write to the reference bit in the control register to select the internal refer ence operation The AD7322 also features power down options to
38. ation board data sheet for more information Rev A Page 33 of 36 AD7322 NOTES Rev A Page 34 of 36 AD7322 NOTES Rev A Page 35 of 36 AD7322 NOTES 2005 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D04863 0 1 10 A DEVICES www analo g com Rev A Page 36 of 36
39. ative Full Scale Error Match This is the difference in negative full scale error between any two input channels Track and Hold Acquisition Time The track and hold amplifier returns into track mode after the 14 SCLK rising edge Track and hold acquisition time is the time required for the output of the track and hold amplifier to reach its final value within 1 2 LSB after the end of a conversion For the 2 5 V range the specified acquisition time is the time required for the track and hold amplifier to settle to within 1 LSB Signal to Noise Distortion Ratio This is the measured ratio of signal to noise distortion at the output of the ADC The signal is the rms amplitude of the fundamental Noise is the sum of all nonfundamental signals up to half the sampling frequency fs 2 excluding dc The ratio is dependent on the number of quantization levels in the digi tization process The more levels there are the smaller the quantization noise becomes Theoretically the signal to noise distortion ratio for an ideal N bit converter with a sine wave input is given by Signal to Noise Distortion 6 02 N 1 76 dB For a 13 bit converter this is 80 02 dB Total Harmonic Distortion Total harmonic distortion THD is the ratio of the rms sum of harmonics to the fundamental For the AD7322 it is defined as JV V V V Ve THD dB 20 log V 1 where V is the rms amplitude of the fundamental and V2 V3 Va
40. dge tio 2 2 ns min DIN hold time after SCLK falling edge POWER UP 750 750 ns max Power up from autostandby 500 500 us max Power up from full shutdown autoshutdown mode internal reference 25 25 us typ Power up from full shutdown autoshutdown mode external reference 1 Sample tested during initial release to ensure compliance All input signals are specified with tr tf 5 ns 10 to 90 of Vorive and timed from a voltage level of 1 6 V When using the 0 V to 10 V unipolar range running at 1 MSPS throughput rate with t2 at 20 ns the mark space ratio must be limited to 50 50 DOUT THREE ZERO STATE ty DIN 04863 002 Figure 2 Serial Interface Timing Diagram Rev A Page 6 of 36 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 4 Parameter Rating Vop to AGND DGND 0 3V to 16 5 V Vss to AGND DGND Voo to Vcc Vcc to AGND DGND Vorive to AGND DGND AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND REFIN to AGND Input Current to Any Pin Except Supplies Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package Osa Thermal Impedance Osc Thermal Impedance Pb Free Temperature Soldering Reflow ESD 0 3 V to 16 5 V Vcc 0 3 V to 16 5 V 0 3 V to 7 V 0 3 V to 7 V 0 3 V to 0 3 V Vss 0 3 V to Voo 0 3 V 0 3 V to 7 V 0 3 V to Vorve 0 3 V 0 3V to
41. erential mode The AD7322 can operate with either an internal or external reference In Figure 32 the AD7322 is configured to operate with the internal 2 5 V reference A 680 nF decoupling capacitor is required when operating with the internal reference The Vcc pin can be connected to either a 3 V supply voltage or a 5 V supply voltage Vpp and Vss are the dual supplies for the high voltage analog input structures The voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels see Table 6 The Vorive pin is connected to the supply voltage of the microprocessor The voltage applied to the Vprivz input controls the voltage of the serial interface Vprive can be set to 3 V or 5 V ASV O O Voc 42 7V TO 5 25V ANALOG INPUTS HOV 5V 2 5V Q VNO OV TO 10V SERIAL INTERFACE 15V O DEPEND ON THE HIGHEST ANALOG INPUT T 0 1uF TS 1MINIMUM Vpp AND Vss SUPPLY VOLTAGES RANGE SELECTED 04863 025 Figure 32 Typical Connection Diagram ANALOG INPUT Single Ended Inputs The AD7322 has a total of two analog inputs when operating in single ended mode Each analog input can be independently programmed to one of the four analog input ranges In applications where the signal source is high impedance it is recommended to buffer the signal before applying it to the ADC analog inputs Figure 33 shows the configuration of the AD7322 in single ended mode
42. g input section 7 8 VinO V n1 Analog Input 0 and Analog Input 1 The analog inputs are multiplexed into the on chip track and hold The analog input channel for conversion is selected by programming the ADDO channel address bit in the control register The inputs can be configured as single ended true differential or pseudo differential see Table 10 The configuration of the analog inputs is selected by programming the mode bits Bit Mode 1 and Bit Mode 0 in the control register The input range on each input channel is controlled by programming the range register Input ranges of 10 V 5 V 2 5 V and OV to 10 V can be selected on each analog input channel when a 42 5 V reference voltage is used see the Registers section 9 Vop Positive Power Supply Voltage This is the positive supply voltage for the analog input section 10 Vcc Analog Supply Voltage 2 7 V to 5 25 V This is the supply voltage for the ADC core on the AD7322 This supply should be decoupled to AGND 11 Vorive Logic Power Supply Input The voltage supplied at this pin determines at what voltage the interface operates This pin should be decoupled to DGND The voltage at this pin may be different from that at Vcc but it should not exceed Vcc by more than 0 3 V 12 DOUT Serial Data Output The conversion output data is supplied to this pin as a serial data stream The bits are clocked out on the falling edge of the SCLK input and 16 SCLKs are required to access the data
43. he Nyquist rate of the ADC The AD7322 can handle frequencies up to 22 MHz The track and hold enters its tracking mode on the 14 SCLK rising edge after the CS falling edge The time required to acquire an input signal depends on how quickly the sampling capacitor is charged With zero source impedance 305 ns is sufficient to acquire the signal to the 13 bit level The acquisition time required is calculated using the following formula taco 10 x Rsource R C where C is the sampling capacitance and R is the resistance seen by the track and hold amplifier looking back on the input For the AD7322 the value of R includes the on resistance of the input multiplexer and is typically 300 Q Rsounc should include any extra source impedance on the analog input AD7322 The AD7322 enters track mode on the 14 SCLK rising edge When running the AD7322 at a throughput rate of 1 MSPS with a 20 MHz SCLK signal the ADC has approximately 1 5 SCLK ts touer to acquire the analog input signal The ADC goes back into hold mode on the CS falling edge As the Vpp Vss supply voltage is reduced the on resistance of the input multiplexer increases Therefore based on the equation for taco it is necessary to increase the amount of acquisition time provided to the AD7322 and therefore decrease the overall throughput rate Figure 31 shows that if the throughput rate is reduced when operating with minimum Vpp and Vss supplies the specified
44. nversion Phase Single Ended Rev A Page 15 of 36 AD7322 Figure 25 shows the differential configuration during the acquisition phase For the conversion phase SW3 opens and SW1 and SW2 move to Position B see Figure 26 The output impedances of the source driving the Vin and Vin pins must be matched otherwise the two inputs will have different settling times resulting in errors CAPACITIVE DAC 4863 019 NOTES 1 Viyt REFERS TO V0 AND Viy REFERS TO Vi Figure 25 ADC Differential Configuration During Acquisition Phase CAPA D CITIVE AC COMPARATOR ii 04863 020 NOTES 1 Vint REFERS TO VjyO AND Vy REFERS TO V y1 Figure 26 ADC Differential Configuration During Conversion Phase Output Coding The AD7322 default output coding is set to twos complement The output coding is controlled by the coding bit in the control register To change the output coding to straight binary coding the coding bit in the control register must be set When operat ing in sequence mode the output coding for each channel in the sequence is the value written to the coding bit during the last write to the control register Transfer Functions The designed code transitions occur at successive integer LSB values that is 1 LSB 2 LSB and so on The LSB size is dependent on the analog input range selected Table 7 LSB Sizes for Each Analog Input Range Input Range Full Scale Range 8192 Codes LSB Size
45. owed VinO Vin1 VinO Vin1 Vin1 AGND Rev A Page 22 of 36 AD7322 Table 11 Power Mode Selection PM1 PMO Description 1 1 Full shutdown mode In this mode all internal circuitry on the AD7322 is powered down Information in the control register is retained when the AD7322 is in full shutdown mode 1 0 Autoshutdown mode The AD7322 enters autoshutdown on the 15 SCLK rising edge when the control register is updated All internal circuitry is powered down in autoshutdown 0 1 Autostandby mode In this mode all internal circuitry is powered down excluding the internal reference The AD7322 enters autostandby mode on the 15 SCLK rising edge after the control register is updated 0 0 Normal mode All internal circuitry is powered up at all times Table 12 Sequencer Selection Seq1 Seq2 Sequence Type 0 X The channel sequencer is not used The analog channel selected by programming the ADDO bit in the control register selects the next channel for conversion 1 0 This configuration is used in conjunction with the channel address bit in the control register This allows continuous conversions on a consecutive sequence of channels from Channel 0 up to Channel 1 as selected by the channel address bits in the control register The range for each channel defaults to the ranges previously written into the range register 1 1 The channel sequencer is not used The analog channel selected by programming the
46. ower up much faster This allows faster throughput rates to be achieved As is the case with the autoshutdown mode the AD7322 enters standby on the 15 SCLK rising edge when the control register is updated see Figure 47 The part retains information in the registers during standby Once in autostandby mode the CS signal must remain low to keep the part in autostandby mode The AD7322 remains in standby until it receives a CS rising edge The ADC begins to power up on the CS rising edge On the CS rising edge the track and hold which was in hold mode while the part was in standby returns to track The power up time from standby is 750 ns The user should ensure that 750 ns have elapsed before bringing CS low to attempt a valid conversion Once this valid conversion is complete the AD7322 again returns to standby on the 15 SCLK rising edge The CS signal must remain low to keep the part in standby mode Figure 47 shows the part entering autoshutdown mode The sequence of events is the same when entering autostandby mode In Figure 47 the power management bits are configured for auto shutdown For autostandby mode the power management bits PMI and PMO should be set to 0 and 1 respectively THE PART IS FULLY POWERED UP ONCE tpower up HAS ELAPSED 1 15 16 VALID DATA DATA INTO CONTROL REGISTER 04863 042 Figure 47 Entering Autoshutdown Autostandby Mode Rev A Page 28 of 36 AD7322 POWER vs THROUGHPUT RATE
47. result The first leading zero bit is clocked out on the CS falling edge and the second zero bit is clocked out on the first SCLK falling edge 04863 036 Figure 50 Serial Interface Timing Diagram Control Register Write Rev A Page 30 of 36 MICROPROCESSOR INTERFACING The serial interface on the AD7322 allows the part to be directly connected to a range of different microprocessors This section explains how to interface the AD7322 with some common micro controller and DSP serial interface protocols AD7322 TO ADSP 21xx The ADSP 21xx family of DSPs interface directly to the AD7322 without requiring glue logic The Vorive pin of the AD7322 takes the same supply voltage as that of the ADSP 21xx This allows the ADC to operate at a higher supply voltage than its serial interface The SPORTO on the ADSP 21xx should be configured as shown in Table 14 Table 14 SPORTO Control Register Setup Setting Description TFSW RFSW 1 Alternative framing INVRFS INVTFS 1 Active low frame signal DTYPE 00 Right justify data SLEN 1111 16 bit data word ISCLK 1 Internal serial clock TFSR RFSR 1 Frame every word IRFS 2 0 Internal receive frame sync ITFS 1 Internal transmit frame sync The connection diagram is shown in Figure 51 The ADSP 21xx has TFSO and RFS0 tied together TFSO is set as an output and RES0 is set as an input The DSP operates in alternative framing mode and the SPORT0 control register i
48. s requirement when operating in single ended mode The AD8021 needs an external compensating NPO type of capacitor The AD8022 can also be used in high frequency applications where a dual version is required For lower frequency applications op amps such as the AD797 AD845 and the AD8610 can be used in the AD7322 single ended mode configuration Differential operation requires that Vin and the Vm be simulta neously driven with two signals of equal amplitude that are 180 out of phase The common mode must be set up externally to the AD7322 The common mode range is determined by the REFIN OUT voltage the Vcc supply voltage and the particular amplifier used to drive the analog inputs Differential mode with either an ac input or a dc input provides the best THD performance over a wide frequency range Because not all applications have a signal preconditioned for differential operation there is often a need to perform the single ended to differential conversion This single ended to differential conversion can be performed using an op amp pair Typical connection diagrams for an op amp pair are shown in Figure 42 and Figure 43 In Figure 42 the common mode signal is applied to the noninverting input of the second amplifier 04863 029 Figure 42 Single Ended to Differential Configuration with the AD845 4420 Vin AD8021 ov V 04863 030 Figure 43 Single Ended to Differential Configuration with the AD80
49. s set up as described in Table 14 The frame synchronization signal generated on the TES is tied to CS and as with all signal processing applications requires equidistant sampling However as in this example the timer interrupt is used to control the sampling rate of the ADC and under certain conditions equidistant sampling cannot be achieved AD73221 ADSP 21xx1 04863 037 TADDITIONAL PINS OMITTED FOR CLARITY Figure 51 Interfacing the AD7322 to the ADSP 21xx The timer registers are loaded with a value that provides an interrupt at the required sampling interval When an interrupt is received a value is transmitted with TFS DT ADC control word The TFS is used to control the RFS and therefore the reading of data AD7322 The frequency of the serial clock is set in the SCLKDIV register When the instruction to transmit with TFS is given AX0 TX0 the state of the serial clock is checked The DSP waits until the SCLK goes high low and then high again before starting the transmission If the timer and SCLK are chosen so that the instruction to transmit occurs on or near the rising edge of SCLK data can be transmitted either immediately or at the next clock edge For example the ADSP 2111 has a master clock frequency of 16 MHz If the SCLKDIV register is loaded with the value 3 an SCLK of 2 MHz is obtained and eight master clock periods elapse for every one SCLK period If the timer registers are loaded with the val
50. scriptions Pin No Mnemonic Description 1 CS Chip Select Active low logic input This input provides the dual function of initiating conversions on the AD7322 and framing the serial data transfer 2 DIN Data Input Data to be written to the on chip registers is provided on this input and is clocked into the register on the falling edge of SCLK see the Registers section 3 13 DGND Digital Ground Ground reference point for all digital circuitry on the AD7322 The DGND and AGND voltages ideally should be at the same potential and must not be more than 0 3 V apart even on a transient basis 4 AGND Analog Ground Ground reference point for all analog circuitry on the AD7322 All analog input signals and any external reference signal should be referred to this AGND voltage The AGND and DGND voltages ideally should be at the same potential and must not be more than 0 3 V apart even on a transient basis 5 REFIN OUT Reference Input Reference Output The on chip reference is available on this pin for use external to the AD7322 The nominal internal reference voltage is 2 5 V which appears at the pin A 680 nF capacitor should be placed on the reference pin see the Reference section Alternatively the internal reference can be disabled and an external reference applied to this input On power up the external reference mode is the default condition 6 Vss Negative Power Supply Voltage This is the negative supply voltage for the analo
51. te 32 Power Supply Configuratlon sse 32 Outline Dimensions 252r tete teet it 33 Ordering Guides etie pep 33 Changes to Figure 40 and Figure 41 sss 20 Changes to Autostandby Mode PMI 0 PM 1 Section 28 Changes to Table 14 and Table 15 sss 31 Added Power Supply Configuration Section sz 32 Added Table 16 Renumbered Sequentially 32 Added Figure 53 Renumbered Seguentially 32 Updated Outline Dimensions eee 33 12 05 Revision 0 Initial Version Rev A Page 2 of 36 SPECIFICATIONS AD7322 Unless otherwise noted Von 12 V to 16 5 V Vss 12 V to 16 5 V Vcc 4 75 V to 5 25 V Vorive 2 7 V to 5 25 V Vrer 2 5 V to 3 0 V internal external fscix 20 MHz fs 1 MSPS Ta Tmax to Tmn for Vcc lt 4 75 V all specifications are typical Table 2 B Version Parameter Min Typ Max Unit Test Conditions Comments DYNAMIC PERFORMANCE fin 50 kHz sine wave Signal to Noise Ratio SNR 76 dB Differential mode 72 5 dB Single ended pseudo differential mode Signal to Noise Distortion SINAD 75 dB Differential mode 2 5 V and 5 V ranges 76 dB Differential mode 0 V to 10 V and 10 V ranges 72 dB Single ended pseudo differential mode 2 5 V and 5 V ranges 72 5 dB Single ended pseudo differential mode OV to 10 V and 10 V ranges Total Harmonic Distortion THDP 80
52. te to the control register is necessary to set the Ref bit to 1 During the control register write the conversion result from the first initial conversion is invalid The reference buffer requires 500 us to power up and charge the 680 nF decoupling capacitor during the power up time The AD7322 is specified for a 2 5 V to 3 V reference range When a 3 V reference is selected the ranges are 12 V 6 V 3 V and 0 V to 12 V For these ranges the Vpn and Vss supply must be equal to or greater than the maximum analog input range selected see Table 6 Vorive The AD7322 has a Vpr ve feature to control the voltage at which the serial interface operates V pr ve allows the ADC to easily interface to both 3 V and 5 V processors For example if the AD7322 is operated with a Vcc of 5 V the Vorive pin can be powered from a 3 V supply This allows the AD7322 to accept large bipolar input signals with low voltage digital processing Rev A Page 26 of 36 MODES OF OPERATION The AD7322 has several modes of operation that are designed to provide flexible power management options These options can be chosen to optimize the power dissipation throughput rate ratio for different application reguirements The mode of operation of the AD7322 is controlled by the power manage ment bits Bit PMI and Bit PMO in the control register as shown in Table 11 The default mode is normal mode in which all internal circuitry is fully powered up NORM
53. the actual common mode range is determined by the amplifier s output swing If the differential inputs are not driven from an amplifier the common mode range is determined by the supply voltage on the Vp supply pin and the Vss supply pin Rev A Page 18 of 36 When a conversion takes place the common mode is rejected resulting in a noise free signal of amplitude 2 x 4 x Vrer to 2 x 4 x Vrer corresponding to Digital Code 4096 to Digital Code 4095 5V RANGE 5V RANGE 42 5V RANGE Vcom RANGE V 2 16 5V Vpp Vss O 12v Vpp Vsg V Figure 35 Common Mode Range for Vcc 3 V and REFIN OUT 3 8 5V RANGE 5V RANGE 2 5V 12 5V RANGE RANGE Vcom RANGE V N 2 16 5V Vpp Vss Bill 12V Vpp Vss E Figure 36 Common Mode Range for Vcc 5 V and REFIN OUT 3 V 5V RANGE 5V RANGE 12 5V 10V RANGE RANGE Vcom RANGE V 04863 047 16 5V Vpp Vss Bill 12V Vpp Vss Figure 37 Common Mode Range for Vcc 3 Vand REFIN OUT 2 5 V AD7322 Vcom RANGE V 5V RANGE 04863 048 116 5V Vpp Vss B 12v Vpp Vss Figure 38 Common Mode Range for Vcc 5 Vand REFIN OUT 2 5 V Pseudo Differential Inputs The AD7322 can have one pseudo differential pair The Vn input is coupled to the signal source and must have an amplitude within the selected range for that channel as programmed in the range register
54. two single ended inputs one true differential input or one pseudo differential input 3 1 MSPS serial interface SPI OSPT DSP MICROWTRE compatible interface 4 Low power 31 mW maximum at 1 MSPS throughput rate 5 Channel sequencer Table 1 Similar Devices Number of Channels Device Throughput Number Rate Number of bits AD7329 1000 kSPS AD7328 1000 kSPS AD7327 500 kSPS AD7324 1000 kSPS AD7323 500 kSPS AD7321 500 kSPS 12 bit plus sign 8 12 bit plus sign 12 bit plus sign 12 bit plus sign 12 bit plus sign 12 bit plus sign N A A One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 2010 Analog Devices Inc All rights reserved AD7322 TABLE OF CONTENTS Features e REIR IE N Ge S 1 Functional Block Diagram sse 1 General Description 1 Product Highlights seen 1 REVISO HSL ORY e ooo i e RS eet 2 Specifications eerta ner te MPO Reiter ees 3 Timing Specifications seen 6 Absolute Maximum Ratings seen 7 ESD Cautions eicere iE ees 7 Pin Configuration and FunctionDescriptions 8 Typical Performance Characteristics sse 9 Terminology eee e tiene E bte itn 13 Theory of Op ration enit tee eerte tm 15 Circuit Inform tor esisiini 15 Converter Operation 15 Analog Input
55. ue 803 100 5 SCLKs occur between interrupts and subsequently between transmit instructions This situation leads to nonequidistant sampling because the transmit instruction occurs on an SCLK edge If the number of SCLKs between interrupts is an integer of N equidistant sampling is implemented by the DSP AD7322 TO ADSP BF53x The ADSP BF53x family of DSPs interface directly to the AD7322 without requiring glue logic as shown in Figure 52 The SPORTO Receive Configuration 1 register should be set up as outlined in Table 15 AD73221 ADSP BF53x1 O Vpp 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 52 Interfacing the AD7322 to the ADSP BF53x 04863 038 Table 15 SPORTO Receive Configuration 1 Register Setting Description RCKFE 1 Sample data with falling edge of RSCLK LRFS 1 Active low frame signal RFSR 1 Frame every word IRFS 1 Internal RFS used RLSBIT 0 Receive MSB first RDTYPE 00 Zero fill IRCLK 1 Internal receive clock RSPEN 1 Receive enable SLEN 1111 16 bit data word TFSR RFSR 1 Transmit and receive frame sync Rev A Page 31 of 36 AD7322 APPLICATION HINTS LAYOUT AND GROUNDING The printed circuit board that houses the AD7322 should be designed so that the analog and digital sections are confined to certain areas of the board This design facilitates the use of ground planes that can easily be separated To provide optimum shielding for ground planes a minimum etch
56. utoshutdown The track and hold is in hold mode during autoshutdown On the rising CS edge the track and hold which was in hold during shutdown returns to track as the AD7322 begins to power up The power up from autoshutdown is 500 ps When the control register is programmed to transition to autoshut down mode it does so on the 15 SCLK rising edge Figure 47 shows the part entering autoshutdown mode Once in autoshut down mode the CS signal must remain low to keep the part in autoshutdown mode The AD7322 automatically begins to power up on the CS rising edge The tvowrr u for autoshutdown is reguired before a valid conversion initiated by bringing the CS signal low can take place When this valid conversion is complete the AD7322 powers down again on the 15 SCLK rising edge The CS signal must remain low again to keep the part in autoshutdown mode PART BEGINS TO POWER UP ON CS RISING EDGE Tee TA PART ENTERS SHUTDOWN MODE ON THE 15TH RISING SCLK EDGE AS PM1 1 PM0 0 SCLK SDATA VALID DATA DIN DATA INTO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS PM1 gt 1 PMO AUTOSTANDBY MODE PM1 0 PMO 1 In autostandby mode portions of the AD7322 are powered down but the on chip reference remains powered up The reference bit in the control register should be 1 to ensure that the on chip reference is enabled This mode is similar to auto shutdown but allows the AD7322 to p
57. uts true differential inputs or pseudo differential inputs see Table 10 7 6 PM1 PMO The power management bits are used to select different power mode options on the AD7322 see Table 11 5 Coding This bit is used to select the type of output coding the AD7322 uses for the next conversion result If coding 0 the output coding is twos complement If coding 1 the output coding is straight binary When operating in sequence mode the output coding for each channel is the value written to the coding bit during the last write to the control register 4 Ref The reference bit is used to enable or disable the internal reference If Ref 0 the external reference is enabled and used for the next conversion and the internal reference is disabled If Ref 1 the internal reference is used for the next conversion When operating in sequence mode the reference used for each channel is the value written to the Ref bit during the last write to the control register 3 2 Seq1 Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer see Table 12 Table 10 Analog Input Configuration Selection Channel Address Bit Mode 1 1 Mode 0 1 Mode 1 1 Mode 0 0 1 Fully Differential Input Mode 1 0 Mode 0 1 1 Pseudo Differential Input Mode 1 0 Mode0 0 2 Single Ended Inputs ADDO Vint Vin Vint Vin Vint Vin Vint Vin 0 Not allowed ViNO Vin1 ViNO ViN1 ViNO AGND 1 Not all
58. voltages it is recommended that these supplies be symmetrical For the 0 V to 4 x Vrer range Vss can be tied to AGND as per minimum supply recommendations outlined in Table 6 Table 16 Nonsymmetrical Vpp and Vss Requirements Vo Typical Vss Range 5V 5 V to 5 5 V 6V 5 V to 8 5 V 7V 5 V to 11 5 V 8V 5Vto 15V 9V 5 V to 16 5 V 10V to 16 5 V 5 V to 16 5 V Rev A Page 32 of 36 OUTLINE DIMENSIONS COPLANARITY 0 49 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB 1 Figure 54 14 Lead Thin Shrink Small Outline Package TSSOP Dimensions show in millimeters 061908 A AD7322 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7322BRUZ 40 C to 85 C 14 Lead TSSOP RU 14 AD7322BRUZ REEL 40 C to 85 C 14 Lead TSSOP RU 14 AD7322BRUZ REEL7 40 C to 85 C 14 Lead TSSOP RU 14 EVAL AD7322CBZ EVAL CONTROL BRD2Z Evaluation Board Controller Board Z RoHS Compliant Part This can be used as a standalone evaluation board or in conjunction with the EVAL CONTROL board for evaluation demonstration purposes 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators To order a complete evaluation kit the particular ADC evaluation board for example EVAL AD7322CBZ the EVAL CONTROL BRD2Z and a 12 V transformer must be ordered See the relevant evalu
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ANALOG DEVICES AD7322 English products handbook