Home

ANALOG DEVICES AD6655 English products handbook Rev A

1. WHO 9 gu 48 2 lt a g i 5 2 et M9 OTs r 9 s 3 3 5 5 4 2 WHO 925 gt Figure 85 Evaluation Board Schematic Channel A Analog Inputs Rev A Page 64 of 88 002 60 90 AD6655 8 3 8 8 noo zm 958 E ns E SNIA WHO 0 VVV 280 ZISCSNSH wo QaAv m nro 1 T WHO 0 A m M go ZISZSWSH noo TWO ad ad HLYd LAdNI H3ldlTdAV Ln v33aa Ti ia ANN e E kd gt 9 9 ial 2 1 11 e 1o 5 B TH 2 m 5 m 84 46 EL f wi lt PPM lt g 2 i E 2 zoek nro WHOO nro ANN 6 vvv 998 nro WHO OL 19 NIV Figure 86 Evaluation Board Schematic Channel B Analog Inputs Rev A Page 65 of 88 AD6655 202 6090 8 2 WHO6 v2 5 5 520 x 8 5 amp ill est 2 5 5 2 5 zoo Ds x g z a E 3 O a 078 0 001U
2. Digital Input 52 SYNC Input Digital Synchronization Pin Slave mode only Digital Outputs 12 DOA LSB Output Channel A CMOS Output Data 13 D1A Output Channel A CMOS Output Data 14 D2A Output Channel A CMOS Output Data 15 D3A Output Channel A CMOS Output Data 16 D4A Output Channel A CMOS Output Data 17 D5A Output Channel A CMOS Output Data 18 D6A Output Channel A CMOS Output Data 19 D7A Output Channel A CMOS Output Data 22 D8A Output Channel A CMOS Output Data 23 D9A Output Channel A CMOS Output Data 25 D10A Output Channel A CMOS Output Data 26 D11A Output Channel A CMOS Output Data 27 D12A Output Channel A CMOS Output Data 28 D13A MSB Output Channel A CMOS Output Data 58 DOB LSB Output Channel B CMOS Output Data 59 D1B Output Channel B CMOS Output Data 60 D2B Output Channel B CMOS Output Data 61 D3B Output Channel B CMOS Output Data 62 D4B Output Channel B CMOS Output Data 63 D5B Output Channel B CMOS Output Data 2 D6B Output Channel B CMOS Output Data 3 D7B Output Channel B CMOS Output Data 4 D8B Output Channel B CMOS Output Data 5 D9B Output Channel B CMOS Output Data 6 D10B Output Channel B CMOS Output Data 7 D11B Output Channel B CMOS Output Data 8 D12B Output Channel B CMOS Output Data 9 D13B MSB Output Channel B CMOS Output Data 11 DCOA Output Channel A Data Clock Output DCOB Output Channel B Data Clock Output
3. The fast detect pins are FDOA FDOB to FD3A FD3B for the CMOS mode configuration and FD0 FD0 to FD3 FD3 for the LVDS mode configuration See the ADC Overrange OR and Gain Switching sections for more information about OR C_UT F_UT F_LT IG and DG ADC FAST MAGNITUDE When the fast detect output pins are configured to output the ADC fast magnitude that is when the fast detect mode select bits are set to 0b000 the information presented is the ADC level from an early converter stage with a latency of only two clock cycles in CMOS output modes In LVDS output mode the fast detect bits have a latency of six cycles in all fast detect modes Using the fast detect output pins in this configuration provides the earliest possible level indication information Because this information is provided early in the datapath there is signifi cant uncertainty in the level indicated The nominal levels along with the uncertainty indicated by the ADC fast magnitude are shown in Table 22 Because the DCO is at one half the sample rate the user can obtain all the fast detect information by sampling the fast detect outputs on both the rising and falling edge of DCO see Figure 2 for timing information Table 22 ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits 000 ADC Fast Nominal Input Nominal Input Magitude on Magnitude Magnitude FD 3 0 Pins Below FS dB Uncertainty dB 0000 lt 24 Minimum to
4. Table 20 FIR Filter Coefficients COMBINED FILTER PERFORMANCE Coefficient Normalized Decimal Coefficient The combined response of the half band filter and the FIR filter Number Coefficient 21 Bit is shown in Figure 74 The act of bandlimiting the ADC data with C65 0 0001826 383 the half band filter ideally provides a 3 dB improvement in the C1 C64 0 0006824 1431 SNR at the expense of the sample rate and available bandwidth C2 C63 0 0009298 1950 of the output data As a consequence of finite math additional C3 C62 0 0000458 96 quantization noise is added to the system due to truncation in C61 0 0012689 2661 the NCO and half band As a consequence of the digital filter C5 C60 0 0008345 1750 rejection of out of band noise assuming no quantization in the C6 C59 0 0011806 2476 filters and with a white noise floor from the ADC there should C7 C58 0 0011387 2388 bea 3 16 dB improvement in the ADC SNR However the added C8 C57 0 0018439 3867 quantization lessens improvement to about 2 66 dB C9 C56 0 0024557 5150 0 C10 C55 0 0018063 3788 10 C11 C54 0 0035825 7513 20 C12 C53 0 0021510 4511 C13 C52 0 0056810 11914 S dn C14 C51 0 0017405 3650 C15 C50 0 0078602 16484 16 49 0 0013437 2818 a C17 C48 0 0110626 23200 C18 C47 0 0000229 48 C19 C46 0 0146618 30748 20 45 0 0018959 3976 21 C21 C44 0 0195594 41019 110 0 02 0 3 0 4 5 C22
5. SPI Control 48 SCLK DFS Input SPI Serial Clock Data Format Select Pin in External Pin Mode 47 SDIO DCS Input Output SPI Serial Data l O Duty Cycle Stabilizer Pin in External Pin Mode 51 CSB Input SPI Chip Select Active low Signal Monitor Port 33 SMI SDO OEB Input Output Signal Monitor Serial Data Output Output Enable Input Active Low in External Pin Mode 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync 34 SMI SCLK PDWN Input Output Signal Monitor Serial Clock Output Power Down Input Active High in External Pin Mode Rev A Page 20 of 88 DRVDD D1 D1 2 2 4 D4 DCO 10 DCO 11 5 12 D5 13 6 14 D6 15 D7 16 NOTES 1 THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION Figure 4 PIN 1 47 INDICATOR AD6655 64 DRGND 63 00 LSB 62 DO LSB 61 FD3 60 FD3 59 FD2 58 FD2 57 DVDD 56 FD1 55 FD1 54 00 53 52 SYNC 51 CSB 50 CLK 49 CLK 8 SCLK DFS 7 SDIO DCS EXPOSED PADDLE PIN 0 BOTTOM OF PACKAGE AD6655 PARALLEL LVDS TOP VIEW Not to Scale 4 SMI SCLK PDWN 3 SMI SDO OEB D7 17 D8 18 D8 19 DRGND 20 DRVDD 21 D9 22 D9 23 DVDD 24 10 25 D10 26 D11 27 D11 28 12 29 D12 30 D13 MSB 31 D13 MSB 32 06709 0
6. Load Regulation 1 0 mA Full 7 7 mV INPUT REFERRED NOISE VREF 1 0V 25 C 0 85 0 85 LSB rms ANALOG INPUT Input Span VREF 1 0 V Full 2 2 V p p Input Capacitance Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kQ POWER SUPPLIES Supply Voltage AVDD DVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 V DRVDD CMOS Mode Full 1 7 33 3 6 1 7 3 3 3 6 V DRVDD LVDS Mode Full 1 7 1 8 1 9 1 7 1 8 1 9 V Supply Current 2 3 Full 235 315 mA 2 3 Full 175 225 3 3 V CMOS Full 18 21 mA 1 8 V CMOS Full 8 11 mA 1 8 V LVDS Full 55 56 mA POWER CONSUMPTION DC Input Full 470 490 620 650 mW Sine Wave Input DRVDD 1 8V Full 755 995 mW Sine Wave Input DRVDD 3 3 V Full 800 1040 mW Standby Power Full 52 68 mW Power Down Power Full 2 5 8 2 5 8 mW Input capacitance refers to the effective capacitance between one differential input pin and AGND See Figure 11 for the equivalent analog input structure 2 Measured with 9 7 MHz full scale sine wave input NCO enabled with a frequency of 13 MHz FIR filter enabled and the fs 8 output mix enabled with approximately 5 pF loading on each output bit 3 The maximum limit applies to the combination of lavop and currents Standby power is measured with a dc input and with the CLK pin inactive set to AVDD or AGND Rev A Page 5 of 8 AD6655 ADC DC SPECIFICATIONS AD6655BCPZ 125 AD6655BCPZ 150 A
7. VS C145 0 1U d E M 18 8 2 n 9 TS Po 8 e 2 9 E 2 5 e E 8 z 2 2 T gt E Jam o S WOOL S o o 2 2 Figure 87 Evaluation Board Schematic DUT Clock Input Rev A Page 66 of 88 AD6655 02 60290 g 9 Smg LNO SA nro nro ure 019 OXDA amp 3S3H 43939 0109 05 2850 8 82 82 2 ee a 2 BR eee 885 8 Ladd D 02 eu 02 nro 03 91 o e B pino 104100 us no 1 N 100 Gov 681n0 QNO Are S 2110 SA I X NI 10 002 teino MIO E ii 915607 wz fino E ERRA zn LNO SA 62110 SA x DNAS 05 904199 91560v OL e No BS J3H 34M 3S 43 orv mw 4 OL 53 d9 90 De 1934M 0 8 moo un B Y Gs mno I pnn amp mno Frid SN M SA lt lt P 2 o 0 2 8 S Ses 8 6g 2 2 2 6 g 32 5 4 4 227 140 000 ous va S NINO m 2
8. 0603 1 10 W 1 resistor 0603 Components NRCO6F1403TRF 26 1 R14 147 0603 1 10 W 1 resistor R0603 NIC Components NRCO6F1473TRF 27 1 R15 78 7 kO 0603 1 10 W 196 resistor R0603 NIC Components NRCO6F7872TRF Rev A Page 82 of 88 AD6655 Reference Item Qty Designator Description Package Manufacturer Mfg Part Number 28 1 R16 261 O 0603 1 10 W 1 resistor R0603 NIC Components NRCO6F2610TRF 29 3 R17 R22 R23 100 kQ 0603 1 10 W 1 resistor R0603 NIC Components NRCO6F1003TRF 30 7 R18 R24 R63 R65 10 0402 1 16 W 1 resistor R04025M NIC Components NRCO4F1002TRF R82 R118 R140 31 R19 R21 1 0603 1 10 W 1 resistor R0603 NIC Components NRCO6F1001TRF 32 9 R26 R27 R43 33 0402 1 16 W 5 resistor 04025 Components NRC04J330TRF R46 R47 R70 R71 R73 R74 33 5 R57 R59 to R62 22 16 8 resistor 742 CTS Corporation 742C163220JPTR resistor array 34 1 R58 22 0 8 4 resistor RES_ARRY CTS Corporation 742C083220JPTR resistor array 35 1 R76 200 0402 1 16 W 1 resistor 04025 Components NCRO4F2000TRF 36 4 S2 3 55 12 SMA inline male SMA EDGE Emerson Network 142 0701 201 coaxial connector Power 37 1 5135 1 8 W 1 resistor SLDR_PAD2MUYLAR NIC Components NRC10ZOTRF 38 5 1 to T5 Balun TRAN6B M A COM MABA 007159 000000 39 1 U1 IC AD6655 LFCSP64 9X9 9E A
9. 2 0 amp 5 3 2 O d gos ids a a 8 soaroias ias ias 8 aaa zaon 2 80 0 9 57 apNA 2 mo H s asw geld gg99qVv asnas 0 wood EES x V NIA M NIA D00 vod E 9L 2 l asrvoa vann Ie Ni 2 Hi el 9 via H sas uma 26 a YOSTIVLSNI x ons NMad nos uMd 8 B 5 MON NvVdS 1fldNIAZ A3HA AIHOJTTV LSNI Sf 52 24515586585 X X 5 3 E 5 55245555 586888 NvdSLAdNI AIH3HA AS 0 HOJTTV LSNI 5 8 8 8 a 8 a 8 8 1000 8 a AIEVSIGLNdLNOYOSTIVLSNI 8f NMddYOSTIVLSNI Zf 5405 Figure 90 Evaluation Board Schematic DUT Rev A Page 69 of 88 AD6655 902 60 90 nro 920 8 lt 4 923 is 09 1 0s 199 SA ol 00 5405 m lt 0 WHOO 2 m NN HOO i VVV i as ee 245 SA 913539 QZINH
10. Soft reset LSB first 0x18 The nibbles are mirrored so that LSB first or MSB first mode registers correctly regardless of shift mode 0x01 Chip ID Global 8 bit Chip ID 7 0 AD6655 0 00 default 0x0D Default is unique chip ID different for each device this is a read only register 0x02 Chip Grade Global Open Open Speed Grade ID 4 3 00 2 150 MSPS 01 125 MSPS 10 105 MSPS 11 80 MSPS Speed grade ID used to differentiate devices this is a read only register Channel Index and Transfer Registers 0x05 Channel Index Open Open Open Open Open Open Data Channel B default Data Channel A default 0x03 Bits are set to determine which device on chip receives the next write command applies to local registers OxFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Fun ction Registers 0x08 Power Modes Open Open External power down pin function global 0 pdwn 1 stndby Open Open Open Internal power down mode local 00 normal operation 01 full power down 10 standby 11 normal operation 0x00 Determines various generic modes of chip operation 0x09 Global Clock
11. THE EXPOSED PAD REFER L IHHHHHHHHHHHHHHHLEG Y 0 02 NOM FUNGHON DESCRIPTIONS SEATING 0 30 SECTION OF THIS DATA SHEET PLANE 0 23 0 20 0 18 COMPLIANT JEDEC STANDARDS MO 220 VMMD 4 Figure 103 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 mm x 9 mm Body Very Thin Quad CP 64 3 Dimensions shown in millimeters 0 60 0 60 _ INDICATOR PIN 1 INDICATOR 0 50 7 65 TOP VIEW BSC EXPOSED PAD 7 50SQ BOTTOM VIEW 7 35 0 50 0 40 030 0 25 MIN 100 12 MAX 0 80 MAX 0 85 0 65 FOR PROPER CONNECTION OF THE EXPOSED PAD REFER THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET COMPLIANT TO JEDEC STANDARDS MO 220 VMMD 4 Figure 104 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 mm x 9 mm Body Very Thin Quad CP 64 6 Dimensions shown in millimeters Rev A Page 84 of 88 080108 C 041509 A ORDERING GUIDE Model AD6655ABCPZ 150 AD6655ABCPZ 125 AD6655ABCPZ 105 AD6655ABCPZ 80 AD6655ABCPZRL7 150 AD6655ABCPZRL7 125 AD6655BCPZ 150 AD6655BCPZ 125 AD6655BCPZ 105 AD6655BCPZ 80 AD6655 125EBZ AD6655 150EBZ 17 RoHS Compliant Part Temperature Range Package Description 64 Lead Lead Frame Chip Scale Package LFCSP VQ 64 Lead Lead Frame Chip Scale Package LFCSP VQ 64 Lead Lead Frame Chip Scale Package LFCSP VQ 64 Lead Lead Frame Chip Sca
12. s SMI SDFS OYA Figure 8 Signal Monitor SPORT Output Timing Rev A Page 17 of 88 AD6655 ABSOLUTE MAXIMUM RATINGS Ambient Table 10 Parameter Rating ELECTRICAL AVDD DVDD to AGND 0 3V to 2 0V DRVDD to DRGND 0 3V to 43 9 V AGND to DRGND 0 3V to 40 3 V VIN A VIN B VIN A VIN B to AGND 0 3 V to AVDD 0 2 V CLK CLK to AGND 0 3V to 43 9 V SYNC to AGND 0 3V to 43 9 V VREF to AGND 0 3 V to AVDD 0 2 V SENSE to AGND 0 3 V to AVDD 0 2 V CML to AGND 0 3 V to AVDD 0 2 V RBIAS to AGND 0 3 V to AVDD 0 2 V CSB to AGND 0 3 V to 3 9 V SCLK DFS to DRGND 0 3 V to 3 9 V SDIO DCS to DRGND 0 3 V to DRVDD 0 3 V SMI SDO OEB to DRGND 0 3 V to DRVDD 0 3 V SMI SCLK PDWN to DRGND 0 3 V to DRVDD 0 3 V SMI SDFS to DRGND 0 3 V to DRVDD 0 3 V DOA DOB through D13A D13B 0 3 V to DRVDD 0 3 V to DRGND FDOA FDOB through FD3A FD3Bto 0 3 V to DRVDD 0 3 V DRGND DCOA DCOB to DRGND 0 3 V to DRVDD 0 3 V ENVIRONMENTAL Operating Temperature Range 40 to 85 C Ambient Maximum Junction Temperature 150 C Under Bias Storage Temperature Range 65 C to 125 C THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package Soldering the exposed paddle to the customer board increases the reliability of the solder joints maximizing the thermal capability of the package Table 11 Thermal Resist
13. 1 25 1 00 0 75 1 25 0 75 0 50 0 25 Rev A Page 34 of 88 TOTAL POW 0 25 50 75 100 SAMPLE RATE MSPS 125 150 Figure 64 AD6655 150 Power and Current vs Sample Rate TOTAL POWER 25 SAMPLE RATE MSPS 50 75 100 0 6 0 5 0 4 0 3 0 2 0 1 0 125 Figure 65 AD6655 125 Power Current vs Sample Rate TOTAL POWER 0 25 SAMPLE RATE MSPS 50 Figure 66 AD6655 105 Power and Current vs Sample Rate SUPPLY CURRENT A SUPPLY CURRENT A SUPPLY CURRENT A 06709 065 06709 166 06709 167 AD6655 0 75 0 3 TOTAL POWER E g t 5 4 0 50 02 5 gt lt d 2 0 25 IDRVDD M M 4 0 0 20 40 60 80 SAMPLE RATE MSPS Figure 67 AD6655 80 Power and Current vs Sample Rate 06709 168 By asserting PDWN either through the SPI port or by asserting the PDWN pin high the AD6655 is placed in power down mode In this state the ADC typically dissipates 2 5 mW During power down the output drivers are placed in a high impedance state Asserting the PDWN pin low returns the AD6655 to its normal operating mode Note that PDWN is referenced to the digital output driver supply DRVDD and should not exceed that supply voltage PDWN can be driven with
14. 50 pA Full 0 05 0 05 V CMOS Mode DRVDD 1 8V High Level Output Voltage lou 50 Full 1 79 1 79 V lou 0 5 mA Full 1 75 1 75 V Low Level Output Voltage lo 1 6 mA Full 0 2 0 2 V lo 50 pA Full 0 05 0 05 V LVDS Mode DRVDD 1 8V Differential Output Voltage VOD Full 250 350 450 250 350 450 mV ANSI Mode Output Offset Voltage VOS Full 1 15 1 25 1 35 1 15 1 25 1 35 V ANSI Mode Differential Output Voltage VOD Full 150 200 280 150 200 280 mV Reduced Swing Mode Output Offset Voltage VOS Full 1 15 1 25 1 35 1 15 1 25 1 35 V Reduced Swing Mode Pull up Pull down Rev A Page 12 of 88 AD6655 SWITCHING SPECIFICATIONS AD6655BCPZ 80 AD6655BCPZ 105 Table 7 AD6655BCPZ 80 AD6655BCPZ 105 Parameter Temp Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate DCS Enabled Full 20 80 20 105 MSPS DCS Disabled Full 10 80 10 105 MSPS CLK Period Divide by 1 Mode tax Full 12 5 9 5 ns CLK Pulse Width High taxu Divide by 1 Mode DCS Enabled Full 3 75 625 8 75 285 4 75 6 65 ns Divide by 1 Mode DCS Disabled Full 563 625 688 428 475 5 23 ns Divide by 2 Mode DCS Enabled Full 1 6 1 6 ns Divide by 3 Through Divide by 8 Modes DCS Enabled Full 0 8 0 8 ns DATA OUTPUT PARAMETERS DATA FD CMOS Noninterleaved Mode DRVDD 1 8 V Data Propagation Delay tpo Full 1 6 3 9 6 2 1 6 3 9 6 2 ns DCO Propagation Delay toco Full 4
15. DRVDD 3 3 V Full 1275 1450 mW Standby Power Full 77 77 mW Power down Power Full 2 5 8 2 5 8 mW Input capacitance refers to the effective capacitance between one differential input pin and AGND See Figure 11 for the equivalent analog input structure 2 Measured with 9 7 MHz full scale sine wave input NCO enabled with a frequency of 13 MHz FIR filter enabled and the fs 8 output mix enabled with approximately 5 pF loading on each output bit 3 The maximum limit applies to the combination of lavop and lovop currents 4 Standby power is measured with a dc input the CLK pin inactive set to AVDD or AGND Rev A Page 6 of 8 ADC AC SPECIFICATIONS AD6655BCPZ 80 AD6655BCPZ 105 AVDD 1 8 V DVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled NCO enabled half band filter enabled FIR filter enabled unless otherwise noted AD6655 Table 3 AD6655BCPZ 80 AD6655BCPZ 105 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL TO NOISE RATIO SNR fin 2 4 MHz 25 C 74 9 74 8 dB fin 70 MHz 25 C 74 8 74 7 Full 73 0 73 0 dB fin 140 MHz 25 C 74 5 74 3 dB fin 220 MHz 25 C 73 4 73 4 dB WORST SECOND OR THIRD HARMONIC fin 2 4 MHz 25 C 86 86 dBc fin 70 MHz 25 C 85 85 dBc Full 74 74 dBc fin 140 MHz 25 C 84 84 dBc fin 220 MHz 25 C 83 83 dBc SPURIOUS FREE DYNAMIC RANGE SFDR fin
16. dino x ic Optional AD9516 Clock Circuit Figure 88 Evaluation Board Schemati Rev A Page 67 of 88 AD6655 WHO OL 702 60290 g Sole 8 T VVV 8 71 5 5 WHO g 3 WHO 8 8 gt 52 lt 8 ope eg a 9 5 5 gt WHO WHO WHO WHO VV 9016 8014 lt a 2 x o WHO 18H S 8 z 5 E 5 gt s 4 i z a Li 5 2 a 5 9 8 i 84 e i 3 d g 9 8 28 EE e ig o z o0 8 2 Ons x 9 2 2 9 cones 2 WHO a o 5 R136 a BYPASS 100 Figure 89 Evaluation Board Schematic Optional AD9516 Loop Filter VCO and SYNC Input Rev A Page 68 of 88 AD6655 902 604 niooo nro nro 1819 6019 10070 2210 Ua 8 8 a S nro nro miooo ni000 ozto Oro 9219 4215 E 8 5 8 3 3 8 5 5 9 L 9 29 Oo
17. impedance matching from 70 MHz to 200 MHz For more bandwidth response the differ ential capacitor across the analog inputs can be changed or removed see Table 14 The common mode of the analog inputs is developed from the center tap of the transformer via the CML pin of the ADC see the Analog Input Considerations section VREF VREF is set to 1 0 V by tying the SENSE pin to ground by adding a jumper on Header J5 Pin 1 to Pin 2 This causes the ADC to operate in 2 0 V p p full scale range To place the ADC in 1 0 V p p mode VREF 0 5 V a jumper should be placed on Header J4 A separate external reference option is also included on the evalua tion board To use an external reference connect J6 Pin 1 to Pin 2 and provide an external reference at TP5 Proper use of the VREF options is detailed in the Voltage Reference section RBIAS RBIAS requires 10 resistor R503 to ground and is used to set the ADC core bias current CLOCK The default clock input circuitry is derived from a simple balun coupled circuit using a high bandwidth 1 1 impedance ratio balun T5 that adds a very low amount of jitter to the clock path The clock input is 50 Q terminated and ac coupled to handle single ended sine wave inputs The transformer converts the single ended input to a differential signal that is clipped before entering the ADC dock inputs When the AD6655 input clock divider is utilized clock frequencies up to 625 MHz can
18. tem ie eR 29 Analog Input Considerations eee 29 Voltage References 31 Clock Input Considerations sees 32 Power Dissipation and Standby Mode 34 Digital Outputs ierit tine ide 35 Digital Downconverter sseseeeeneeteetetenttntentntennen 37 Downconverter Modes sse 37 Numerically Controlled Oscillator NCO 37 Half Band Decimating Filter and FIR Filter 37 fanc 8 Fixed Frequency NCO sse 37 Numerically Controlled Oscillator NCO 38 Frequency Translation eee 38 Synchronization eerte 38 Phase Offset ode eti teo e n ete etate 38 NCO Amplitude and Phase Dither sss 38 Decimating Half Band Filter and FIR filter 39 Half Band Filter Coefficients sse 39 Half Band Filter Features sete 39 Fixed Coefficient FIR Filter sees 39 Synchronization eig REIR ERE 40 Combined Filter Performance see 40 Einal NGOs 40 ADC Overrange and Gain Control sss 41 Fast Detect Overview ADC Fast Magnitude irme gere 41 ADG Overrange OR eire 42 Gain SwitchiDg
19. cost sensitive applications In this configuration SFDR and distortion performance degrade due to the large input common mode swing If the source impedances on each input are matched there should be little effect on SNR performance Figure 51 shows a typical single ended input configuration AVDD 10 AD6655 S e m 06709 053 Figure 51 Single Ended Input Configuration VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD6655 The input range can be adjusted by varying the reference voltage applied to the AD6655 using either the internal reference or an externally applied reference voltage The input span of the ADC tracks reference voltage changes linearly The various reference modes are summarized in the sections that follow The Reference Decoupling section describes the best practices PCB layout of the reference Internal Reference Connection A comparator within the AD6655 detects the potential at the SENSE pin and configures the reference into four possible modes which are summarized in Table 15 If SENSE is grounded the reference amplifier switch is connected to the internal resistor divider see Figure 52 setting VREF to 1 0 V Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin completing the loop and providing a 0 5 V reference output If a resistor divider is connected externally to the chip as shown in Figure 53 the sw
20. eoeoeo e eo Figure 99 Evaluation Board Layout Ground Plane Rev A Page 78 of 88 06709 104 nin ui Figure 100 Evaluation Board Layout Secondary Side Mirrored Image Rev A Page 79 of 88 AD6655 AD6655 wo ANALOG 09640 MsomsPs POWER IN DEVICES MAD9627 5 5 5 6VDC MAD6655 25 5 5 n diis MAD6653 Mi50MSPS ts PWRIN 4 3 C135 X r2 AMPVDD P4 6 PWR lt PWR ON gt lt 5 2 79 420 4 pvoo 275 29 GND RL J18 v S oni AVDD J19 TP25 fee N DRVDDIN DVDD v DTG rud 1 aci S PDWN we T7 9 7281 1088 S RII J10 J CHANNEL A gt R110 TP7 2 253 R62 R61 U15 gt c27 9 pL GND 25 i 2 Te J 5 R60 u MATE 2 fup 5 5 cn 36 45 44 rs 4 DCOA c mc D DCOB 5 TP6 5 c E E D8B CH_B Fav TP16 S E 4 7 SZz GN s RING SDa 0 1378 146 GND 2 5 E J11 2519 oggi R57 58 peo CHANNEL B gt SC Bs R62 R51 lt lt R34 Do m GND R99 RN 1 ne Qu NC 8 2 0 pg x S 121 Ji E DA 1105 2sCOMP CSB DCS 58 25 c99 31 1 ENABLE REF SEL CRS J14 SPI 010 E 53 LOCK 1 CLK 1 TP24
21. offset binary format of ANSI global local theidata LVDS 1Vto 1 8 V CMOS or reduced LVDS global 0x16 Clock Phase Invert Open Open Open Open Input clock divider phase adjust 0x00 Allows Control DCO clock 000 no delay selection of Global 001 1 input clock cycle clock delays 010 2 input clock cycles into the input 011 3 input clock cycles Ande 100 4 input clock cycles 101 5 input clock cycles 110 6 input clock cycles 111 7 input clock cycles 0x17 DCO Output Open Open Open DCO clock delay 0x00 Delay delay 2500 ps x register value 31 Global 00000 0 ps 00001 81 ps 00010 161 ps 11110 2419 ps 11111 2500 ps 0x18 VREF Select Reference voltage Open Open Open Open Open Open 0 0 Global selection 00 1 25 V p p 01 1 5 V p p 10 1 75 V p p 11 2 0 V p p default Digital Feature Control Registers 0x100 Sync Control Signal Half band Half band NCO32 NCO32 Clock Clock Master sync 0x00 Global monitor next sync sync next sync sync divider divider enable sync only enable only enable next sync enable sync enable only 0x101 6 8 Output Open Open 5 8 start state Open Open 5 8 next 6 8 sync 0x00 Mix Control synconly enable Global 0x102 FIR Filter and Open Open Open Open FIR gain 6 8 Complex FIR filter 0x00 Output Mode 0 gain of output output enable Control 2 mix enable Global 1 gain of disable 1 0x103 Digital Filter Open Open Open Open Half band Spectral High pass Open 0x01 Control deci
22. output enable and power down feature control In this mode the CSB chip select should be connected to AVDD which disables the serial port interface Table 27 Mode Selection AD6655 SPI ACCESSIBLE FEATURES Table 28 provides a brief description of the general features that are accessible via the SPI These features are described in detail in Application Note AN 877 Interfacing to High Speed ADCs via SPI see www analog com The AD6655 part specific features are described in the Memory Map Register Description section Table 28 Features Accessible Using the SPI Feature Name Description Mode Allows the user to set either power down mode or standby mode Clock Offset Test I O Output Mode Output Phase Output Delay VREF Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage External Pin Voltage Configuration SDIO DCS AVDD default Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled SCLK DFS AVDD Twos complement enabled AGND default Offset binary enabled SMI SDO OEB AVDD Outputs in high impedance AGND default Outputs enabled SMI SCLK PDWN AVDD Chip in power down or
23. path enable DC correction for signal monitor enable 0x00 0x10D Signal Monitor DC Value Channel A Register 0 Global DC Value Channel A 7 0 Read only Ox10E Signal Monitor DC Value Channel A Register 1 Global Open Open DC Value Channel A 13 8 Read only Ox10F Signal Monitor DC Value Channel B Register 0 Global DC Value Channel B 7 0 Read only 0x110 Signal Monitor DC Value Channel B Register 1 Global Open Open DC Value Channel B 13 8 Read only 0 111 Signal Monitor SPORT Control Global Open RMS magnitude output enable Peak detector output enable Threshold crossing output enable SPORT SMI SCLK divide 00 Undefined 01 divide by 2 10 divide by 4 11 2 divide by 8 SPORT SMI SCLK sleep Signal monitor SPORT output enable 0x04 Rev A Page 53 of 88 AD6655 Default Default Addr Register Bit 7 Bit 0 Value Notes Hex Name MSB Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Hex Comments 0x112 Signal Complex Open Open Open Signal Signal monitor mode Signal 0x00 Monitor power monitor 00 rms ms monitor Control calculation rms ms magnitude enable Global mode select 01 peak detector enable 0 rms 10 threshold crossing 1 ms 11 threshold crossing 0x113 Signal Signal Monitor Period 7 0 0x80 In ADC clock
24. 1 8 V logic even when DRVDD is at 3 3 V Low power dissipation in power down mode is achieved by shutting down the reference reference buffer biasing networks and clock Internal capacitors are discharged when entering power down mode and then must be recharged when returning to normal operation As a result wake up time is related to the time spent in power down mode and shorter power down cycles result in proportionally shorter wake up times When using the SPI port interface the user can place the ADC in power down mode or standby mode Standby mode allows the user to keep the internal reference circuitry powered when faster wake up times are required See the Memory Map Register Description section and Application Note AN 877 Interfacing to High Speed ADCs via SPI at www analog com for additional details DIGITAL OUTPUTS The AD6655 output drivers can be configured to interface with 1 8 V to 3 3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic Alternatively the AD6655 outputs can be configured for either ANSI LVDS or reduced drive LVDS using a 1 8 V DRVDD supply In CMOS output mode the output drivers are sized to provide sufficient output current to drive a wide variety of logic families However large drive currents tend to cause current glitches on the supplies that may affect converter performance Applica tions requiring the ADC to drive large capacitive loads or large fanouts may
25. 150 FREQUENCY MHz 5 SAMPLE RATE MSPS Figure 39 AD6655 150 Two Tone FFT with 29 12 MHz 32 12 MHz Figure 42 AD6655 150 Single Tone SNR SFDR vs Sample Rate with fs 150 MSPS fuco 22 MHz fin 2 3 MHz Rev A Page 27 of 88 AD6655 o E 21 m 3 2 N i N N 1 2 OUTPUT CODE Figure 43 AD6655 Grounded Input Histogram 90 8 5 SFDR DCS 5 SFDR DCS 2 2 a SNR DCS ON 70 20 30 40 50 60 70 80 DUTY CYCLE 90 8 2 a amp 75 65 0 2 0 8 1 0 1 2 1 4 COMMON MODE VOLTAGE V Figure 45 AD6655 150 SNR SFDR vs Input Common Mode Vcm with fiy 30 3 MHz fuco 45 MHz 06709 042 06709 044 06709 043 Figure 44 AD6655 150 SNR SFDR vs Duty Cycle with 30 3 MHz fuco 45 MHz Rev A Page 28 of 88 THEORY OF OPERATION The AD6655 has two analog input channels two decimating channels and two digital output channels The intermediate frequency IF input signal passes through several stages before appearing at the output port s as a filtered decimated digital signal The dual ADC design can be used for diversity reception of signals where the ADCs operate identically on the same carrier but from two separate antennae The ADCs can also be operated with independent analog inputs The user can sample any fs 2 frequency
26. 2 4 MHz 25 86 86 dBc fin 70 MHz 25 C 85 85 dBc Full 74 74 dBc fin 140 MHz 25 C 84 84 dBc fin 220 MHz 25 83 83 dBc WORST OTHER HARMONIC OR SPUR fin 2 4 MHz 25 C 93 93 dBc fin 70 MHz 25 C 90 90 dBc Full 82 82 dBc fin 140 MHz 25 C 289 289 dBc fin 220 MHz 25 C 86 86 dBc TWO TONE SFDR 29 12 MHz 32 12 MHz 7 dBFS 25 C 85 85 dBc fin 169 12 MHz 172 12 MHz 7 dBFS 25 C 81 81 dBc CROSSTALK Full 95 95 dB ANALOG INPUT BANDWIDTH 25 C 650 650 MHz 1 See Application Note AN 835 Understanding High Speed ADC Testing and Evaluation for a complete set of definitions 2 See the Applications Information section for more information about the worst other specifications for the AD6655 3 Crosstalk is measured at 100 MHz with 1 dBFS on one channel and with no input on the alternate channel Rev A Page 7 of 8 AD6655 ADC AC SPECIFICATIONS AD6655BCPZ 125 AD6655BCPZ 150 AVDD 1 8 V DVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled NCO enabled half band filter enabled FIR filter enabled unless otherwise noted Table 4 AD6655BCPZ 125 AD6655BCPZ 150 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL TO NOISE RATIO SNR fin 2 4 MHz 25 C 74 7 74 6 fin 70 MHz 25 C 74 6 74 5 Full 73 0 72 5 dB fin 140 MHz 25 C 74 2 73 9 dB fin 220 MHz 25 C 73 3 73 0
27. DRVDD current can be higher than the typical value until the part is placed in LVDS mode This additional DRVDD current does not cause damage to the AD6655 but it should be taken into account when consid ering the maximum DRVDD current for the part Rev A Page 59 of 88 AD6655 To avoid this additional DRVDD current the AD6655 outputs can be disabled at power up by taking the OEB pin high After the part is placed into LVDS mode via the SPI port the OEB pin can be taken low to enable the outputs Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground AGND to achieve the best electrical and thermal performance A continuous exposed no solder mask copper plane on the PCB should mate to the AD6655 exposed paddle Pin 0 The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB These vias should be filled or plugged with nonconductive epoxy To maximize the coverage and adhesion between the ADC and the PCB a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections This provides several tie points between the ADC and the PCB during the reflow process Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB See the evaluation board for a PCB layo
28. High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 40 132 40 132 pA Input Resistance Full 26 26 Input Capacitance Full 2 2 pF LOGIC INPUT SCLK DFS High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 92 135 92 135 Low Level Input Current Full 10 10 10 10 Input Resistance Full 26 26 Input Capacitance Full 2 2 pF LOGIC INPUTS SDIO DCS SMI SDFS High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 38 128 38 128 Input Resistance Full 26 26 kQ Input Capacitance Full 5 5 pF Rev A Page 11 of 88 AD6655 AD6655BCPZ 125 AD6655BCPZ 150 Parameter Temp Min Typ Max Min Typ Max Unit LOGIC INPUTS SMI SDO OEB SMI SCLK PDWN High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 90 134 90 134 Low Level Input Current Full 10 10 10 10 Input Resistance Full 26 26 Input Capacitance Full 5 5 pF DIGITAL OUTPUTS CMOS Mode DRVDD 3 3 V High Level Output Voltage lou 50 Full 3 29 3 29 V lou 0 5 mA Full 3 25 3 25 V Low Level Output Voltage lo 1 6 mA Full 0 2 0 2 V lo
29. Monitor cycles Period Register 0 Global 0x114 Signal Signal Monitor Period 15 8 0x00 I In ADC clock Monitor cycles Period Register 1 Global 0x115 Signal Signal Monitor Period 23 16 0x00 In ADC clock Monitor cycles Period Register 2 Global 0x116 Signal Signal Monitor Result Channel A 7 0 Read only Monitor Result Channel A Register 0 Global 0x117 Signal Signal Monitor Result Channel A 15 8 Read only Monitor Result Channel A Register 1 Global 0x118 Signal Open Open Open Open Signal Monitor Result Channel A 19 16 Read only Monitor Result Channel A Register 2 Global 0x119 Signal Signal Monitor Result Channel B 7 0 Read only Monitor Result Channel B Register 0 Global Ox11A Signal Signal Monitor Result Channel B 15 8 Read only Monitor Result Channel B Register 1 Global 0x11B Signal Open Open Open Open Signal Monitor Result Channel B 19 16 Read only Monitor Result Channel B Register 2 Global 0x11D NCO Control Open Open Open Open Open NCO32 NCO32 NCO32 0x00 Global phase amplitude enable dither dither enable enable 0 11 NCO Frequency Value 7 0 0x00 Frequency 0 0 11 NCO Frequency Value 15 8 0x00 Frequency 1 0x120 NCO NCO Frequency Value 23 16 0x00 Frequency 2 Rev A Page 54 of 88 AD6655 Default Default Addr Register B
30. Output Enable Input Active Low in External Pin Mode 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync 34 SMI SCLK PDWN Input Output Signal Monitor Serial Clock Output Power Down Input Active High in External Pin Mode Rev A Page 22 of 88 AD6655 EQUIVALENT CIRCUITS 1 1k VIN SCLK DFS 26 Figure 11 Equivalent Analog Input Circuit Figure 15 Equivalent SCLK DFS Input Circuit 06709 004 06709 008 SENSE 19 Figure 12 Equivalent Clock Input Circuit Figure 16 Equivalent SENSE Circuit DRVDD AVDD 26kQ CSB DRGND 8 Figure 13 Equivalent Digital Output Circuit Figure 17 Equivalent CSB Input Circuit AVDD DRVDD DRVDD VREF 26kQ SDIO DCS Figure 14 Equivalent SDIO DCS Circuit or SMI SDFS Circuit Figure 18 Equivalent VREF Circuit Rev A Page 23 of 88 AD6655 TYPICAL PERFORMANCE CHARACTERISTICS AVDD 1 8 V DVDD 1 8 V DRVDD 1 8 V sample rate 150 MSPS DCS enabled 1 0 V internal reference 2 V p p differential input VIN 1 0 dBFS 64k sample T4 25 C NCO enabled FIR filter enabled unless otherwise noted In the FFT plots that follow the location of the second and third harmonics is noted when they fall in the pass band of the filter 150 5 5 2 4MHz 1dBFS SNR 74 7dBc 75 7dBFS SFDR 86 54 fuco 18 75MHz SECOND HARMONIC THIRD HARMONIC AMPLITUDE dBFS 0 5 10 15 20 25 30 35 FREQUENCY MH
31. cable for making connections to the evaluation board Enter the desired frequency and amplitude for the ADC The AD6655 evaluation board from Analog Devices Inc can accept a 2 8 V p p or 13 dBm sine wave input for the clock When connecting the analog input source it is recom mended that a multipole narrow band band pass filter with 50 terminations be used Band pass filters of this type are available from Allen Avionics and K amp L Microwave Inc Connect the filter directly to the evaluation board if possible OUTPUT SIGNALS The parallel CMOS outputs interface directly with the Analog Devices standard ADC data capture board HSC ADC EVALCZ For more information on the ADC data capture boards and their optional settings visit www analog com FIFO HSC ADC EVALCZ FPGA BASED DATA CAPTURE BOARD RUNNING VISUAL ANALOG AND SPI PARALLEL CONTROLLER CMOS SOFTWARE 14 BIT CMOS USB CONNECTION 06709 108 Figure 84 Evaluation Board Connection Rev A Page 61 of 88 AD6655 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD6655 evaluation board POWER Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500 VIN The evaluation board is set up for a double balun configuration analog input with optimum 50
32. characteristics and to estimate the peak average ratio or even the shape of the complementary cumulative distribution function CCDF curve of the input signal This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real world signals The signal monitor result values can be obtained from the part by reading back internal registers at Address 0x116 to Address 0x11B using the SPI port or the signal monitor SPORT output The output contents of the SPI accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register Address 0x112 Both ADC channels must be configured for the same signal monitor mode Separate SPI accessible 20 bit signal monitor result SMR registers are provided for each ADC channel Any combination of the signal monitor functions can also be output to the user via the serial SPORT interface These outputs are enabled using the peak detector output enable the rms magnitude output enable and the threshold crossing output enable bits in the signal monitor SPORT control register Address 0x1111 For each signal monitor measurement a programmable signal monitor period register SMPR controls the duration of the measurement This time period is programmed as the number of input clock cycles in a 24 bit signal monitor period register located at Address 0x113 Address 0x114 and Address 0x115 This register can be programmed wit
33. low enables the low pass mode default Bit 0 Reserved Bit 0 reads back 1 Fast Detect Control Register 0x104 Bits 7 4 Reserved Bits 3 1 Fast Detect Mode Select Bits 3 1 set the mode of the fast detect output bits according to Table 29 Bit 0 Fast Detect Enable Bit 0 is used to enable the fast detect output pins When the FD outputs are disabled the outputs go into a high impedance state In LVDS mode when the outputs are interleaved the outputs go high Z only if both channels are turned off power down standby output disabled If only one channel is turned off power down standby output disabled the fast detect outputs repeat the data of the active channel Coarse Upper Threshold Register 0x105 Bits 7 3 Reserved Bits 2 0 Coarse Upper Threshold These bits set the level required to assert the coarse upper threshold indication see Table 25 Fine Upper Threshold Register Ox106 and Register 0x107 Register 0x107 Bits 7 5 Reserved Register 0x107 Bits 4 0 Fine Upper Threshold Bits 12 8 Register 0x106 Bits 7 0 Fine Upper Threshold Bits 7 0 These registers provide a fine upper limit threshold The 13 bit value is compared to the 13 bit magnitude from the ADC block If the ADC magnitude exceeds this threshold value the F UT indicator is set Fine Lower Threshold Register 0x108 and Register 0x109 Register 0x109 Bits 7 5 Reserved Register 0x109 Bits 4 0 Fine Lowe
34. output data is routed through Port A with the ADC Channel A output data present on the rising edge of DCO and the ADC Channel B output data present on the falling edge of DCO Timing The AD6655 provides latched data with a pipeline delay that is dependent on which of the digital back end features are enabled Data outputs are available one propagation delay trp after the rising edge of the clock signal The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6655 These transients can degrade converter dynamic performance The lowest typical conversion rate of the AD6655 is 10 MSPS At clock rates below 10 MSPS dynamic performance may degrade Data Clock Output DCO The AD6655 also provides data clock output DCO intended for capturing the data in an external register Figure 2 through Figure 6 show a graphical timing description of the AD6655 output modes Rev A Page 35 of 88 AD6655 Table 17 Output Data Format Input V Condition V Offset Binary Output Mode Twos Complement Mode OR VIN VIN VREF 0 5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN VIN VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN VIN 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN VIN 4VREF 1 0 LSB 11111111111111 01 1111 1111 1111 0 VIN VIN gt VREF 0 5 LSB 11111111111111 01111111111111 1 Rev Page 36 of 88 AD6655 DIGITA
35. partitioning of the PCB analog digital and clock sections optimum performance is easily achieved f 2 Spurious Because the AD6655 output data rate is at one half the sampling frequency there is significant fs 2 energy in the outputs of the part If this fs 2 spur falls in band care must be taken to ensure that this fs 2 energy does not couple into either the clock circuit or the analog inputs of the AD6655 When fs 2 energy is coupled in this fashion it appears as a spurious tone reflected around fs 4 3fs 4 55 4 and so on For example a 125 MSPS sampling application with a 90 MHz single tone analog input this energy generates a tone at 97 5 MHz In this example the center of the Nyquist zone is 93 75 MHz therefore the 90 MHz input signal is 3 75 MHz from the center of the Nyquist zone As a result the fs 2 spurious tone appears at 97 5 MHz or 3 75 MHz above the center of the Nyquist zone These frequencies are then tuned by the NCOs before being output by the AD6655 Depending on the relationship of the IF frequency to the center of the Nyquist zone this spurious tone may or may not exist in the AD6655 output band Some residual fs 2 energy is present in the AD6655 and the level of this spur is typically below the level of the harmonics at clock rates of 125 MSPS and below Figure 82 shows a plot of the fs 2 spur level vs analog input frequency for the AD6655 125 At sampling rates above 125 MSPS the 5 2 spur level in
36. require external buffers or latches The output data format can be selected for either offset binary or twos complement by setting the SCLK DFS pin when operating in the external pin mode see Table 16 As detailed in Application Note AN 877 Interfacing to High Speed ADCs via SPI the data format can be selected for offset binary twos complement or gray code when using the SPI control Table 16 SCLK DFS Mode Selection External Pin Mode Voltage at Pin SCLK DFS SDIO DCS AGND default Offset binary DCS disabled AVDD Twos complement DCS enabled Digital Output Enable Function OEB The AD6655 has a flexible three state ability for the digital output pins The three state mode is enabled using the SMI SDO OEB pin or through the SPI interface If the SMI SDO OEB pin is low the output data drivers are enabled If the SMI SDO OEB pin is high the output data drivers are placed in a high impedance state This OEB function is not intended for rapid access to the data bus Note that OEB is referenced to the digital output driver supply DRVDD and should not exceed that supply voltage OEB can be driven with 1 8 V logic even when DRVDD is at 3 3 V When using the SPI interface the data and fast detect outputs of each channel can be independently three stated by using the output enable bar bit Bit 4 in Register 0x14 Interleaved CMOS Mode Setting Bit 5 in Register 0x14 enables interleaved CMOS output mode In this mode
37. s cete 42 Signal ei e 44 Peak Detector Mode ette retta 44 RMS MS Magnitude Mode sse 44 Threshold Crossing Mode 45 Additional Control sse 45 DC Correction 45 Signal Monitor SPORT Output sss 46 Channel Chip Synchronization see 47 Serial Port Interface SPI eene 48 Configuration Using the SPI see 48 Hardware Interface zoe t reete setius 48 Configuration Without the SPI sss 49 SPI Accessible Features 49 Memory REUNIR ERE RE 50 Reading the Memory Map Register 50 Memory Map Register Table sse 51 Memory Map Register Description sss 55 Applications Information 59 Design Guidelines rte 59 Evaluation Board eere ene eet 61 Power Supplies e DIRE ettet 61 Input 5 8 eei PEDE REID PRIORES 61 Rev A Page 2 of 88 Qutp t edet etis 61 Default Operation and Jumper Selection Settings 62 Alternative Clock Configurations eee 62 Alternative Analog Input Drive Configuration 63 Sclienidtics tetto tee s
38. segment from dc to 150 MHz using appropriate low pass or band pass filtering at the ADC inputs with little loss in ADC performance Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion In nondiversity applications the AD6655 can be used as a base band receiver where one ADC is used for I input data and the other is used for Q input data Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices The NCO phase can be set to produce a known offset relative to another channel or device Programming and control of the AD6655 are accomplished using a 3 bit SPI compatible serial interface ADC ARCHITECTURE AD6655 architecture consists of a front end sample and hold amplifier SHA followed by a pipelined switched capacitor ADC The quantized outputs from each stage are combined into a final 14 bit result in the digital correction logic The pipelined archi tecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples Sampling occurs on the rising edge of the clock Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor digital to analog converter DAC and an interstage residue amplifier MDAC The residue amplifier magnifies the difference between the reconstructed DAC output and the flash i
39. show an example of a 20 MHz input as it is processed by the blocks of the AD6655 06709 066 50 24 14 404 14 24 50 Figure 68 Example AD6655 Real 20 MHz Bandwidth Input Signal Centered at 14 MHz faoc 100 MHz 50 38 28 18 10 0 10 50 Figure 69 Example AD6655 20 MHz Bandwidth Input Signal Tuned to DC Using the NCO NCO Frequency 14 MHz 06709 067 50 38 28 18 10 0 10 50 Figure 70 Example AD6655 20 MHz Bandwidth Input Signal wth the Negative Image Filtered by the Half Band and FIR Filters 8 e 8 E 5 8 06709 069 50 0 25 12 5 22 5 50 Figure 71 Example AD6655 20 MHz Bandwidth Input Signal Tuned to fapc 8 for Real Output Rev A Page 37 of 88 AD6655 NUMERICALLY CONTROLLED OSCILLATOR NCO FREQUENCY TRANSLATION This processing stage comprises a digital tuner consisting of a 32 bit complex numerically controlled oscillator NCO The two channels of the AD6655 share a single NCO The NCO is optional and can be bypassed by clearing Bit 0 of Register 0x11D This NCO block accepts a real input from the ADC stage and outputs a frequency translated complex I and Q output The NCO frequency is programmed in Register 0x11E Register 0 11 Register 0 120 and Register 0x121 These four 8 bit registers make up a 32 bit unsigned frequency programming word Frequencies between 2 and CLK 2 are represented using the following frequency words 0 8000 0000 represents a freque
40. standby AGND default Normal operation t th E 05 9 gt ton CSB SCLK DON T CARE IGH 4 gt 1 1 1 1 DON T CARE Figure 81 Serial Port Interface Timing Diagram Rev A Page 49 of 88 06709 079 AD6655 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations The memory map is roughly divided into four sections the chip configuration registers Address 0x00 to Address 0x02 the channel index and transfer registers Address 0x05 and Address OxFF the ADC functions registers including setup control and test Address 0x08 to Address 0x18 and the digital feature control registers Address 0x100 to Address 0x123 The memory map register table see Table 29 documents the default hexadecimal value for each hexadecimal address shown The column with the heading Bit 7 MSB is the start of the default hexadecimal value given For example Address 0x18 the VREF select register has a hexadecimal default value of 0xCO0 This means that Bit 7 1 Bit 6 1 and the remaining bits are 08 This setting is the default reference selection setting The default value uses a 2 0 V p p reference For more information on this function and others see Application Note AN 877 Interfacing to High Speed ADCs via SPI T
41. that the loop is not locked the DCS loop is bypassed and internal device timing is dependent on the duty cycle of the input clock signal In such applications it may be appropriate to disable the duty cycle stabilizer In all other applications enabling the DCS circuit is recommended to maximize ac performance Jitter Considerations High speed high resolution ADCs are sensitive to the quality of the clock input The degradation in SNR at a given input frequency fx due to jitter 6 can be calculated by SNRur 10 x x tius 10 SNF In the equation the rms aperture jitter represents the root mean square of all jitter sources which include the clock input the analog input signal and the ADC aperture jitter specification IF undersampling applications are particularly sensitive to jitter as shown in Figure 63 Rev A Page 33 of 88 AD6655 SNR dBc 1 10 100 1000 INPUT FREQUENCY MHz 06709 064 Figure 63 SNR vs Input Frequency and Jitter The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6655 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators make the best clock sources If the clock is generated from anot
42. used a complex bandwidth of 22 of the input rate is available In the event of even Nyquist zone sampling the half band filter can be configured to provide a spectral reversal Setting Bit 2 high in Address 0x103 enables the spectral reversal feature The half band decimation phase can be selected such that the half band filter starts on the first or second sample following synchronization This shifts the output from the half band between the two input sample clocks The decimation phase can be set to 0 or 1 using Bit 3 of Register 0x103 FIXED COEFFICIENT FIR FILTER Following the half band filters is a 66 tap fixed coefficient FIR filter This filter is useful in providing extra alias protection for the decimating half band filter It is a simple sum of products FIR filter with 66 filter taps and 21 bit fixed coefficients Note that this filter does not decimate The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are listed in Table 20 The user can either select or bypass this filter but the FIR filter can be enabled only when the half band filter is enabled Writing Logic 0 to the enable FIR filter bit Bit 0 in Register 0x102 bypasses this fixed coefficient filter The filter is necessary when using the final NCO with a real output bypassing it when using other configurations results in power savings Rev A Page 39 of 88 AD6655
43. value Rev A Page 40 of 88 ADC OVERRANGE AND GAIN CONTROL In receiver applications it is desirable to have a mechanism to reliably determine when the converter is about to be clipped The standard overflow indicator provides after the fact infor mation on the state of the analog input that is of limited usefulness Therefore it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs In addition because input signals can have significant slew rates latency of this function is of major concern Highly pipelined converters can have significant latency A good compro mise is to use the output bits from the first stage of the ADC for this function Latency for these output bits is very low and overall resolution is not highly significant Peak input signals are typically between full scale and 6 dB to 10 dB below full scale A 3 bit or 4 bit output provides adequate range and resolution for this function Using the SPI port the user can provide a threshold above which an overrange output is active As long as the signal is below that threshold the output should remain low The fast detect outputs can also be programmed via the SPI port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature In this mode all 14 bits of the converter are examined in the traditional manner and the output is high for the condi
44. 0 010 0 10 010 0 10 010 a vs OUT DR avs 5437 5936 0 0010 WHOL 84 602 60 90 8 4 gt e a gt T 9 82 11 58 g 4 5 58 EN 2 SE L 2 5 gt rig 9 gt 62 5 5 5 e als a 52 5 p e gt er oer 8 1 gt 2 5 m Figure 94 Evaluation Board Schematic Power Supply Continued Rev A Page 73 of 88 Power Supply ByPass Capacitors AD6655 AD6655 a e 23 e DO m T e gt E e e e e e 00008 2 A TE og Ji D e cay Uso e wi ct o gt e X H t 5 ry m e 9 e E EH B E A Figure 95 Evaluation Board Layout Primary Side AD6655 eoeoeo 9500 eu 5 2 5 8 Figure 96 Evaluation Board Layout Ground Plane Rev A Page 75 of 88 AD6655 Figure 97 Evaluation Board Layout Power Plane Rev A Page 76 of 88 06709 102 AD6655 06709 103 Figure 98 Evaluation Board Layout Power Plane Rev A Page 77 of 88 AD6655 e
45. 0 5 4 7 3 4 0 5 4 7 3 ns Setup Time ts Full 14 0 11 0 ns Hold Time Full 11 0 8 0 ns CMOS Noninterleaved Mode DRVDD 3 3 V Data Propagation Delay tpo Full 1 9 4 1 6 4 1 9 4 1 6 4 ns DCO Propagation Delay toco Full 44 5 8 7 7 4 4 5 8 7 7 ns Setup Time ts Full 14 2 11 2 ns Hold Time Full 10 8 78 ns CMOS Interleaved and IO Mode DRVDD 1 8 V Data Propagation Delay tpo Full 1 6 3 9 6 2 1 6 3 9 6 2 ns DCO Propagation Delay toco Full 3 4 4 8 6 7 3 4 4 8 6 7 ns Setup Time ts Full 7 15 5 65 ns Hold Time Full 5 35 3 85 ns CMOS Interleaved and IO Mode DRVDD 3 3 V Data Propagation Delay ten Full 1 9 4 1 6 4 1 9 4 1 6 4 ns DCO Propagation Delay toco Full 3 8 5 2 7 1 3 8 5 2 7 1 ns Setup Time ts Full 7 35 5 85 ns Hold Time Full 5 15 3 65 ns LVDS Mode DRVDD 1 8 V Data Propagation Delay teo Full 2 5 4 8 7 0 2 5 4 8 7 0 ns DCO Propagation Delay toco Full 3 7 5 3 7 3 3 7 5 3 7 3 ns Pipeline Delay Latency NCO FIR fs 8 Mix Disabled Full 38 38 Cycles Pipeline Delay Latency NCO Enabled FIR and fs 8 Mix Disabled Full 38 38 Cycles Complex Output Mode Pipeline Delay Latency NCO FIR and fs 8 Mix Enabled Full 109 109 Cycles Aperture Delay ta Full 1 0 1 0 ns Aperture Uncertainty Jitter t Full 0 1 0 1 ps rms Wake Up Time Full 350 350 us OUT OF RANGE RECOVERY TIME Full 2 2 Cycles Conversion rate is the clock rate after the divider Output propagation delay is measured from CLK 509
46. 0076 A WHOL AN nro WHOOOL 189 ved 008 148 2 850 WHOM SA WHOL SIA A oas v 5 005 105 3195 850 Figure 92 Evaluation Board Schematic SPI Circuitry Rev A Page 71 of 88 AD6655 802 60 90 N aana NK M8 97 8 0 6 201 Sc 3282 ee vid a d aa 9 WHO 000 WHOM 94 wew ely 9 S INIOd 1531 GND N DITA AN td d 9 Eee s 2 Q td 3 A nro 019 2010 CM3OV3H aona l e e z or t pd A S 75 nro nmi e wd S 459 2807 5 3 S 5 H3MOd WNOILdO v P 5 SY 9 BNET 5 1 Odd ves K 1 oad ves 1 ves 1038 LOHS 880 or AQ 1 H3MOd Rev A Page 72 of 88 1001 AMPVDD 10U4 a NN L1 0130 ee dU PWR IN vaa C110 C112 C108 111 115 C114 C113 C107 C116 10105 4 0 1U 0 10 010 010 0 1
47. 03 10 LFCSP Interleaved Parallel LVDS Pin Configuration Top View Table 13 Pin Function Descriptions Interleaved Parallel LVDS Mode Mnemonic ADC Power Supplies 20 64 DRGND Ground Digital Output Ground 1 21 DRVDD Supply Digital Output Driver Supply 1 8 V to 3 3 V 24 57 DVDD Supply Digital Power Supply 1 8 V Nominal 36 45 46 AVDD Supply Analog Power Supply 1 8 V Nominal 0 AGND Ground Analog Ground The exposed thermal pad on the bottom of the package provides the analog Exposed Pad ground for the part This exposed pad must be connected to ground for proper operation ADC Analog 37 VIN A Input Differential Analog Input Pin for Channel A 38 VIN A Input Differential Analog Input Pin for Channel A 44 VIN B Input Differential Analog Input Pin for Channel B 43 VIN B Input Differential Analog Input Pin for Channel B 39 VREF Input Output Voltage Reference Input Output 40 SENSE Input Voltage Reference Mode Select See Table 15 for details 42 RBIAS Input Output External Reference Bias Resistor 41 CML Output Common Mode Level Bias Output for Analog Inputs 49 CLK Input ADC Clock Input True 50 CLK Input ADC Clock Input Complement ADC Fast Detect Outputs 54 53 56 55 59 58 Output Output Output Output Output Output Output Output Channel A Channel B LVDS Fast Detect Indicator 0 True See Table 21 for d
48. 18 07 0001 24 to 14 5 30 14 to 12 04 0010 14 5 to 10 18 07 to 8 52 0011 10 to 7 12 0410 6 02 0100 7 0 5 8 52 to 4 08 0101 5 to 3 25 6 02 to 2 5 0110 3 25 to 1 8 4 08 to 1 16 0111 1 8 to 0 56 2 5 to FS 1000 0 56 to 0 1 16to 0 Rev A Page 41 of 88 AD6655 When the fast detect mode select bits are set to 0b001 0b010 or 0b011 a subset of the fast detect output pins are available In these modes the fast detect output pins have a latency of six clock cycles and the greater of the two input samples is output at the DCO rate Table 23 shows the corresponding ADC input levels when the fast detect mode select bits are set to 05001 that is when the ADC fast magnitude is presented on the FD 3 1 pins Table 23 ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits 001 ADC Fast Nominal Input Nominal Input Magitude Magnitude Magnitude FD 2 0 Pins Below FS dB Uncertainty dB 000 lt 24 Minimum to 18 07 001 24 to 14 5 30 14 to 12 04 010 14 5 to 10 18 07 to 8 52 011 10 to 7 12 04 to 6 02 100 7 to 5 8 52 to 4 08 101 5 to 3 25 6 02 to 2 5 110 3 25 to 1 8 4 08 to 1 16 111 1 8100 2 5100 Coarse Upper Threshold 0 The coarse upper threshold indicator is asserted if the ADC fast magnitude input level is greater than the level programmed in the coa
49. 27 P88 209545 CSB 1 13 R22 1 O SYNCB SCLK GND 8144 59 O RESETB 12 979 SDI M5 qup Rae D9516 GND T5 VE OUTS Ran T TP18 SDO R 1 07434 1 28 C145 C64 cn 4 9516 e R3 R76 TP21 Ws 58 gt le R85 Sp ENG Tock EN 09516 EVALUATION AUTA R30 CLOCK A 1 OUT4 SYNC IN OUT4 1 56 CLKIN BOARD 511 510 55 57 512 9640 01 Figure 101 Evaluation Board Layout Silkscreen Primary Side Rev A Page 80 of 88 06709 106 VR4 Mi 189 VR3 AMPVDD F1 R C130 C136 2 CR12 1 4 T TEM CR10 119 C118 124 14 4 C131 Xo C132 L8 110 L6 9 C58 C103 8 c52 ca E AN C102 PER TI E N 10 gt C69 ak 139 22 oU S 2 o SS Ly D5A CR2 7 qe 74 C65 Ww v DCOA 012573 DCOB UN D8B C121 1 864 4 R87 wt e see E 4 lt ES re gt lt b 12 SV C68 ip s gt 2 aise C15 C76 2 GN Se a 7 e 3 2 E E 5 9 ao TeS a OG C100 i 892 c98 Rins auc y 2 1 RIL C81 cls 29
50. 3 AD6655 125 Single Tone SNR SFDR vs Input Frequency fiw and Figure 36 AD6655 150 Two Tone SFDR IMDS vs Input Amplitude with Temperature with DRVDD 1 8 V 29 12 MHz 32 12 MHz fs 150 MSPS fuco 22 MHz Rev A Page 26 of 88 AD6655 150MSPS 169 12MHz 7dBFS 172 12 2 7dBFS SFDR 85 5dBc 92 5dBFS fuco 177MHz AMPLITUDE dBFS SFDR IMD3 dBc AND dBFS dBFS 00 78 6 4 2 30 8 6 5 8 INPUT AMPLITUDE dBFS 5 FREQUENCY MHz 5 Figure 37 AD6655 150 Two Tone SFDR IMD3 vs Input Amplitude with Figure 40 AD6655 150 Two Tone FFT with 169 12 MHz 169 12 MHz 172 12 MHz fs 150 MSPS 177 MHz 172 12 MHz fs 150 MSPS fuco 177 MHz 0 0 NPR 64 5dBc NOTCH 18 5MHz 20 20 NOTCH WIDTH 3MHz _ 40 Lo Es m gt 60 5 60 TT 80 5 80 5 5 5 100 100 140 8 140 1 0 5 10 15 20 25 30 0 7 5 15 0 22 5 37 5 5 FREQUENCY MHz FREQUENCY MHz 5 Figure 38 AD6655 125 Two 64k WCDMA Carriers with fin 170 MHz Figure 41 AD6655 150 Noise Power Ratio NPR fs 122 88 MHz fuco 168 96 MHz 150MSPS 29 12MHz 7dBFS 32 12MHz 7dBFS SFDR 89 1dBc 96 1dBFS fuco 22MHz dBc o m m kJ 8 5 5 SNR a lt 0 5 10 15 20 25 30 35 8 0 25 50 75 100 125
51. 4 EE ES 0104 2 cao R125 59 9 1 E 1 R109R108 414 1 78139 R107R106 e 1 087 se fum R1027 1 3 2 52 J13 2 U3 di 221 C25 550 5 5 2 5 e o R45 10 11 512 ST Figure 102 Evaluation Board Layout Silkscreen Secondary Side Rev A Page 81 of 88 06709 107 AD6655 AD6655 BILL OF MATERIALS Table 30 Evaluation Board Bill of Materials Reference Item Qty Designator Description Package Manufacturer Mfg Part Number 1 1 AD6655CE_REVB PCB PCB Analog Devices 2 55 C1 to C3 C6 C7 0 1 pF 16 V ceramic 04025 Murata GRM155R71C104KA88D 14 C17 C18 capacitor SMT 0402 C20 to C26 C32 C57 to C61 C65 to C76 C81 to C83 C96 to C101 C103 C105 C107 C108 C110 to C116 C145 3 1 C80 18 pF COG 50 V 596 ceramic 04025 Murata GJM1555C1H180JB01J capacitor SMT 0402 4 2 C5 C84 4 7 pF COG 50 V 5 ceramic 04025 Murata GJM1555C1H4R7CB01J capacitor SMT 0402 5 10 C33 C35 C63 0 001 uF X7R 25 V 10 04025 Murata GRM155R71H102KA01D C93 to C95 C122 ceramic capacitor SMT 0402 C126 C127 C137 6 13 C15 C42 to C45 1 pF X5R 25 V 1096 ceramic C0805 Murata GR4M219R61A105KCO1D C129 to C136 capacitor SMT 0805 7 10 C27 C41 C52 to 10 uF X5R 10 V 10 ceramic C1206 Murata GRM31CR61C106KC31L C54 C62 C102
52. 6 transition to DATA 5096 transition with a 5 pF load 3 Wake up time is dependent on the value of the decoupling capacitors Rev A Page 13 of 88 AD6655 SWITCHING SPECIFICATIONS AD6655BCPZ 125 AD6655BCPZ 150 Table 8 AD6655BCPZ 125 AD6655BCPZ 150 Parameter Temp Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate DCS Enabled Full 20 125 20 150 MSPS DCS Disabled Full 10 125 10 150 MSPS CLK Period Divide by 1 Mode tax Full 8 6 66 ns CLK Pulse Width High taxu Divide by 1 Mode DCS Enabled Full 24 4 5 6 2 0 3 33 4 66 ns Divide by 1 Mode DCS Disabled Full 3 6 4 4 4 3 0 3 33 3 66 ns Divide by 2 Mode DCS Enabled Full 1 6 1 6 ns Divide by 3 Through Divide by 8 Modes DCS Enabled Full 0 8 0 8 ns DATA OUTPUT PARAMETERS DATA FD CMOS Noninterleaved Mode DRVDD 1 8 V Data Propagation Delay tpo Full 1 6 3 9 6 2 1 6 3 9 6 2 ns DCO Propagation Delay toco Full 4 0 5 4 7 3 4 0 5 4 7 3 ns Setup Time ts Full 9 5 8 16 ns Hold Time tu Full 6 5 5 16 ns CMOS Noninterleaved Mode DRVDD 3 3 V Data Propagation Delay ten Full 1 9 4 1 6 4 1 9 4 1 6 4 ns DCO Propagation Delay toco Full 44 5 8 7 7 4 4 5 8 7 7 ns Setup Time ts Full 9 7 8 36 ns Hold Time tu Full 6 3 4 96 ns CMOS Interleaved and IO Mode DRVDD 1 8 V Data Propagation Delay ten Full 1 6 3 9 6 2 1 6 3 9 6 2 ns DCO Propagation Delay toco Full 34 4 8 6 7 3 4 4 8 6 7 ns Setup
53. 655 receiver digitizes a wide spectrum of IF frequencies Each receiver is designed for simultaneous reception of the main channel and the diversity channel This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods Flexible power down options allow significant power savings when desired Programming for setup and control is accomplished using a 3 bit SPI compatible serial interface The AD6655 is available in a 64 lead LFCSP and is specified over the industrial temperature range of 40 C to 85 C Rev A Page 4 of 8 SPECIFICATIONS ADC DC SPECIFICATIONS AD6655BCPZ 80 AD6655BCPZ 105 AVDD 1 8 V DVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled unless otherwise noted AD6655 Table 1 AD6655BCPZ 80 AD6655BCPZ 105 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full 0 2 0 6 0 2 0 6 FSR Gain Error Full 3 6 18 0 1 4 3 22 0 5 90 FSR MATCHING CHARACTERISTIC Offset Error 25 C 0 2 0 6 0 2 0 6 FSR Gain Error 25 C 0 2 0 75 0 2 0 75 FSR TEMPERATURE DRIFT Offset Error Full 15 15 ppm C Gain Error Full 95 95 ppm C INTERNAL VOLTAGE REFERENCE Output Voltage Error 1 V Mode Full 18 18
54. 75 6dBFS SFDR 86 1dBc 150MSPS 445 1MHz 1dBFS SNR 67 4dBc 65 4dBFS SFDR 74 1dBc fuco 429MHz fuco 78MHz 5 SECOND HARMONIC kJ kJ u THIRD HARMONIC a THIRD HARMONIC 2 2 E E m m n a FREQUENCY MHz 5 FREQUENCY MHz Figure 25 AD6655 150 Single Tone FFT with 445 1 MHz fuco 429 MHz Figure 28 AD6655 125 Single Tone FFT with fi 70 3 MHz fuco 78 MHz 0 125MSPS 125MSPS 2 4MHz 14 5 140 1MHz 1dBFS SNR 74 5dBc 75 5dBFS 20 SNR 74 1dBc 75 1dBFS SFDR 87 8dBc SFDR 90 34 fuco 15 75MHz fuco 142MHz m 40 A gt 60 SECOND HARMONIC THIRD HARMONIC 2 THIRD HARMONIC 5 80 a a 100 120 140 0 5 10 15 20 25 30 8 8 FREQUENCY MHz 5 FREQUENCY MHz 5 Figure 26 AD6655 125 Single Tone FFT with 2 4 MHz fuco 15 75 MHz Figure 29 AD6655 125 Single Tone FFT with fw 140 1 MHz fuco 142 MHz 125MSPS 125MSPS 30 3MHz 1dBFS 220 1MHz 1dBFS SNR 74 7dBc 75 7dBFS SNR 73 4dBc 74 4dBFS SFDR 89 6dBc SFDR 90 2dBc fuco 21MHz fuco 231MHz ta t 5 5 2 2 E E n lt 0 5 10 15 20 25 5 0 5 10 15 20 25 8 FREQUENCY MHz 5 FREQUENCY MHz 5 Figure 27 AD6655 125 Single Tone FFT with fiy 30 3 MHz fuco 21 MHz Figure 30 AD6655 125 Single Tone FFT with fiw 220 1 MH
55. ANALOG DEVICES IF Diversity Receiver AD6655 FEATURES SNR 74 5 dBc 75 5 dBFS in a 32 7 MHz BW at 70 MHz 150 MSPS SFDR 80 dBc to 70 MHz 150 MSPS 1 8 V analog supply operation 1 8 V to 3 3 V CMOS output supply or 1 8 V LVDS output supply Integer 1 to 8 input clock divider Integrated dual channel ADC Sample rates up to 150 MSPS IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample and hold inputs Flexible analog input range 1 V p p to 2 V p p ADC clock duty cycle stabilizer 95 dB channel isolation crosstalk Integrated wideband digital downconverter DDC 32 bit complex numerically controlled oscillator NCO Decimating half band filter and FIR filter Supports real and complex output modes Fast attack threshold detect bits Composite signal monitor Energy saving power down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers 3G TD SCDMA WiMax WCDMA CDMA2000 GSM EDGE LTE 1 Q demodulation systems Smart antenna systems General purpose software radios Broadband data applications PRODUCT HIGHLIGHTS 1 Integrated dual 14 bit 150 MSPS ADC 2 Integrated wideband decimation filter and 32 bit complex NCO 3 Fast overrange detect and signal monitor with serial output 4 Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz 5 Flexible output modes including independent CMOS
56. C43 0 0053153 11147 FRACTION OF INPUT SAMPLE RATE C23 C42 0 0255623 53608 Figure 74 Half Band Filter and FIR Filter Composite Response C24 C41 0 0104036 21818 C25 C40 0 0341468 71611 FINAL NCO C26 C39 0 0192165 40300 The output of the 32 bit fine tuning NCO is complex and C27 C38 0 0471258 98830 typically centered in frequency around dc This complex output C28 C37 0 0354118 74264 is carried through the stages of the half band and FIR filters to C29 C36 0 0728111 152696 provide proper antialiasing filtering The final NCO provides C30 C35 0 0768890 161248 means to move this complex output signal away from dc so that C31 C34 0 1607208 337056 a real output can be provided from the AD6655 The final NCO C32 C33 0 4396725 922060 if enabled translates the output from dc to a frequency equal to the ADC sampling frequency divided by 8 8 This provides SYNCHRONIZATION the user a decimated output signal centered at fanc 8 in frequency The AD6655 half band filters within a single part or across Optionally this final NCO can be bypassed and the dc centered multiple parts can be synchronized using the external SYNC I and values can be output in an interleaved fashion input Bit 5 and Bit 6 of Register 0x100 allow the half bands to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written A valid SYNC causes the half band filter to restart at the programmed decimation phase
57. Features Uer 1 5 i circiter e er bate He eben IR CURIE 1 Prod ct Highlights ttd 1 Functional Block Diagram 1 REVISION HIStory RRRRRURE RISE 3 General Descriptio cette etre 4 SpecificatioliS eise rte net eerte et one da 5 ADC DC Specifications AD6655BCPZ 80 665 22105 temet eee 5 ADC DC Specifications AD6655BCPZ 125 6655 15 0 eerie 6 ADC AC Specifications AD6655BCPZ 80 AD6655BCPZ 105 e esto etm 7 ADC AC Specifications AD6655BCPZ 125 6655 150 8 Digital Specifications AD6655BCPZ 80 AD6655BCPZ 105 9 Digital Specifications AD6655BCPZ 125 6655 7 150 11 Switching Specifications AD6655BCPZ 80 6655 05 13 Switching Specifications AD6655BCPZ 125 AD6655BCPZ VSO isa 14 Timing Specifications eee peterent epe ee 15 Absolute Maximum Ratings essent 18 Thermal Characteristics sente 18 ESD Caution 18 Pin Configurations and Function Descriptions 19 Equivalent Circuits sss 23 Typical Performance Characteristics 24 Theory of Operation serred n tenentes 29 ADC Architect re
58. Global Open Open Open Open Open Open Open Duty cycle stabilize default 0x01 OxOB Clock Divide Global Open Open Open Open Open Clock divide ratio 000 divide by 1 001 divide by 2 010 divide by 3 011 divide by 4 100 divide by 5 101 divide by 6 110 divide by 7 111 divide by 8 0x00 Clock divide values other than 000 automatically activate duty cycle stabilization Rev A Page 51 of 88 AD6655 Default Default Addr Register Bit 7 Bit 0 Value Notes Hex Name MSB Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Hex Comments Test Mode Open Open Reset Reset Open Output test mode 0x00 When Local PN long PN short 000 off default enabled the sequence sequence 001 midscale short test data is 010 positive FS placed on the 011 negative FS output ps in place of 100 alternating ADC output checkerboard data 101 PN long sequence 110 short sequence 111 one zero word toggle 0x10 Offset Adjust Open Open Offset adjust in LSBs from 31 to 32 twos complement format 0x00 Local 0x14 Output Mode Drive Output Interleaved Output Open Output 00 offset binary 0x00 Configures strength type CMOS enable invert 01 twos complement the outputs OV to 3 3 0 5 global bar local local 01 gray code and the VCMOS or 1 LVDS 11
59. K INPUTS CLK Logic Compliance CMOS LVDS LVPECL CMOS LVDS LVPECL Internal Common Mode Bias Full 1 2 1 2 V Differential Input Voltage Full 0 2 6 0 2 6 Vp p Input Voltage Range Full AVDD 0 3 AVDD 1 6 AVDD 0 3 AVDD 1 6 V Input Common Mode Range Full 1 1 AVDD 1 1 AVDD V High Level Input Voltage Full 12 3 6 1 2 3 6 V Low Level Input Voltage Full 0 0 8 0 0 8 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 10 10 10 10 Input Capacitance Full 4 4 pF Input Resistance Full 8 10 12 8 10 12 SYNC INPUT Logic Compliance CMOS CMOS Internal Bias Full 1 2 1 2 Input Voltage Range Full AVDD 0 3 AVDD 1 6 AVDD 03 AVDD 1 6 V High Level Input Voltage Full 12 3 6 1 2 3 6 V Low Level Input Voltage Full 0 0 8 0 0 8 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 10 10 10 10 Input Capacitance Full 4 4 pF Input Resistance Full 8 10 12 8 10 12 LOGIC INPUT CSB High Level Input Voltage Full 1 22 3 6 1 22 3 6 Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 40 132 40 132 Input Resistance Full 26 26 kQ Input Capacitance Full 2 2 pF LOGIC INPUT SCLK DFS High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 92 135 92 135 Low Level Input Current Full 10 10 10 10 Input Resistance Fu
60. L DOWNCONVERTER The AD6655 includes a digital processing section that provides filtering and reduces the output data rate This digital processing section includes a numerically controlled oscillator NCO a half band decimating filter an FIR filter and a second coarse NCO fanc 8 fixed value for output frequency translation Each of these processing blocks except the decimating half band filter has control lines that allow it to be independently enabled and disabled to provide the desired processing function The digital downconverter can be configured to output either real data or complex output data These blocks can be configured in five recommended combinations to implement different signal processing functions DOWNCONVERTER MODES Table 18 details the recommended downconverter modes of operation in the AD6655 Table 18 Downconverter Modes Mode NCO Filter Output Type 1 Half band filter only Real Half band filter and FIR filter Real NCO and half band filter Complex NCO half band filter and FIR filter Complex NCO half band filter FIR filter and Real fapc 8 NCO NUMERICALLY CONTROLLED OSCILLATOR NCO Frequency translation is accomplished with an NCO Each of the two processing channels shares common NCO Amplitude and phase dither can be enabled on chip to improve the noise and spurious performance of the NCO A phase offset word is available to create a known phase relationship between
61. O 240V AC 47Hz TO 63Hz SWITCHING SUPPLY ROHDE amp SCHWARZ SMA100A BAND PASS 2V p p SIGNAL FILTER SYNTHESIZER ROHDE amp SCHWARZ SMA100A 2V p p SIGNAL SYNTHESIZER ROHDE amp SCHWARZ SMA100A 2V p p SIGNAL SYNTHESIZER DRVDD IN BAND PASS AD6655 EVALUATION BOARD PARALLEL AD6655 External supplies can be used to operate the evaluation board by removing L1 L3 L4 and L13 to disconnect the voltage regulators supplied from the switching power supply This enables the user to individually bias each section of the board Use P3 and P4 to connect a different supply for each section At least one 1 8 V supply is needed with a 1 A current capability for AVDD and DVDD a separate 1 8 V to 3 3 V supply is recom mended for DRVDD To operate the evaluation board using the AD8352 option a separate 5 0 V supply AMP VDD with a 1 A current capability is needed To operate the evaluation board using the alternate SPI options a separate 3 3 V analog supply VS is needed in addition to the other supplies The 3 3 V supply VS should have a 1 A current capability as well Solder Jumper SJ35 allows the user to separate AVDD and DVDD if desired INPUT SIGNALS When connecting the clock and analog source use clean signal generators with low phase noise such as the Rohde amp Schwarz 5 100 signal generators or the equivalent Use 1 m long shielded RG 58 50 coaxial
62. OOAL ZN Eo m 019 QLWrvze9 XAH 89 69 ew maid A ga ma 000 IZWH OOAL mo yS ved aso H ved wa QLWrtec9 SEEFEEREEERDEE 3 2 2 lt 100 nos M EB 105 100 5405 5 05 ZO IVA3 9QV 9SH TV LIOIG sin Figure 91 Evaluation Board Schematic Digital Output Interface Rev A Page 70 of 88 AD6655 2402 60290 NOLLVH3dO dS HOdHH3d WI TIV LSNI ber 108110 INAWNdWOO SOML Z OL SNIdH3dl n NOIL VH3dO dS HOJ OL cSNIdH3dlWnf er 3I8VN3 558 HOS ZOL I 5 NOIL VH3dO dS HOS OL eSNIdH3dlWnf LP 848 01 257 80 185 90 5 2 AOS 145 5 wH nos p L 2
63. P SYNCHRONIZATION The AD6655 has a SYNC input that allows the user flexible The SYNC input is internally synchronized to the sample clock synchronization options for synchronizing the internal blocks However to ensure that there is no timing uncertainty between The sync feature is useful for guaranteeing synchronized operation multiple parts the SYNC input signal should be synchronized across multiple ADCs The input clock divider NCO half band to the input clock signal The SYNC input should be driven filters and signal monitor block can be synchronized using the using a single ended CMOS type signal SYNC input Each of these blocks except for the signal monitor can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence Rev A Page 47 of 88 AD6655 SERIAL PORT INTERFACE SPI The AD6655 serial port interface SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC The SPI gives the user added flexibility and customization depending on the application Addresses are accessed via the serial port and can be written to or read from via the port Memory is organized into bytes that can be further divided into fields These fields are documented in the Memory Map section For detailed operational information see Application Note AN 877 Interfacing to High Speed ADCs via SPI CONFIGURATION USING THE SPI T
64. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DRVDD D6B D7B D8B D9B D10B D11B D12B D13B MSB DCOB 10 DCOA 11 DOA LSB 12 DIA 13 D2A 14 D3A 15 D4A 16 NOTES 1 THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION PIN 1 O lt INDICATOR 8 SCLK DFS EXPOSED PADDLE PIN 0 4 VIN B BOTTOM OF PACKAGE 3 VIN B AD6655 0 SENSE PARALLEL CMOS 9 VREF TOP VIEW 8 VIN A Not to Scale 7 VIN A 4 SMI SCLK PDWN 3 SMI SDO OEB O OQ vr f 10 00 O v7 v7 v7 ON ON ON lt lt lt lt lt lt lt lt lt lt lt gt gt 2 lt e a 06709 002 Figure 9 LFCSP Parallel CMOS Pin Configuration Top View Table 12 Pin Function Descriptions Parallel CMOS Mode Pin No ADC Power Supplies Mnemonic __ Description 20 64 DRGND Ground Digital Output Ground 1 21 DRVDD Supply Digital Output Driver Supply 1 8 V to 3 3 V 24 57 DVDD Supply Digital Power Supply 1 8 V Nominal 36 45 46 AVDD Supply Analog Power Supply 1 8 V Nominal 0 AGND Ground Analog Ground The exposed thermal pad on the bottom of the package provides the Exposed Pad analog groun
65. Time ts Full 4 9 4 23 ns Hold Time Full 3 1 2 43 ns CMOS Interleaved and IO Mode DRVDD 3 3 V Data Propagation Delay tpo Full 1 9 4 1 6 4 1 9 4 1 6 4 ns DCO Propagation Delay toco Full 3 8 5 2 7 1 3 8 5 2 7 1 ns Setup Time ts Full 5 1 4 43 ns Hold Time tu Full 2 9 2 23 ns LVDS Mode DRVDD 1 8 V Data Propagation Delay tpo Full 2 5 48 7 0 2 5 48 7 0 ns DCO Propagation Delay toco Full 3 7 5 3 7 3 3 7 53 73 ns Pipeline Delay Latency NCO FIR fs 8 Mix Disabled Full 38 38 Cycles Pipeline Delay Latency NCO Enabled FIR and 5 8 Mix Disabled Full 38 38 Cycles Complex Output Mode Pipeline Delay Latency NCO FIR and fs 8 Mix Enabled Full 109 109 Cycles Aperture Delay ta Full 1 0 1 0 ns Aperture Uncertainty Jitter 1 Full 0 1 0 1 ps rms Wake Up Time Full 350 350 us OUT OF RANGE RECOVERY TIME Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider Output propagation delay is measured from CLK 50 transition to DATA 50 transition with 5 pF load Wake up time is dependent on the value of the decoupling capacitors Rev A Page 14 of 88 AD6655 TIMING SPECIFICATIONS Table 9 SYNC TIMING REQUIREMENTS tssync SYNC to the rising edge of CLK setup time SYNC to the rising edge of CLK hold time SPI TIMING REQUIREMENTS tos Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of t
66. VDD 1 8 V DVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled unless otherwise noted Table 2 AD6655BCPZ 125 AD6655BCPZ 150 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full 0 3 0 6 0 2 0 6 FSR Gain Error Full 4 7 2 7 0 8 5 1 32 1 0 FSR MATCHING CHARACTERISTIC Offset Error 25 C 0 3 0 7 0 2 0 7 FSR Gain Error 25 C 0 1 0 7 0 2 0 8 FSR TEMPERATURE DRIFT Offset Error Full 15 15 Gain Error Full 95 95 INTERNAL VOLTAGE REFERENCE Output Voltage Error 1 V Mode Full 5 18 5 18 mV Load Regulation 1 0 mA Full 7 7 mV INPUT REFERRED NOISE VREF 1 0 V 25 C 0 85 0 85 LSB rms ANALOG INPUT Input Span VREF 1 0 V Full 2 2 V p p Input Capacitance Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 POWER SUPPLIES Supply Voltage AVDD DVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 V DRVDD CMOS Mode Full 1 7 1 8 3 6 1 7 1 8 3 6 V DRVDD LVDS Mode Full 1 7 1 8 1 9 1 7 1 8 1 9 V Supply Current 2 3 Full 390 705 440 805 mA 150023 Full 270 320 mA 3 3 V CMOS Full 26 28 mA 1 8 V CMOS Full 13 17 mA 1 8 V LVDS Full 57 57 mA POWER CONSUMPTION DC Input Full 770 810 870 920 mW Sine Wave Input DRVDD 1 8 V Full 1215 1395 mW Sine Wave Input
67. Y IN ACCURACY AND LATENCY NOTE OUTPUTS FOLLOW THE INSTANTEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES AD6655 with the magnitude at the output of the ADC This comparison is subject to the ADC clock latency but allows a finer more accurate comparison The fine upper threshold magnitude is defined by the following equation dBFS 20 log Threshold Magnitude 2 The decrement gain output works from the ADC fast detect output pins providing a fast indication of potential overrange conditions The increment gain uses the comparison at the output of the ADC requiring the input magnitude to remain below an accurate programmable level for a predefined period before signaling external circuitry to increase the gain The operation of the increment gain output and decrement gain output is shown graphically in Figure 75 UPPER THRESHOLD COARSE OR FINE DWELL TIME TIMER RESET BY RISE ABOVE F_LT 1 FINE LOWER THRESHOLD 06709 073 Figure 75 Threshold Settings for C UT UT LT DG and IG Rev A Page 43 of 88 AD6655 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC The signal monitor computes the rms input magnitude the peak magnitude and or the number of samples by which the magnitude exceeds a particular threshold Together these functions can be used to gain insight into the signal
68. Y1 to provide the clock input to the part To enable this crystal Resistor R8 0 and Resistor R85 10 should be installed and Resistor R82 and Resistor R30 should be removed A second clock option is to use a differential LVPECL clock to drive the ADC input using the AD9516 U2 When using this drive option the AD9516 charge pump filter components need to be populated see Figure 89 Consult the AD9516 data sheet for more information To configure the clock input from 5 to drive the AD9516 reference input instead of directly driving the ADC the following components need to be added removed and or changed 1 Remove R32 R33 R99 and R101 in the default dock path 2 Populate C78 and C79 with 0 001 capacitors and R78 and R79 with 0 resistors in the clock path In addition unused AD9516 outputs one LVDS and one LVPECL are routed to optional Connector 58 through Connector 511 the evaluation board Rev A Page 62 of 88 AD6655 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352 When using this particular drive option some additional components need to be populated For more details on the AD8352 differential driver including how it works and its optional pin settings consult the AD8352 data sheet To configure the analog input to drive the AD8352 instead of the default transformer option
69. age VOS Full 1 15 1 25 1 35 1 15 1 25 1 35 V Reduced Swing Mode Pull up Pull down Rev A Page 10 of 88 DIGITAL SPECIFICATIONS AD6655BCPZ 125 AD6655BCPZ 150 AVDD 1 8 V DVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled unless otherwise noted AD6655 Table 6 AD6655BCPZ 125 AD6655BCPZ 150 Parameter Temp Min Typ Max Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS CLK Logic Compliance CMOS LVDS LVPECL CMOS LVDS LVPECL Internal Common Mode Bias Full 1 2 1 2 V Differential Input Voltage Full 0 2 6 0 2 6 Vp p Input Voltage Range Full AVDD 0 3 AVDD 1 6 AVDD 0 3 AVDD 1 6 Input Common Mode Range Full AVDD AVDD V High Level Input Voltage Full 1 2 3 6 12 3 6 V Low Level Input Voltage Full 0 0 8 0 0 8 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 10 10 10 10 Input Capacitance Full 4 4 pF Input Resistance Full 8 10 12 8 10 12 ka SYNC INPUT Logic Compliance CMOS CMOS Internal Bias Full 1 2 1 2 Input Voltage Range Full AVDD 0 3 AVDD 1 6 AVDD 03 AVDD 1 6 High Level Input Voltage Full 1 2 3 6 12 3 6 V Low Level Input Voltage Full 0 0 8 0 0 8 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 10 10 10 10 Input Capacitance Full 4 4 pF Input Resistance Full 8 10 12 8 10 12 kQ LOGIC INPUT CSB
70. al receiver has two channels and provides processing flexibility Each receive channel has four cascaded signal processing stages a 32 bit frequency translator numerically controlled oscillator NCO a half band decimating filter a fixed FIR filter and an fApc 8 fixed frequency NCO In addition to the receiver DDC the AD6655 has several functions that simplify the automatic gain control AGC function in the system receiver The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency In addition the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency If the input signal level exceeds the programmable threshold the coarse upper threshold indicator goes high Because this threshold indicator has low latency the user can quickly turn down the system gain to avoid an overrange condition The second AGC related function is the signal monitor This block allows the user to monitor the composite magnitude of the incoming signal which aids in setting the gain to optimize the dynamic range of the overall system After digital processing data can be routed directly to the two external 14 bit output ports These outputs can be set from 1 8 V to 3 3 V CMOS or as 1 8 V LVDS The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A The AD6
71. alue in the SMR is a 20 bit fixed point number The following equation can be used to determine the ms magnitude in dBFS from the MAG value in the register Note that if the SMP is a power of 2 the second term in the equation becomes 0 MS Magnitude 10 log 236 10 log 26 266 8 THRESHOLD CROSSING MODE In the threshold crossing mode of operation the magnitude of the input port signal is monitored over a programmable time period given by SMPR to count the number of times it crosses certain programmable threshold value This mode is set by programming Logic 1x where x is a don t care bit in the signal monitor mode bits of the signal monitor control register or by setting the threshold crossing output enable bit in the signal monitor SPORT control register Before activating this mode the user needs to program the 24 bit SMPR and the 13 bit upper threshold register for each individual input port The same upper threshold register is used for both signal monitor ing and gain control see the ADC Overrange and Gain Control section After entering this mode the value in the SMPR is loaded into a monitor period timer and the countdown is started The magnitude of the input signal is compared with the upper threshold register programmed previously on each input clock cycle If the input signal has a magnitude greater than the upper threshold register the internal count register is incremented by 1 The initial va
72. ance Airflow Package Velocity Type m s Osc Unit 64 Lead LFCSP 0 18 8 0 6 6 0 C W 9mmx9mm 1 0 16 5 C W 6 9 2 0 15 8 C W Per JEDEC 51 7 plus JEDEC 25 5 252 test board Per JEDEC JESD51 2 still air or JEDEC JESD51 6 moving air 3 MIL Std 883 Method 1012 1 Per JEDEC JESD51 8 still air Typical is specified for a 4 layer PCB with solid ground plane As shown airflow increases heat dissipation which reduces 054 In addition metal in direct contact with the package leads from metal traces through holes ground and power planes reduces the ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Rev A Page 18 of 88 AD6655
73. aster sync enable bit Register 0x100 Bit 0 and the NCO32 sync enable bit Register 0x100 Bit 3 are high Bit 4 allows the NCO32 to synchronize following the first sync pulse it receives and ignore the rest Bit 3 of Register 0x100 resets after a sync occurs if Bit 4 is set Bit 3 NCO32 Sync Enable Bit 3 gates the sync pulse to the 32 bit NCO When this bit is set high the sync signal causes the NCO to resynchronize starting at the NCO phase offset value This sync is active only when the master sync enable bit Register 0x100 Bit 0 is high This is continuous sync mode Bit 2 Clock Divider Next Sync Only If the master sync enable bit Register 0x100 Bit 0 and the clock divider sync enable bit Register 0x100 Bit 1 are high Bit 2 allows the clock divider to synchronize following the first sync pulse it receives and ignores the rest Bit 1 of Register Ox100 resets after it synchronizes Bit 1 Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider The sync signal is passed when Bit 1 and Bit 0 are high This is continuous sync mode Bit 0 Master Sync Enable Bit 0 must be high to enable any of the sync functions f 8 Output Mix Control Register 0x101 Bits 7 6 Reserved Bits 5 4 f 8 Start State Bit 5 and Bit 4 set the starting phase of the fs 8 output mix Bits 3 2 Reserved Bit 1 fs 8 Next Sync Only If the master sync enable bit Register 0x100 Bit 0 and the fs 8 sync e
74. be input into the evaluation board through Connector S5 PDWN To enable the power down feature connect J7 shorting the PDWN pin to AVDD CSB The CSB pin is internally pulled up setting the chip into external pin mode to ignore the SDIO and SCLK information To connect the control of the CSB pin to the SPI circuitry on the evaluation board connect J21 Pin 1 to J21 Pin 2 SCLK DFS If the SPI port is in external pin mode the SCLK DFS pin sets the data format of the outputs If the pin is left floating the pin is inter nally pulled down setting the default data format condition to offset binary Connecting J2 Pin 1 to J2 Pin 2 sets the format to twos complement If the SPI port is in serial pin mode connecting J2 Pin 2 to J2 Pin 3 connects the SCLK pin to the on board SPI circuitry see the Serial Port Interface SPI section SDIO DCS If the SPI port is in external pin mode the SDIO DCS pin sets the duty cycle stabilizer If the pin is left floating the pin is internally pulled up setting the default condition to DCS enabled To disable the DCS connect J1 Pin 1 to J1 Pin 2 If the SPI port is in serial pin mode connecting J1 Pin 2 to J1 Pin 3 connects the SDIO pin to the on board SPI circuitry see the Serial Port Interface SPI section ALTERNATIVE CLOCK CONFIGURATIONS Two alternate clocking options are provided on the AD6655 evaluation board The first option is to use an on board crystal oscillator
75. capacitor SMT 1206 C118 C119 C124 1 CR5 Schottky diode HSMS2822 SOT23 SOT23 Avago Technologies HSMS 2822 BLKG 2 CR6 CR9 LED RED SMT 0603 SS type LED0603 Panasonic LNJ208R8ARA 10 4 CR7 CR10 to CR12 50 V 2 A diode DO_214AA Micro Commercial Components S2A TP 11 1 CR8 30V 3A diode DO 214AB Micro Commercial Components SK33 TP 12 1 F1 EMI filter FLTHMURATABNXO1 Murata BNX016 01 13 1 F2 6 0 V 3 0 A trip current L1206 Tyco Raychem NANOSMDC150F 2 resettable fuse 14 2 J1 J2 3 pin male single row HDR3 Samtec TWS 1003 08 G S straight header 15 9 to J9 J18 J19 2 pin male straight header HDR2 Samtec TWS 102 08 G S J21 16 3 J10 to J12 Interface connector TYCO HM ZD Tyco 6469169 1 17 1 J14 8 pin male double row CNBERG2X4H350LD Samtec TSW 104 08 T D straight header 18 1 J16 DC power jack connector PWR JACK1 Cui Stack PJ 002A 19 10 L1 L3 14 L6 L8 10 pH 2 A bead core 1210 1210 Panasonic EXC CL3225U1 toL13 20 1 P3 6 terminal connector PTMICRO6 Weiland Electric Inc 25 531 3625 0 21 1 4 4 terminal connector PTMICRO4 Weiland Electric Inc 25 531 3425 0 22 3 R7 R30 R45 57 6 0603 1 10 W 0603 Components NRCO6F57R6TRF 1 resistor 23 27 R2 R3 R4 R32 1 16 W 5 resistor 04025 Components NRCO4ZOTRF R33 R42 R64 R67 R69 R90 R96 R99 R101 R104 R110 to F113 R115 R119 R121 R123 R141 to R145 24 1 R13 76 8 0603 1 10 W 1 resistor R0603 NIC Components NRCO6F7682TRF 25 1 R25 140
76. creases and is at a higher level than the worst harmonic as shown in Figure 83 which shows the AD6655 150 fs 2 levels AD6655 For the specifications provided in Table 2 the fs 2 spur if in band is excluded from the SNR values It is treated as a harmonic in terms of SNR The fs 2 level is included in the SFDR and worst other specifications 60 80 SFDR 100 SFDR AND 5 2 SPUR dBFS b 15 2 SPUR 110 2 3 9 8 8 5 8 0 0 50 100 150 200 250 300 350 400 450 50 INPUT FREQUENCY MHz Figure 82 AD6655 125 SFDR and 2 Spurious Level vs Input Frequency fiw with DRVDD 1 8 V Parallel CMOS Output Mode SFDR AND 15 2 SPUR dBFS 110 06709 084 0 50 100 150 200 250 300 350 400 450 50 ANALOG INPUT FREQUENCY MHz Figure 83 AD6655 150 SFDR and 2 Spurious Level vs Input Frequency fiw with DRVDD 1 8 V Parallel CMOS Output Mode Operating the part with a 1 8 V DRVDD voltage rather than a 3 3 V DRVDD lowers the fs 2 spur In addition using LVDS CMOS interleaved or CMOS IQ output modes also reduces the 5 2 spurious level LVDS Operation The AD6655 defaults to CMOS output mode on power up If LVDS operation is desired this mode must be programmed using the SPI configuration registers after power up When the AD6655 powers up in CMOS mode with LVDS termination resistors 100 on the outputs the
77. d for the part This pad must be connected to ground for proper operation ADC Analog 37 VIN A Input Differential Analog Input Pin for Channel A 38 VIN A Input Differential Analog Input Pin for Channel A 44 VIN B Input Differential Analog Input Pin for Channel B 43 VIN B Input Differential Analog Input Pin for Channel B 39 VREF Input Output Voltage Reference Input Output 40 SENSE Input Voltage Reference Mode Select See Table 15 for details 42 RBIAS Input Output External Reference Bias Resistor 41 CML Output Common Mode Level Bias Output for Analog Inputs 49 CLK Input ADC Clock Input True 50 CLK Input ADC Clock Input Complement ADC Fast Detect Outputs 29 30 31 32 53 54 55 56 FDOA FD1A FD2A FD3A FDOB FD1B FD2B FD3B Output Output Output Output Output Output Output Output Channel A Fast Detect Indicator See Table 21 for details Channel A Fast Detect Indicator See Table 21 for details Channel A Fast Detect Indicator See Table 21 for details Channel A Fast Detect Indicator See Table 21 for details Channel B Fast Detect Indicator See Table 21 for details Channel B Fast Detect Indicator See Table 21 for details Channel B Fast Detect Indicator See Table 21 for details Channel B Fast Detect Indicator See Table 21 for details Rev A Page 19 of 88 AD6655
78. d timer and the countdown is started immediately Each input sample is converted to floating point format and squared It is then converted to 11 bit fixed point format and added to the contents of the 24 bit accumulator The integration continues until the monitor period timer reaches a count of 1 When the monitor period timer reaches a count of 1 the square root of the value in the accumulator is taken and transferred after some formatting to the signal monitor holding register which can be read through the SPI port or output through the SPORT serial port The monitor period timer is reloaded with the value in the SMPR and the countdown is restarted Rev A Page 44 of 88 In addition the first input sample signal power is updated in the accumulator and the accumulation continues with the subsequent input samples Figure 77 illustrates the rms magnitude monitoring logic FROM T MEMORY INTERRUPT MAP CONTROLLER POWER MONITOR PERIOD REGISTER 06709 075 Figure 77 ADC Input RMS Magnitude Monitoring Block Diagram For rms magnitude mode the value in the signal monitor result SMR register is a 20 bit fixed point number The following equation can be used to determine the rms magnitude in dBFS from the MAG value in the register Note that if the signal monitor period SMP is a power of 2 the second term in the equation becomes 0 RMS Magnitude 20 236 10 log 8 For ms magnitude mode the v
79. dB WORST SECOND OR THIRD HARMONIC fin 2 4 MHz 25 C 86 85 dBc fin 70 MHz 25 C 85 84 dBc Full 73 73 fin 140 MHz 25 C 84 83 dBc fin 220 MHz 25 C 83 77 SPURIOUS FREE DYNAMIC RANGE SFDR fin 2 4 MHz 25 C 86 85 dBc fin 70 MHz 25 C 85 80 dBc Full 73 73 dBc fin 140 MHz 25 C 84 76 dBc fin 220 MHz 25 C 83 74 dBc WORST OTHER HARMONIC OR SPUR2 fin 2 4 MHz 25 C 92 87 dBc fin 70 MHz 25 C 90 80 Full 82 80 dBc fin 140 MHz 25 C 88 76 fin 220 MHz 25 C 84 74 dBc TWO TONE SFDR fin 29 12 MHz 32 12 MHz 7 dBFS 25 C 85 85 dBc fn 169 12 MHz 172 12 2 7 dBFS 25 C 81 81 CROSSTALK Full 95 95 dB ANALOG INPUT BANDWIDTH 25 C 650 650 MHz See Application Note AN 835 Understanding High Speed ADC Testing and Evaluation for a complete set of definitions See the Applications Information section for more information about the worst other specifications for the AD6655 3 Crosstalk is measured at 100 MHz with 1 dBFS on one channel and with no input on the alternate channel Rev A Page 8 of 88 DIGITAL SPECIFICATIONS AD6655BCPZ 80 AD6655BCPZ 105 AVDD 1 8 V DVDD 1 8 V DRVDD 1 8 V maximum sample rate VIN 1 0 dBFS differential input 1 0 V internal reference DCS enabled unless otherwise noted AD6655 Table 5 AD6655BCPZ 80 AD6655BCPZ 105 Parameter Temp Min Typ Max Min Typ Max Unit DIFFERENTIAL CLOC
80. e reduced In combination with the driving source impedance the shunt capacitors limit the input bandwidth Refer to Appli cation Note AN 742 Frequency Domain Response of Switched Capacitor ADCs Application Note AN 827 A Resonant Approach to Interfacing Amplifiers to Switched Capacitor ADCs and the Analog Dialogue article Transformer Coupled Front End for Wideband A D Converters for more information on this subject see www analog com In general the precise values are dependent on the application S 5 Cs VIN PAR Cs VIN 3 Figure 46 Switched Capacitor SHA Input For best dynamic performance the source impedances driving VIN and VIN should be matched such that common mode settling errors are symmetrical These errors are reduced by the common mode rejection of the ADC An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core The output common mode of the reference buffer is set to approximately 1 6 V Input Common Mode The analog inputs of the AD6655 are not internally dc biased In ac coupled applications the user must provide this bias externally Setting the device so that Vcm 0 55 x AVDD is recommended for optimum performance but the device functions over a wider range with reasonable performance see Figure 45 Rev A Page 29 of 88 AD6655 An on board common mode v
81. egister 0x123 PHASE is the desired NCO phase in degrees NCO AMPLITUDE AND PHASE DITHER The NCO block contains amplitude and phase dither to improve the spurious performance Amplitude dither improves performance by randomizing the amplitude quantization errors within the angular to Cartesian conversion of the NCO This option reduces spurs at the expense of a slightly raised noise floor With amplitude dither enabled the NCO has an SNR of gt 93 dB and an SFDR of gt 115 dB With amplitude dither disabled the SNR is increased to gt 96 dB at the cost of SFDR performance which is reduced to 100 dB The NCO amplitude dither is recommended and is enabled by setting Bit 1 of Register Ox11D Rev A Page 38 of 88 AD6655 DECIMATING HALF BAND FILTER AND FIR FILTER The goal of the AD6655 half band digital filter is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest This filter is designed to operate as either a low pass or a high pass filter and to provide gt 100 dB of alias protection for 11 of the input rate of the structure Used in conjunction with the NCO and the FIR filter the half band filter can provide an effective band pass For an ADC sample rate of 150 MSPS this provides a maximum usable bandwidth of 33 MHz HALF BAND FILTER COEFFICIENTS The 19 tap symmetrical fixed coefficient half band filter has low power consumption due to its polyphase implementa
82. erefore is subject to a latency of 12 ADC clock cycles An overrange at the input is indicated by this bit 12 clock cycles after it occurs GAIN SWITCHING The AD6655 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed Fast detect mode select bits 010 through fast detect mode select bits 101 support various combinations of the gain switching options One such use is to detect when an ADC is about to reach full scale with a particular input condition The result is to provide an indicator that can be used to quickly insert an attenuator that prevents ADC overdrive Fine Upper Threshold UT The fine upper threshold indicator is asserted if the input magnitude exceeds the value programmed in the fine upper threshold register located in Register 0x106 and Register 0x107 The 13 bit threshold register is compared with the signal magni tude at the output of the ADC This comparison is subject to the ADC clock latency but is accurate in terms of converter resolution The fine upper threshold magnitude is defined by the following equation dBFS 20 log Threshold Magnitude 2 Fine Lower Threshold LT The fine lower threshold indicator is asserted if the input magni tude is less than the value programmed in the fine lower thres
83. es place when the transfer bit is set and the bit autoclears Channel Specific Registers Some channel setup functions such as the signal monitor thresholds can be programmed differently for each channel In these cases channel address locations are internally duplicated for each channel These registers and bits are designated in Table 29 as local These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05 If both bits are set the subsequent write affects the registers of both channels In a read cycle only Channel A or Channel B should be set to read one of the two registers If both bits are set during an SPI read cycle the part returns the value for Channel A Registers and bits designated as global in Table 29 affect the entire part or the channel features where independent settings are not allowed between channels The settings in Register 0x05 do not affect the global registers and bits Rev A Page 50 of 88 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 29 are not currently supported for this device Table 29 Memory Map Registers AD6655 Addr Hex Register Name Bit 7 MSB Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Default Value Hex Default Notes Comments Chip Configuration Regis ters 0x00 SPI Port Configuration Global 0 LSB first Soft reset
84. etails Channel A Channel B LVDS Fast Detect Indicator O Complement See Table 21 for details Channel A Channel LVDS Fast Detect Indicator 1 True See Table 21 for details Channel A Channel LVDS Fast Detect Indicator 1 Complement See Table 21 for details Channel A Channel B LVDS Fast Detect Indicator 2 True See Table 21 for details Channel A Channel B LVDS Fast Detect Indicator 2 Complement See Table 21 for details Channel A Channel B LVDS Fast Detect Indicator 3 True See Table 21 for details Channel A Channel B LVDS Fast Detect Indicator 3 Complement See Table 21 for details Rev A Page 21 of 88 AD6655 Digital Input 52 SYNC Input Digital Synchronization Pin Slave mode only Digital Outputs 63 Output Channel A Channel LVDS Output Data 0 True 62 Output Channel A Channel LVDS Output Data 0 Complement 3 Output Channel A Channel B LVDS Output Data 1 True 2 Output Channel A Channel B LVDS Output Data 1 Complement 5 Output Channel A Channel B LVDS Output Data 2 True 4 Output Channel A Channel B LVDS Output Data 2 Complement 7 Output Channel A Channel B LVDS Output Data 3 True 6 Output Channel A Channel B LVDS Output Data 3 Complement 9 Output Channel A Channel B LVDS Output Data 4 True 8 Output Channel A Channel LVDS Output Data 4 Complement 13 Output Channel A Channel B LVDS Output Data 5 True 12 Output Chan
85. g errors back into the signal path if these prove to be a problem in the system Doing so however has the disadvantage of spreading the frequency content of the clock If desired the SMI SCLK can be left running to ease frequency planning SMI SDFS The SMI SDFS is the serial data frame sync and it defines the start of a frame One SPORT frame includes data from both datapaths The data from Datapath A is sent just after the frame sync followed by data from Datapath B SMISDO The SMI SDO is the serial data output of the block The data is sent MSB first on the next positive edge after the SMI SDFS Each data output block includes one or more of rms magnitude peak level and threshold crossing values from each datapath in the stated order If enabled the data is sent rms first followed by peak and threshold as shown in Figure 79 GATED BASED ON CONTROL smsexx nar SMI SDFS 20 CYCLES 16 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES 16 CYCLES Figure 79 Signal Monitor SPORT Output Timing RMS Peak and Threshold Enabled GATED BASED ON CONTROL SMI SDFS 20 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES Figure 80 Signal Monitor SPORT Output Timing RMS and Threshold Enabled VV SMI SDO XX 06709 078 Rev A Page 46 of 88 06709 077 AD6655 CHANNEL CHI
86. gnal monitor block Signal Monitor Period Register 0x113 to Register 0x115 Register 0x115 Bits 7 0 Signal Monitor Period 23 16 Register 0x114 Bits 7 0 Signal Monitor Period 15 8 Register 0x113 Bits 7 0 Signal Monitor Period 7 0 This 24 bit value sets the number of clock cycles over which the signal monitor performs its operation The minimum value for this register is 128 cycles programmed values less than 128 revert to 128 Signal Monitor Result Channel A Register 0x116 to Register 0x118 Register 0x118 Bits 7 4 Reserved Register 0x118 Bits 3 0 Signal Monitor Result Channel A 19 16 Register 0x117 Bits 7 0 Signal Monitor Result Channel A 15 8 Register 0x116 Bits 7 0 Signal Monitor Result Channel A 7 0 This 20 bit value contains the power value calculated by the signal monitor block for Channel A The content is dependent on the settings in Register 0x112 Bits 2 1 Signal Monitor Result Channel B Register 0x119 to Register Ox11B Register Ox11B Bits 7 4 Reserved Register 0x11B Bits 3 0 Signal Monitor Result Channel B 19 16 Register 0x11A Bits 7 0 Signal Monitor Result Channel B 15 8 Register 0x119 Bits 7 0 Signal Monitor Result Channel B 7 0 This 20 bit value contains the power value calculated by the signal monitor block for Channel B The content is dependent on the settings in Register 0x112 Bits 2 1 NCO Control Register Ox11D Bits 7 3 Reser
87. h a period from 128 samples to 16 78 2 million samples Because the dc offset of the ADC can be significantly larger than the signal of interest affecting the results from the signal monitor a dc correction circuit is included as part of the signal monitor block to null the dc offset before measuring the power PEAK DETECTOR MODE The magnitude of the input port signal is monitored over a programmable time period determined by SMPR to give the peak value detected This function is enabled by programming a Logic 1 in the signal monitor mode bits of the signal monitor control register or by setting the peak detector output enable bit in the signal monitor SPORT control register The 24 bit SMPR must be programmed before activating this mode After enabling this mode the value in the SMPR is loaded into a monitor period timer and the countdown is started The magnitude of the input signal is compared with the value in the internal peak level holding register not accessible to the user and the greater ofthe two is updated as the current peak level The initial value of the peak level holding register is set to the current ADC input signal magnitude This comparison continues until the monitor period timer reaches a count of 1 When the monitor period timer reaches a count of 1 the 13 bit peak level value is transferred to the signal monitor holding register not accessible to the user which can be read through the SPI port or out
88. he SCLK ts Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state trow Minimum period that SCLK should be in a logic low state 500 Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge tois 500 Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge SPORT TIMING REQUIREMENTS tcsscik Delay from rising edge of CLK to rising edge of SMI SCLK 1581 Delay from rising edge of SMI SCLK to SMI SDO 16661 50 5 Delay from rising edge of SMI SCLK to SMI SDFS Timing Diagrams CLK tpp toco DECIMATED CHANNEL A B CHANNEL A B CHANNEL A B CMOS DATA DATA BITS DATA BITS DATA BITS DECIMATED CHANNEL A B CHANNEL A B CHANNEL A B CHANNEL A B CHANNEL A B CHANNEL A B FD DATA FD BITS FD BITS FD BITS FD BITS FD BITS FD BITS gt DECIMATED 8 DCOA DCOB t 5 Figure 2 Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing Fast Detect Mode Select Bits 000 CLK tpp toco DECIMATED CHANNEL A B CHANNEL A B CHANNEL A B CMOS DATA DATA BITS DATA BITS DATA BITS CHANNEL A B CHANNEL A B CHANNEL A B Dig or FD BITS FD BITS FD BITS ts DECIMATED t DCOA DCOB H 06709 012 Figure 3 Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing Fast Detect Mode Select Bits 001 Through Fast Detec
89. her type of source by gating dividing or another method it should be retimed by the original clock at the last step Refer to Application Note AN501 and Application Note AN756 for more information about jitter performance as it relates to ADCs see www analog com POWER DISSIPATION AND STANDBY MODE As shown in Figure 64 through Figure 67 the power dissipated by the AD6655 is proportional to its sample rate In CMOS output mode the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit The maximum DRVDD current Iprvpp can be calculated by X Croan xN where N is the number of output bits 30 in the case of the AD6655 assuming the FD bits are inactive This maximum current occurs when every output bit switches on every clock cycle that is a full scale square wave at the Nyquist frequency of fcix 2 In practice the DRVDD current is established by the average number of output bits switching which is determined by the sample rate and the characteristics of the analog input signal Reducing the capacitive load presented to the output drivers can minimize digital power consumption The data in Figure 64 through Figure 67 was taken using the same operating conditions as those used for the Typical Performance Characteristics with a 5 pF load on each output driver TOTAL POWER W TOTAL POWER W TOTAL POWER W 1 50
90. his document details the functions controlled by Register 0x00 to Register OxFF The remaining registers from Register 0x100 to Register 0x123 are documented in the Memory Map Register Description section Open Locations All address and bit locations that are not included in Table 29 are not currently supported for this device Unused bits of a valid address location should be written with 0s Writing to these locations is required only when part of an address location is open for example Address 0x18 If the entire address location is open for example Address 0x13 this address location should not be written Default Values After the AD6655 is reset critical registers are loaded with default values The default values for the registers are given in the memory map register table Table 29 Logic Levels An explanation of logic level terminology follows e Bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit e Clear a is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit Transfer Register Map Address 0x08 to Address 0x18 and Address 0x11E to Address 0x123 are shadowed Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address OxFE setting the transfer bit This allows these registers to be updated internally and simultaneously when the transfer bit is set The internal update tak
91. hold register located at Register 0x108 and Register 0x109 The fine lower threshold register is a 13 bit register that is compared with the signal magnitude at the output of the ADC This comparison is subject to ADC clock latency but is accurate in terms of converter resolution The fine lower threshold magnitude is defined by the following equation dBFS 20 log Threshold Magnitude 2 The operation of the fine upper threshold and fine lower threshold indicators is shown in Figure 75 Rev A Page 42 of 88 Increment Gain IG and Decrement Gain DG The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control The decrement gain indicator works in conjunction with the coarse upper threshold bits asserting when the input magnitude is greater than the 3 bit value in the coarse upper threshold register Address 0x105 The increment gain indicator similarly corresponds to the fine lower threshold bits except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses The dwell time is set by the 16 bit dwell time value located at Address 0x10A and Address 0x10B and is set in units of ADC input clock cycles ranging from 1 to 65 535 The fine lower threshold register is a 13 bit register that is compared 1 IG 1 1 C_UT AND F_UT DIFFER ONL
92. hree pins define the SPI of this ADC the SCLK DFS pin the SDIO DCS pin and the CSB pin see Table 26 The SCLK DFS serial clock pin is used to synchronize the read and write data presented from to the ADC The SDIO DCS serial data input output pin is a dual purpose pin that allows data to be sent and read from the internal ADC memory map registers The CSB chip select bar pin is an active low control that enables or disables the read and write cycles Table 26 Serial Port Interface Pins Pin Function SCLK Serial Clock The serial shift clock input which is used to synchronize serial interface reads and writes SDIO Serial Data Input Output A dual purpose pin that typically serves as an input or an output depending on the instruction being sent and the relative position in the timing frame 58 Chip Select Bar active low control that gates the read and write cycles The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing An example of the serial timing and its definitions can be found in Figure 81 and Table 9 Other modes involving the CSB are available The CSB can be held low indefinitely which permanently enables the device this is called streaming The CSB can stall high between bytes to allow for additional external timing When CSB is tied high SPI functions are placed in a high impedance mode This mode turns on any SPI pin secondar
93. hreshold Crossing Output Enable Bit 4 enables the 13 bit threshold measurement as output on the SPORT Bits 3 2 SPORT SMI SCLK Divide The values of these bits set the SPORT SMI SCLK divide ratio from the input clock A value of 0x01 sets divide by 2 default a value of 0x10 sets divide by 4 and a value of 0x11 sets divide by 8 Bit 1 SPORT SMI SCLK Sleep Setting Bit 1 high causes the SMI SCLK to remain low when the signal monitor block has no data to transfer Bit 0 Signal Monitor SPORT Output Enable When set Bit 0 enables the signal monitor SPORT output to begin shifting out the result data from the signal monitor block Signal Monitor Control Register 0x1 12 Bit 7 Complex Power Calculation Mode Enable This mode assumes I data is present on one channel and Q data is present on the alternate channel The result reported is the complex power measured as JP Q Bits 6 4 Reserved Bit 3 Signal Monitor RMS MS Select Setting Bit 3 low selects rms power measurement mode Setting Bit 3 high selects ms power measurement mode Bits 2 1 Signal Monitor Mode Bit 2 and Bit 1 set the mode of the signal monitor for data output to registers at Address 0x116 through Address 0x11B Setting these bits to 0x00 selects rms ms magnitude output setting these bits to 0x01 selects peak detector output and setting 0x10 or 0x11 selects threshold crossing output Bit 0 Signal Monitor Enable Setting Bit 0 high enables the si
94. ing this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path Bit O DC Correction for Signal Monitor Enable This bit enables the dc correction function in the signal monitor block The dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal Removing this dc from the measurement allows a more accurate power reading Signal Monitor DC Value Channel A Register 0 100 and Register Ox10E Register Ox10E Bits 7 6 Reserved Register Ox10E Bits 5 0 DC Value Channel A 13 8 Register 0x10D Bits 7 0 DC Value Channel A 7 0 These read only registers hold the latest dc offset value computed by the signal monitor for Channel A Rev A Page 56 of 88 AD6655 Signal Monitor DC Value Channel B Register Ox10F and Register 0x110 Register 0x110 Bits 7 6 Reserved Register 0x110 Bits 5 0 Channel DC Value Bits 13 8 Register 0 10 Bits 7 0 Channel B DC Value Bits 7 0 These read only registers hold the latest dc offset value computed by the signal monitor for Channel B Signal Monitor SPORT Control Register 0x111 Bit 7 Reserved Bit 6 RMS MS Magnitude Output Enable Bit 6 enables the 20 bit rms or ms magnitude measurement as output on the SPORT Bit 5 Peak Detector Output Enable Bit 5 enables the 13 bit peak measurement as output on the SPORT Bit 4 T
95. interleaved CMOS IQ mode CMOS and interleaved LVDS 6 SYNC input allows synchronization of multiple devices 7 3 bit SPI port for register programming and register readback FUNCTIONAL BLOCK DIAGRAM AVDD O FD 0 3 A O FD BITS THRESHOLD DETECT lt gt lt AD6655 DECIMATING HB FILTER FIR 5 e 95 o DECIMATING 2a HB FILTER 2 FIR PROGRAMMING DATA 99 Q o MULTI CHIP FD BITS THRESHOLD SIGNAL MONITOR SIGNAL MONITOR SYNC DETECT DATA INTERFACE AGND SYNC FD 0 3 B SM SMI SDIO SCLK CSB DRGND SDFS SCLK SDO DCS DFS PDWN NOTES 1 PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY SEE FIGURE 10 FOR LVDS PIN NAMES Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 06709 001 Figure 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 2009 Analog Devices Inc All rights reserved AD6655 TABLE OF CONTENTS
96. it 7 Bit 0 Value Notes Hex Name MSB Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 LSB Hex Comments 0 121 NCO Frequency Value 31 24 0x00 Frequency 3 0 122 NCO Phase NCO Phase Value 7 0 0x00 Offset 0 0x123 NCO Phase NCO Phase Value 15 8 0x00 Offset 1 MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register see Application Note AN 877 Interfacing to High Speed ADCs via SPI at www analog com SYNC Control Register 0x100 Bit 7 Signal Monitor Sync Enable Bit 7 enables the sync pulse from the external sync input to the signal monitor block The sync signal is passed when Bit 7 and Bit 0 are high This is continuous sync mode Bit 6 Half Band Next Sync Only If the master sync enable bit Register 0x100 Bit 0 and the half band sync enable bit Register 0x100 Bit 5 are high Bit 6 allows the NCO32 to synchronize following the first sync pulse it receives and ignore the rest If Bit 6 is set Bit 5 of Register 0x100 resets after this sync occurs Bit 5 Half Band Sync Enable Bit 5 gates the sync pulse to the half band filter When Bit 5 is set high the sync signal causes the half band to resynchro nize starting at the half band decimation phase selected in Register 0x103 Bit 3 This sync is active only when the master sync enable bit Register 0x100 Bit 0 is high This is continuous sync mode Bit 4 NCO32 Next Sync Only If the m
97. itch again sets to the SENSE pin Table 15 Reference Configuration Summary AD6655 This puts the reference amplifier in a noninverting mode with the VREF output defined as follows VREF 0 5 The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference VIN A VIN B 06709 054 SELECT LOGIC AD6655 06709 055 Figure 53 Programmable Reference Configuration Resulting Differential Selected Mode SENSE Voltage Resulting VREF V Span V p p External Reference AVDD N A 2 x external reference Internal Fixed Reference VREF 0 5 1 0 R2 Programmable Reference 0 2 V to VREF 0 5 0 see Figure 53 2 x VREF Internal Fixed Reference AGND to 0 2 V 1 0 2 0 Rev A Page 31 of 88 AD6655 If the internal reference of the AD6655 is used to drive multiple converters to improve gain matching the loading of the reference by the other converters must be considered Figure 54 depicts how the internal reference voltage is affected by loading 0 b 3 REFERENCE VOLTAGE ERROR 5 4 a 1 L 5 eee 1 25 0 0 5 1 0 1 5 2 0 LOAD CURRENT mA Figure 54 VREF Accuracy vs Load 06709 056 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac teristics Fig
98. le Package LFCSP VQ 64 Lead Lead Frame Chip Scale Package LFCSP VQ 64 Lead Lead Frame Chip Scale Package LFCSP VQ 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 Lead Lead Frame Chip Scale Package LFCSP_VQ Evaluation Board with AD6655 and Software Evaluation Board with AD6655 and Software Rev A Page 85 of 88 AD6655 Package Option CP 64 6 CP 64 6 CP 64 6 CP 64 6 CP 64 6 CP 64 6 CP 64 3 CP 64 3 CP 64 3 CP 64 3 AD6655 NOTES Rev A Page 86 of 88 AD6655 NOTES Rev A Page 87 of 88 AD6655 NOTES 2007 2009 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06709 0 9 09 A DEVICES www analo g com Rev A Page 88 of 88
99. lex Power Calculation Mode Enable Bit When this bit is set the part assumes that Channel A is digitizing the I data and Channel B is digitizing the Q data for a complex input signal or vice versa In this mode the power reported is equal to This result is presented in the Signal Monitor DC Value Channel A register if the signal monitor mode bits are set to 00 The Signal Monitor DC Value Channel B register continues to compute the Channel B value DC CORRECTION Because the dc offset of the ADC may be significantly larger than the signal being measured a dc correction circuit is included to null the dc offset before measuring the power The dc correction circuit can also be switched into the main signal path but this may not be appropriate if the ADC is digitizing a time varying signal with significant dc content such as GSM Rev A Page 45 of 88 AD6655 DC Correction Bandwidth The correction circuit is a high pass filter with a programmable bandwidth ranging between 0 15 Hz and 1 2 kHz at 125 MSPS The bandwidth is controlled by writing the 4 bit dc correction control register located at Register 0x10C Bits 5 2 The following equation be used to compute the bandwidth value for the correction circuit DC Corr BW 2 x 2 where k is the 4 bit value programmed in Bits 5 2 of Register 0x10C values between 0 and 13 are valid for k programming 14 or 15 provides the same result as programmi
100. ll 26 26 kQ Input Capacitance Full 2 2 pF LOGIC INPUTS SDIO DCS SMI 5065 High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 10 10 10 10 Low Level Input Current Full 38 128 38 128 Input Resistance Full 26 26 kQ Input Capacitance Full 5 5 pF Rev A Page 9 of 88 AD6655 AD6655BCPZ 80 AD6655BCPZ 105 Parameter Temp Min Typ Max Min Typ Max Unit LOGIC INPUTS SMI SDO OEB SMI SCLK PDWN High Level Input Voltage Full 1 22 3 6 1 22 3 6 V Low Level Input Voltage Full 0 0 6 0 0 6 V High Level Input Current Full 90 134 90 134 Low Level Input Current Full 10 10 10 10 Input Resistance Full 26 26 kQ Input Capacitance Full 5 5 pF DIGITAL OUTPUTS CMOS Mode DRVDD 3 3 V High Level Output Voltage lon 50 pA Full 3 29 3 29 V lou 0 5 mA Full 3 25 3 25 V Low Level Output Voltage lo 1 6 mA Full 0 2 0 2 V lot 50 Full 0 05 0 05 V CMOS Mode DRVDD 1 8V High Level Output Voltage lou 50 pA Full 1 79 1 79 lou 0 5 mA Full 1 75 1 75 V Low Level Output Voltage lo 1 6 mA Full 0 2 0 2 V lo 50 Full 0 05 0 05 V LVDS Mode DRVDD 1 8 V Differential Output Voltage VOD Full 250 350 450 250 350 450 mV ANSI Mode Output Offset Voltage VOS Full 1 15 1 25 1 35 1 15 1 25 1 35 V ANSI Mode Differential Output Voltage VOD Full 150 200 280 150 200 280 mV Reduced Swing Mode Output Offset Volt
101. lue of the internal count register is set to 0 This comparison and incrementing of the internal count register continues until the monitor period timer reaches a count of 1 AD6655 When the monitor period timer reaches a count of 1 the value in the internal count register is transferred to the signal monitor holding register which can be read through the SPI port or output through the SPORT serial port The monitor period timer is reloaded with the value in the SMPR register and the countdown is restarted The internal count register is also cleared to a value of 0 Figure 78 illustrates the threshold crossing logic The value in the SMR register is the number of samples that have a magnitude greater than the threshold register FROM MEMORY MAP TO INTERRUPT CONTROLLER TO MEMORY POWER MONITOR MAP COMPARE HOLDING REGISTER REGISTER 06709 076 Figure 78 ADC Input Threshold Crossing Block Diagram ADDITIONAL CONTROL BITS For additional flexibility in the signal monitoring process two control bits are provided in the signal monitor control register They are the signal monitor enable bit and the complex power calculation mode enable bit Signal Monitor Enable Bit The signal monitor enable bit located in Bit 0 of Register 0x112 enables operation of the signal monitor block If the signal monitor function is not needed in a particular application this bit should be cleared to conserve power Comp
102. ly through the AD8352 differential driver The ADC can also be driven in a single ended fashion Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry Each input configuration can be selected by proper connection of various components see Figure 85 to Figure 94 Figure 84 shows the typical bench characterization setup used to evaluate the ac performance of the AD6655 It is critical that the signal sources used for the analog input and clock have very low phase noise lt lt 1 ps rms jitter to realize the optimum performance of the converter Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance See Figure 85 to Figure 102 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides 6 V 2 A maximum output Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz The output of the supply is a 2 1 mm inner diameter circular jack that connects to the PCB at J16 Once on the PC board the 6 V supply is fused and conditioned before connection to six low dropout linear regulators that supply the proper bias to each of the various sections on the board WALL OUTLET 100V T
103. mation reversal low pass Global phase select Rev A Page 52 of 88 AD6655 Addr Hex Register Name Bit 7 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Default Value Hex Default Notes Comments 0 1 04 Fast Detect Control Local Open Open Open Open Fast Detect Mode Select 2 0 Fast detect enable 0x00 0 1 05 Coarse Upper Threshold Local Open Open Open Open Open Coarse Upper Threshold 2 0 0x00 0 1 06 Fine Upper Threshold Register 0 Local Fine Upper Threshold 7 0 0x00 0 1 07 Fine Upper Threshold Register 1 Local Open Open Open Fine Upper Threshold 12 8 0x00 0 1 08 Fine Lower Threshold Register 0 Local Fine Lower Threshold 7 0 0x00 0 1 09 Fine Lower Threshold Register 1 Local Open Open Open Fine Lower Threshold 12 8 0x00 0 10 Increase Gain Dwell Time Register 0 Local Increase Gain Dwell Time 7 0 0x00 In ADC clock cycles 0x10B Increase Gain Dwell Time Register 1 Local Increase Gain Dwell Time 15 8 0x00 In ADC clock cycles 0x10C Signal Monitor DC Correction Control Global Open DC correction freeze DC Correction Bandwidth k 3 0 DC correction for signal
104. multiple AD6655s Because the decimation filter prevents usage of half the Nyquist spectrum a means is needed to translate the sampled input spectrum into the usable range of the decimation filter To achieve this a 32 bit fine tuning complex NCO is provided This NCO mixer allows the input spectrum to be tuned to dc where it can be effectively filtered by the subsequent filter blocks to prevent aliasing HALF BAND DECIMATING FILTER AND FIR FILTER The goal of the AD6655 digital filter block is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest The half band filter is designed to operate as either a low pass or high pass filter and to provide greater than 100 dB of alias protection for 2296 of the input rate of the structure For an ADC sample rate of 150 MSPS this provides a maximum usable bandwidth of 16 5 MHz when using the filter in real mode NCO bypassed or a maximum usable bandwidth of 33 0 MHz when using the filter in the complex mode NCO enabled The optional fixed coefficient FIR filter provides additional filtering capability to sharpen the half band roll off to enhance the alias protection It removes the negative frequency images to avoid aliasing negative frequencies for real outputs 8 FIXED FREQUENCY NCO A fixed fanc 8 NCO is provided to translate the filtered decimated signal from dc to fanc 8 to allow a real output Figure 68 to Figure 71
105. nable bit Register 0x101 Bit 0 are high Bit 1 allows the fs 8 output mix to synchronize following the first sync pulse it receives and ignore the rest Bit 0 of Register 0x100 resets after it synchronizes Bit O fs 8 Sync Enable Bit 0 gates the sync pulse to the fs 8 output mix This sync is active only when the master sync enable bit Register 0x100 Bit 0 is high This is continuous sync mode FIR Filter and Output Mode Control Register 0x102 Bits 7 4 Reserved Bit 3 FIR Gain When Bit 3 is set high the FIR filter path if enabled has a gain of 1 When Bit 3 set low the FIR filter path has a gain of 2 Bit 2 f 8 Output Mix Disable Bit 2 disables the fs 8 output mix when enabled Bit 2 should be set along with Bit 1 to enable complex output mode Bit 1 Complex Output Mode Enable Setting Bit 1 high enables complex output mode Bit 0 FIR Filter Enable When set high Bit 0 enables the FIR filter When Bit 0 is cleared the FIR filter is bypassed and shut down for power savings Rev A Page 55 of 88 AD6655 Digital Filter Control Register 0x103 Bits 7 4 Reserved Bit 3 Half Band Decimation Phase When set high Bit 3 uses the alternate phase of the decimating half band filter Bit 2 Spectral Reversal Bit 2 enables the spectral reversal feature of the half band filter Bit 1 High Pass Low Pass Select Bit 1 enables the high pass mode of the half band filter when set high Setting this bit
106. nal or only on the first SYNC signal after the register is written A valid SYNC causes the clock divider to reset to its initial state This synchro nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and as a result may be sensitive to clock duty cycle Commonly a 5 tolerance is required on the clock duty cycle to maintain dynamic performance characteristics The AD6655 contains a duty cycle stabilizer DCS that retimes the nonsampling falling edge providing an internal clock signal with a nominal 5096 duty cycle This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6655 Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on as shown in Figure 44 Jitter on the rising edge of the input clock is still of paramount concern and is not easily reduced by the internal stabilization circuit The duty cycle control loop does not function for clock rates less than 20 MHz nominally The loop has a time constant associated with it that must be considered when the clock rate can change dynamically A wait time of 1 5 us to 5 us is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal During the time period
107. nalog Devices AD6655BCPZ 40 1 U2 Clock distribution PLL IC LFCSP64 9X9 Analog Devices AD9516 4BCPZ 41 1 U3 Dual inverter IC SC70 6 Fairchild Semiconductor NC7WZO4P6X NL 42 1 U7 Dual buffer IC SC70 6 Fairchild Semiconductor NC7WZ07P6X NL open drain circuits 43 1 U8 UHS dual buffer IC 5 70 6 Fairchild Semiconductor NC7WZ16P6X NL 44 3 U15 to U17 16 bit CMOS buffer IC 5 48 8 1 Fairchild Semiconductor 74VCX16244MTDX_NL 45 2 VR1 VR2 Adjustable regulator LFCSP8 3X3 Analog Devices ADP3334ACPZ 46 1 VR3 1 8 V high accuracy regulator SOT223 HS Analog Devices ADP3339AKCZ 1 8 47 1 VR4 5 0 V high accuracy regulator SOT223 HS Analog Devices ADP3339AKCZ 5 0 48 2 VR5 VR6 3 3 V high accuracy regulator SOT223 HS Analog Devices ADP3339AKCZ 3 3 49 1 Y1 Oscillator clock VFAC3 OSC CTS CB3 Valpey Fisher VFAC3 BHL 50 2 71 72 High speed IC op amp LFCSP16 3X3 PAD Analog Devices AD8352ACPZ This bill of materials is ROHS compliant The bill of materials lists only those items that are normally installed in the default condition Items that are not installed are not included in the BOM Rev A Page 83 of 88 AD6655 OUTLINE DIMENSIONS gt 0 60 MAX 0 60 MAX PIN 1 INDICATOR PIN 1 INDICATOR 0 50 7 25 TOP VIEW 5 BSC EXPOSED PAD 71050 BOTTOM VIEW 6 95 0 50 0 40 0 30 0 25 MIN 100 12 0 80 ___ 0 85 0 65 FOR PROPER CONNECTION OF 280 0 05
108. ncy given by CLK 2 e 0 0000 0000 represents dc frequency 0 Hz e Ox7FFF FFFF represents CLK 2 CLK 2 Use the following equation to calculate the NCO frequency 4 FREQ 2 x f CLK where NCO FREQ is a 32 bit twos complement number representing the NCO frequency register fis the desired carrier frequency in hertz Hz faxis the AD6655 ADC clock rate in hertz Hz NCO SYNCHRONIZATION The AD6655 NCOs within a single part or across multiple parts can be synchronized using the external SYNC input Bit 3 and Bit 4 of Register 0x100 allow the NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written A valid SYNC causes the NCO to restart at the programmed phase offset value PHASE OFFSET The NCO phase offset register at Address 0x122 and Address 0x123 adds a programmable offset to the phase accumulator of the NCO This 16 bit register is interpreted as a 16 bit unsigned integer A 0x00 in this register corresponds to no offset and a OxFFFF corresponds to an offset of 359 995 Each bit represents a phase change of 0 005 This register allows multiple NCOs to be synchronized to produce outputs with predictable phase differences Use the following equation to calculate the NCO phase offset value NCO PHASE 25 x PHASE 360 where NCO_PHASE is a decimal number equal to the 16 bit binary number to be programmed at Register 0x122 and R
109. nel A Channel B LVDS Output Data 5 Complement 15 Output Channel A Channel B LVDS Output Data 6 True 14 Output Channel A Channel B LVDS Output Data 6 Complement 17 Output Channel A Channel B LVDS Output Data 7 True 16 Output Channel A Channel B LVDS Output Data 7 Complement 19 Output Channel A Channel B LVDS Output Data 8 True 18 Output Channel A Channel B LVDS Output Data 8 Complement 23 Output Channel A Channel B LVDS Output Data 9 True 22 Output Channel A Channel B LVDS Output Data 9 Complement 26 Output Channel A Channel B LVDS Output Data 10 True 25 Output Channel A Channel B LVDS Output Data 10 Complement 28 Output Channel A Channel B LVDS Output Data 11 True 27 Output Channel A Channel B LVDS Output Data 11 Complement 30 Output Channel A Channel B LVDS Output Data 12 True 29 Output Channel A Channel B LVDS Output Data 12 Complement 32 Output Channel A Channel LVDS Output Data 13 True 31 Output Channel A Channel B LVDS Output Data 13 Complement Output Channel A Channel B LVDS Data Clock Output True Output Channel A Channel B LVDS Data Clock Output Complement SPI Control 48 SCLK DFS Input SPI Serial Clock Data Format Select Pin in External Pin Mode 47 SDIO DCS Input Output SPI Serial Data l O Duty Cycle Stabilizer in External Pin Mode 51 CSB Input SPI Chip Select Active Low Signal Monitor Port 33 SMI SDO OEB Input Output Signal Monitor Serial Data Output
110. ng 13 faxis the AD6655 ADC sample rate in hertz Hz DC Correction Readback The current dc correction value can be read back in Register 0x10D and Register 0 10 for Channel A and Register 0x10F and Register 0x110 for Channel The dc correction value is a 14 bit value that can span the entire input range of the ADC DC Correction Freeze Setting Bit 6 of Register 0x10C freezes the DC correction at its current state and continues to use the last updated value as the dc correction value Clearing this bit restarts dc correction and adds the currently calculated value to the data DC Correction Enable Bits Setting Bit 0 of Register 0x10C enables dc correction for use in the signal monitor calculations The calculated dc correction value can be added to the output data signal path by setting Bit 1 of Register 0x10C SIGNAL MONITOR SPORT OUTPUT The SPORT is a serial interface with three output pins the SMI SCLK SPORT clock SMI SDFS SPORT frame sync and SMI SDO SPORT data output The SPORT is the master and drives all three SPORT output pins on the chip SMI SCLK The data and frame sync are driven on the positive edge of the SMI SCLK The SMI SCLK has three possible baud rates 1 2 1 4 or 1 8 the ADC clock rate based on the SPORT controls The SMI SCLK can also be gated off when not sending any data based on the SPORT SMI SCLK sleep bit Using this bit to disable the SMI SCLK when it is not needed can reduce any couplin
111. nput for the next stage in the pipeline One bit of redundancy is used in each stage to facilitate digital correction of flash errors The last stage simply consists of a flash ADC The input stage of each channel contains a differential SHA that can be ac or dc coupled in differential or single ended modes The output staging block aligns the data corrects errors and passes the data to the output buffers The output buffers are powered from a separate supply allowing adjustment of the output voltage swing During power down the output buffers go into a high impedance state AD6655 ANALOG INPUT CONSIDERATIONS The analog input to the AD6655 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal The clock signal alternatively switches the SHA between sample mode and hold mode see Figure 46 When the SHA is switched into sample mode the signal source must be capable of charging the sample capacitors and settling within 1 2 of a clock cycle A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source A shunt capacitor can be placed across the inputs to provide dynamic charging currents This passive network creates a low pass filter at the ADC input therefore the precise values are dependent on the application In IF undersampling applications any shunt capacitors should b
112. nt jitter performance 0 1pF CLOCK INPUT AD951x LVDS DRIVER CLOCK 6 INPUT 50 06709 061 Figure 60 Differential LVDS Sample Clock Up to 625 MHz In some applications it may be acceptable to drive the sample clock inputs with a single ended CMOS signal In such applica tions the CLK pin should be driven directly from a CMOS gate and the 1 pin should be bypassed to ground with a 0 1 capacitor in parallel with a 39 resistor see Figure 61 CLK can be driven directly from CMOS gate Although the CLK input circuit supply is AVDD 1 8 V this input is designed to withstand input voltages of up to 3 6 V making the selection of the drive logic voltage very flexible Vcc OPTIONAL CLOCK 951 1000 CLK NEUT CMOS DRIVER 500 ADC AD6655 0 1pF 06709 062 OPTIONAL 4000 1HF AD951x CMOS DRIVER CLK ADC AD6655 0 147 4 Figure 62 Single Ended 3 3 V CMOS Sample Clock Up to 150 MSPS 06709 063 AD6655 Input Clock Divider The AD6655 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8 If a divide ratio other than 1 is selected the duty cycle stabilizer is auto matically enabled The AD6655 clock divider can be synchronized using the external SYNC input Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC sig
113. oltage reference is included in the design and is available from the CML pin Optimum perform ance is achieved when the common mode voltage of the analog input is set by the CML pin voltage typically 0 55 x AVDD Differential Input Configurations Optimum performance is achieved while driving the AD6655 in a differential input configuration For baseband applications the AD8138 ADA4937 2 and ADA4938 2 differential drivers provide excellent performance and a flexible interface to the ADC The output common mode voltage of the AD8138 is easily set with the CML pin ofthe AD6655 see Figure 47 and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal Vp p 49 90 O VIN AD6655 CML O 06709 049 Figure 47 Differential Input Configuration Using the AD8138 For baseband applications where SNR is a key parameter differential transformer coupling is the recommended input configuration An example is shown in Figure 48 To bias the analog input the CML voltage can be connected to the center tap of the secondary winding of the transformer 06709 050 0 1 ANALOG INPUT O AD8352 ANALOG INPUT 0 09 The signal characteristics must be considered when selecting a transformer Most RF transformers saturate at frequencies below a few megahertz MHz Excessive signal power can also cause core saturation which leads
114. put through the SPORT serial interface The monitor period timer is reloaded with the value in the SMPR and the countdown is restarted In addition the magnitude of the first input sample is updated in the peak level holding register and the comparison and update procedure as explained previously continues Figure 76 is a block diagram of the peak detector logic The SMR register contains the absolute magnitude of the peak detected by the peak detector logic FROM 5 AP INTERRUPT POWER MONITOR DOWN CONTROLLER PERIOD REGISTER gt COUNTER 1 E FROM TO INPUT MEMORY MAP MAGNITUDE POWER MONITOR STORAGE HOLDING REGISTER A REGISTER COMPARE gt 06709 074 Figure 76 ADC Input Peak Detector Block Diagram RMS MS MAGNITUDE MODE In this mode the root mean square rms or mean square ms magnitude of the input port signal is integrated by adding an accumulator over a programmable time period determined by SMPR to give the rms or ms magnitude of the input signal This mode is set by programming Logic 0 in the signal monitor mode bits of the signal monitor control register or by setting the rms magnitude output enable bit in the signal monitor SPORT control register The 24 bit SMPR representing the period over which integration is performed must be programmed before activating this mode After enabling the rms ms magnitude mode the value in the SMPR is loaded into a monitor perio
115. r Threshold Bits 12 8 Register 0x108 Bits 7 0 Fine Lower Threshold Bits 7 0 These registers provide a fine lower limit threshold This 13 bit value is compared with the 13 bit magnitude from the ADC block If the ADC magnitude is less than this threshold value the LT indicator is set Increase Gain Dwell Time Register and Register 0x10B Register 0x10B Bits 7 0 Increase Gain Dwell Time Bits 15 8 Register 0x10A Bits 7 0 Increase Gain Dwell Time Bits 7 0 These register values set the minimum time in ADC sample clock cycles after clock divider that a signal needs to stay below the fine lower threshold limit before the F LT and IG are asserted high Signal Monitor DC Correction Control Register 0x10C Bit 7 Reserved Bit 6 DC Correction Freeze When Bit 6 is set high the dc correction is no longer updated to the signal monitor block which holds the last dc value calculated Bits 5 2 DC Correction Bandwidth Bits 5 2 set the averaging time of the signal monitor dc correction function This 4 bit word sets the bandwidth of the correction block according to the following equation DC Corr BW 22 x 2 where kis the 4 bit value programmed in Bits 5 2 of Register 0 10 values between 0 and 13 are valid for k programming 14 or 15 provides the same result as programming 13 faxis the AD6655 ADC sample rate in hertz Hz Bit 1 DC Correction for Signal Path Enable Sett
116. r clock source is converted from a single ended signal to a differential signal using an RF transformer The back to back Schottky diodes across the transformer secondary limit clock excursions into the AD6655 to approximately 0 8 V p p differential This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6655 while preserving the fast rise and fall times of the signal which are critical to a low jitter performance Mini Circuits ADT1 1WT 1 12 0 1pF 0 1pF b eh soo 1000 0 1uF SCHOTTKY 8 DIODES 2 HSMS2822 8 Figure 57 Transformer Coupled Differential Clock Up to 200 MHz SCHOTTKY DIODES CLOCK INPUT l J 500 0 1uF SL HSMS2822 Figure 58 Balun Coupled Differential Clock Up to 625 MHz 06709 157 If a low jitter clock source is not available another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 59 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 AD9516 clock drivers offer excellent jitter performance Rev A Page 32 of 88 0 1pF CLOCK INPUT um AD951x o iyr PECL DRIVER AD6655 CLOCK A 6 INPUT 50kQ 50kQ 2400 2400 06709 060 Figure 59 Differential PECL Sample Clock Up to 625 MHz A third option is to ac couple a differential LVDS signal to the sample clock input pins as shown in Figure 60 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 AD9516 clock drivers offer excelle
117. rse upper threshold register Address 0x105 2 0 This value is compared with the ADC Fast Magnitude Bits 2 0 The coarse upper threshold output is output two clock cycles after the level is exceeded at the input and therefore provides a fast indication of the input signal level The coarse upper threshold levels are shown in Table 25 This indicator remains asserted for a minimum of two ADC clock cycles or until the signal drops below the threshold level Table 25 Coarse Upper Threshold Levels When the fast detect mode select bits are set to 05010 or 05011 that is when ADC fast magnitude is presented on the FD 2 1 pins the LSB is not provided The input ranges for this mode are shown in Table 24 C_UT Is Active When Signal Coarse Upper Threshold Magnitude Below FS Register 2 0 Is Greater Than dB 000 24 001 24 010 14 5 011 10 100 7 101 5 110 3 25 111 1 8 Table 24 ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits 010 or 011 ADC Fast Nominal Input Nominal Input Magitude on Magnitude Magnitude FD 2 1 Pins Below FS dB Uncertainty dB 00 14 5 Minimum to 12 04 01 14 5 to 7 18 07 to 6 02 10 7 to 3 25 8 52 0 2 5 11 3 25 00 4 08 00 ADC OVERRANGE OR The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC The overrange condition is determined at the output of the ADC pipeline and th
118. rted or when an NCO SYNC signal is received This process allows the NCO to be started with a known nonzero phase Use the following equation to calculate the NCO phase offset value NCO PHASE 25 x PHASE 360 where NCO PHASE is a decimal number equal to the 16 bit binary number to be programmed at Register 0x122 and Register 0x123 PHASE is the desired NCO phase in degrees Rev A Page 58 of 88 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD6655 it is recommended that the designer become familiar with these guidelines which discuss the special circuit connections and layout requirements needed for certain pins Power and Ground Recommendations When connecting power to the AD6655 it is recommended that two separate 1 8 V supplies be used one supply should be used for analog AVDD and digital DVDD and a separate supply should be used for the digital outputs DRVDD The AVDD and DVDD supplies while derived from the same source should be isolated with a ferrite bead or filter choke and separate decoupling capacitors The designer can employ several different decoupling capacitors to cover both high and low frequencies These capacitors should be located close to the point of entry at the PC board level and close to the pins of the part with minimal trace length A single PCB ground plane should be sufficient when using the AD6655 With proper decoupling and smart
119. s an output during readback The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers One method for SPI configuration is described in detail in Application Note AN 812 Microcontroller Based Serial Port Interface SPI Boot Circuit The SPI port should not be active during periods when the full dynamic performance of the converter is required Because the SCLK signal the CSB signal and the SDIO signal are typically asynchronous to the ADC clock noise from these signals can degrade converter performance If the on board SPI bus is used for other devices it may be necessary to provide buffers between this bus and the AD6655 to prevent these signals from transi tioning at the converter inputs during critical sampling periods Some pins serve a dual function when the SPI interface is not being used When the pins are strapped to AVDD or ground during device power on they are associated with a specific function The Digital Outputs section describes the strappable functions supported on the AD6655 Rev A Page 48 of 88 CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers the SDIO DCS pin the SCLK DFS pin the SMI SDO OEB pin and the SMI SCLK PDWN pin serve as standalone CMOS compatible control pins When the device is powered up it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer output data format
120. t Mode Select Bits 100 Rev A Page 15 of 88 AD6655 CLK DECIMATED INTERLEAVED CMOS DATA DECIMATED INTERLEAVED FD DATA DECIMATED CLK DECIMATED CMOS IQ OUTPUT DATA tpp CHANNEL A DATA CHANNEL A FD BITS CHANNEL B DATA CHANNEL B FD BITS CHANNEL A DATA CHANNEL A FD BITS CHANNEL B DATA CHANNEL B FD BITS CHANNEL B DATA CHANNEL B FD BITS Figure 4 Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing toco CHANNEL A B CHANNEL A B CHANNEL A B CHANNEL CHANNEL A B DATA Q DATA DATA Q DATA DATA CHANNEL A B CHANNEL A B CHANNEL A B CHANNEL A B CHANNEL A B FD BITS FD BITS FD BITS FD BITS FD BITS 4 1 4 ty Figure 5 Decimated IQ Mode CMOS Data and Fast Detect Output Timing LVDS CHANNEL A CHANNEL A DATA DATA DATA CMOS FD CHANNEL A B DATA FD BITS DECIMATED DCOA DCOB LVDS FAST DET DCO DCO Figure 6 Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing CLK gt SYNC Figure 7 SYNC Timing Inputs 06709 016 Rev A Page 16 of 88 06709 015 06709 013 06709 014 AD6655 CLK NURSES FN cok Sg O Ne 7022243 SMI SCLK
121. tent itu uite 64 REVISION HISTORY 9 09 Rev 0 to Rev A Added Exposed Pad Notation to Figure 9 and Table 12 19 Added Exposed Pad Notation to Figure 10 and Table 13 21 Updated Outline Dimensions eerte 84 Changes to Ordering Guide 11 07 Revision 0 Initial Version AD6655 Evaluation Board Layouts see Bill of Materials Outline Dimensiot Siorino a a ALN Ordering Guide Rev A Page 3 of 8 AD6655 GENERAL DESCRIPTION The AD6655 is a mixed signal intermediate frequency IF receiver consisting of dual 14 bit 80 MSPS 105 MSPS 125 MSPS 150 MSPS ADCs and a wideband digital downconverter DDC AD6655 is designed to support communications applications where low cost small size and versatility are desired The dual ADC core features a multistage differential pipelined architecture with integrated output error correction logic Each ADC features wide bandwidth differential sample and hold analog input amplifiers supporting a variety of user selectable input ranges An integrated voltage reference eases design consid erations A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle allowing the converters to maintain excellent performance ADC data outputs are internally connected directly to the digital downconverter DDC of the receiver simplifying layout and reducing interconnection parasitics The digit
122. the following components need to be added removed and or changed for Channel A For Channel B the corresponding components should be changed Rev A Page 63 of 88 1 Remove C17 C18 and C117 in the default analog input path Populate C8 and C9 with 0 1 uF capacitors in the analog input path To drive the AD8352 in the differential input mode populate the T10 transformer the R1 R37 R39 R126 and R127 resistors and the C10 C11 and C125 capacitors Populate the optional amplifier output path with the desired components including an optional low pass filter Install 0 resistors R44 and R48 R43 and R47 should be increased typically to 100 Q to increase to 200 Q the output impedance seen by the AD8352 AD6655 SCHEMATICS ce 010 WHO Wu 10K OHM AMPVID OPTIONAL AMPLIFIER INPUT PATH AMPA C12 1 10 9 0 00U 8 2 AMPVID 2 ane e lt moer gt WA e z 6294 Su TT oc a al o mi 8 gt 2 g 22 5 525 lt 213 8 gt og d lt gt 8 2 8 2 3 E AMPA HSMS2812 R26 C17 WHO g E Re VINA Transformer amp channel A HSMS2812 27 ANN
123. tion Table 19 lists the coefficients of the half band filter The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are also listed Coefficients not listed in Table 19 are 0s Table 19 Fixed Coefficients for Half Band Filter Coefficient Normalized Decimal Coefficient Number Coefficient 20 Bit 0 C18 0 0008049 844 C2 C16 0 0059023 6189 C4 C14 0 0239182 25080 C6 C12 0 0755024 79170 C8 C10 0 3066864 321584 C9 0 5 524287 HALF BAND FILTER FEATURES In the AD6655 the half band filter cannot be disabled The filter can be set for a low pass or high pass response For a high pass filter Bit 1 of Register 0x103 should be set for a low pass response this bit should be cleared The low pass response of the filter with respect to the normalized output rate is shown in Figure 72 and the high pass response is shown in Figure 73 AMPLITUDE dBc 0 0 1 0 2 0 3 0 4 FRACTION OF INPUT SAMPLE RATE 06709 070 Figure 72 Half Band Filter Low Pass Response AMPLITUDE dBc 0 0 1 0 2 0 3 0 4 FRACTION OF INPUT SAMPLE RATE 06709 071 Figure 73 Half Band Filter High Pass Response The half band filter has a ripple of 0 000182 dB and a rejection of 100 dB For an alias rejection of 100 dB the alias protected bandwidth is 11 of the input sample rate If both the I and the Q paths are
124. tion normally defined as overflow In either mode the magnitude of the data is considered in the calculation of the condition but the sign of the data is not considered The threshold detection responds identically to positive and negative signals outside the desired range magnitude FAST DETECT OVERVIEW The AD6655 contains circuitry to facilitate fast overrange detection allowing very flexible external gain control imple mentations Each ADC has four fast detect FD output pins that are used to output information about the current state of the ADC input level The function of these pins is programmable via the fast detect mode select bits and the fast detect enable bit in Register 0x104 allowing range information to be output from several points in the internal data path These output pins can also be set up to indicate the presence of overrange or underrange conditions according to programmable threshold levels Table 21 shows the six configurations available for the fast detect pins AD6655 Table 21 Fast Detect Mode Select Bits Settings Fast Detect Information Presented on Mode Select bits Fast Detect FD Pins of Each ADC Register 0x104 3 1 FDI3 FDI2 FD 1 01 000 ADC fast magnitude see Table 22 001 ADC fast magnitude OR see Table 23 010 ADC fast OR F LT magnitude see Table 24 011 ADC fast C UT F IT magnitude see Table 24 100 OR C UT F UT 101 F_UT IG DG
125. to distortion At input frequencies in the second Nyquist zone and above the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD6655 For applications where SNR is a key parameter differential double balun coupling is the recommended input configuration see Figure 49 An alternative to using a transformer coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver is shown in Figure 50 See the AD8352 data sheet for more information In addition if the application requires an amplifier with variable gain the AD8375 or AD8376 digital variable gain amplifiers DVGAs provide good performance driving the AD6655 In any configuration the value of the shunt capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed Table 14 displays recom mended values to set the RC network However these values are dependent on the input signal and should be used only as a starting guide Table 14 Example RC Network Frequency Range R Series C Differential MHz Q Each pF Oto 70 33 15 70 to 200 33 5 200 to 300 15 5 gt 300 15 Open 10 0 147 06709 051 AD6655 0 1pF 06709 052 Y Figure 50 Differential Input Configuration Using the AD8352 Rev A Page 30 of 88 Single Ended Input Configuration A single ended input can provide adequate performance in
126. ure 55 shows the typical drift characteristics of the internal reference in both 1 0 V and 0 5 V modes 2 5 2 0 1 5 1 0 REFERENCE VOLTAGE ERROR mV 40 20 0 20 40 60 80 TEMPERATURE C Figure 55 Typical VREF Drift When the SENSE pin is tied to AVDD the internal reference is disabled allowing the use of an external reference An internal reference buffer loads the external reference with an equivalent 6 load see Figure 18 The internal buffer generates the positive and negative full scale references for the ADC core Therefore the external reference must be limited to a maximum of 1 0 V CLOCK INPUT CONSIDERATIONS For optimum performance the AD6655 sample clock inputs CLK and CLK should be clocked with a differential signal The signal is typically ac coupled into the CLK and CLK pins via a transformer or capacitors These pins are biased internally see Figure 56 and require no external bias 06709 057 AVDD 06709 058 Figure 56 Equivalent Clock Input Circuit Clock Input Options The AD6655 has a very flexible clock input structure Clock input can be a CMOS LVDS LVPECL or sine wave signal Regardless of the type of signal being used clock source jitter is of the most concern as described in the Jitter Considerations section Figure 57 and Figure 58 show two preferred methods for clocking the AD6655 at clock rates to up to 625 MHz A low jitte
127. ut example For detailed information about packaging and PCB layout of chip scale packages refer to Application Note AN 772 A Design and Manufacturing Guide for the Lead Frame Chip Scale Package LFCSP see www analog com CML The CML pin should be decoupled to ground with a 0 1 uF capacitor as shown in Figure 48 RBIAS The AD6655 requires that a 10 resistor be placed between the RBIAS pin and ground This resistor sets the master current reference of the ADC core and should have at least a 1 tolerance Reference Decoupling The VREF pin should be externally decoupled to ground with a low ESR 1 0 uF capacitor in parallel with a low ESR 0 1 uF ceramic capacitor SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required Because the SCLK CSB and SDIO signals are typically asynchronous to the ADC clock noise from these signals can degrade converter performance If the on board SPI bus is used for other devices it may be necessary to provide buffers between this bus and the AD6655 to keep these signals from transitioning at the converter inputs during critical sampling periods Rev A Page 60 of 88 EVALUATION BOARD The AD6655 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configura tions The converter can be driven differentially through a double balun configuration default or optional
128. ved Bit 2 NCO22 Phase Dither Enable When Bit 2 is set phase dither in the NCO is enabled When Bit 2 is cleared phase dither is disabled Bit 1 NCO32 Amplitude Dither Enable When Bit 1 is set amplitude dither in the NCO is enabled When Bit 1 is cleared amplitude dither is disabled Rev A Page 57 of 88 AD6655 Bit O NCO32 Enable When Bit 0 is set this bit enables the 32 bit NCO operating at the frequency programmed into the NCO frequency register When Bit 0 is cleared the NCO is bypassed and shuts down for power savings NCO Frequency Register 0x11E to Register 0x121 Register 0x11E Bits 7 0 NCO Frequency Value 7 0 Register 0x11F Bits 7 0 NCO Frequency Value 15 8 Register 0x120 Bits 7 0 NCO Frequency Value 23 16 Register 0x121 Bits 7 0 NCO Frequency Value 31 24 This 32 bit value is used to program the NCO tuning frequency The frequency value to be programmed is given by the following equation FREQ 23 x 9 CLK where FREQ is a 32 bit twos complement number representing the NCO frequency register fis the desired carrier frequency in hertz Hz faxis the AD6655 ADC clock rate in hertz Hz NCO Phase Offset Register 0x122 and Register 0x123 Register 0x122 Bits 7 0 NCO Phase Value 7 0 Register 0x123 Bits 7 0 NCO Phase Value 15 8 The 16 bit value programmed into the NCO phase value register is loaded into the NCO block each time the NCO is sta
129. y functions During an instruction phase a 16 bit instruction is transmitted Data follows the instruction phase and its length is determined by the WO bit and the W1 bit All data is composed of 8 bit words The first bit of each individual byte of serial data indicates whether a read command or a write command is issued This allows the serial data input output SDIO pin to change direction from an input to an output In addition to word length the instruction phase determines whether the serial frame is a read or write operation allowing the serial port to be used both to program the chip and to read the contents of the on chip memory If the instruction is a readback operation performing a readback causes the serial data input output SDIO pin to change direction from an input to an output at the appropriate point in the serial frame Data can be sent in MSB first mode or in LSB first mode MSB first is the default on power up and can be changed via the SPI port configuration register For more information about this and other features see Application Note AN 877 Interfacing to High Speed ADCs via SPI at www analog com HARDWARE INTERFACE The pins described in Table 26 comprise the physical interface between the user programming device and the serial port of the AD6655 The SCLK pin and the CSB pin function as inputs when using the SPI interface The SDIO pin is bidirectional functioning as an input during write phases and a
130. z Figure 19 AD6655 150 Single Tone FFT with fiw 2 4 MHz fuco 18 75 MHz 150MSPS 30 3MHz 1dBFS SNR 74 8dBc 75 8dBFS SFDR 100dBc fuco 24MHz AMPLITUDE dBFS 0 5 10 15 20 25 30 35 FREQUENCY MHz Figure 20 AD6655 150 Single Tone FFT with 30 3 MHz fuco 24 MHz 150MSPS 140 1MHz 1dBFS SNR 74 3dBc 75 3dBFS SFDR 83 3dBc fuco 56MHz THIRD HARMONIC 1 AMPLITUDE dBFS FREQUENCY MHz Figure 21 AD6655 150 Single Tone FFT with fw 70 1 MHz fuco 56 MHz 06709 018 06709 019 06709 020 AMPLITUDE dBFS AMPLITUDE dBFS AMPLITUDE dBFS Rev A Page 24 of 88 150MSPS 140 1MHz 14 5 SNR 73 7dBc 74 7dBFS SFDR 82 8dBc fuco 126MHz THIRD HARMONIC SECOND HARMONIC FREQUENCY MHz fuco 126 MHz 150MSPS 220 1MHz 9 1dBFS SNR 71 8dBc 72 8dBFS Figure 22 AD6655 150 Single Tone FFT with 140 1 MHz SFDR 81 4dBc fuco 205MHz THIRD HARMONIC 5 10 15 20 25 FREQUENCY MHz fuco 205 MHz 150MSPS 332 1MHz 1dBFS SNR 71 7dBc 72 7dBFS SFDR 95 0dBc fuco 321 5MHz 30 35 Figure 23 AD6655 150 Single Tone FFT with fiw 220 1 MHz FREQUENCY MHz fuco 321 5 MHz Figure 24 AD6655 150 Single Tone FFT with 332 1 MHz 06709 021 06709 022 06709 023 AD6655 125MSPS 70 3MHz 1dBFS SNR 74 6dBc
131. z fuco 231 MHz Rev A Page 25 of 88 AD6655 95 90 SFDR dBFS SFDR 85 C a 85 SFDR 25 5 g y lt 5 80 SFDR 40 o a 5 75 a 2 5 7o SNR 185 z 485 5 gt ENCE LINE SNR 40 4 65 SNR dBc 60 8 90 80 70 60 50 40 30 20 10 0 8 0 50 100 150 200 250 300 350 400 450 9 INPUT AMPLITUDE dBFS 5 INPUT FREQUENCY MHz 5 Figure 31 AD6655 150 Single Tone SNR SFDR vs Input Amplitude with Figure 34 AD6655 125 Single Tone SNR SFDR vs Input Frequency and fin 2 4 MHz fuco 18 75 MHz Temperature with DRVDD 3 3 V 120 SFDR dBFS 100 SNR dBFS 25 80 5 2 a u 2 amp p 9 60 g E SFDR dBc ui 2 u G 40 lt 85dB o 5 REFERENCE LINE 20 SNR dBc 0 i 90 80 70 0 50 40 30 20 10 0 8 40 20 0 20 40 60 80 8 INPUT AMPLITUDE dBFS 5 TEMPERATURE C 5 Figure 32 AD6655 150 Single Tone SNR SFDR vs Input Amplitude with Figure 35 AD6655 150 Gain and Offset vs Temperature fin 98 12 MHz fuco 100 49 MHz SFDR 85 C 2 SFDR dBc a m P 5 8 2 IMD3 dBc tt o 5 5 2 n SFDR dBFS 103 dBFS INPUT FREQUENCY MHz 8 INPUT AMPLITUDE dBFS 5 Figure 3

ANALOG DEVICES AD6655 English products handbook Rev A

Contents

Download Pdf Manuals

Related Search

Related Contents