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ANALOG DEVICES AD9239 English products handbook Rev B

1. Default Default Addr Register MSB LSB Value Notes Hex Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Comments OF adc_input Analog VCM 0x00 local disconnect enable enable 1 1 0 off 0 off default default 10 offset 6 bit Device Offset Adjustment 5 0 0x00 Device local 011111 31LSB offset 011110 30 LSB trim 011101 29 LSB 000010 2 LSB 000001 1 LSB 000000 0 LSB 111111 1LSB 111110 2LSB 111101 3 LSB 100001 31 LSB 100000 32 LSB 14 output_mode Output Output Data format select 0x00 Configures local global enable bar invert global the outputs local global 00 offset binary and the 1 off enable default format of 1 01 twos the data default 0 off complement default 10 gray code 15 output_adjust Output Drive 0x00 VCM output global Current 1 0 adjustments 00 400 mV default 01 500 mV 10 440 mV 11 320 mV 18 vref Ref_Vfs 4 0 0x00 Select global Reference full scale adjust adjustments 10000 0 98 V p p for Veer 10001 1 00 V p p 10010 1 02 V p p 10011 1 04 V p p 11111 1 23 V p p 00000 1 25 V p p default 00001 1 27 V p p 01110 1 48V p p 01111 1 5 V p p 19 user B7 B6 B5 B4 B3 B2 B1 BO OxA5 User defined patt1_Isb pattern local 1 LSB 1A user_ B15 B14 B13 B12 B11 B10 9 B8 0x66 User defined patt1 msb pattern local 1 MSB 1B user B7 B6 B5 B4 B3 B2 B1 BO 0x53 User defined
2. lt 3 gt Jg R 1 S 8 5 wo lt 2 gt lt 0 gt lt 8 gt N lt 4 gt lt 1 gt p3 h74h6 h54h44d1 lt 11 gt 4d1 lt 10 gt 4d1 lt 9 gt 4d1 lt 8 gt 4d1 lt 3 gt 4d1 lt 2 gt 4d1 lt 1 gt 4d1 lt 0 gt d2 lt 7 gt 4d2 lt 6 gt 4d2 lt 5 gt 4d2 lt 4 gt d2 lt 0 gt d3 lt 11 gt d3 lt 10 gt d3 lt 9 gt 4d3 lt 4 gt 4d3 lt 3 gt d3 lt 2 gt d3 lt 1 gt 4d4 lt 9 gt 4d4 lt 8 gt d4 lt 7 gt d4 lt 6 gt 4d4 lt 2 gt 4d4 lt 1 gt d4 lt 0 gt Figure 72 p3 Bit for 64 Bit Packet 12 Bit Case lt 4 gt 5 A S s h7 A 9 lt 11 gt a g A 1 lt 10 gt g A wo lt 11 gt N N lt 10 gt D2 lt 9 gt D3 lt 6 gt D4 lt 3 gt D2 lt 8 gt D3 lt 5 gt Figure 73 p4 Bit for 64 Bit Packet 12 Bit Case lt 9 gt h3 lt 8 gt h2 lt 7 gt D3 lt 6 gt D3 lt 5 gt g 5 03 lt 4 gt g A 10 3 lt 2 gt lt 8 gt lt 1 gt 5 lt 7 gt lt 0 gt g A 6 11 g A 6 lt 2 gt g A 5 10
3. 70 65 60 SNR SNR SFDR dB 55 50 45 40 1 0 1 1 1 2 1 3 1 4 ANALOG INPUT COMMON MODE VOLTAGE V Figure 33 SNR SFDR vs Analog Input Common Mode Voltage fiy 84 3 MHz 250 MSPS 1 5 1 6 1 7 1 8 06980 108 06980 109 06980 087 AD9239 3dB CUTOFF 2 780MHz AMPLITUDE dBFS 2 10 1 10 100 16 106 AIN FREQUENCY Hz Figure 34 Full Power Bandwidth Amplitude vs AIN Frequency 250 MSPS 06980 088 Rev B Page 16 of 40 09239 EQUIVALENT CIRCUITS AVDD AVDD AVDD 2500 SDI SDIO 30kO 06980 005 06980 009 Figure 39 Equivalent SDI SDIO Input Circuit AVDD AVDD 1 4V TEMPOUT Figure 36 Analog Inputs Figure 40 Equivalent TEMPOUT Output Circuit 1000 1750 1750 SCLK RBIAS WN RESET Figure 37 Equivalent SCLK PDWN PGMx RESET Input Circuit Figure 41 Equivalent RBIAS Input Output Circuit AVDD 1750 26kQ 1kQ CSB Figure 38 Equivalent CSB Input Circuit Figure 42 Equivalent VCMx Output Circuit Rev B Page 17 of 40 AD9239 AVDD SDO DRVDD 4mA RrERM 4mA AVDD DOUT x p DOUT x 3450 4mA 4mA Figure 43 Equivalent Digital Output Circuit Figure 44 Equivalent SDO Output Circuit Rev B Page 18 of 40 THEORY OF OPERATION The AD9239 architecture consists of a different
4. lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt m p7 p6 p5 p4 p3 p2 pt Figure 68 64 Bit Packet 12 Bit Case D1 D1 D1 D1 D1 D1 D1 h3 h2 h1 5 A o a A lt 11 gt lt 10 gt lt 9 gt lt 8 gt lt 7 gt lt 6 gt 5 N N N D2 lt 11 gt lt 10 gt lt 9 gt lt g A g A g A o N lt 7 gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt 6 D2 D3 D3 D3 D3 D3 D3 D3 03 D3 D3 D4 D4 lt 0 gt lt 11 gt lt 10 gt lt 9 gt lt 8 gt lt 7 gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt lt 11 gt lt 10 gt 04 04 04 04 04 04 04 04 04 D4 8 PS lt g gt lt 8 gt lt gt lt 6 gt lt 5 gt lt a gt lt 3 gt lt 2 gt lt 1 gt lt o gt P 0 P2 pt 8 Figure 69 64 Bit Packet Hamming Template for 12 Bit Case D1 01 01 01 hZ h5 h3 hi lt 11 gt lt 9 gt lt 7 gt lt 5 gt D1 D1 D2 D2 D2 D2 D2 D2 lt 3 gt lt 1 gt lt 11 gt lt 9 gt lt 7 gt lt 5 gt lt 3 gt lt 1 gt D2 D3 D3 D3 D3 D3 D3 D4 lt 0 gt lt 10 gt lt 8 gt lt 6 gt lt 4 gt lt 2 gt lt 0 gt lt 10 gt D4
5. Figure 9 Single Tone 32k FFT with fin 84 3 MHz fsampte 250 MSPS AD9239 AIN 1 0dBFS SNR 63 90dB 20 ENOB 10 32 BITS SFDR 73 10dBc SFDR dBFS AMPLITUDE dBFS 5 e e 100 le ot E 120 0 20 40 60 80 100 120 50 70 90 110 130 150 170 190 210 230 250 FREQUENCY MHz 8 ENCODE MSPS 8 Figure 10 Single Tone 32k FFT with fin 171 3 MHz 250 MSPS Figure 13 SFDR vs Encode fin 84 3 MHz 1 1 0dBFS SNR 63 41dB ENOB 10 24 BITS SFDR 77 49dBc DR dB SNR dBFS SNR SFDR dB 0 20 40 60 80 100 120 90 80 70 60 50 40 30 2 10 08 FREQUENCY MHz 8 ANALOG INPUT LEVEL dBFS 2 Figure 11 Single Tone 32k FFT with f n 240 3 MHz fsaueie 250 MSPS Figure 14 SNR SFDR vs Analog Input Level 84 3 MHz 170 MSPS 100 SFDR dBFS 80 70 SNR dBFS a 60 a a 50 SFDR dB 2 E 40 7 30 SNR dB 20 10 5 0 g 50 70 90 110 130 150 170 190 210 230 2502 90 80 70 60 50 40 30 20 10 05 ENCODE MSPS 8 ANALOG INPUT LEVEL dBFS Figure 12 SNR vs Encode fiw 84 3 MHz Figure 15 SNR SFDR vs Analog Input Level f 84 3 MHz fsavece 210 MSPS Rev Page 12 of 40
6. 400 250 4 NEM lt 200 a ce gt 1 E 0 150 W 5 gt 200 100 w 50 nee EYE ALL BITS OFFSET 0 015 600 ULS 5000 40044 TOTAL 8000 40044 200 100 0 100 200 50 0 50 TIME ps TIME ps ULS 0 5 06980 095 Figure 64 Digital Outputs Data Eye with Trace Lengths Greater than 12 Inches on Standard FR 4 External 100 Terminations at Receiver An example of the digital output default data eye and a time To change the output data format to twos complement or gray interval error TIE jitter histogram with trace lengths less than code see the Memory Map section 6 inches on standard FR 4 material is shown in Figure 63 Table 9 Digital Output Coding Figure 64 shows an example of trace lengths exceeding 12 inches on standard FR 4 material Notice that the TIE jitter histogram Code jiu Span i p p V cea bert Offset Binary reflects the decrease of the data eye opening as the edge deviates gues 111111111 from the ideal position It is the user s responsibility to determine 2048 1000 0000 0000 if the waveforms meet the timing budget of the design when the 2047 0 000305 0111 1111 1111 trace lengths exceed 6 inches 0 0 625 0000 0000 0000 Additional SPI options allow the user to further increase the output driver voltage swing of all four outputs in
7. Rev B Page 27 of 40 09239 Calculating the Parity Bits for the Hamming Code The Hamming bits are defined as follows The definition is shown in the charts for a 12 bit example The Hamming parity bits are shown interleaved in the data This makes it easier to see the numeric relationship The decoding on the receive side is just the inversion A separate document will show the proper way to correct an error in the transmission The p8 bit MSB of the parity bits will always be 0 The p7 bit is a parity bit for the entire packet after the other parity bits are calculated 5 5 g A g A 5 D1 D1 h2 ht ho lt 11 gt lt 10 gt lt 9 gt lt 8 gt lt 7 gt lt 6 gt lt 5 gt lt 4 gt h7 h6 h5 h4 h3 N N N N N 01 01 02 02 02 02 lt 3 gt lt 2 gt lt 1 gt lt 0 gt lt 11 gt lt 10 gt lt 9 gt lt 8 gt lt 7 gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt o D3 D D3 03 D3 D3 D3 D3 D3 D3 lt 11 gt lt 10 gt lt 9 gt lt 8 gt lt 7 gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt lt 11 gt lt 10 gt lt 9 gt lt 8 gt 04 04 04 04 04 04 DA 04 5 lt 7 gt lt 6 gt lt 5 gt
8. The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 1 or 8 388 607 bits A description of the PN sequence and how it is generated can be found in Section 5 6 of the ITU T 0 150 05 96 standard The only differences are that the starting value must be a specific value instead of all 1s see Table 11 for the initial values and the AD9239 inverts the bit stream with relation to the ITU standard Table 11 PN Sequence Initial First Three Output Samples Sequence Value MSB First PN Sequence Short 0x0df 0xdf9 0x353 0x301 PN Sequence Long 0x29b80a 0x591 0xfd7 0x0a3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI 14 bit word lengths in order to verify data capture to the receiver Digital Output Scrambler and Error Code Correction The data from the AD9239 is sent serially in packets of 64 bits These numbers are derived from the necessity to have the output data streaming at 16x the encode clock The data packets consist of a header data and error correction code that is 8 Bits of Header 48 Bits of Data 4 Conv 8 Bits of ECC 64 Bits The 12 bit protocol is shown in Figure 2 and Table 5 Error Correction Code The error correction code ECC is a Hamming code due to the ease of implementation Seven bits are used for the ECC to correct one error or detect one or two errors during tr
9. 0111 One zero word toggle 1111 1111 1111 0000 0000 0000 No 1 All test mode options except PN sequence short and PN sequence long can support 8 to Register 14 allows the user to invert the digital outputs from their nominal state This is not to be confused with inverting the serial stream to an LSB first mode In default mode as shown in Figure 2 the MSB is first in the data output serial stream However this can be inverted so that the LSB is first in the data output serial stream There are eight digital output test pattern options available that can be initiated through the SPI This feature is useful when validating receiver capture and timing Refer to Table 10 for the output bit sequencing options available Some test patterns have two serial sequential words and can be alternated in various ways depending on the test pattern chosen It should be noted that some patterns do not adhere to the data format select option In addition custom user defined test patterns can be assigned in the 0x19 0x1A Ox1B 0x1C Ox1D Ox1E 0 1 and 0x20 register addresses The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 1 or 511 bits A description of the PN sequence and how it is generated can be found in Section 5 1 of the ITU T 0 150 05 96 standard The only difference is that the starting value must be a specific value instead of all 1s see Table 11 for the initial values
10. All PGMx pins are automatically initialized as sync pins by default These pins can be used to lock the FPGA timing and data capture during initial startup These pins are respective to each channel PGM3 Channel A 3 Each sync pin is held low until its respective PGMx pin receives a high signal input from the receiver during which time the ADC outputs a training pattern 4 training pattern defaults to the values implemented by the user in Register 19 through Register 20 5 When the receiver finds the frame boundary the sync identification is deasserted high via the sync pin or via a SPI write The ADC outputs the valid data on the next packet boundary The time necessary for sync establishment is highly dependent on the receiver logic processing Refer to the Switching Specifications section the switching timing is directly related to the ADC channel 6 Once steady state operation for the device has occurred these pins can each be assigned to be a standby option by using Register 53 see Table 15 All other pins act as universal sync pins To minimize skew and time misalignment between each channel of the digital outputs the following actions should be taken to ensure that each channel data packet is within 1 clock cycle of its specified switching time For some receiver logic this is not required 1 Full power down through external PDWN pin 2 Chip reset via external RESET pin 3 Power back up by releasing externa
11. D4 D4 D4 D4 D4 0 1 lt 9 gt lt 7 gt lt 5 gt lt 3 gt lt 2 gt lt 0 gt p1 h7 h5 h3 h1 d1 lt 11 gt d1 lt 9 gt d1 lt 7 gt d1 lt 5 gt d1 lt 3 gt d1 lt 1 gt d2 lt 11 gt d2 lt 9 gt d2 lt 7 gt d2 lt 5 gt d2 lt 3 gt d2 lt 1 gt d2 lt 0 gt d3 102 d3 8 d3 6 2 d3 42 d3 2 d3 0 d4 10 2 d4 9 d4 72 d4 5 d4 3 2 d4 22 d4 02 0 Figure 70 p1 Bit for 64 Bit Packet 12 Bit Case D4 8 h3 D2 11 D3 8 D4 5 h2 D2 10 D3 lt 7 gt D4 lt 4 gt D1 D1 lt 7 gt lt 6 gt D2 D2 lt 3 gt lt 2 gt D3 D4 lt 0 gt lt 11 gt 0 2 p2 h7 h64h34h2 d1 lt 11 gt 4d1 lt 10 gt 4d1 lt 7 gt 4d1 lt 6 gt 4d1 lt 3 gt d1 lt 2 gt 4d2 lt 11 gt 4d2 lt 10 gt 4d2 lt 7 gt d2 lt 6 gt d2 lt 3 gt 4d2 lt 2 gt 4 d2 lt 0 gt 4d3 lt 11 gt 4d3 lt 8 gt 4d3 lt 7 gt d3 lt 4 gt 4d3 lt 3 gt 4d3 lt 0 gt 4d4 lt 11 gt 4d4 lt 9 gt d4 lt 8 gt 4d4 lt 5 gt 4d4 lt 4 gt d4 lt 2 gt d4 lt 1 gt 40 Figure 71 p2 Bit for 64 Bit Packet 12 Bit Case Rev B Page 28 of 40 06980 098 06980 099 h7 h6 D1 D1 lt 3 gt lt 2 gt D2 D3 lt 0 gt lt 11 gt D4 D4 lt 9 gt lt 8 gt g A 1 lt 10 gt D lt 7 gt g A lt 6 gt 5 lt 11 gt lt 7 gt lt 4 gt Jg R 2 g A 10 N lt 6 gt
12. Pin To set the internal core bias current of the ADC place a resistor nominally equal to 10 0 between ground and the RBIAS pin The resistor current is derived on chip and sets the AVDD current of the ADC to a nominal 725 mA at 250 MSPS Therefore it is imperative that a 1 or less tolerance on this resistor be used to achieve consistent performance VCMx Pins The common mode output pins can be enabled through the SPI to provide an external reference bias voltage of 1 4 V for driving the VIN x VIN x analog inputs These pins may be required when connecting external devices such as an amplifier or transformer to interface to the analog inputs RESET Pin The RESET pin sets all SPI registers to their default values and the datapath Using this pin requires the user to resync the digital outputs This pin is only 1 8 V tolerant PDWN Pin When asserted high the PDWN pin turns off all the ADC channels including the output drivers This function can be changed to a standby function See Register 8 in Table 15 Using this feature allows the user to put all channels into standby mode The output drivers transmit pseudorandom data until the outputs are disabled using Register 14 By asserting the PDWN pin high AD9239 is placed into power down mode shutting down the reference reference buffer PLL and biasing networks In this state the ADC typically dissipates 3 mW If any of the SPI features are changed before
13. Temperature fn 84 3 MHz 80 SFDR 210MSPS SFDR 250MSPS SFDR 170MSPS 40 20 0 20 40 60 TEMPERATURE C Figure 26 SFDR vs Temperature fiw 84 3 MHz 80 500 1000 1500 2000 2500 3000 3500 CODE Figure 27 INL fn 9 7 MHz 250 MSPS 4000 06980 080 06980 081 06980 082 NUMBER OF HITS NUMBER OF HITS DNL LSB 0 500 1000 1500 2000 2500 3000 3500 4000 CODE Figure 28 DNL 9 7 MHz 250 MSPS INPUT REFERRED NOISE 0 72 LSB N 3 2 N 1 N 1 N 2 N 3 MORE BIN Figure 29 Input Referred Noise Histogram fsampte 170 MSPS INPUT REFERRED NOISE 0 70 LSB N 3 N 2 N 1 N 1 N 2 N 3 MORE BIN Figure 30 Input Referred Noise Histogram 210 MSPS 06980 083 06980 106 06980 107 Rev 15 of 40 NUMBER OF HITS AMPLITUDE dBFS 09239 INPUT REFERRED NOISE 0 71 LSB N 3 2 N 1 N 1 N 2 N 3 MORE Figure 31 Input Referred Noise Histogram 250 MSPS NPR 52dB NOTCH 18 40 2 NOTCH WIDTH 1MHz 9MHz 100 120 FREQUENCY Hz Figure 32 Noise Power Ratio NPR fsampte 250 MSPS 90 85 SFDR 80 75 dBc
14. Understanding High Speed ADC Testing and Evaluation for definitions and details on how these tests were completed 2 AVDD DRVDD with link established 3 Overrange condition is specified as 6 dB above the full scale input range Rev B Page 3 of 40 AD9239 AC SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V Tun 40 C Tmax 85 C 1 25 V differential input AIN 1 0 dBFS DCS enabled unless otherwise noted Table 2 AD9239BCPZ 170 AD9239BCPZ 210 AD9239BCPZ 250 Parameter Temp Min Typ Max Min Typ Max Min Unit SIGNAL TO NOISE RATIO SNR fin 9 7 MHz 25 C 64 5 dB fin 84 3 MHz Full 63 5 64 5 63 2 64 2 63 1 64 1 dB fin 170 3 MHz 25 C 63 9 dB fin 240 3 MHz 25 C 64 1 63 2 63 3 dB SIGNAL TO NOISE RATIO SINAD fin 9 7 MHz 25 C 64 2 dB fin 84 3 MHz Full 63 3 64 4 62 8 63 9 628 63 8 dB fin 170 3 MHz 25 C 63 1 dB fin 240 3 MHz 25 C 63 9 63 63 1 dB EFFECTIVE NUMBER OF BITS ENOB fin 9 7 MHz 25 C 10 4 Bits fin 84 3 MHz Full 10 2 10 4 10 1 103 10 1 10 3 Bits 4 fin 170 3 MHz 25 C 10 2 Bits fin 240 3 MHz 25 C 10 3 10 2 10 2 Bits WORST HARMONIC SECOND fin 9 7 MHz 25 C 90 dBc fin 84 3 MHz Full 875 78 6 86 77 86 74 5 dBc fin 170 3 MHz 25 76 dBc fin 240 3 MHz 25 C 82 80 82 dBc WORST HARMONIC THIRD fin 9 7 MHz 25 C 78 dBc fin 84 3 MHz Full 79 74 76 72 6 76 72 5 dBc fin 170 3 MHz 25 74 dBc fin 240
15. data bytes which is determined by Bit Field WO and Bit Field W1 An example of the serial timing and its definitions can be found in Figure 78 and Table 14 During normal operation CSB is used to signal to the device that SPI commands are to be received and processed When CSB is brought low the device processes SCLK and SDI SDIO to execute instructions Normally CSB remains low until the communication cycle is complete However if connected to a slow device CSB can be brought high between bytes allowing older microcontrollers enough time to transfer data into shift registers CSB can be stalled when transferring one two or three bytes of data When W0 and W1 are set to 11 the device enters streaming mode and continues to process data either reading or writing until CSB is taken high to end the communication cycle This allows complete memory transfers without requiring 09239 additional instructions Regardless of the mode if CSB is taken high in the middle of a byte transfer the SPI state machine is reset and the device waits for a new instruction In addition to the operation modes the SPI port configuration influences how the AD9239 operates For applications that do not require a control port the CSB line can be tied and held high This places the SDI SDIO pin into its secondary mode as defined in the SDI SDIO Pin section CSB can also be tied low to enable 2 wire mode When CSB is tied low SCLK and SDI SDIO are the on
16. in Figure 58 to Figure 60 the power dissipated by the AD9239 is proportional to its clock rate The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the digital output drivers POWER W CURRENT mA 50 70 90 110 130 150 170 ENCODE MSPS Figure 58 Supply Current vs Encode for fiw 84 3 MHz 170 MSPS 06980 056 2 0 0 8 0 7 1 6 0 6 1 4 0 5 lt 1 2 10 POWER x 9 x 033 0 6 0 2 0 4 I m DRVDD 0 1 0 0 50 70 90 110 130 150 170 190 210 ENCODE MSPS Figure 59 Supply Current vs Encode for fiy 84 3 MHz 210 MSPS 06980 057 2 0 0 8 18 0 7 1 6 0 6 1 4 12 POWER 0 5 lt E 1 0 0 4 5 a 0 8 03 3 0 6 0 2 0 4 DRVDD 0 1 0 0 50 70 90 110 130 150 170 190 210 230 250 ENCODE MSPS Figure 60 Supply Current vs Encode for fiw 84 3 MHz fsamere 250 MSPS 06980 058 Rev B Page 22 of 40 Digital Start Up Sequence The output digital data from the AD9239 is coded and packetized which requires the device to have a certain start up sequence The following steps should be initialized by the user to capture coherent data at the receiving logic 1 Initialize a soft reset via Bit 5 of Register 0 see Table 15 2
17. is organized into bytes that can be further divided into fields as documented in the Memory Map section Detailed operational information can be found in the Analog Devices Inc AN 877 Application Note Interfacing to High Speed ADCs via SPI Four pins define the SPI SCLK SDI SDIO SDO and CSB see Table 13 The SCLK pin is used to synchronize the read and write data presented to the ADC The SDI SDIO pin is a dual purpose pin that allows data to be sent to and read from the internal ADC memory map registers The CSB pin is an active low control that enables or disables the read and write cycles Table 13 Serial Port Pins Pin Function SCLK Serial Clock The serial shift clock input SCLK is used to synchronize serial interface reads and writes SDI SDIO Serial Data Input Output A dual purpose pin that typically serves as an input or output depending on the SPI wire mode and instruction sent and the relative position in the timing frame SDO Serial Data Output is used only in 4 wire SPI mode When set the SDO pin becomes active When cleared the SDO pin remains in tristate and all read data is routed to the SDI SDIO pin CSB Chip Select Bar Active Low This control gates the read and write cycles The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence During an instruction phase a 16 bit instruction is transmitted followed by one more
18. low all information on the SDO and SDI SDIO pins are written to the device This feature allows the user to reduce the number of traces to the device if necessary This pin is only 1 8 V tolerant PGMx Pins All PGMx pins are automatically initialized as a sync pin by default These pins are used to lock the FPGA timing and data capture during initial startup These pins are respective to each channel PGM3 Channel A The sync pin should be pulled low until this pin receives a high signal input from the receiver during which time the ADC outputs a training word The training word defaults to the values implemented by the user in Register 19 through Register 20 When the receiver finds the frame boundary the sync identification is deasserted high and the ADC outputs the valid data on the next packet boundary Once steady state operation for the device has occurred these pins can be assigned as a standby option using Register 53 in Table 15 All other pins change to a global sync pin This pin is only 1 8 V tolerant Rev B Page 30 of 40 SERIAL PORT INTERFACE SPI The AD9239 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC This may provide the user with additional flexibility and customization depending on the application Addresses are accessed via the serial port and can be written to or read from via the port Memory
19. of 40 09239 TIMING DIAGRAM N 1 SAMPLE N ANALOG INPUT SIGNAL SAMPLE RATE CLOCK SAMPLE 1t RATE CLOCK SERIAL CODED SAMPLES 40 N 39 N 38 N 37 OC 000C DATA PACKET 1 gt 64 BITS 8 BIT HEADER 48 BIT ADC 8 BIT ERROR CHANNEL ID DATA WORD CORRECTION 8 Figure 2 Timing Diagram Table 5 Packet Protocol Bits 64 57 Bits 56 45 Bits 44 33 Bits 32 21 Bits 20 9 Bits 8 1 Header Data 1 Data 2 Data 3 Data 4 ECC 8 bits MSB first 12 bits MSB first 12 bits MSB first 12 bits MSB first 12 bits MSB first 8 bits MSB first Rev B Page 7 of 40 09239 ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating Electrical AVDD to AGND 0 3 V to 2 0V DRVDD to DRGND 0 3 V to 2 0V AGND to DRGND 0 3 V to 0 3 V AVDD to DRVDD 2 0 V to 2 0V DOUT x to DRGND 0 3 V to DRVDD 0 3 V SDO SDI SDIO CLKz VIN x 0 3V to AVDD 0 3 V VCMx TEMPOUT RBIAS to AGND SCLK CSB PGMx RESET 0 3V to AVDD 0 3 V PDWN to AGND Environmental Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature 300 C Soldering 10 sec Junction Temperature 150 C THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package Soldering the exposed paddle to the customer board increases the reliability of the solder joint
20. registers For more information on this and other functions consult the AN 877 Application Note Interfacing to High Speed ADCs via SPI 09239 RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power up DEFAULT VALUES When the AD9239 comes out of a reset critical registers are preloaded with default values These values are indicated in Table 15 where an X refers to an undefined feature LOGIC LEVELS An explanation of various registers follows bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit Similarly clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit Rev B Page 33 of 40 AD9239 Table 15 Memory Map Register Default Default Addr Register MSB LSB Value Notes Hex Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Comments Chip Configuration Registers 00 chip_port_ SDO active LSB Soft 16 bit 0x18 config local not first reset address master required default ignored if mode for not used ADCs 01 chip_id 8 bit Chip ID Bits 2 0 Read global 0x0B AD9239 12 bit quad only 02 chip_grade Speed grade Re
21. 06980 055 the power down feature is enabled the chip continues to function after PDWN is pulled low without requiring a reset The AD9239 returns to normal operating mode when the PDWN pin is pulled low This pin is only 1 8 V tolerant SDO Pin The SDO pin is for use in applications that require a 4 wire SPI mode operation For normal operation it should be tied low to AGND through a 10 resistor Alternatively the device pin can be left open and the 345 internal pull down resistor pulls this pin low This pin adheres to only 1 8 V logic SDI SDIO Pin The SDI SDIO pin is for use in applications that require either a 4 or 3 wire SPI mode operation For normal operation it should be tied low to AGND through a 10 resistor Alternatively the device pin can be left open and the 30 internal pull down resistor pulls this pin low This pin is only 1 8 V tolerant SCLK Pin For normal operation the SCLK pin should be tied to AGND through 10 resistor Alternatively the device pin can be left open and the 30 internal pull down resistor pulls this pin low This pin is only 1 8 V tolerant CSB Pin For normal operation the CSB pin should be tied high to AVDD through 10 resistor Alternatively the device pin can be left open and the 26 kO internal pull up resistor pulls this pin high By tying the CSB pin to AVDD all SCLK and SDI SDIO information is ignored In comparison by tying the CSB pin
22. 09239 AIN1 AND AIN2 7 0dBFS SFDR 7 76 88dBc IMD2 78 75dBc IMD3 78 68dBc Ga CQ M SFDR dBFS A r SNR dBFS LZ SNR SFDR dB 0 20 40 60 80 100 FREQUENCY MHz 90 80 70 60 50 40 30 20 10 0 ANALOG INPUT LEVEL dBFS Figure 16 SNR SFDR vs Analog Input Level fv 84 3 MHz 250 MSPS Figure 19 Two Tone 32k FFT with fi 170 2 MHz and fiw 171 3 MHz fsampte 2 10 MSPS 06980 071 06980 074 AIN1 AND AIN2 7 0dBFS AIN1 AND AIN2 7 0dBFS SFDR 7 77 26dBc SFDR 74 48dBc 20 IMD2 86 55dBc 20 IMD2 76 10dBc IMD3 77 269 IMD3 74 48dBc AMPLITUDE dBFS AMPLITUDE dBFS 5 100 100 120 a 120 1 Ju FREQUENCY MHz 5 FREQUENCY MHz Figure 17 Two Tone 32k FFT with fiw 140 2 MHz and fix 141 3 MHz Figure 20 Two Tone 32k FFT with fiw 140 2 MHz and fiw 141 3 MHz fsampte 170 MSPS 250 MSPS 0 0 AIN1 AND AIN2 7 0dBFS AIN1 AND AIN2 7 0dBFS SFDR 75 44dBc SFDR 74 29dBc 20 IMD2 78 34dBc 20 IMD2 76 51dBc IMD3 75 44dBc IMD3 74 30dBc D 40 a 40 kJ kJ 60 B 60 P 5 5 a a lt 80 100 100 dalla mro maim 120 1
23. 20 i e 0 20 40 60 80 100 5 0 20 40 60 80 100 120 5 FREQUENCY MHz 8 FREQUENCY MHz Figure 18 Two Tone 32k FFT with 140 2 MHz and fi 141 3 MHz Figure 21 Two Tone 32k FFT with 170 2 MHz and fi 171 3 MHz 210 MSPS 250 MSPS Rev B Page 13 of 40 AD9239 95 90 85 80 75 70 65 AMPLITUDE dBFS 60 55 50 45 AMPLITUDE dBFS x 95 90 85 80 75 70 65 AMPLITUDE dBFS 60 55 50 45 SFDR dB SNR dB 0 50 100 150 200 250 300 AIN FREQUENCY MHz Figure 22 SNR SFDR Amplitude vs AIN Frequency 170 MSPS 350 400 450 500 SFDR dB SNR dB 50 100 150 200 250 300 AIN FREQUENCY MHz Figure 23 SNR SFDR Amplitude vs AIN Frequency 210 MSPS 350 400 450 500 SFDR dB SNR dB 50 100 150 200 250 300 350 400 450 500 AIN FREQUENCY MHz Figure 24 SNR SFDR Amplitude AIN Frequency 250 MSPS 6980 077 6980 078 06980 079 Rev B Page 14 of 40 SNR dB SFDR dB INL LSB SNR 170MSPS SNR 210MSP 20 0 20 40 60 TEMPERATURE C Figure 25 SNR vs
24. 3 MHz 25 C 84 77 80 dBc WORST OTHER EXCLUDING SECOND OR THIRD fin 9 7 MHz 25 C 85 dBc fin 84 3 MHz Full 96 86 90 83 7 94 83 6 dBc fin 170 3 MHz 25 C 85 dBc fin 240 3 MHz 25 C 88 88 85 dBc TWO TONE INTERMOD DISTORTION IMD 140 2 MHz fio 141 3 MHz 25 C 78 77 76 dBc AIN1 and AIN2 7 0 dBFS 170 2 MHz fio 171 3 MHz 25 C 77 76 dBc AIN1 AIN2 7 0 dBFS 1 the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for definitions and details on how these tests were completed 2 Tested at 210 MSPS and 250 MSPS only Rev B Page 4 of 40 DIGITAL SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V 40 C Tmax 85 C 1 25 V differential input AIN 1 0 dBFS DCS enabled unless otherwise noted 09239 Table 3 AD9239BCPZ 170 AD9239BCPZ 210 AD9239BCPZ 250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS CLK CLK Logic Compliance Full LVPECL LVDS CMOS LVPECL LVDS CMOS LVPECL LVDS CMOS Differential Input Voltage Full 0 2 6 0 2 6 0 2 6 Vp p Input Voltage Range Full AVDD AVDD AVDD AVDD AVDD AVDD V 0 3 1 6 0 3 1 6 0 3 1 6 Internal Common Mode Bias Full 1 2 1 2 1 2 V Input Common Mode Voltage Full 1 1 AVDD 1 1 AVDD 1 1 AVDD V High Level Input Voltage Vir Full 1 2 3 6 1 2 3 6 1 2 3 6 V Low Level Input Voltage Vi Full 0 0 8 0 0 8 0 0 8 V High Level Input Current l
25. ANALOG Quad 12 Bit 170 MSPS 210 MSPS 250 MSPS DEVICES Serial Output 1 8 V ADC AD9239 FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND O O O FEATURES 4 ADCs 1 package Coded serial digital outputs with ECC per channel On chip temperature sensor 95 dB channel to channel crosstalk SNR 65 dBFS with 85 MHz at 250 MSPS SFDR 77 dBc with AIN 85 MHz at 250 MSPS Excellent linearity DNL 0 3 LSB typical INL 0 7 LSB typical 780 MHz full power analog bandwidth Power dissipation 380 mW per channel at 250 MSPS 1 25 V p p input voltage range adjustable up to 1 5 V p p 1 8 V supply operation Clock duty cycle stabilizer Serial port interface features Power down modes Digital test pattern enable Programmable header Programmable pin functions PGMx PDWN APPLICATIONS Communication receivers Cable head end equipment M CMTS Broadband radios Wireless infrastructure transceivers Radar military aerospace subsystems Test equipment GENERAL DESCRIPTION The AD9239 is a quad 12 bit 250 MSPS analog to digital converter ADC with an on chip temperature sensor and a high speed serial interface It is designed to support digitizing high frequency wide dynamic range signals with an input bandwidth up to 780 MHz The output data are serialized and presented in packet format consisting of channel specific information coded samples and error correction code The ADC requires a single 1 8 V power supp
26. It is specified over the industrial temperature range of 40 C to 85 PRODUCT HIGHLIGHTS 1 Four ADCs are contained a small space saving package 2 on chip PLL allows users to provide a single ADC sampling clock and the PLL distributes and multiplies up to produce the corresponding data rate clock 3 Coded data rate supports up to 4 0 Gbps per channel Coding includes scrambling to ensure proper dc common mode embedded clock and error correction 4 The AD9239 operates from a single 1 8 V power supply 5 Flexible synchronization schemes and programmable mode pins 6 On chip temperature sensor One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 2010 Analog Devices Inc All rights reserved AD9239 TABLE OF CONTENTS Features oos uer 1 Applications ueste ventis i tene 1 Functional Block Diagram a 1 General Description oett o e RE A IDEE 1 Product Highlights sentent 1 ReviSIOnirlist Py2u Sasa sss 2 Specifications 3 AG SDecifIcatIons ee inet itte 4 Digital Specifications hasa uya 5 Switching Specifications u 6 Timing Diagram aasawa nennen 7 Absolute Maximum Ratings 8 Thermal Resistan e idee nene tree tel aqa 8 ESD GCaution
27. NR and SINAD performance degrades if the analog input is driven with a single ended signal For best dynamic performance the source impedances driving VIN x and VIN x should be matched such that common mode settling errors are symmetrical These errors are reduced by the common mode rejection of the ADC A small resistor in 3 3V SIGNAL GENERATOR SIGNAL GENERATOR 09239 series with each input can help reduce the peak transient current injected from the output stage of the driving source In addition low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC Such use of low Q inductors or ferrite beads is required when driving the converter front end at high intermediate frequency IF Either a shunt capacitor or two single ended capac itors can be placed on the inputs to provide a matching passive network This ultimately creates a low pass filter at the input to limit unwanted broadband noise See the AN 827 Application Note and the Analog Dialogue article Transformer Coupled Front End for Wideband A D Converters Volume 39 April 2005 for more information on this subject In general the precise values depend on the application Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration In the case of the AD9239 the default i
28. O OQ O O LO 10 10 LO LO A x NC 1 PIN 1 NC TEMPOUT 2 INDICATOR PGMO RBIAS 3 PGM1 AVDD 4 PGM2 NC 5 PIN 0 EPAD AGND PGM3 NC 6 NC AVDD 7 AVDD VCMD 8 AD9239 VCMA AVDD 9 TOP VIEW AVDD VIN D 10 Not to Scale VIN A VIN D 11 VIN A AVDD 12 AVDD AVDD 13 AVDD AVDD 14 AVDD AVDD 15 CSB CLK 16 SCLK CLK 17 SDI SDIO AVDD 18 SDO NOTES 1 NC NO CONNECT 2 THE EXPOSED PADDLE MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE SOLDERING THE EXPOSED PADDLE TO THE CUSTOMER BOARD INCREASES THE RELIABILITY OF THE SOLDER JOINTS MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE 06980 004 Table 8 Pin Function Descriptions Figure 3 Pin Configuration AD9239 Pin No Mnemonic Description 0 AGND Analog Ground Exposed Paddle 23 34 DRGND Digital Output Driver Ground 4 7 9 12 13 14 AVDD 1 8 V Analog Supply 15 18 20 21 41 42 43 46 48 55 57 60 61 62 64 65 66 69 71 24 33 DRVDD 1 8V Digital Output Driver Supply 2 TEMPOUT Output Voltage to Monitor Temperature 3 RBIAS External Resistor to Set the Internal ADC Core Bias Current 8 VCM D Common Mode Output Voltage Reference 10 VIN D ADC D Analog Complement 11 VIN D ADC D Analog True 16 CLK Input Clock Complement 17 CLK Input Clock True 22 RESET Digital Output Timing Reset 25 DOUT D ADC D True Digital Output 26 DOUT D ADC D Complement Digital Output 27 DOUT C ADC C True Digital Outp
29. TORS ARE OPTIONAL Figure 53 Differential PECL Sample Clock 06980 019 AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1uF AD9516 AD9518 O0 iuF CLK CLK ADC 0 1 CLK 500 500 06980 020 500 RESISTORS ARE OPTIONAL Figure 54 Differential LVDS Sample Clock In some applications it is acceptable to drive the sample clock inputs with a single ended CMOS signal In such applications CLK should be driven directly from a CMOS gate and the CLK pin should be bypassed to ground with a 0 1 uF capacitor in parallel with a 39 kO resistor see Figure 55 Although the AD9239 CLK input circuit supply is AVDD 1 8 V this input is designed to withstand input voltages of up to 3 3 V and therefore offers several selections for the drive logic voltage AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 AD9516 AD9518 OPTIONAL 1000 CLK ADC AD9239 0 1uF 50Q RESISTOR IS OPTIONAL Figure 55 Single Ended 1 8 V CMOS Sample Clock 06980 021 AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1 AD9516 AD9518 OPTIONAL 1000 06980 022 500 RESISTOR IS OPTIONAL Figure 56 Single Ended 3 3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals As a result these ADCs may be sensitive to the clock duty cycle Commonly a 5 tolerance is required on the clock duty cycle to maintain dynamic perfor mance charac
30. ad global 010 170 only 100 210 101 250 Device Index and Transfer Registers 05 device_ ADCA ADCB ADC C ADC D 0x0F Bits are set index_A to determine global which device on chip receives the next write command The default is all devices on chip FF device_ SW 0x00 Synchro update local transfer nously master 1 transfers 0 off data from default the master shift register to the slave ADC Functions Registers 08 modes External 00 chip run 0x00 Determines local PDWN default various ge pin 01 full power down neric modes function 10 standby of chip 00 full 11 reset operation PDWN default 01 standby 09 Clock Duty 0x01 Turns the global cycle internal stabilize duty cycle 1 on stabilizer default on and off 0 off oD test_io Reset PN Reset PN Flex output test mode 0x00 When set local long gen short gen 0000 off normal operation the test data 1 1 0001 midscale short is placed on 0 off 0 off 0010 FS short the output default default 0011 FS short pins in place 0100 checkerboard output of normal 0101 PN 23 sequence data 0110 PN 9 sequence 0111 one zero word toggle OE test bist BIST init BIST 0x00 When Bit O local 1 on enable is set the 0 off 1 built in self default 0 off test function default is initiated Rev B Page 34 of 40 09239
31. ansmission The MSB of the ECC is always 0 and is not used to detect an error The six LSBs of the ECC are the result of the XORs of the given bits see Figure 68 to Figure 75 These bits allow for a parity check for any bit in the header and data field The seventh parity bit is applied to the entire packet after the Hamming parity bits are calculated This parity check allows correction of an error in the data or in the ECC bits In the general implementation the parity bits are located in the power of 2 positions but are pulled from these locations and placed together at the end of the packet Figure 68 to Figure 75 show which header and data bits are associated with the parity bits In the receiver these parity checks are performed and the receiver parity bits are calculated The difference between the received parity bits and the calculated parity bits indicate which bit was in error Rev B Page 25 of 40 09239 Scramblers There are three scramblers on the AD9239 The scramblers are an Ethernet scrambler x x 1 a SONET scrambler x 1 and a static inverter scrambler inverts bits at set locations in the packet The scramblers are used to help balance the number of 1s and 0s in the packet The Ethernet and SONET scramblers work on scrambling the whole packet 64 bits the header and the data 56 bits or just the data 48 bits The scrambler is self synchronizing on the descramble end or receive en
32. ations Rev B Page 20 of 40 CLOCK INPUT CONSIDERATIONS For optimum performance the AD9239 sample clock inputs CLK and should be clocked with a differential signal This signal is typically ac coupled to the CLK and CLK pins via a transformer or capacitors These pins are biased internally to 1 2 V and require no additional biasing Figure 52 shows a preferred method for clocking the AD9239 The low jitter clock source is converted from a single ended signal to a differential signal using an RF transformer The back to back Schottky diodes across the secondary transformer limit clock excursions into the AD9239 to approximately 0 8 V p p differential This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9239 and it preserves the fast rise and fall times of the signal which are critical to low jitter performance Mini Circuits ADT1 1WT 1 12 As O4pF 500 0 1yF SCHOTTKY 0 1uF DIODES E HSM2812 E Figure 52 Transformer Coupled Differential Clock Another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 53 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 AD9516 AD9518 family of clock drivers offers excellent jitter performance AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1uF 9516 09518 1 CLK CLK ADC PECL DRIVER 0 1yF CLK 500 500 500 RESIS
33. d and does not require an additional sync bit For a copy of either the Ethernet or SONET scrambler code send an email to highspeed converters analog com Figure 65 and Figure 66 show the serial implementation of the Ethernet and SONET scramblers The parallel implementation allows the scrambler and descrambler to run at a slower clock rate and can be implemented in the fabric of a receiver The serial implementations of the Ethernet and SONET scramblers more easily show what is being done The parallel implementation must be derived from the serial implementation The end product depends on how many bits need to be processed in parallel For the scrambler 64 bits are processed even in the 56 and 48 bit cases To achieve this for 56 bits and 48 bits a portion of two samples is used to fill the rest of the input word Inverter Balance Example The inverter implementation uses predetermined bit positions to balance the packet in an overrange condition all 1s or all 0s in the converter The inversions are present in all conditions not just the overrange condition The descrambler can be based off any number of bits the user chooses to process In the inverter based scrambler the packet is balanced based on an overranged condition If each packet is balanced the bit stream should be balanced Instead of a random sequence that changes from packet to packet certain inverts are set at predetermined bit positions within the packet This allo
34. dBFS e 100 Figure 6 Single Tone 32k FFT with fi 84 3 MHz 210 MSPS ENOB 10 49 BITS SFDR 77 57dBc 0 10 20 30 40 50 60 70 80 FREQUENCY MHz AIN 1 0dBFS SNR 63 95dB ENOB 10 33 BITS SFDR 78 90dBc VY OTT DOR WEE UIS 0 10 20 30 40 50 60 70 80 FREQUENCY MHz 1 0dBFS SNR 64 65dB ENOB 10 44 BITS SFDR 77 54dBc PYT 0 20 40 60 80 100 FREQUENCY MHz 09239 AIN 1 0dBFS SNR 63 13dB ENOB 10 19 BITS SFDR 76 07 AMPLITUDE dBFS 5 100 0 20 40 60 FREQUENCY MHz 06980 059 80 100 AIN 1 0dBFS SNR 64 62dB ENOB 10 44 BITS SFDR 75 48dBc 1 AMPLITUDE dBFS 5 100 d TARPS k42 04 12 0 20 40 60 80 FREQUENCY MHz 06980 060 AIN 1 0dBFS SNR 64 50dB 100 120 20 10 42 BITS SFDR 77 97dBc AMPLITUDE dBFS 5 1 100 kuq ott bet 20 40 60 80 FREQUENCY MHz 06980 061 Rev Page 11 of 40 100 120 06980 062 Figure 7 Single Tone 32k FFT with fin 240 3 MHz 210 MSPS 06980 063 Figure 8 Single Tone 32k FFT with fi 10 3 MHz fsamece 250 MSPS 06980 064
35. dation in SNR at a given input frequency fa due only to aperture jitter t can be calculated by SNR Degradation 20 x log 10 1 2 x m x fa x tj In this equation the rms aperture jitter represents the root mean square of all jitter sources including the clock input analog input signal and ADC aperture jitter IF undersampling applications are particularly sensitive to jitter see Figure 57 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9239 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators are the best clock sources If the clock is generated from another type of source by gating dividing or another method it should be retimed by the original clock during the last step Refer to the AN 501 Application Note the AN 756 Application Note and the Analog Dialogue article Analog to Digital Converter Clock Optimization A Test Engineering Perspective Volume 42 Number 2 February 2008 for more in depth information about jitter performance as it relates to ADCs visit www analog com 130 RMS CLOCK JITTER REQUIREMENT 120 110 100 90 m B x 80 2 2 T0 60 50 40 30 1 10 100 1000 ANALOG INPUT FREQUENCY MHz Figure 57 Ideal SNR vs Input Frequency and Jitter Power Dissipation Asshown
36. e ettet ee ettet E E A Quya Sua 8 Pin Configuration and Function Description 9 REVISION HISTORY 5 10 Rev A to Rev B Changes to Table Suara bete 35 36 2 10 Rev 0 to Rev A Changes to Analog Inputs Differential Input Voltage Range Parameter and Endnote 3 Table 1 sss 3 Changes to Table 8 deterret 9 Changes to Clock Duty Cycle Considerations Section 21 Changes to Digital Outputs and Timing Section 23 Changes to Table 15 teet teet med 34 10 08 Revision 0 Initial Version Typical Performance Characteristics 22 2 11 Equivalent Circuits a a a a tetti aridis 17 Theory of Operation tabernae ette teeth 19 Analog Input Considerations 19 Clock Input Considerations 21 Serial Port Interface SPI eee 31 Hardware Interface 31 33 Reading the Memory Table sss 33 Reserved Locations eee epe 33 Default Values ER 33 Logic Levels consecteter ertt eni tiit iias 33 Outline Dimensions Ordering Guide Rev B Page 2 of 40 SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V Tum 40 C Tmax 85 C 1 25 V differential input AIN 1 0 dBFS DCS enabled unless otherwise noted 09239 Table 1 AD9239BCPZ 170 AD9239BCPZ 210 AD9239BCPZ 250 Parame
37. g A 5 78 p5 h7 h6 h5 h4 h3 h2 hi h0 di 11 d1 10 d1 9 d1 8 d1 7 d1 6 d1 5 d1 4 d2 0 d3 11 d3 lt 10 gt 4d3 lt 9 gt 4d3 lt 8 gt d3 lt 7 gt 4d3 lt 6 gt d3 lt 5 gt 4d3 lt 4 gt 4d3 lt 3 gt d3 lt 2 gt 4d3 lt 1 gt 4d3 lt 0 gt 4d4 lt 11 gt 4d4 lt 10 gt Figure 74 p5 Bit for 64 Bit Packet 12 Bit Case D1 D1 D1 D1 D1 h7 h6 h5 h4 h3 h2 kgs D1 D1 D1 D1 D1 02 02 02 D2 D2 02 02 02 02 lt 4 gt lt 3 gt lt 2 gt lt 1 gt lt 0 gt lt 11 gt lt 10 gt lt 9 gt lt 8 gt lt 7 gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt Figure 75 p6 Bit for 64 Bit Packet 12 Bit Case Rev B Page 29 of 40 06980 100 06980 101 06980 102 06980 103 AD9239 AD9239 TEMPOUT Pin The TEMPOUT pin can be used as a course temperature sensor to monitor the internal die temperature of the device This pin typical has a 734 mV output with a clock rate of 250 MSPS and a negative temperature going coefficient 1 12 mV C The voltage response of this pin is characterized in Figure 76 0 85 0 75 N wo TEMPOUT PIN VOLTAGE V e o 0 67 0 65 40 30 20 10 0 10 20 30 40 50 60 70 80 TEMPERATURE C Figure 76 TEMPOUT Pin Voltage vs Temperature RBIAS
38. ial input buffer front end sample and hold amplifier SHA followed by a pipelined switched capacitor ADC The quantized outputs from each stage are combined into a final 12 bit result in the digital correction logic The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples Sampling occurs on the rising edge of the clock Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier for example a multiplying digital to analog converter MDAC The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline One bit of redundancy is used in each stage to facilitate digital correction of flash errors The last stage simply consists of a flash ADC The input stage contains a differential SHA that can be ac or dc coupled in differential or single ended mode The output of the pipeline ADC is put into its final serial format by the data serializer encoder and CML drivers block The data rate multiplier creates the clock used to output the high speed serial data at the CML outputs ANALOG INPUT CONSIDERATIONS The analog input to the AD9239 is a differential buffer This input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially S
39. iu Full 10 10 10 10 10 10 Low Level Input Current li Full 10 10 10 10 10 10 Differential Input Resistance 25 C 16 20 24 16 20 24 16 20 24 kQ Input Capacitance 25 C 4 4 4 pF LOGIC INPUTS PDWN CSB SDI SDIO SCLK RESET PGMx Logic 1 Voltage Full 0 8 x 0 8 x 0 8 x V AVDD AVDD AVDD Logic 0 Voltage Full 0 2 x 0 2 x 0 2 x V AVDD AVDD AVDD Logic 1 Input Current CSB Full 0 0 0 Logic 0 Input Current CSB Full 60 60 60 Logic 1 Input Current Full 55 55 55 SCLK PDWN SDI SDIO RESET PGMx Logic 0 Input Current Full 0 0 0 SCLK PDWN SDI SDIO RESET PGMx Input Resistance 25 30 30 30 kQ Input Capacitance 25 C 4 4 4 pF LOGIC OUTPUTS SDO Logic 1 Voltage Full 1 2 AVDD 1 2 AVDD 1 2 AVDD V 0 3 0 3 0 3 Logic 0 Voltage Full 0 0 3 0 0 3 0 0 3 V DIGITAL OUTPUTS DOUT x DOUT x Logic Compliance Current Current Current mode mode mode logic logic logic Differential Output Voltage Full 0 8 0 8 0 8 Common Mode Level Full DRVDD 2 DRVDD 2 DRVDD 2 V 1 the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for definitions and details on how these tests were completed Specified for 13 SDI SDIO pins sharing the same connection Rev B Page 5 of 40 09239 SWITCHING SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V Tun 40 C Tmax 85 C 1 25 differential input AIN 1 0 dBFS DCS enabled unless
40. l PDWN pin Digital Outputs and Timing The AD9239 has differential digital outputs that power up on default The driver current is derived on chip and sets the output current at each output equal to a nominal 4 mA Each output presents 100 dynamic internal termination to reduce unwanted reflections 09239 100 differential termination resistor should be placed at each receiver input to result in a nominal 400 mV p p swing at the receiver Alternatively single ended 50 termination can be used When single ended termination is used the termination voltage should be DRVDD 2 otherwise ac coupling capacitors can be used to terminate to any single ended voltage The AD9239 digital outputs can interface with custom application specific integrated circuits ASICs and field programmable gate array FPGA receivers providing superior switching performance in noisy environments Single point to point net topologies are recommended with a single differential 100 termination resistor placed as close to the receiver logic as possible The common mode of the digital output automatically biases itself to half the supply of DRVDD if dc coupled connecting is used For receiver logic that is not within the bounds of the DRVDD supply an ac coupled connection should be used Simply place a 0 1 uF capacitor on each output pin and derive 100 differential termination close to the receiver side If there is no far end receiver ter
41. levels are met Assuming the same load for each AD9239 Figure 77 shows the number of SDI SDIO pins that can be connected together and the resulting level This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers providing the user with an alternative method other than a full SPI controller to program the ADC see the AN 812 Application Note For users who wish to operate the ADC without using the SPI remove any connections from the CSB SCLK SDO and SDI SDIO pins By disconnecting these pins from the control bus the ADC can function in its most basic operation Each of these pins has an internal termination that floats to its respective level Rev B Page 31 of 40 AD9239 CSB SCLK DON T CARE Vou V 10 20 30 80 90 100 NUMBER OF SDI SDIO PINS CONNECTED TOGETHER Figure 77 SDI SDIO Pin Loading 06980 104 DON T CARE Table 14 Serial Timing Definitions Figure 78 Serial Timing Details Parameter Timing Minimum ns Description tos 5 Setup time between the data and the rising edge of SCLK toH 2 Hold time between the data and the rising edge of SCLK tak 40 Period of the clock ts 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK 16 Minimum period that SCLK should be in a logic high state tio 16 Minimum
42. ly and the input clock may be driven differentially with a sine wave LVPECL TTL or LVDS A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles The on chip reference eliminates the need for external decoupling and can be adjusted by means of SPI control Various power down and standby modes are supported The ADC typically consumes 145 mW per channel with the digital link still in operation when standby operation is enabled Rev Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners AD9239 C DOUT A CHANNEL A C DOUT A C DOUT B CHANNEL B QO DOUT B CML DRIVERS DOUT C CHANNEL C DOUT C Q DOUT D PIPELINE 12 CHANNEL D ES D REFERENCE O PGM3 C PGM2 DATA SERIALIZER ENCODER AND DATA RATE MULTIPLIER PGM1 PGMO RESET SCLK SDI SDO CSB CLK SDIO 06980 001 Figure 1 Fabricated on an advanced CMOS process the AD9239 is avail able in a Pb free RoHS compliant 72 lead LFCSP package
43. ly pins required for communication Although the device is synchronized during power up the user should ensure that the serial port remains synchronized with the CSB line when using this mode When operating in 2 wire mode it is recommended to use a 1 2 or 3 byte transfer exclusively Without an active CSB line streaming mode can be entered but not exited In addition to word length the instruction phase determines if the serial frame is a read or write operation allowing the serial port to be used to both program the chip and read the contents of the on chip memory If the instruction is a readback operation performing a readback causes the SDI SDIO pin to change from an input to an output at the appropriate point in the serial frame Data can be sent in MSB or LSB first mode MSB first mode is the default at power up and can be changed by adjusting the configuration register For more information about this and other features see the AN 877 Application Note Interfacing to High Speed ADCs via SPI HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the user s programming device and the serial port of the AD9239 The SDO SCLK and CSB pins function as inputs when using the SPI The SDI SDIO pin is bidirectional functioning as an input during write phases and as an output during readback If multiple SDI SDIO pins share a common connection care should be taken to ensure that proper Vou
44. mination or there is poor differential trace routing timing errors may result To avoid such timing errors it is recommended that the trace length be less than 6 inches and that the differential output traces be close together and at equal lengths DRVDD 1000 DIFFERENTIAL TRACE PAIR 092 OUTPUT SWING 400 ei xX Vom DRVDD 2 5 Figure 61 DC Coupled Digital Output Termination Example 06980 1000 DIFFERENTIAL 0 14pF TRACE PAIR DRVDD 06980 093 OUTPUT SWING 400mV ei xX Vom Rx Vom Figure 62 AC Coupled Digital Output Termination Example Rev B Page 23 of 40 AD9239 HEIGHT1 EYE DIAGRAM TIE1 HISTOGRAM TJ BERI BATHTUB y1 375 023m 600 2 409 847m Ay 784 671m Ho 200 3 4 3 VOLTAGE mV o 1 HITS EYE ALL BITS OFFSET 0 015 600 uis 5000 40044 TOTAL 12000 80091 1 200 100 0 100 200 30 10 10 0 5 ULS Figure 63 Digital Outputs Data Eye with Trace Lengths Less than 6 Inches on Standard FR 4 External 100 Q Terminations at Receiver 06980 094 HEIGHT1 EYE DIAGRAM TIE1 HISTOGRAM TJ BERI BATHTUB 300 papayuq le 600 9
45. nput span is 1 25 V To configure the ADC for a different input span see Register 18 For the best performance an input span of 1 25 V p p or greater should be used see Table 15 for details Differential Input Configurations There are several ways to drive the AD9239 either actively or passively in either case optimum performance is achieved by driving the analog input differentially For example using the ADA4937 differential amplifier to drive the AD9239 provides excellent performance and a flexible interface to the ADC see Figure 45 and Figure 46 for baseband and second Nyquist 100 MHz IF applications In either application 1 resistors should be used for good gain matching It should also be noted that the dc coupled configuration will show some degradation in spurious performance For further reference consult the ADA4937 data sheet AVDD DRVDD AD9239 ADC INPUT IMPEDANCE OPTIONAL C 06980 090 1 8V 1 8V AVDD DRVDD AD9239 ADC INPUT IMPEDANCE OPTIONAL C VCMx 06980 091 Figure 46 Differential Amplifier Configuration for DC Coupled Baseband Applications Rev B Page 19 of 40 AD9239 For applications where SNR is a key parameter differential 1 25V p p transformer coupling is the recommended input configuration see Figure 47 to Figure 49 to achieve the true performance of the AD9239 BALUN 0 1uF 330 VIN x ADC eeo AD9239 0 1 Regardless of the config
46. on Board 17 RoHS Compliant Part Rev B Page 38 of 40 AD9239 NOTES Rev B Page 39 of 40 AD9239 NOTES 2008 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06980 0 5 10 B DEVICES www analo g com Rev B Page 40 of 40
47. only one supply is available it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD The user can employ several different decoupling capacitors to cover both high and low frequencies These should be located close to the point of entry at the printed circuit board PCB level and close to the parts with minimal trace lengths A single PCB ground plane should be sufficient when using the AD9239 With proper decoupling and smart partitioning of the analog digital and clock sections of the PCB optimum performance can easily be achieved Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC is connected to analog ground AGND to achieve the best electrical and thermal performance of the AD9239 An exposed continuous copper plane on the PCB should mate to the AD9239 exposed paddle Pin 0 The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB These vias should be solder filled or plugged with nonconductive epoxy To maximize the coverage and adhesion between the ADC and PCB partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections This provides several tie points between the ADC and PCB during the reflow process whereas using one c
48. ontinuous plane with no partitions guarantees only one tie point See Figure 79 for a PCB layout example For detailed information on packaging and the PCB layout of chip scale packages see the AN 772 Application Note A Design and Manufacturing Guide for the Lead Frame Chip Scale Package LFCSP at www analog com SILKSCREEN PARTITION PIN 1 INDICATOR 06980 029 Figure 79 Typical PCB Layout Rev B Page 37 of 40 AD9239 OUTLINE DIMENSIONS 0 60 0 60 042 0 42 x 0 24 i 0 24 UUU PIN 1 INDICATOR PIN 1 INDICATOR 0 50 9 75 BSC SQ BSC EXPOSED PAD BOTTOM VIEW F 0 65 TYP 0 80 L PEE eue FOR PROPER CONNECTION OF 0 02 Nom THE EXPOSED PAD REFER SEATING_ 0 30 COPLANARITY THE PIN CONFIGURATION AND PLANE 0 23 0 20 REF 0 08 FUNCTION DESCRIPTIONS aa SECTION OF THIS DATA SHEET 030408 A COMPLIANT TO JEDEC STANDARDS MO 220 VNND 4 Figure 80 72 Lead Lead Frame Chip Scale Package LFCSP_VQ 10 mm x 10 mm Body Very Thin Quad CP 72 3 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9239BCPZ 170 409 to 85 C 72 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 72 3 AD9239BCPZ 210 40 to 85 C 72 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 72 3 AD9239BCPZ 250 40 to 85 C 72 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 72 3 AD9239 250KITZ Evaluati
49. order to drive Data from each ADC is serialized and provided on a separate longer trace lengths see Register 15 in Table 15 Even though channel The data rate for each serial stream is equal to N bits this produces sharper rise and fall times on the data edges and is times the sample clock rate in addition to some amount of less prone to bit errors the power dissipation of the DRVDD overhead to account for the 8 bit header and error correction for a supply increases when this option is used See the Memory Map maximum of 3 15 Gbps that is 12 bits x 210 MSPS x 25 section for more details 3 15 Gbps The lowest typical clock rate is 100 MSPS For clock rates slower than 100 MSPS refer to Register 21 in the SPI Memory Map This option allows the user to adjust the PLL loop bandwidth in order to use clock rates as low as 50 MSPS The format of the output data is offset binary by default An example of the output coding format can be found in Table 9 Rev B Page 24 of 40 Table 10 Flexible Output Test Modes 09239 Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off default N A N A Yes 0001 Midscale short 1000 0000 0000 Same Yes 0010 Full scale short 1111 1111 1111 Same Yes 0011 Full scale short 0000 0000 0000 Same Yes 0100 Checkerboard 1010 1010 1010 0101 0101 0101 No 0101 PN sequence long N A N A Yes 0110 PN sequence short N A N A Yes
50. otherwise noted Table 4 AD9239BCPZ 170 AD9239BCPZ 210 AD9239BCPZ 250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK Clock Rate Full 170 100 210 100 250 100 MSPS Clock Pulse Width High ten Full 2 65 2 9 2 15 24 1 8 2 0 ns Clock Pulse Width Low Full 2 65 2 9 2 15 24 1 8 2 0 ns DATA OUTPUT PARAMETERS Data Output Period or UI Full 1 16 x fax 1 16 x faq 1 16 x faq sec DOUT x DOUT x Data Output Duty Cycle 25 C 50 50 50 Data Valid Time 25 C 0 8 0 8 0 8 Ul PLL Lock Time 25 C 4 4 4 us Wake Up Time Standby 25 C 250 250 250 ns Wake Up Time Power Down 25 C 50 50 50 us Pipeline Latency Full 40 40 40 CLK cycles Data Rate per Channel NRZ 25 C 2 72 3 36 4 0 Gbps Deterministic Jitter 25 C 10 10 10 ps max Random Jitter 25 C 6 6 6 ps rms Channel to Channel Bit Skew 25 C 0 0 0 sec Channel to Channel Packet Skew 25 C 1 1 1 CLK cycles Output Rise Fall Time 25 C 50 50 50 ps TERMINATION CHARACTERISTICS Differential Termination Resistance 25 C 100 100 100 Q APERTURE Aperture Delay ta 25 C 1 2 1 2 1 2 ns Aperture Uncertainty Jitter 25 C 0 2 0 2 0 2 ps rms OUT OF RANGE RECOVERY TIME 25 C 1 1 1 CLK cycles 1 the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for definitions and details on how these tests were completed Receiver dependent 3 See the Digital Start Up Sequence section Rev B Page 6
51. patt2 Isb pattern local 2LSB 1C user B15 B14 B13 B12 B11 B10 B9 B8 0x35 User defined patt2 msb pattern local 2MSB 1D user B7 B6 B5 B4 B3 B2 B1 BO OxBB User defined patt3 Isb pattern local 3LSB 1E user B15 B14 B13 B12 B11 B10 B9 B8 OxDD User defined patt3 msb pattern local 3 MSB Rev B Page 35 of 40 AD9239 Default Default Addr Register MSB LSB Value Notes Hex Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Comments 1F user_ B7 B6 B5 B4 B3 B2 B1 BO OxAA User defined patt4_Isb pattern local 4LSB 20 user_ B15 B14 B13 B12 B11 B10 9 8 OxCC User defined patt4_msb pattern local 4 MSB 21 serial_control PLL 0x08 Serial stream global high control encode rate mode global 0 low rate 1 high rate default 24 misr Isb B7 B6 B5 B4 B3 B2 B1 BO 0x00 Least local significant byte of MISR Read only 25 misr msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 Most local significant byte of MISR Read only 32 adi link Hamming Scramble Data flow Over Scramble options Scramble Ox4B Default is options enable data only order rangein 00 inverted enable 56 bit global 1 0 0 header 01 SONET default 1 5 default scramble ECC last 1 10 Ethernet default scrambler 0 off header default default 0 off with over anddata 1 0 off range in the default Sc
52. period that SCLK should be in a logic low state _ 0 52 10 Minimum time for the SDI SDIO pin to switch from an input to an output relative to the SCLK falling edge not shown in Figure 78 tpis spyspio 10 Minimum time for the SDI SDIO pin to switch from an output to an input relative to the SCLK rising edge not shown in Figure 78 Rev B Page 32 of 40 06980 028 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table Table 15 has eight bit locations The memory map is divided into three sections the chip configuration registers Address 0x00 to Address 0x02 the device index and transfer registers Address 0x05 and Address OxFF and the ADC functions registers Address 0x08 to Address 0x53 The leftmost column of the memory map indicates the register address number and the default value is shown in the second rightmost column The Bit 7 column is the start of the default hexadecimal value given For example Address 0x09 the clock register has a default value of 0x01 meaning that Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 and Bit 0 1 or 0000 0001 in binary This setting is the default for the duty cycle stabilizer in the on condition By writing a 0 to Bit 0 of this address followed a 0x01 in Register 0xFF transfer bit the duty cycle stabilizer turns off It is important to follow each writing sequence with a transfer bit to update the SPI
53. rambler header bits 1 last scramble Override data only 0x032 5 34 Channel ID Channel ID 0x00 local Only Bits 3 0 used if overrange is included in header 50 coarse_ Gain adjust Coarse Gain Adjust 5 0 Output 63 0 0x00 gain_adj enable 000000 0000 0001 local 1 000001 0000 0011 0 off 000010 0000 0111 default 111101 0011 1111 111110 0111 1111 111111 1111 1111 51 fine_ Fine Gain Adjust 3 0 Output 15 0 0x00 gain_adj 0000 0000000000000001 local 0001 0000000000000010 0010 0000000000000100 1101 2 0010000000000000 1110 2 0100000000000000 1111 1000000000000000 52 gain_cal_ctl Temp sensor Gain quar Gaincal Gain cal 0x02 enable ter LSB resetb enable 1 1 1 1 0 off 0 off default 0 off default default 0 off default 53 Dynamic pgm 3 pgm 2 1 0 0 00 Standby pgm pins 00 sync 00 sync 00 sync 00 sync ADC core global 01 standby 01 standby 01 standby 01 standby D off PN23 10 standby A and D 10 standby B and C 10 standby C and 10 standby D and enabled 11 2 standby A and B 11 standby Band A 11 standby D 11 standby D and C serial channel enabled Rev B Page 36 of 40 09239 Power and Ground Recommendations When connecting power to the AD9239 it is recommended that two separate 1 8 V supplies be used one for analog AVDD and one for digital DRVDD If
54. s maximizing the thermal capability of the package Table 7 Thermal Resistance Package Type Unit 72 Lead LFCSP CP 72 3 16 2 7 9 0 6 C W Typical and values are specified for a 4 layer board in still air Airflow increases heat dissipation effectively reducing In addition metal in direct contact with the package leads from metal traces and through holes ground and power planes reduces the ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 8 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTION mm m 8 8922555055959 2 55 5 2454554425444 55 lt gt lt m O O D D oO
55. ter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25 C 2 12 2 12 2 12 mV Offset Matching 25 C 4 12 4 12 4 12 mV Gain Error 25 C 2 8 1 47 28 1 T4 28 1 47 FS Gain Matching 25 C 0 9 2 7 0 9 2 7 0 9 2 7 FS Differential Nonlinearity DNL Full 0 28 06 0 28 0 6 0 3 0 6 LSB Integral Nonlinearity INL Full 0 45 0 9 0 7 1 3 0 7 1 3 LSB ANALOG INPUTS Differential Input Voltage Range Full 1 0 1 25 1 5 1 0 1 25 1 5 1 0 1 25 1 5 V p p Common Mode Voltage Full 1 4 1 4 1 4 Input Capacitance 25 C 2 2 2 pF Input Resistance Full 4 3 43 4 3 kO Analog Bandwidth Full Power Full 780 780 780 MHz Voltage Common Mode VCMx Voltage Output Full 14 1 44 1 5 14 1 44 1 5 14 1 44 1 5 V Current Drive Full 1 1 1 mA Temperature Sensor Output 1 12 1 12 1 12 mV C Voltage Output Full 739 737 734 mV Current Drive Full 10 10 10 POWER SUPPLY AVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 1 7 1 8 1 9 V DRVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 1 7 1 8 1 9 V Full 535 570 610 650 725 775 mA Ipevoo Full 98 105 111 120 123 133 mA Total Power Dissipation Full 1 139 1 215 1 298 1 386 1 526 1 634 W Including Output Drivers Power Down Dissipation Full 3 3 3 mW Standby Dissipation Full 152 173 195 mW CROSSTALK Full 95 95 95 dB Overrange Condition Full 90 90 90 1 the AN 835 Application Note
56. teristics The AD9239 contains a duty cycle stabilizer DCS that retimes the nonsampling edge providing an internal clock signal with a nominal 50 duty cycle This allows a wide range of clock input duty cycles without affecting the performance of the AD9239 When the DCS is on default noise and distortion performance are nearly flat for a wide range of duty cycles However some applications may require the DCS function to be off If so keep in mind that the dynamic range performance may be affected when operated in this mode See the Memory Map section for more details on using this feature Jitter in the rising edge of the input is an important concern and it is not reduced by the internal stabilization circuit The duty cycle control loop does not function for clock rates of less than 50 MHz nominal It is not recommended that this ADC clock be dynamic in nature Moving the clock around dynamically requires long wait times for the back end serial capture to retime and resynchronize to the receiving logic This long time constant far exceeds the time it takes for the DCS and PLL to lock and stabilize Only in rare applications would it be necessary to disable the DCS circuitry of Register 9 see Table 15 Keeping the DCS circuit enabled is recommended to maximize ac performance Rev B Page 21 of 40 09239 Clock Jitter Considerations High speed high resolution ADCs are sensitive to the quality of the clock input The degra
57. uration the value of the shunt capacitor VIN x is dependent on the input frequency and may need to be reduced BALUN or removed 06980 017 ADT1 1WT 1 1 2 RATIO L 330 VIN x Figure 50 Differential Balun Coupled Configuration 1 25V 6 0 1uF Pee 9 for Wideband IF Applications lt NIN REND Single Ended Input Configuration 0 WFF A single ended input may provide adequate performance in cost sensitive applications In this configuration SFDR and Figure 47 Differential Transformer Coupled Configuration distortion per formance can degr ade due to Input common mode for Baseband Applications swing mismatch If the application requires a single ended input ADT1 IWT configuration ensure that the source impedances on each input 125VPP OAF 44 ZRATIO L 330 P P are well matched in order to achieve the best possible performance A full scale input of 1 25 V p p can be applied to the ADCs VIN x pin while the VIN x pin is terminated Figure 51 details a typical single ended input configuration 650 06980 014 Figure 48 Differential Transformer Coupled Configuration for Wideband IF Applications 0 1uF 1 25V p p 49 90 1p 4 ADT1 1WT 1 25Vp P O 4UF 4 12 RATIO 330 250 0 1 1 Figure 51 Single Ended Input Configuration 06980 016 CpIFF IS OPTIONAL 06980 015 Figure 49 Differential Transformer Coupled Configuration for Narrow Band IF Applic
58. ut 28 DOUT C ADC C Complement Digital Output 29 DOUT B ADC B True Digital Output 30 DOUT B ADC B Complement Digital Output 31 DOUT A ADC A True Digital Output 32 DOUT A ADC A Complement Digital Output 35 PDWN Power Down Rev B Page 9 of 40 09239 Pin No Mnemonic Description 37 SDO Serial Data Output Used for 4 wire SPI interface 38 SDI SDIO Serial Data Input Serial Data IO for 3 Wire SPI Interface 39 SCLK Serial Clock 40 CSB Chip Select Bar 44 VIN A ADC A Analog Input True 45 VIN A ADC A Analog Input Complement 47 VCM A Common Mode Output Voltage Reference 50 PGM3 Optional Pin to be Programmed by Customer 51 PGM2 Optional Pin to be Programmed by Customer 52 PGM1 Optional Pin to be Programmed by Customer 53 PGMO Optional Pin to be Programmed by Customer 56 VCM B Common Mode Output Voltage Reference 58 VIN B ADC B Analog Input Complement 59 VIN ADC B Analog Input True 67 VIN ADC C Analog Input True 68 VIN ADC C Analog Input Complement 70 VCM C Common Mode Output Voltage Reference 1 5 6 19 36 NC No Connection 49 54 63 72 Rev B Page 10 of 40 TYPICAL PERFORMANCE CHARACTERISTICS 1 0dBFS SNR 64 88dB 20 120 Figure 4 Single Tone 32k FFT with 84 3 MHz 170 MSPS 20 AMPLITUDE dBFS 5 e 100 Figure 5 Single Tone 32k FFT with 240 3 MHz 170 MSPS 20 AMPLITUDE
59. ws the decoding to be done in the receiver end Figure 67 shows the inverters in the packet for the 12 bit data case and the inverter order in the header Table 12 shows the average value of the packet for various conditions Table 12 Average of 1s and 0s in Overrange Conditions Assuming Header Bits are All 0 12 Bit ECC No Scramble Data 0 0 00000000 No Scramble Data 1 0 844 00111111 Average of Negative and Positive 0 422 Overrange Scramble Only Data Data 0 0 375 00000000 Scramble Only Data Data 1 0 469 00111111 Average of Negative and Positive 0 422 Overrange Scramble Data and Header Data 0 0 437 00000000 Scramble Data and Header Data 1 0 531 00111111 Average of Negative and Positive 0 484 Overrange If the analog signal is out of range there should be about the same number of out of range positive and out of range negative values The average for no scrambling and for scrambling just the data is about the same If the header is used to indicate out of range the balance improves for the 12 bit case Rev B Page 26 of 40 09239 POLYNOMIAL 1 x39 x58 06980 025 Figure 65 Serial Implementation of Ethernet Scrambler POLYNOMIAL 1 x 7 boe 57 57 m 52 Figure 66 Serial Implementation of SONET Scrambler 06980 026 06980 105 b INVERTED BIT Figure 67 Scrambler Inverters for 64 Bit Packet 12 Bit Case

ANALOG DEVICES AD9239 English products handbook Rev B

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