INTERNATIONAL RECTIFIER IR3843WMPbF Manual
Contents
1. C3 180 pF Fig 16 Application circuit diagram for a 12V to 1 8 V 2 A Point Of Load Converter Suggested Bill of Materials for the application circuit Quantity Value Description Manufacturer Part Number EEV FK1E331P 1fouF 1206 25V X5R 20 TDK C3216X5R1E106M 1 tuF 1uF 10V X5R 0805 ECJ 2FB1C105K 3uH 3 30H 8A 2096 6 5MMx7 MM IHLP2525EZ 01 3 3uH 0805 6 3V X5R 20 ECJ 2FB0J226M 9 9k 49 9K 0603 1 10 W 1 MCRO3EZPFX4992 MCRO3EZPFX7501 MCROSEZPFX2372 is loeoatowm rom MCROBEZPFXISA1 MCROSEZPFX1002 0 1uF 0603 25V X7R 10 Panasonic ECG ECJ 1VB1E104K 2 74k 0603 1 10W 1 MCRO3EZPFX2741 1 180pF 50V 0603 NPO 5 Murata GRM1885C1H181JA01D ECJ 1VB1H822K MCRO3EZPFX4991 R9 A 316k 060831M0WA Rohm MCROGEZPFX 161 1 1 1 PG Part Reference pM R8 O Rev 10 0 International TOR Rectifier PD 97507 IR3843WMPbF TYPICAL OPERATING WAVEFORMS Vin 12 0V Vcc 5V Vo 1 8V lo 0 2A Room Temperature No Air Flow File Edit Vertical Horiz Acq Trig Display Cursors Measure Masks Math Utilities Help Tek Stopped 1 cqs Chi Position 3 0div Ch1 Scale 2 0V Enable i Ch1 2 04 Bw Ch2 500rnv Bw M 4 0mns 250kS s 4 ys pt Ch3 500m Bw Ch4 1 0V Bw A Ch3 1 34 Fig 17 Start up at 2A Load Ch V Ch5 V Ch4 V Ch Enable File Edit Vertical Horiz cq Ing Display Cursors Measte Utilities Help Tek Stopped 398 Acqs ek2. 28 26 Resistance mQ 24 22 20 40 20 0 20 40 60 80 100 120 140 Temperature C Ctrl FET Sync FET Rev 10 0 International PD 97507 TOR Rectitier IR3843WMPbF Typical Efficiency and Power Loss Curves Vin 12V Vcc 5V lo 0 2A 2A F 600kHz Room Temperature No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement O Qo OO R Efficiency oo N N Co N O 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 lout A QV 1V Vv 2V 1 5V 1 8V 2 5V 33V 5V 0 55 0 5 0 45 o R 0 35 0 25 Power Loss W W gt N 0 15 0 1 0 05 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 lout A 0 9V 1V 1 1V 1 2V 1 5V 1 8V 92 5V 33V 5V 10 Rev 10 0 International TOR Rectitier Typical Efficiency and Power Loss Curves PD 97507 IR3843WMPbF Vin 5V Vcc 5V lo 0 2A 2A F 600kHz Room Temperature No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement PCMBOGST 1R5MS PCMBOGST 1R5MS IHLP2525EZ 01 2 2uH IHLP2525EZ 01 3 3uH IHLP2525EZ 01 2 2uH Efficiency 96
3. Fig 4 Pre Bias startup Rev 10 0 PD 97507 IR3843WMPbF HORV Jl JL LL JL IL dL db JL LDRiss jl n un L 25 50 15 LDRV Ls esee leh des 82 16 l 8 o Fig 5 Pre Bias startup pulses Soft Start The IR3843W has a programmable soft start to control the output voltage rise and to limit the current surge at the start up To ensure correct start up the soft start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready POR signal The internal current source typically 20uA charges the external capacitor C linearly from OV to 3V Figure 6 shows the waveforms during the soft start The start up time can be estimated by _ 1 4 0 7 C start 204A During the soft start the OCP is enabled to protect the device for any short circuit and over current condition t3 t1 Q Fig 6 Theoretical operation waveforms during soft start International TOR Rectitier PD 97507 IR3843WMPbF Operating Frequency The switching frequency can be programmed between 250kHz 1500kHz by connecting an external resistor from R pin to Gnd Table 1 tabulates the oscillator frequency versus R Table 1 Switching Frequency and lpcset VS External Resistor R 294 11 5 121 7 Shutdown The IR3843W can be shutdown by pulling the Enable pin below its 1 V threshold This
4. its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows z e w 26 Fp m po warownia 27 Fp EXT T EIS 28 Re 2 71 lt o aaa acne 29 E QNT TLI oe M 30 Cross over frequency is expressed as F R 0 os 2 V ss 2n L C 7 Based on the frequency of the zero generated by the output capacitor and its ESR relative to crossover frequency the compensation type can be different The table below shows the compensation types and location of the crossover frequency Rev 10 0 Compensator Type Output Capacitor F sp VS F Electrolytic PEM Tantalum FLc lt FesR lt Fo lt F 2 Tantalum T Hl ype Ceramic FLc lt Fo lt FEsR The higher the crossover frequency the potentially faster the load transient response However the crossover frequency should be low enough to allow attenuation of switching noise Typically the control loop bandwidth or crossover frequency is selected such that F lt 1 5 1 10 F The DC gain should be large enough to provide high DC regulation accuracy The phase margin should be greater than 45 for overall stability For this design we have Vi 712V Vo71 8V V 7 1 8V OSC V 70 7V L 73 3 uH C 2x22uF ESR 3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value For instance t
5. 0 8 1 1 2 lout A 1 4 1 6 1 8 7V 0 75V 9V V V 12V 5V 8V 2 5V 3 3V 0 35 w gt N u N Power Loss W o 1 2 lout A 1 4 1 6 1 8 fy 0 75V 0 9V 1V 1 1V 1 2V 1 5V 1 8V 2 5V 3 3V Rev 10 0 11 International TOR Rectitier PD 97507 IR3843WMPbF Circuit Description THEORY OF OPERATION Introduction The IR3843W uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types The switching frequency is programmable from 250kHz to 1 5MHz and provides the capability of optimizing the design in terms of size and performance IR3843W provides precisely regulated output voltage programmed via two external resistors from 0 7V to 0 9 Vin The IR3843W operates with an external bias supply from 4 5V to 5 5V allowing an extended operating input voltage range from 1 5V to 16V The device utilizes the on resistance of the low side MOSFET as current sense element this method enhances the converter s efficiency and reduces cost by eliminating the need for external current sense resistor IR3843W includes two low Rasion MOSFETs using IRs HEXFET technology These are specifically designed for high efficiency applications Under
6. 2 00 xe Stencil Aperture Dimensions in mm 0 6834 xe 0 7194 1 1600 x4 33 International PD 97507 TOR Rectitier IR3843WMPbF 0 40 R 0 200 TYP 4X 0 775 BSC R 0 125 TYP 34X R 0 125 TYP 9X 0 650 BSC IL EANA AA o mI dL la BOTTOM VIEW UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILIMETERS DECIMAL ANGULAR X X t z XXX 0 10 X XXX 0 050 IR WORLD HEADQUARTERS 233 Kansas St El Segundo California 90245 USA Tel 310 252 7105 TAC Fax 310 252 7903 This product has been designed and qualified for the Consumer market Visit us at www irf com for sales contact information Data and specifications subject to change without notice 01 09 34 Rev 10 0
7. 3 0div Ch4 Scale 2 0V Ch2 S00mV Bw M 4 0rns 250kS s 4 0pszpt Ch3 500mv Bw A Ch3 2 34 Fig 22 Short Hiccup Recovery Ch4 V Ch4 Vss Rev 10 0 25 International PD 97507 TOR Rectitier IR3843WMPbF TYPICAL OPERATING WAVEFORMS Vin 12V Vcc 5V Vo 1 8V lo 1A 2A Room Temperature No Air Flow File Edit Vertical Horiz Acq Trig Display Cursors Measure Masks Math Utilities Help Tek Stopped 244 Acts Buttons J Pk PkiC1 80 0mV 44 Chi 50 0m Bw M 100ys 2 5MS s 400ns pt Ch4 1 04 Q By A Chg 2225 File Edit Vertical Horizjacq Trig Display Cursors Measure Masks Math Utilities Help File Edit Vertical Horiz Acq Trig Display Cursors Measure Masks Math Utilities Help Tek Stopped 0 SO pone Buttons Tek Stopped o 45A EIER ators Ch4 Position Ch4 Position 3 0div 3 0div GM Scale Ch4 Scale E 1 04 i 1 04 Yo i PAW 0 ptit aT YYYY NANA BAA YYYY WA i i ROSES REPEAT AOC CES LI epe ped t lo lo 4 Ay Ch1 50 0m Bw M 10 0us 25 0MS s 40 0ns pt Ch4 104 Q Bw A Ch4 s 2 224 j Ch1 50 0mV Bw M 10 0ps 25 0MS s 40 0ns pt Ch 1 08 Q By A Ch4 x 2 224 Fig 23 Transient Response 1A to 2A step 2 5A us Ch V Ch l Rev 10 0 d International PD 97507 TOR Rectifier IR3843WMPbF TYPICAL OPERATING WAVEFORMS Vin 12V Vcc 5V Vo 1 8V lo 2A Room Temperature No Air Flow Frequency 85 54 kH Magni
8. IR3843WMPbF Lead lands the 11 IC pins width should be equal to nominal part lead width The minimum lead to lead spacing should be 2 0 2mm to minimize shorting Lead land length should be equal to maximum part lead length 0 3 mm outboard extension The outboard extension ensures a large and inspectable toe fillet Pad lands the 4 big pads other than the 11 IC pins length and width should be equal to maximum part pad length and width However the minimum metal to metal spacing should be no less than 0 17mm for 2 oz Copper no less than 0 1mm for 1 oz Copper and no less than 0 23mm for 3 oz Copper A RANA x3 _ V S00 x3 2 2900 JI Sk X400 x11 pu EA e M E 2 A k 4 4 POS A x ja AE T ALL a s la LA Aur of d M Nee Lf of KS n pee i TRA USD x 7 I ox E EG ip poa ay KST AR aur YP AJ dul oda Gu uw es IN FA y m 4 35900 x X x m gt 0 3000 x11 AC Li L E Ai LO AU Dimensions in mm Component Rev 10 0 31 International PD 97507 IGR Rectifier IR3843WMPbF Solder Resist It is recommended that the lead lands are Non Solder Mask Defined NSMD The solder resist shoul
9. Output Capacitor F c Resonant Frequency of the Output Filter Rg Feedback Resistor To cancel one of the LC filter poles place the zero before the LC filter resonant frequency pole Use equations 20 21 and 22 to calculate C4 One more capacitor is sometimes added in parallel with C4 and R3 This introduces one more pole which is mainly used to suppress the switching noise The additional pole is given by IC ZEE 23 Ir R C CeoiE j C CpoLE The pole sets to one half of the switching frequency which results in the capacitor Cpo c 1 1 CpoLE NENEESEE o D aam 24 S For a general solution for unconditional stability for any type of output capacitors and a wide range of ESR values we should implement local feedback with a type Ill compensation network The typically used compensation network for voltage mode controller is shown in figure 15 Again the transfer function is given by V Ve _ js Z Vo Zin By replacing Z and Z according to figure 15 the transfer function can be expressed as 1 sR C 1 sC Rz Ry sR C C I sn Je SRC 4 V3 H s Rev 10 0 21 International TOR Rectitier PD 97507 IR3843WMPbF ak a SA 1 C3 i i C Io DOL ca Rio Raj Zf P NR ME L EH Fb J Ve Ro Comp d VREF Gain dB H s dB Fa Fe FR Fe Freauency Fig 15 Type Ill Compensation network and
10. PGood RE RF Simultaneous Powerup Fig 8b Application Circuit for Simultaneous Fig 8a Simultaneous Power up of the slave Sequencing with respect to the master Power Good Output Through these pins voltage sequencing such as simultaneous and sequential can be implemented Figure 8 shows simultaneous sequencing configurations In simultaneous power up the voltage at the Seq pin of the slave reaches 0 7V before the Fb pin of the master For Rg R R R therefore the output voltage of the slave follows that of the master until the voltage at the Seq pin of the slave reaches O 7 V After the voltage at the Seq pin of the slave exceeds 0 85V the internal 0 7V reference of the slave dictates its output voltage It is recommended that irrespective of the sequencing configuration used the input voltage should be allowed to come up to its nominal value first followed by V and Enable before the sequencing signal is applied For non sequenced operation the Seq pin should be tied to a voltage greater than 0 85V such as 3 3V or V Again the input voltage should be allowed to come up before V o and Enable C Rev 10 0 The IC continually monitors the output voltage via Feedback Fb pin The feedback voltage forms an input to a window comparator whose upper and lower thresholds are 0 805V and 0 595V respectively Hence the Power Good signal is flagged when the Fb pin voltage is within
11. Voltage Lockout and POR The under voltage lockout circuit monitors the input supply Vcc and the Enable input It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds Normal operation resumes once Vcc and Enable rise above their thresholds The POR Power On Ready signal is generated when all these signals reach the valid logic level see system block diagram When the POR is asserted the soft start sequence starts see soft start section Enable The Enable features another level of flexibility for start up The Enable has precise threshold which is internally monitored by Under Voltage Lockout UVLO circuit Therefore the IR3843W will turn on only when the voltage at the Enable pin exceeds this threshold typically 1 2V If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider it can be ensured that the IR3843W does not turn on until the bus voltage reaches the desired level Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold thus enabling the IR3843W Therefore in addition to being a logic input pin to enable the IR3843W the Enable feature with its precise threshold also allows the user to implement an Under Voltage Lockout for the bus voltage V This is desirable particularly for high output voltage applications where we might want the IR
12. efficiency and high output noise Generally the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor 4 The optimum point is usually found between 20 and 50 ripple of the output current For the buck converter the inductor value for the desired operating ripple current can be determined using the following relation Vin Vo La At Dx 3r 14 Vi Maximum input voltage V Output Voltage Ai Inductor ripple current F Switching frequency At Turn on time D Duty cycle If Ai 40 then the output inductor is calculated to be 3 19uH Select 23 3 pH The IHLP2525EZ 01 3 3uH from Vishay provides a compact low profile inductor suitable for this application Rev 10 0 International TOR Rectitier PD 97507 IR3843WMPbF Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values The criteria is normally based on the value of the Effective Series Resistance ESR However the actual capacitance value and the Equivalent Series Inductance ESL are other contributing components These components can be described as AV AVoesry AVo EsL AVo c AV FSR Al a ESR V V AV ost m 5 J Est Al Cm SERIE O S AV Output voltage ripple Al lnductor ripple current Since the output capacitor has a major role in the overall performance of the converter and determ
13. ini 0 001 dB Phas 55 509 deg Fig 24 Bode Plot at 2A load shows a bandwidth of 86kHz and phase margin of 56 degrees 27 Rev 10 0 International PD 97507 TOR Rectitier IR3843WMPbF Simultaneous Tracking at Power Up and Power Down Vin 12V Vo 1 8V lo 2A Room Temperature No Air Flow VouT IR3843W 4 99K Rs 4 99K Seq Fb 3 16K Ro 3 16K File Edit Vertical Horz cq Ing Display Cursors Measure Masks Math Utilities Help Tek Stopped Single Seg DA 0 o rm T Seq Ch4 Position 3 0div Ch4 Scale 500 0mY Ch2 500m Bw M 4 ms 125kS s 8 0usipt Ch3 500mV Bw Ch4 500mY Bw A Ch2 1 17 File Edit Vertical Horz cq Ing Display Cursors Measure Masks Math Utilities Help Tek Stopped 12 Acqs HMM MEME EE SS Ch4 Position i 0div Seq i Ch4 Scale i 500 0mV Ch2 S00mV Bw M 4 ms 125kS s 8 0ps pt Ch3 500rny By Ch4 S500mV Bw A Ch2 x 1 17V Fig 25 Simultaneous Tracking a 3 3V input at power up and shut down Ch2 Vout Ch3 SS Ch4 Seq Rev 10 0 5 International TOR Rectifier Layout Considerations The layout is very important when designing high frequency switching converters Layout will affect noise pickup and can cause a good design to perform with less than expected results Make all the connections for the power components in the top layer with wide copper filled areas or polygons In general it is desirable to make proper use of power plane
14. switching frequency with 250 ns off time Max Duty Cycle OTO 01000010 OI RES Max Duty Cycle OTO O 4 4 CO CO O 250 450 650 850 1050 1250 1450 1650 Switching Frequency kHz Fig 10 Maximum duty cycle v s switching frequency International TOR Rectitier PD 97507 IR3843WMPbF Application Information Design Example The following example is a typical application for IR3843W The application circuit is shown on page 23 V 12V 13 2V max V 1 8V l 72A AV lt 54mV F 600 kHz Enabling the IR3843W As explained earlier the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage IR3843W Enable V R SR EN 6 Vin min VEN For a Vi min 10 2V R 749 9K and R 7 5K is a good choice Programming the frequency For F 600 kHz select R 23 7 kQ using Table 1 Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider The Fb pin is the inverting input of the error amplifier which is internally referenced to 0 7V The divider is ratioed to provide 0 7V at the Fb pin when the output is at its desired value The output voltage is defined by using the following equation R ME 7 o el 7 9 when an external resistor divider is connected to the output as shown in figure 11 Equation 7 can b
15. the PGood window i e between 0 595V to 0 805V as shown in Fig 9 The PGood pin is open drain and it needs to be externally pulled high High state indicates that output is in regulation Fig 9a shows the PGood timing diagram for non tracking operation In this case during startup PGood goes high after the SS voltage reaches 2 1V if the Fb voltage is within the PGood comparator window Fig 9a and Fig 9 b also show a 256 cycle delay between the Fb voltage entering within the thresholds defined by the PGood window and PGood going high International PD 97507 IGR Rectitier IR3843WMPbF TIMING DIAGRAM OF PGOOD FUNCTION 0 805V 256 Fs 256 Fs Fig 9a IR3843W Non Tracking Operation Seq Vcc SS HIGH 0 Seq 0 805V MEM A po e Pgood window Fb NE 0 MEN EE NE PGood 0 lt gt i Fig 9b IR3843W Tracking Operation Rev 10 0 International TOR Rectitier Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on and this depends on the internal timing delays For the IR3843W the typical minimum on time is specified as 100 ns Any design or application using the IR3843W must ensure operation with a pulse width that is higher than this minimum on time and preferably higher than 150 ns This is necessary for the circuit to operate without jitter and pulse skipp
16. will tri state both the high side driver as well as the low side driver Alternatively the output can be shutdown by pulling the soft start pin below 0 3V Normal operation is resumed by cycling the voltage at the Soft Start pin Over Current Protection The over current protection is performed by sensing current through the Rps on of low side MOSFET This method enhances the converter s efficiency and reduces cost by eliminating a current sense resistor As shown in figure 7 an external resistor Rocs t is connected between OCSet pin and the switch node SW which sets the current limit set point An internal current source sources current locse out of the OCSet pin This current is a function of the switching frequency and hence of R Rev 10 0 Table 1 shows lpcs at different switching frequencies The internal current source develops a voltage across Rocs When the low side MOSFET is turned on the inductor current flows through the Q2 and results in a voltage at OCSet which is given by Vocset locset Rocset Rpgron fL 3 Vin Q1 SW Q2 Rocset PGnd Hiccup 7 Control a OCSet D locse FS Vec Fig 7 Connection of over current sensing resistor An over current is detected if the OCSet pin goes below ground Hence at the current limit threshold Vocsei 0 Then for a current limit setting mip Roc
17. 3843W to be disabled at least until V exceeds the desired output voltage level Bus Voltage 12V __ Vin 10 2V Vcc 5V Enable Enable Threshold 1 2V _ d EE Fig 3a Normal Start up Device turns on when the Bus voltage reaches 10 2V Figure 3b shows the recommended start up sequence for the non sequenced operation of IR3843W Bus Voltage 12V Seq Vcc 5V Fig 3b Recommended startup sequence Non Sequenced operation Figure 3c shows the recommended startup sequence for sequenced operation of IR3843W Rev 10 0 12 International TOR Rectitier Bus Voltage 12V Vec 5V Enable gt 1 2 V SS Seq gt 0 85V Fig 3c Recommended startup sequence Sequenced operation Pre Bias Startup IR3843W is able to start up into pre charged output which prevents oscillation and disturbances of the output voltage The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated Figure 4 shows a typical Pre Bias condition at start up The synchronous MOSFET always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25 50 75 and 100 until it reaches the steady state value The number of these startup pulses for the synchronous MOSFET is internally programmed Figure 5 shows a series of 32 16 8 startup pulses V Vo Pre Bias Voltage Time
18. International PD 97507 TOR Rectifier IR3843WMPbF Sup RBuck HIGHLY EFFICIENT INTEGRATED 2A SYNCHRONOUS BUCK REGULATOR Description The IR3843W Sup RBuck is an easy to use fully integrated and highly efficient DC DC synchronous Buck regulator The MOSFETs co packaged with the on chip PWM controller make Features e Wide Input Voltage Range 1 5V to 16V e Wide Output Voltage Range 0 7V to 0 9 Vin e Continuous 2A Load Capability e Integrated Bootstrap diode e High Bandwidth E A for excellent transient performance IR3843W a space efficient solution providing e Programmable Switching Frequency up to 1 5MHz accurate power delivery for low output voltage Programmable Over Current Protection applications e PGood output e Hiccup Current Limit e Precision Reference Voltage 0 7V 1 e Programmable Soft Start e Enable Input with Voltage Monitoring Capability e Enhanced Pre Bias Start up e Seq input for Tracking applications e 409C to 125 C operating junction temperature It also features important protection functions e Thermal Protection such as Pre Bias startup hiccup current limit and Multiple current ratings in pin compatible footprint thermal shutdown to give required system level omm x 6mm Power QFN Package 0 9 mm height security in the event of fault conditions e Lead free halogen free and RoHS compliant IR3843W is a versatile regulator which offers programmability of start up time switching fr
19. Set the switching frequency Connect an external resistor from this pin 5 Rt a to Gnd to set the switching frequency Soft start shutdown This pin provides user programmable soft start function Connect an external capacitor from this pin to Gnd to set the start up time of the output voltage The converter can be shutdown by pulling this pin below 0 3V Power Good status pin Output is open drain Connect a pull up resistor from this pin to Vcc If unused it can be left open This pin powers the internal IC and the drivers A minimum of 1uF high frequency SU W must be connected from this pin to the power Power Ground This pin serves as a separated ground for the MOSFET drivers and should be connected to the system s power ground plane Switch node This pin is connected to the output inductor Input voltage connection pin connected from this pin to SW Enable pin to turn on and off the device Use two external resistors to 14 Enable set the turn on threshold see Enable section Connect this pin to Vcc if it is not used Signal ground for internal reference and control circuitry 1 OO UJ O O Rev 10 0 International PD 97507 Rectifier IR3843WMP bF Recommended Operating Conditions input Voltage Supply Voltage Vve Output Voltage i oup Cure 8 2 l Fs Switching Frequency _ 228 1650 kHz LT junction Temperature 40 125 Boot to S
20. W Supply Voltage Electrical Specifications Unless otherwise specified these specification apply over 4 5V lt V_ lt 5 5V V 12V 09C lt T lt 1259C Typical values are specified at T 25 C Power Loss Power Loss P oss Vccz5V Vin 12V Vo 1 8V l522A 0 394 W Fs 600kHz L 3 3uH Note4 MOSFET Ras on 5 mQ Reference Voltage Supply Current Vec Supply Current Dyn Icc Dyn SS 3V Vcc 5V Fs 500kHz 10 mA Enable high Under Voltage Lockout Vcc Start Threshold Vcc UVLO Start Vcc Rising Trip Level BINNEN VocStop Threshold Threshold Vcc UVLO Vos UVLO Stop Vcc Vcc Falling Trip Level Trip Level 365 65 385 85 Start Threshold d UVLO Start build ramping up V Enable Stop Threshold Enable UVLO Stop Supply ramping down a Rev 10 0 International PD 97507 IGR Rectitier IR3843WMPbF Electrical Specifications continued Unless otherwise specified these specifications apply over 4 5V lt V lt 5 5V V 12V 09C T 125 C Typical values are specified at T 25 C Parameter Symbol Test Condition Min TYP MAX Units Oscillator Frequency Fs 225 250 275 450 500 550 kHz mo j Min Pulse Width Dmin ctrl Notet 100 Error Amplifier Input Offset Voltage Vos Vfb Vseq 10 0 10 mV Vseq 0 8V Input Bias Current IFb E A 1 Input Bias Current IVp E A 1 Sink Current Isink E A 0 85 1 2 Source Current Isource E A ey 10 13 m Slew Rate 7 12 20 V us G
21. ain Bandwidth Product 20 30 40 MHz Fs 500kHz 43 48 8 54 6 uA Fs 1500kHz 136 154 172 OC Comp Offset Voltage VGFESET Note4 SEE 81 10 mV SS off time SS_Hiccup 4096 Cycles Over Current Protection OCSET Current Fs 250kHz Maximum Voltage Vmax E A Vcc 4 5V 3 5 3 75 V Minimum Voltage Vmin E A 120 220 mV Soft Start SD Soft Start Current ISS Source 14 20 26 pA Soft Start Clamp Voltage Vss clamp 3 0 3 3 Shutdown Output Threshold SD d P gt Bootstrap Diode Forward Voltage I Boot 30mA 470 mV Deadband Rev 10 0 International PD 97507 Rectifier IR3843WMPbF Electrical Specifications continued Unless otherwise specified these specification apply over 4 5V lt V_ lt 5 5V V 12V 0 C lt T lt 125 C Typical values are specified at T 25 C aram SY Test Gonaiion 77 Wim T TYP o MAX T Unis Thermal Shutdown Thermal Shutdown Note4 140 C Power Good mue mmm e Lm aaa m Threshold Delay Threshold Delay Threshold Hysteresis SW Bias Current SW OV Enable 0V TT Isw SW oV Enable hians8 Bxvseg 0V Note4 Note3 Cold temperature performance is guaranteed via correlation using statistical quality control Not tested in production Note4 Guaranteed by Design but not tested in production Rev 10 0 International TOR Rectifier PD 97507 IR3843WMPbF TYPICAL OPERATING CHARACTERISTICS 40 C 125 C F 500 kHz Icc Sta
22. d be pulled away from the metal lead lands by a minimum of 0 025mm to ensure NSMD pads The land pad should be Solder Mask Defined SMD with a minimum overlap of the solder resist onto the copper of 0 05mm to accommodate solder resist mis alignment Ensure that the solder resist in between the lead lands and the pad land is 2 0 15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land 4 3500 a 1 3500 18 50 ri 4 50 M i O 580 pm 1 1500 8 50 1 0500 a 3x3 05898 x11 Oe KAA PT TSZT ZA ES i i 34500 35530 8500 xe 1 i I i 1 29500 x2 4 3000 x2 E 2 95 4 x 26520 x8 2 3000 x11 04000 x11 2 2500 X R L I YF R ARATYR K JJ TF 4 9500 x11 0 8500 x11 N CEREREM a All Dimensions in mm NOTE a 11x Signal Pins are NSMD PCB Copper 4x Power Pins are SMD FLB Solaer Resist XZ PA p Rev 10 0 ue International TOR Rectifier Stencil Design PD 97507 IR3843WMPbF The Stencil apertures for the lead lands should be approximately 80 of the area o
23. e rewritten as For the calculated values of R8 and R9 see feedback compensation section VouT IR3843W Fb Fig 11 Typical application of the IR3843W for programming the output voltage Soft Start Programming The soft start timing can be programmed by selecting the soft start capacitance value From 1 for a desired start up time of the converter the soft start capacitor can be calculated by using Css HF Ton ms x0 02857 9 Where T is the desired start up time ms For a start up time of 3 5ms the soft start capacitor will be 0 099uF Choose a 0 1uF ceramic capacitor Bootstrap Capacitor Selection To drive the Control FET it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin which is connected the source of the Control FET This is achieved by using a bootstrap configuration which comprises the internal bootstrap diode and an external bootstrap capacitor C6 as shown in Fig 12 The operation of the circuit is as follows When the lower MOSFET is turned on the capacitor node connected to SW is pulled down to ground The capacitor charges towards V through the internal bootstrap diode which has a forward voltage drop Vp The voltage V across the bootstrap capacitor C6 is approximately given as When the upper MOSFET turns on in the next cycle the capacitor node connected to SW rises to the bus voltage V However if the value of C6 is a
24. ed 8V Note2 Vcc must not exceed 7 5V for Junction Temperature between 10 C and 40 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied PACKAGE INFORMATION 5mm x 6mm POWER QFN 6 35C W 0 7 22C W J PCB ORDERING INFORMATION Seq FB COMP Gnd Rt SS OCSet PACKAGE PACKAGE PIN PARTS PER DESIGNATOR DESCRIPTION COUNT REEL Rev 10 0 International PD 97507 TOR Rectitier IR3843WMPbF Block Diagram Vec EJ Boot Thermal Shutdown Vin Vcc Enable Driver Digital Pulse H PGood Generation Pre Bias Fig 2 Simplified block diagram of the IR3843W Rev 10 0 International PD 97507 Rectifier IR3843WMP bF Pin Description Pin Name Description Sequence pin Use two external resistors to set Simultaneous Power up UNE A T d UEM Inverting em to the error amplifier This pin is connected directly to the 2 Fb output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier Output of error amplifier An external resistor and capacitor network is typically connected from this pin to Fb pin to provide loop compensation e Signal ground for internal reference and control circuitry
25. equency and current limit while operating in wide input and output voltage range The switching frequency is programmable from 250kHz to 1 5MHz for an optimum solution Applications e Server Applications e Netcom Applications e Storage Applications e Computing Peripheral Voltage Regulators e Embedded Telecom Systems e General DC DC Converters e Distributed Point of Load Power Architectures 1 5V lt Vin lt 16V i 4 5V Vcc 5 5V Enable PGood Fig 1 Typical application diagram Rev 10 0 International PD 97507 IGR Rectitier IR3843WMPbF ABSOLUTE MAXIMUM RATINGS Voltages referenced to GND unless otherwise specified JE acs ee etre eee n 0 3V to 25V A C Ap 0 3V to 8V Note2 e BOOL rr 0 3V to 33V OM EE E E E T E OWE 0 3V to 25V DC 4V to 25V AC 100ns BOOI OSII waste ZSEE WA 0 3V to Vcc 0 3V Note7 E S ccm 0 3V to 30V 30mA e Input output PINS zzananaaaaaaaaaassaaaaaaaan aaa 0 3V to Vcc 0 3V Note1 PGND TO GND eese rincon ton bar Vi Eau cnec beris re li in 0 3V to 0 3V e Storage Temperature Range 55 C To 150 C e Junction Temperature Range 40 C To 150 C Note2 e ESD Classification uaaaaa aaa aaa nawa sees JEDEC Class 1C e Moisture sensitivity level sseeeuesssuesesse JEDEC Level 3 260 C Note1 Must not exce
26. f the lead lads Reducing the amount of solder deposited will minimize the occurrences of lead shorts If too much solder is deposited on the center pad the part will float and the lead lands will be open The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0 2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste 014 0 92600 x2 UCAJJ x4 xc nd xe 24585 xe 0 2850 x3 0 45255 xe Q 3800 x8 j Q6200 x4 0 5600 x4 mE 0 6950 x3 ro 04250 x4 0 3500 x3 0 3500 x3 n 5000 E L r 0 4950 x4 i 0 2900 p 0 3673 i i 0 5625 12200 x2 EN den 2 0550 x2 d Ea gt 48950 x4 1 0156 0 6190 L 4 i gt c 0 2230 x2 A ASSAT XE 4 PA PN 7 3 P f 00040 x1 dc 00 x 11 R QLSOxLI M Al Rev 10 0 rm Q
27. he small signal capacitance of the 22uF capacitor used in this design is 12uF at 1 8 V DC bias and 600 kHz frequency It is this value that must be used for all computations related to the compensation The small signal value may be obtained from the manufacturers datasheets design tools or SPICE models Alternatively they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency F and using equation 16 to compute the small signal o These result to F c 17 88 kHz F s 4 4 MHz F 2 300 kHz Select crossover frequency F 80 kHz Since F g lt F lt F 2 lt Fes p Typelll is selected to place the pole and zeros 22 International TOR Rectitier Detailed calculation of compensation Typelll Desired Phase Margin 70 1 sin 1 sin psp qna 1 sin Select F 0 5 F 7 05 kHz and E F 14 11 kHz Fo 0 5 F 300 kHz Select C 2 2 nF Calculate R C and C _22 F L C V R sc R 2 71 kQ C i Vn Select R 2 74 kQ 4 c C 8 24 nF Select C 28 2 nF 27 Fa Ra 1 C 193 62 pF Select C 180 pF 2a fa p i Calculate R R and R I E R 160 Q Select R 2158 Q 22 C Ep 1 PR R 5 kQ OR 7 Select K 4 99 kQ VAL RR 3 18 kQ Select R 3 16 kQ o ref R Rev 10 0 PD 97507 IR3843WMPbF Programming the Current Limit The Curre
28. ines the result of transient response selection of the capacitor is critical The IR3843W can perform well with all types of capacitors As a rule the capacitor must have low enough ESR to meet output ripple and load transient requirements The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size Two of the Panasonic ECJ 2FB0J226ML 22uF 6 3V 3mOhm capacitors is a good choice Feedback Compensation The IR3843W is a voltage mode controller The control loop is a single voltage feedback path including error amplifier and error comparator To achieve fast transient response and accurate output regulation a compensation circuit is necessary he goal of the compensation network is to provide a closed loop transfer function with the highest 0 dB crossing frequency and adequate phase margin greater than 45 The output LC filter introduces a double pole 40dB decade gain slope above its corner resonant frequency and a total phase lag of 180 see figure 13 The resonant frequency of the LC filter is expressed as follows Figure 13 shows gain and phase of the LC filter Since we already have 180 phase shift from the output filter alone the system runs the risk of being unstable Gain Phase 0 dB Qo 40dB decade 1800 Fic Frequency Fic Frequency Fig 13 Gain a
29. ing which can cause high inductor current ripple and high output voltage ripple Vout V x F S In any application that uses the IR3843W the following condition must be satisfied t on min ton t o Vout on min V F V rs Vin X F lt UE t on min The minimum output voltage is limited by the reference voltage and hence V j 0 7 V Therefore for V ye 0 7 V out min out min 0 7 V X lt XF lt 4 67 x 10 V s 150 ns Therefore at the maximum recommended input voltage 16V and minimum output voltage the converter should be designed at a switching frequency that does not exceed 290 kHz However practical considerations dictate that any application that demands a pulse width smaller than 175ns may not exhibit jitter free operation over the entire load range This means that for 16 V input voltage the operation frequency should be limited to 250 kHz Rev 10 0 PD 97507 IR3843WMPbF Maximum Duty Ratio Considerations A fixed off time of 200 ns maximum is specified for the IR3843W This provides an upper limit on the operating duty ratio at any given switching frequency It is clear that higher the switching frequency the lower is the maximum duty ratio at which the IR3843W can operate To allow a margin of 50ns the maximum operating duty ratio in any application using the IR3843W should still accommodate about 250 ns off time Fig 10 shows a plot of the maximum duty ratio v s the
30. nd Phase of LC filter The IR3843W uses a voltage type error amplifier with high gain 110dB and wide bandwidth The output of the amplifier is available for DC gain control and AC phase compensation The error amplifier can be compensated either in type II or type III compensation Local feedback with Type Il compensation is shown in Fig 14 This method requires that the output capacitor should have enough ESR to satisfy stability requirements In general the output capacitor s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin The ESR zero of the output capacitor is expressed as follows Boo Lo Son n osa Rev 10 0 20 International TOR Rectitier PD 97507 IR3843WMPbF MER Grove Ca VREF H s dB Frequency Fig 14 Type ll compensation network and its asymptotic gain plot The transfer function V V is given by Ne gy RI a 18 Vo Zin SRC The s indicates that the transfer function varies as a function of frequency This configuration introduces a gain and zero expressed by R gt E c 19 A IR 19 1 r a 20 27 R C 20 First select the desired zero crossover frequency Fo F gt Fesp andF x 1 5 1 10 F Use the following equation to calculate R3 F F R a 21 Vin Fic Where Vi Maximum Input Voltage Vs Oscillator Ramp Voltage F Crossover Frequency Feop Zero Frequency of the
31. ndby 290 270 250 T230 210 190 170 150 E M MH gt gt 40 20 0 20 40 60 80 100 120 Temp C FREQUENCY kHz R R R R R u 01 u u c1 u c1 O N oo e N wW R u V V e o o o o o o o 40 20 0 20 40 60 80 100 120 Temp C Vcc UVLO Start Temp C Enable UVLO Start 1 36 1 34 1 32 1 30 1 28 5 1 26 1 24 1 22 1 20 1 18 1 16 1 14 __ __ 40 20 0 20 40 60 80 100 120 Temp C ISS 26 0 24 0 22 0 20 0 18 0 16 0 14 0 40 20 0 20 40 60 80 100 120 Temp C Rev 10 0 mA Ic Dyn 9 5 R y _ T 40 20 0 20 40 60 80 100 120 Temp C IOCSET 500kHz Temp C Vcc UVLO Stop Temp C Enable UVLO Stop Temp C Vfb 706 701 ae 696 691 686 40 20 0 20 40 60 80 100 120 Templ C International PD 97507 TOR Rectitier IR3843WMPbF Rdson of MOSFETs Over Temperature at Vcc 5V Note Ctrl FET and Sync FET are identical 36 34 32 30
32. nt Limit threshold can be set by connecting a resistor Rocsgr from the SW pin to the OCSet pin The resistor can be calculated by using equation 4 This resistor Rogge must be placed close to the IC The Rpsfon has a positive temperature coefficient and it should be considered for the worst case operation Rocset locset IsEr 7l critica SZ Rpston Rpgon 24 5 mO 1 25 30 625 mO Iser larm 5 2A 1 5 3A 50 over nominal output current locg t 99 07 HA at F 600kHz Rocset 1 55 kQ Select R 21 54 kQ Setting the Power Good Threshold A window comparator internally sets a lower Power Good threshold at 0 6V and an upper Power Good threshold at 0 8V When the voltage at the FB pin is within the window set by these thresholds PGood is asserted The PGood is an open drain output Hence it is necessary to use a pull up resistor Rpa from PGood pin to Vcc The value of the pull up resistor must be chosen such as to limit the current flowing into the PGood pin when the output voltage is not in regulation to less than 5 mA A typical value used is 10 kO 23 International PD 97507 TOR Rectitier IR3843WMPbF Application Diagram Vin 12 V C 1 X 10 uF E 330 uF 1x0 1uF R4 49 9 K Je 4 5 V Vcc b 5V E 75K NZ Enable c6 0 1 uF Vo bi T 3 3uH R7 C7 T IR3843W 154K Rg F 22nF T 4 99 K Seq 158 a E Co 2X22uF R9 C4 R3 3 16 K 8 2 nF 2 74K EG
33. ppropriately chosen Rev 10 0 18 International TOR Rectitier PD 97507 IR3843WMPbF the voltage Vc across C6 remains approximately unchanged and the voltage at the Boot pin becomes VBoor Vin Veg V E 11 IR3843W Fig 12 Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0 1uF is suitable for most applications Input Capacitor Selection The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor The RMS value of this ripple is expressed by loys l 4 D D 12 Where D is the Duty Cycle lpys is the RMS value of the input capacitor current lo is the output current For 2A and D 0 15 the 5 5 0 71 A Ceramic capacitors are recommended due to their peak current capabilities They also feature low ESR and ESL at higher frequency which enables better efficiency For this application it is advisable to have 1x10uF 25V ceramic capacitor C3216X5R1E106M from TDK In addition to these although not mandatory a 1X330uF 25V SMD capacitor EEV FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter Inductor Selection The inductor is selected based on output power operating frequency and efficiency requirements A low inductor value causes large ripple current resulting in the smaller size faster response to a load transient but poor
34. s and polygons for power distribution and heat dissipation The inductor output capacitors and the IR3843W should be as close to each other as possible This helps to reduce the EMI radiated by the power traces due to the high switching currents through them Place the input capacitor directly at the Vin pin of IR3843W The feedback part of the system should be kept away from the inductor and other noise sources The critical bypass components such as capacitors for Vcc should be close to their respective pins lt is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins Compensation parts should be placed as close as possible to the Comp pin Resistors Rt and Rocset should be placed as close as possible to their pins International i ION Ree It ier Mm MEM T m pins BSE g PD 97507 IR3843WMPbF The connection between the OCSet resistor and the Sw pin should not share any trace with the connection between the bootstrap capacitor and the Sw pin Instead it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap capacitor at the Sw pin In a multilayer PCB use one layer as a power ground plane and have a control circuit ground analog ground to which all signals are referenced The goal is to localize the high current path to a separate loop that does not interfere with the more
35. sensitive analog control function These two grounds must be connected together on the PC board layout at a single point The Power QFN is a thermally enhanced package Based on thermal performance it is recommended to use at least a 4 layers PCB To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias Figure 26 illustrates the implementation of the layout guidelines outlined above on the IRDC3843W 4 layer demoboard Enough copper amp minimum length ground path between Input and Output All bypass caps should be placed as close as possible to their connecting wn DPT Fig 26a IRDC3843W demoboard layout considerations Top Layer Rev 10 0 29 International PD 97507 TOR Rectitier IR3843WMPbF Feedback trace should be kept away form noise sources Fig 26b IRDC3843W demoboard layout considerations Bottom Layer Analog Ground plane Power Ground Single point Plane connection between AGND amp PGND should be close to the SuplRBuck kept away from noise sources Fig 26c IRDC3843W demoboard layout considerations Mid Layer 1 Use separate traces for connecting Boot cap and Rocset to the switch node and with the minimum length traces Avoid big loops Fig 26d IRDC3843W demoboard layout considerations Mid Layer 2 Rev 10 0 i International TOR Rectitier PCB Metal and Components Placement PD 97507
36. set is calculated as follows R R DS on Limit OCSet p OCSet An overcurrent detection trips the OCP comparator latches OCP signal and cycles the soft start function in hiccup mode The hiccup is performed by shorting the soft start capacitor to ground and counting the number of switching cycles The Soft Start pin is held low until 4096 cycles have been completed The OCP signal resets and the converter recovers After every soft start cycle the converter stays in this mode until the overload or short circuit is removed The OCP circuit starts sampling current typically 160 ns after the low gate drive rises to about 3V This delay functions to filter out switching noise International TOR Rectitier PD 97507 IR3843WMPbF Thermal Shutdown Temperature sensing is provided inside IR3843W The trip threshold is typically set to 140 C When trip threshold is exceeded thermal shutdown turns off both MOSFETs and discharges the soft start capacitor 1 5V lt Vin lt 16V 4 5V lt Vcc lt 5 5V Vo master PGood Automatic restart is initiated when the sensed temperature drops within the operating range There is a 20 C hysteresis in the thermal shutdown threshold Output Voltage Sequencing The IR8843W can accommodate user programmable sequencing using Seq Enable and Power Good pins 1 5V lt Vin lt 16V LI 4 5V Vcc 5 5V Vo master Vo slave
37. stopped 1 198 ACI 4 Sg SISA J SLAS AI SKJAL Buttons ia Ch3 Position 3 0div Ch3 Scale 500 0mV i Ch2 500rnv Bw M 4 0rns 250kS s 4 Dusit Ch3 500mv Bw A Ch3 2 34 Fig 19 Start up with 1 62V Pre Bias OA Load Ch V Ch4 Vss File Edit Vertical Horz Acq Ing Display Cursors Measure Masks Math Utilities Help Tek Stopped 56704 Acqs Ch2 Position 2 04 div Ch2 Scale 5 0V Freq C2 612 7kHz Ch2 50V M 400ns 1 25GS s 8D ps pt A Ch2 6 6 Fig 21 Inductor node at 2A load Ch LX File Edit Vertical Horz cq Trig Display Cursors Measure Masks Math Utilities Help Tek Stopped 0 Acgs ek topped EE ZAWIE E Buttons Ch4 Position 8 0div Ch4 Scale 2 0V i Chi 20V Bw Ch2 50Orny Bw M 4 0rns 250kS s 4 Ops pt Ch3 500m Bw Ch4 20 Bw A Ch3 1 34 Fig 18 Start up at 2A Load Ch V Ch5 V Ch4 V Cy Ve goog In SS File Edit Vertical Horiz 4cq Trig Display Cursors Measure Masks Math Utilities Help Tek Stopped 503831 Acqs gi EP wy EM 90 You DE ee ee MEM Buttons Ch2 Position 60 0mdiy Ch2 Scale 20 0mY Pk Pk D2 17 6rnY Eril Ch2 200mY 4 Bw M A 1 0us SOOMS s 2 0nsipt Ch2 400pY Fig 20 Output Voltage Ripple 2A load Ch V File Edit Vertical Horz Acq Trig Display Cursors Measure Masks Math Utilities Help Tek Stopped 1 cqs Ch4 Position
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INTERNATIONAL RECTIFIER IR3843WMPbF Manual