FTDI Vinculum VNC1L Embedded USB Host Controller I.C.
Contents
1. FaorrHHO FT SSS ESZEH FERS oO 2xo0oo0gyugUoo2nqg Eaunt tuta x aaa g ecm Figure 2 48 pin LQFP Package Pin Out ADBUSO ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 USB1DM USB1DP USB2DM USB2DP ACBUSO ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 BDBUSO BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUSO BCBUS1 BCBUS2 BCBUS3 Figure 3 VNC1L Pin Out Schematic Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 6 2 2 48 Lead LQFP Package Signal Descriptions Table 1 Pin Out Description Pin No Name Type Description USB Interface Group Power and Ground Group e ew ewm Device analog ground supply for itear oock mupe OoOo O y 17 30 40 vccio 3 3V supply to the ADBUS ACBUS BDBUS and BCBUS Interface pins 11 16 18 23 31 38 41 48 Miscellaneous Signal Group 4 XTIN Input Input to 12MHz Oscillator Cell Connect 12 MHz crystal across pins 4 and 5 with suitable loading capacitors to GND This pin can also be driven by an external 12 MHz clock signal Note that the switching threshold of this pin is VCC 2 so if driving from an external source the source must be driving at DV CMOS2. 373 Scotland Street Glasgow G5 8QB United Kingdom Tel 44 141 429 2777 Fax 44 141 429 2758 E Mail Sales vinculum sales ftdichip com E Mail Support vinculum support1 ftdichip com E Mail General Enquiries admin1 ftdichip com Regional Sales Offices Future Technology Devices International Ltd Taiwan 4F No 18 3 Sec 6 Mincyuan East Road Neihu District Taipei 114 Taiwan R o C Tel 886 2 8791 3570 Fax 886 2 8791 3576 E Mail Sales tw sales1 ftdichip com E Mail Support tw support ftdichip com E Mail General Enquiries tw admin ftdichip com FTDI Company website URL http www ftdichip com Future Technology Devices International Ltd USA 7235 NW Evergreen Parkway Suite 600 Hillsboro OR 97124 5803 USA Tel 1 503 547 0988 Fax 1 503 547 0987 E Mail Sales us sales ftdichip com E Mail Support us support ftdichip com E Mail General Enquiries us admin ftdichip com Vinculum dedicated product website URL http www vinculum com Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007
3. DC Characteristics DC Characteristics Ambient Temperature 0 C to 70 C Table 14 Operating Voltage and Current Parameter E Max Units Conditions CT HC RN Mer VocI peri siov ee 38 ea 3 v ks eemesemiem Teacher bear oreste E Lm em Table 15 UART and CBUS I O Pin Characteristics Parameter E wem Units Table 16 RESET and PROG Pin Characteristics Parameter leans Units Conditions Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 15 Table 17 USB I O Pin USBDP USBDM Characteristics Parameter dicil SEH Max Units Conditions UVDif Differential Input Sensitivity o Driver Output Impedance includes the external USB series resistors on USBDP and USBDM pins Table 18 XTIN XTOUT Pin Characteristics Parameter Description Units Conditions EE EE em EE 54 Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 16 5 Device Ce 5 1 Example VNC1L Schematic MCU UART interface 5V Ferrite Bead 100nF 3v3 100nF Bn Vcc 31 TXD USBA Connector GND 33 RTS 47pF 47pF V GND GND USB1DM 19 04 U09019 1 USB1DP USB2DM USB2DP ACBUSO 10pF ACBUS1 ACBUS2 ACBUS3 40pF ACBUS4 ACBUS5 3V3 ACBUS6 ACBUS7 BDBUSO BDBUS1 l 47k 47k l 47k BDBU
4. level or a c coupled to centre around VCC 2 5 XTOUT Output Output from 12MHz Oscillator Cell Connect 12 MHz crystal across pins 4 and 5 with suitable loading capacitors to GND XTOUT stops oscillating during USB suspend so take care using this signal to clock external logic PLLFLTR External PLL filter circuit input RC filter circuit must be fitted on this pin is TEST Puts the device into I C test mode Must be tied to GND for normal operation RESET Input Can be used by an external device to reset the VNC1L This pin can be used in combination with PROG and the UART interface to program firmware into the VNC1L If not required pull up to VCC via a 10 kO resistor PROG This pin is used in combination with the RESET pin and the UART interface to program firmware into the VNC1L Data and Control Bus Signals Interface Mode UART Inter Parallel FIFO SPI Slave UO Port face Interface Interface m BDBUSO wo 5V sate bidrecional data ewe goo __ Pon0_ hz sosusr wo svsate wicrecional data convolbus B001 __ Pons 3 sosusz vo sae wicrecional RRE F4 sosuss uo svsate wicrecional data ER __ Pena Hs soeuss wo V sate bidrectonldata convotbus eDot __ Ponta he sosuss vo 6v sae wicrecional data eonvorbus bers __ Pons ha sosuss uo sate wicrecional data convolbus B00 Pons he sosusr wo 5 sae vicrecional RER s oeuso uo sae bidir
5. of the USB Physical layer including bit suffing unstuffing CRC generation checking USB frame generation and error checking 12 MHz Oscillator The 12MHz Oscillator cell generates a 12MHz reference clock input to the Clock Multiplier PLL from an exteral 12MHz crystal Clock Multiplier PLL The Clock Multiplier PLL takes the 12MHz input from the Oscillator Cell and generates 24MHz and 48MHz reference clock signals which is used by the USB SIE Blocks the MCU core System Timer and UART Prescaler blocks Program and Test Logic this block provides a means of programming the onboard E Flash memory When PROG is pulled low and the device is reset the onboard E Flash memory is bypassed by an internal hard coded BootStrap Loader ROM which contains code to allow the E Flash memory to be programmed via commands to the UART interface FTDI provides a software utility which allows the VNC1L to be programmed using this method The TEST pin is used in manufacturing to enhance the testability of the various internal blocks and should be tied to GND DMA Controller 1 and 2 The twin DMA controllers in the VNC1L greatly enhance performance by allowing data from the two USB SIE controllers UART FIFO and SPI to be transferred between each other via the data SRAM with minimal MCU intervention Data SRAM This 4k x 8bit block acts as the data variable memory for the Vinculum MCU though it can also be accessed transparently to the MCU by the twin DM
6. A controllers NPU Numeric CoProcessor Most Vinclum MCU operations are 8 bit however there are some scenarios such as transversing disk FAT tables which involve extensive 32 bit arithmetic In order to speed up these operations the MCU has a dedicated 32 bit co processor block UART Prescaler this block provides the master transmit receive clock for the UART block By varying the prescalar value the baud rate of the UART can be adjusted over a range of 300 baud to 1M baud SYSTEM TIMER The system timer provides a regular interrupt to the Vinculum MCU typically at 1mS intervals This is used by the MCU to provide timeouts and other timing functions VINCULUM MCU CORE The heart of the VNC1L is the VMCU core based on FTDI s proprietary 8 bit embedded MCU EMCU architectiure VMCU has a Harvard architecture i e separate code and data space and supports 64k byes of program code 64k byes of paged data space and 256 bytes of IO space It uses enhanced CISC technology typically VNCU instructions would replace several lines of code in conventional CISC or RISC processors giving RISC like performance in a CISC architecture with the advantage over both of excellent code compression in the program ROM space E FLASH Program ROM The VNCL1L has 64k bytes of embedded Flash E Flash memory No special programming voltages are necessary for programming the onboard E FLASH as these are provided internally on chip Commo
7. ILTER RESET USB Host Slave Transceiver 1 USB Host Slave Transceiver 2 12 MHz Oscillator Clock Multiplier PLL Program and Test Logic USB Host Slave SIE 1 USB Host Slave SIE2 SYSTEM INT TIMER DMA Controller HE 1 UART PRESCALER INT DMA Controller Vinculum MCU 24 MHz 2 an 48 MHz 4k x8 DATA SRAM PROGRAM ROM Vinculum PEU 32 Bit NPU ROM INTERNAL IO BUS INTERNAL IO BUS UART amp FIFO I F LOGIC E ADBUS O 7 SPI I F LOGIC ACBUSUI0 7 GPIO 0 I F LOGIC GPIO 1 BDBUS 0 7 I F LOGIC AE GPIO 2 I F LOGIC BCBUSQO 3 s Figure 1 Simplified Block Diagram GPIO 3 I F LOGIC EXTERNAL IO BUS Future Technology Devices Intl Ltd 2006 2007 Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Page 4 2 2 Functional Block Descriptions USB Host Slave Transceivers 1 and 2 The two USB transceiver cells provide the USB host slave physical USB 1 1 USB 2 0 full speed device interface On each the output drivers provide 3 3V level slew rate control signalling whilst a differential receiver and two single ended receivers provide USB data in SEO and USB Reset condition detection These cells also incorporate internal USB pull up or pull down resistors as required for host or slave mode USB Host Slave Serial Interface Engine SIE These blocks handle the parallel to serial and serial to parallel conversion
8. M FTDI Future Technology Chip Devices International Ltd TM V VINCULUM BINDING USB TECHNOLOGIES Vinculum VNC1L Embedded USB Host Controller LC The Vinculum VNC1L is the first of FTDI s Vinculum family of Embedded USB host controller integrated circuit devices Not only is it able to handle the USB Host Interface and data transfer functions but owing to the inbuilt MCU and embedded Flash memory Vinculum can encapsulate the USB device classes as well When interfacing to mass storage devices such as USB Flash drives Vinculum also transparently handles the FAT File structure communicating via UART SPI or parallel FIFO interfaces via a simple to implement command set Vinculum provides a new cost effective solution for providing USB Host capability into products that previously did not have the hardware resources available The VNC1L is available in Pb free ROHS compliant compact 48 Lead LQFP package http www vinculum com Copyright Future Technology Devices International Ltd 2006 Page 2 BENE 40 1 1 Hardware Features Single chip embedded USB host slave controller LC device Entire USB protocol handled on the chip 8 32 bit V MCU Core Twin DMA controllers for hardware acceleration Integrated 12 MHz to 48 MHz clock multiplier Integrated power on reset circuit with optional RESET input pin 64k byte embedded Flash ROM program memory 4k byte internal data SRAM Standard USB firmware libr
9. NC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 8 Figure 4 FIFO Read Cycle RXF RD D 7 0 Valid Data Table 6 FIFO Read Cycle Timings Time Description Min 0 S Load 30pF Figure 5 FIFO Write Cycle TXE WR D 7 0 Valid Data Table 7 FIFO Write Cycle Timings Time Description Min WR Active Pulse Width WR to RD Pre Charge Time Data Hold Time from WR Inactive WR Inactive to TXE TXE Inactive After WR Cycle 50 50 20 5 Data Setup Time before WR Inactive 20 Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 9 2 5 SPI Interface Signal Descriptions and Timing Diagrams Table 8 Data and Control Bus Signal Mode Options SPI Interface W I Type Description SCLK SPI Clock input 12MHz maximum SPI Serial Data Input Output SPI Serial Data Output SPI Chip Select Input Figure 6 SPI Slave Data Read Cycle R W ADD D7 D6 D5 D4 D3 D2 D1 ud nnnm ve y Hou SPI Data In An AF SPI Data Out QO000Q000 START STATUS From Start SPI CS must be held high for the entire read cycle and must be taken low for at least one clock period after the read is completed The first bit on SPI Data In is the R W bit inputting a 1 here allows data to be read from the chip The next bit is the address bit ADD which
10. S2 v3 PLLFLTR BDBUS3 BDBUS4 Venn BDBUS5 1nF BDBUS6 GND BDBUS7 10nF TEST BCBUSO BCBUS1 BCBUS2 BCBUS3 N LED1 LED2 Q O O V GND Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Disclaimer Page 17 Copyright Future Technology Devices International Limited 2006 Version 0 90 Initial Datasheet Created July 2006 Version 0 95 Datasheet Update September 2006 Version 0 96 Datasheet Update March 2007 Neither the whole nor any part of the information contained in or the product described in this manual may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder This product and its documentation are supplied on an as is basis and no warranty as to their suitability for any particular purpose is either made or implied Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product Your statutory rights are not affected This product or any variant of it is not intended for use in any medical appliance device or system in which the failure of the product might reasonably be expected to result in personal injury This document provides preliminary information that may be subject to change without notice Contact FTDI Head Office Future Technology Devices International Ltd
11. address bit MSB first After the data has been clocked in to the chip the status of SPI Data Out should be checked to see if the data read was accepted A 0 level on SPI Data Out means that the data write was accepted A 1 indicates that the internal buffer is full and the write should be repeated Remember that CS must be held low for at least one clock period before being taken high again to continue with the next read or write cycle Figure 8 SPI Slave Data Timing Diagrams SPICLK v SPICS m T4 T5 SPI DATA OUT Table 9 SPI Slave Data Timing Description Min Typical Max Unit SPICLK Period SPICLK High SPICLK Low Input Hold Tlme Output Hold Time Output Valid Time LL m E 0 LL m JinputSetuptime de LL ds po LL le Erst CNN c PR E E ER Table 10 Status Register ADD 1 Description RXF IRQEn TXE IRQEn Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 11 2 6 PS 2 Keyboard and Mouse Interface Table 11 Data and Control Bus Signal Mode Options PS 2 Keyboard and Mouse Interface Pin No W I Type Description 1 Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 12 3 Package Par 3 1 LQFP 48 Dimensions The VNC1L is supplied in a 48 pin LQFP package as standard 12 AL 19 4 ga E 0 09 wid M
12. ary supplied by FTDI Program or update firmware via USB Flash disk or UART interface Firmware easily upgradable in the field PROG firmware programming control pin Two independent USB 2 0 Low speed Full speed USB Host Slave ports with integrated pull up and pull down resistors Four fully configurable data I O and control Buses UART interface mode for data I O firmware programming and command monitor interface FIFO interface mode with 8 bit bi directional data bus and simple 4 wire handshake for data I O and command monitor interface 1 2 Standard Firmware Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 SPI slave interface mode for data I O and command monitor interface Up to 28 GPIO interface pins for data I O and command monitor interface Interface to MCU PLD FPGA via UART FIFO or SPI interface Legacy PS 2 keyboard and mouse interfaces Multi processor configuration capable Support for USB suspend and resume Support for bus powered self powered and high power bus powered USB device configurations 3 3V operation with 5V safe inputs Low operating and USB suspend current 25mA running 2mA stnadby Fully compliant with USB 2 0 specification USB full speed 12 Mbps and low speed 1 5 Mbps USB host and slave device compatible 0 C to 70 C operating temperature range Full driver support for target slave applications Available in compact Pb free and green 48 Pin LQFP package RoHS c
13. d 2 3 UART Interface Signal Descriptions Table 4 Data and Control Bus Signal Mode Options UART Interface Pin No W I Type Description Output Transmit asynchronous data output Receive asynchronous data input Ring Indicator Control Input When the Remote Wake up option is enabled in the EEPROM taking RI low can be used to resume the PC USB Host controller from suspend 41 TXDEN Output Enable Transmit Data for RS485 designs e o ce jco co jo c o SINIJA TSON 2 4 Parallel FIFO Interface Signal Descriptions and Timing Diagrams Table 5 Data and Control Bus Signal Mode Options Parallel FIFO Interface Pin No WETE Type Description pm vo FIFO Data Bus Bit 0 FIFO Data Bus Bit 1 FIFO Data Bus Bit 2 FIFO Data Bus Bit 3 FIFO Data Bus Bit 4 FIFO Data Bus Bit 5 FIFO Data Bus Bit 6 wlll jojo NIOJ STGoit UO OUTPUT When high do not read data from the FIFO When low there is data available in the FIFO which can be read by strobing RD low then high again 42 TXE OUTPUT When high do not write data into the FIFO When low data can be written into the FIFO by strobing WR high then low 43 WR INPUT Enables the current FIFO data byte on DO D7 when low Fetched the next FIFO data byte if avail able from the receive FIFO buffer when RD goes from high to low INPUT Writes the data byte on the DO D7 pins into the transmit FIFO buffer when WR goes from high to low 38 41 Vinculum V
14. ecional data Toonai bus Aoro mx o fsc PoraDo s aosusa uo svsate bcreconal aata eonvolbus aDbt4 prec ba Ponaba 2s ADBUSS uo 6v safe bidirecional data Teona bus AD bts osre os Pons ar peus uo svsate bicrecional aata Teona bus Aie ocos pe Porabs s ADBUST wo 5vsate bidirectional aata convolbus ADbt7 RW or Poor am cmuso uo 5 sate bidirecional data convolbus AC bt DENA xs Poraco Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 7 Table 1 continued Pin Out Description AcBus1 1 0 5V safe bidirectional data control bus AC bit1 Iren Portct Lio safe bdrecional data contol bus Acta w __ io 6V safe bsrecional data erre acta JO O O Lio svsatebirectonardata reonorus acts __ io safe brecional data contol bus acts O 48 ACBUS7 I O 5V safe bidirectional data control bus AC bit 7 PortAC7 To use a 12 MHz crystal with the VNC1L fit a 47 KQ pull down resistor Alternatively fitting a 47 KQ pull up resistor on this pin will switch off the inter nal clock multiplier allowing the device to be fed with an external 48Mz clock signal into XTIN These pins are pulled to VCC via internal 200kO resistors PS 2 Ports can be available while UART FIFO or SPI interface is enable
15. in 0 2 Ma 16 Max 1 60 MAX 1 4 0 05 0 22 0 05 0 2 Mi 0 6 0 15 Figure 9 LQFP 48 Package Dimensions The VNC1L is supplied in a RoHS compliant 48 pin LQFP package The package is lead Pb free and uses a green compound The package is fully compliant with European Union directive 2002 95 EC This package has a 7 00mm x 7 00 mm body 9 00 mm x 9 00 mm including pins The pins are on a 0 50 mm pitch The above mechanical drawing shows the LQFP 48 package all dimensions are in millimetres The date code format is YYWW where WW 2 digit week number YY 2 digit year number An alternative 6mm x 6mm leadless QFN package is also available for projects where PCB area is critical Contact FTDI for availabillity Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 13 3 2 Solder Reflow Profile The VNC1L is supplied in Pb free 48 LD LQFP package The recommended solder reflow profile is shown in below i Critical Zone when Ramp Up D lt gt T is in the range T to T EZ ts Preheat Temperature T Degrees C 25 T 25 C to Tp Time t seconds Figure 10 VNC1L Solder Reflow Profile The recommended values for the solder reflow profile are detailed in Table 4 Values are shown for both a completely Pb free solder process i e the VNC1L is used with Pb free solder and for a non Pb free
16. is used to indicate whether the data register 0 or the status register 1 is read from During the SPI read cycle a byte of data will start being output on SPI Data Out on the next clock cycle after the address bit MSB first After the data has been clocked out of the chip the status of SPI Data Out should be checked to see if the data read is new data A 0 level here on SPI Data Out means that the data read is new data A 1 indicates that the data read is old data and the read cycle should be repeated to get new data Remember that CS must be held low for at least one clock period before being taken high again to continue with the next read or write cycle Figure 7 SPI Slave Data Write Cycle R W ADD D7 D6 D5 D4 D3 D2 D1 WAS d SPI Data In SPI Data Out KE T z 0o z From Start SPI CS must be held high for the entire write cycle and must be taken low for at least one clock period after the write is completed The first bit on SPI Data In is the R W bit inputting a 0 here allows data to be written to the chip The next bit is the address bit ADD which is used to indicate whether the data register 0 or the status Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 10 register 1 is written to During the SPI write cycle a byte of data can be input to SPI Data In on the next clock cycle after the
17. n methods of programming the E FLASH both under control of the VMCU are via the UART by pulling the PROG pin low and resetting the device OR by using the programming via a USB FLASH drive feature provided in many of the VNC1L firmware packages BOOTSTRAP LOADER ROM This is a small block of hard encoded ROM 512 x 8 bits whivh bypasses the main e FLASH memory when PROG is pulled low This provides a means of programming the entire E Flash memory via the UART interface UART and FIFO Logic These provide optional serial and parallel interfaces to the VNC1L equivalent to the interfaces on FTDI s FT232 and FT245 USB UART and FIFO products GPIO Blocks general purpose IO pins See the tables below to determine which are available for any specific configuration Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 5 2 Device Pin Out and Signal Deseriptions 2 1 48 Lead LQFP Pin Out iD st Go GN e O amp O BHABHD GEG zn 222222988 maopmmmmmrodgumuomsmsgu qgaqggaAanaAnAoHHZH OA 4444445520252 4 36 25 ADBUS6 37 24 GND ADBUS7 BCBUS3 GND FIDI BCBUS2 VCCIO BCBUS1 ACBUSO KXXXXX BCBUSO ACBUS1 BDBUS7 ACBUS2 XXXXXXXXX BDBUS6 ACBUS3 VCCIO ACBUSA VNC1 L 1 A BDBUS5 ACBUS5 BDBUS4 ACBUS6 YYWW BDBUS3 ACBUS7 48 13 BDBUS2
18. ompliant Full range of reference designs and evaluation kits available USB slave device and USB Flash disk interface with selectable UART FIFO SPI interface or USB slave device as the command monitor port VDIF firmware FTDI USB slave device and USB Flash disk interface with selectable UART FIFO SPI interface as the command monitor port VDAP firmware USB Flash disk to USB Flash disk with GPIO command monitor interface VDFC firmware FTDI USB slave device and USB Flash disk interface with selectable UART FIFO SPI interface as the command monitor port with audio playback command extensions VMSC firmware 1 3 Typical Applications Add USB host capability to embedded products Interface USB Flash drive to MCU PLD FPGA USB Flash drive to USB Flash drive file transfer interface Digital camera to USB Flash drive or other USB slave device interface PDA to USB Flash driver or other USB slave device interface MP3 Player to USB Flash drive or other USB slave device interface USB MP3 Player to USB MP3 Player Mobile phone to USB Flash drive or other USB slave device interface GPS to mobile phone interface Instrumentation USB Flash drive or other USB slave device interfacing Datalogger USB Flash drive or other USB slave device interface Set Top Box USB device interface Future Technology Devices Intl Ltd 2006 2007 Page 3 2 1 Simplified Block Diagram USB1DP USB1DM USB2DP USB2DM PLL F
19. solder process i e the VNCAL is used with non Pb free solder Table 12 Reflow Profile Parameter Values Profile Feature Pb Free Solder Process Non Pb Free Solder Process Average Ramp Up Rate T to T 3 C second Max 3 C Second Max Preheat Temperature Min T Min 150 C 100 C Temperature Max T Max 200 C 150 C Time t Min to t Max 60 to 180 seconds 60 to 120 seconds Time Maintained Above Critical Temperature T Temperature T 217 C 183 C Time t 60 to 150 seconds 60 to 150 seconds Vinculum VNC1L Embedded USB Host Controller I C Datasheet Version 0 96 Future Technology Devices Intl Ltd 2006 2007 Page 14 4 Device Characteristics and Ratings 4 1 Absolute Maximum Ratings The absolute maximum ratings for the VNC1L devices are as follows These are in accordance with the Absolute Maximum Rating System IEC 60134 Exceeding these may cause permanent damage to the device Table 13 Absolute Maximum Ratings Parameter VELTE Unit Storage Temperature 65 C to 150 C Floor Life Out of Bag At Factory Ambient 168 Hours Hours 30 C 60 Relative Humidity IPC JEDEC J STD 033A MSL Level 3 Compliant Dote ous hbo o o m DC Output Currant Ltb ho o fm If devices are stored out of the packaging beyond this time limit the devices should be baked before use The devices should be ramped up to a temperature of 125 C and baked for up to 17 hours 4 2
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