MICROCHIP MCP6S21/2/6/8 Manual
Contents
1. E Measurement BW 80 kHz Measurement BW 80 kHz Vout 2 Vout 4 Vp p Von 5 0 V 5 0 V 0 1 0 1 2 2 2 G 16 TT 0 01 0 01 G 4 G 1 G 0 001 0 001 1k 10k 100k 100 1k 10k 100k Frequency Hz Frequency Hz FIGURE 2 25 THD plus Noise vs FIGURE 2 28 THD plus Noise vs Frequency Vour 2 Vp p Frequency Vour 4 Vp p 5 0 29 Von 5 0V 4 5 DD 5 5 _ 40 5 gt a J e ae LE D 55 os as a2 gt gt gt O 25 Eg s GV 5 gt M 52 5 20 ot 2T ry NO 8 G G 1 8 1 5 G 5 5 5 1 0 G 32 5 G 32 05 0 0 Time 200 ns div Time 500 ns div FIGURE 2 26 Small Signal Pulse FIGURE 2 29 Large Signal Pulse Response Response 0 65 1 6 0 60 dere ha a Ma 14 5 o c Vout b2. FIGURE 2 3 Ladder Resistance Drift 18 2 16 420 Samples G 1 14 LT 40 to 125 C o JU 8 12 10 HHH 8 6 Mra s 4 HH 9 2 E NN M D d 0 KAKA N p e ps N e e e e e e e e e e e e e e e e e e e e e e e e e e o DC Gain Drift C FIGURE 2 4 DC Gain Drift 1 24 22 420 Samples T 5 20 amp 102 2 18 Ta 40 to 125 C 8 16 H 14 H H 12 HHH o 10 H H H D 8 E E 6 4 UHUHHH 2 4 HHHHHHH 0 e RE N N N N e e e o o o o o o DC Gain Drift C FIGURE 2 5 DC Gain Drift G 2 2 20 490 360 Samples 18 40V 5 16 G 1 E 14 HH 8 12 H H H 10 H HH o 8 H HHH 5 6 HHHHH 5 4 HH HHHH o 5 2 HHH HHH A amp om SB M 8 Input Offset Voltage uV FIGURE 2 6 Input Offset Voltage Vop 4 0V 2003 Microchip Technology Inc DS21117A page 9 MCP6S21 2 6 8 Not
3. 16 Lead PDIP 300 mil MCP6S28 Example 1 1 1 n 1 1 1 1 1 1 1 1 1 XXXXXXXXXXXXXX MCP6828 I P D XXXXXXXXXXXXXX 5 YYWWNNN 0345256 LT LT LT LT LT LT LT LT LT LT LT LT LT LT 16 Lead SOIC 150 mil MCP6S28 Example XXXXXXXXXXXXX MCP6S28 1 SL XXXXXXXXXXXXX A 0345256 DS21117A page 30 2003 Microchip Technology Inc MCP6321 2 6 8 8 Lead Plastic Dual In line P 300 mil PDIP E1 i D d 2 41 1 Y A A1 st eB Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch 100 2 54 Top to Seating Plane A 140 155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane A1 015 0 38 Shoulder to Shoulder Width E 300 313 325 7 62 7 94 8 26 Molded Package Width E1 240 250 260 6 10 6 35 6 60 Overall Length D 360 373 385 9 14
4. si EE RENE f for Device 2 for Device 2 for Device 1 for Device 1 20 0000000000000 first 16 bits out always zeros gt lt Instruction Byte Data Byte for Device 2 for Device 2 FIGURE 5 5 Serial bus sequence for daisy chain configuration SPI 1 1 mode 2003 Microchip Technology Inc DS21117A page 23 MCP6S21 2 6 8 5 4 Power On Reset If the power supply voltage goes below the POR trip voltage Vpp lt Vpog 1 7V the internal POR circuit will reset all of the internal registers to their power up defaults this is a protection against low power supply voltages The POR circuit also holds the part in shut down mode while it is activated It temporarily overrides the software shutdown status The POR releases the shutdown circuitry once it is released Vpp gt Vpog A 0 1 uF bypass capacitor mounted as close as possi ble to the Vpp pin provides additional transient immunity DS21117A page 24 2003 Microchip Technology Inc MCP6S21 2 6 8 6 0 APPLICATIONS INFORMATION 6 1 Changing External Reference Voltage Figure 6 1 shows a MCP6S21 with the VREF pin at 2 5V and Vpp 5 0V This allows the PGA to amplify signals centered on 2 5V instead of ground referenced signals The voltage reference MCP1525 is buffered
5. cs 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK s m x X X X X X X X X x X XXX x Instruction Byte Data Byte SO first 16 bits out are always zeros FIGURE 5 1 Serial bus sequence for the PGA SPI 0 0 mode see Figure 1 5 55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK s fm X X X X X X X X X X x x xXx ess 4 Instruction Byte Data Byte SO first 16 bits out are always zeros FIGURE 5 2 Serial bus sequence for the PGA SPI 1 1 mode see Figure 1 6 DS21117A page 18 2003 Microchip Technology Inc MCP6S21 2 6 8 5 2 Registers The analog functions are programmed through the SPI interface using 16 bit words see Figure 5 1 and Figure 5 2 This data is sent to two of three 8 bit regis ters Instruction Register Register 5 1 Gain Register Register 5 2 and Channel Register Register 5 3 The power up defaults for these three registers are Instruction Register 000x Gain Register x000 Channel Register xxxx x000 Thus these devices are initially programmed with the Instruction Register set for NOP no operation a gain of 1 V V and CHO as the input channel 5 2 1 INSTRUCTION REGISTER The Instruction Register has 3 command bits and 1 indirect address bit see Register 5 1 The command bits include a NOP 000 to support daisy chaining see Section 5 3 Registers the other NOP commands sho
6. 3 1 Analog Output The output pin is a low impedance voltage source The selected gain G selected input CHO CH7 and voltage at VREF determine its value 3 2 Analog Inputs CHO thru CH7 The inputs CHO through CH7 connect to the signal sources They are high impedance CMOS inputs with low bias currents The internal MUX selects which one is amplified to the output 3 3 External Reference Voltage Vref The pin should be at a voltage between Vgs and Vpp the MCP6S22 has Vggr tied internally to Vss The voltage at this pin shifts the output voltage 3 4 Power Supply Vss and Vpp The positive power supply pin Vpp is 2 5V to 5 5V higher than the negative power supply pin Vas For normal operation the other pins are between and Typically these parts are used in a single positive supply configuration In this case Vss is connected to ground and Vpp is connected to the supply Vpp will need a local bypass capacitor 0 1 UF at the Vpp pin It can share a bulk capacitor with nearby analog parts typically 2 2 uF to 10 uF within 4 inches 100 mm of the Vpp pin 3 5 Digital Inputs The SPI interface inputs are Chip Select CS Serial Input SI and Serial Clock SCK These are Schmitt triggered CMOS logic inputs 3 6 Digital Output The MCP6S26 and MCP6S28 devices have SPI interface serial output SO pin This is a CMOS push pull output and does not ever go Hig
7. Temperature 1 000 ECHO Vpp 5 5 V t 100 5 o S a 10 3 2 1 55 65 75 85 95 105 115 125 Ambient Temperature C FIGURE 2 14 Input Bias Current vs Ambient Temperature 100 N G 1 d G 4 G 16 5 104 x 5 X H a EL 1 10 100 1000 Capacitive Load pF FIGURE 2 15 Load Bandwidth vs Capacitive 100 Input Referred 90 5 5 V c 2 SN 5 80 2 5 c o 55 70 amp 7 50 o a 40 10 100 1k 10k 100k Frequency Hz FIGURE 2 16 PSRR vs Frequency 10 000 EVpp 5 5 V T 1 000 J 5 Ta 125 C 5 100 S E m 85 5 10 7 7 1 0 0 0 5 10 1 5 2 0 25 30 35 4 0 45 5 0 5 5 Input Voltage V FIGURE 2 17 Input Bias Current vs Input Voltage 7 6 G 1 4 5 5 G 1
8. CHO 0 3V G CH1 to CH7 0 3V 10 to Vpp 2 and C 60 pF 22 18 G 1 16 20 4 420 Samples 14 12 10 8 6 4 2 Percentage of Occurrences 0 0 040 0 036 0 032 0 028 0 024 0 020 0 016 0 012 0 008 77 0 004 1 0 000 DC Gain Error 0 004 FIGURE 2 1 DC Gain Error G 1 18 16 TG gt 2 420 14 12 10 8 6 4 2 Percentage of Occurrences 0 9 Eo NL ADN o DC Gain Error FIGURE 2 2 DC Gain Error G 2 2 22 20 420 Samples 40 to 125 C 18 16 14 12 10 8 6 4 2 Percentage of Occurrences 0 0 023 0 024 Ladder Resistance Drift C
9. 44 118 921 5820 02 12 03 DS21117A page 42 2003 Microchip Technology Inc
10. Configuration Sensors 0 6 MCP6S28 Vout Sensors 7 14 MCP6S28 FIGURE 6 8 PGA with Expanded Inputs 6 4 6 MCU WITH EXPANDED INPUT CAPABILITY Figure 6 9 shows an 6528 driving an analog input to a microcontroller This greatly expands the input capacity of the microcontroller while adding the ability to select the appropriate gain for each source PICmicro Vin O MCP6S28 Microcontroller SPI FIGURE 6 9 Expanded Input for a Microcontroller 6 4 7 ADC DRIVER The family of PGA s is well suited for driving Analog to Digital Converters ADC The binary gains 1 2 4 8 16 and 32 effectively add five more bits to the input range see Figure 6 10 This works well for applica tions needing relative accuracy more than absolute accuracy e g power monitoring Lowpass Filter 12 Vin 6528 MCP3201 OUT FIGURE 6 10 PGA as an ADC Driver At low gains the ADC s Signal to Noise Ratio SNR will dominate since the PGAs input noise voltage den sity is so low 10 nV Hz 10 kHz typ At high gains the noise will dominate the SNR but its low noise supports most applications Again these PGAs add the flexibility of selecting the best gain for an application The low pass filter in the block diagram reduces the in
11. Lead Thickness 004 006 008 0 09 0 15 0 20 Lead Width B1 007 010 012 0 19 0 25 0 30 Mold Draft Angle Top 0 5 10 0 5 10 Mold Draft Angle Bottom 0 5 10 0 5 10 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 005 0 127mm per side JEDEC Equivalent MO 153 Drawing No C04 087 DS21117A page 36 2003 Microchip Technology Inc MCP6321 2 6 8 16 Lead Plastic Dual In line P 300 mil PDIP I 4 E 1 m 3 i D 02 no H H A2 I p past gt 1 B1 p Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch 100 2 54 Top to Seating Plane A 140 155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane A1 015 0 38 Shoulder to Shoulder Width E 300 313 325 7 62 7 94 8 26 Molded Package Width E1 240 250 260 6 10 6 35 6 60 Overall Length D 740 750 760 18 80 19 05 19 30 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Le
12. SPI 1 1 mode DS21117A page 6 2003 Microchip Technology Inc MCP6321 2 6 8 1 1 DC Output Voltage Specs Model 1 1 1 IDEAL MODEL The ideal PGA output voltage Vour is EQUATION Vo ideal GV iw Veer Vss OV where G is the nominal gain see Figure 1 7 This equation holds when there are no gain or offset errors and when the VREF pin is tied to a low impedance source lt lt 0 1Q at ground potential Vss OV 1 1 2 LINEAR MODEL The PGA s linear region of operation including offset and gain errors is modeled by the line Vo linear Shown in Figure 1 7 i EQUATION gg Vj 0 3V Vos 03V SO os 0V Vo linear VREF The endpoints of this line are at Vo ideal 0 3V and Vpp 0 3V The gain and offset specifications referred to in the electrical specifications are related to Figure 1 7 as follows EQUATION V V gg 100 I GV pp 0 6V V yos eee G 1 05 1 AG AT A Vin V 03 9 3 G G FIGURE 1 7 Output Voltage Model with the standard condition Vper Vss OV 1 1 3 OUTPUT NON LINEARITY Figure 1 8 shows the Integral Non Linearity INL of the output voltage EQUATION INL Vour Vo linear The output non linearity specification in the electrical specifications is related to Figure 1 8 by EQUATION _ max V 4 V3 Yoni Vpp 0
13. Separate circuit functions digital from analog low speed from high speed and low power from high power as this will reduce crosstalk Keep sensitive traces short and straight separating them from interfering components and traces This is especially important for high frequency low rise time signals Use a 0 1 uF supply bypass capacitor within 0 1 inch 2 5 mm of the Vpp pin It must connect directly to the ground plane A multi layer ceramic chip capacitor or high frequency equivalent works best 6 3 2 SIGNAL COUPLING The input pins of the MCP6S21 2 6 8 family of opera tional amplifiers op amps are high impedance This makes them especially susceptible to capacitively cou pled noise Using a ground plane helps reduce this problem When noise is capacitively coupled the ground plane provides additional shunt capacitance to ground When noise is magnetically coupled the ground plane reduces the mutual inductance between traces Increasing the separation between traces makes a significant difference Changing the direction of one of the traces can also reduce magnetic coupling It may help to locate guard traces next to the victim trace They should be on both sides of the victim trace and be as close as possible Connect the guard traces to the ground plane at both ends and in the middle of long traces 6 3 3 HIGH FREQUENCY ISSUES Because the MCP6S21 2 6 8 PGAs reach unity gain near 64 MHz when G 16 and 32 i
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15. 9 46 9 78 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness 008 012 015 0 20 0 29 0 38 Upper Lead Width Bi 045 058 070 1 14 1 46 1 78 Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No C04 018 2003 Microchip Technology Inc DS21117A page 31 MCP6S21 2 6 8 8 Lead Plastic Small Outline SN Narrow 150 mil SOIC A2 gt j Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p 050 1 27 Overall Height A 053 061 069 1 35 1 55 1 75 Molded Package Thickness A2 052 056 061 1 32 1 42 1 55 Standoff 8 A1 004 007 010 0 10 0 18 0 25 Overall Width E 228 237 244 5 79 6 02 6 20 Molded Package Width E1 146 154 157 3 71 3 91 3 99 Overall Length D 189 193 197 4 80 4 90 5 00 Chamfer Dis
16. Foot Angle 0 4 8 0 4 8 Lead Thickness 008 009 010 0 20 0 23 0 25 Lead Width B 014 017 020 0 36 0 42 051 Mold Draft Angle Top 0 12 15 0 12 15 Mold Draft Angle Bottom 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 012 Drawing No C04 065 2003 Microchip Technology Inc DS21117A page 35 MCP6S21 2 6 8 14 Lead Plastic Thin Shrink Small Outline ST 4 4 mm TSSOP ET b D CE n 1 B i 1 Wa i AS Jj 2 2 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch 026 0 65 Overall Height A 043 1 10 Molded Package Thickness A2 033 035 037 0 85 0 90 0 95 Standoff 8 002 004 006 0 05 0 10 0 15 Overall Width E 246 251 256 6 25 6 38 6 50 Molded Package Width 1 169 173 177 4 30 4 40 4 50 Molded Package Length D 193 197 201 4 90 5 00 5 10 Foot Length L 020 024 028 0 50 0 60 0 70 Foot Angle 0 4 8 0 4 8
17. Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No C04 005 DS21117A page 34 2003 Microchip Technology Inc m E1 E 14 Lead Plastic Small Outline SL Narrow 150 mil SOIC MCP6321 2 6 8 i P D 2 B n 1 1 h 45 d S3 Meg A1 B Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch 050 1 27 Overall Height A 053 061 069 1 35 1 55 1 75 Molded Package Thickness A2 052 056 061 1 32 1 42 1 55 Standoff 8 A1 004 007 010 0 10 0 18 0 25 Overall Width E 228 236 244 5 79 5 99 6 20 Molded Package Width E1 150 154 157 3 81 3 90 3 99 Overall Length D T 342 347 8 56 8 69 8 81 Chamfer Distance h 010 015 020 0 25 0 38 0 51 Foot Length L 016 033 050 0 41 0 84 1 27
18. by a MCP6021 which gives a low output impedance ref erence voltage from DC to high frequencies The source driving the VREF pin should have an output impedance of lt 0 10 to maintain reasonable gain accuracy Vpp MCP1525 2 5V ae Dr FIGURE 6 1 Reference Voltage PGA with Different External 6 2 Capacitive Load and Stability Large capacitive loads can cause both stability prob lems and reduced bandwidth for the MCP6S21 2 6 8 family of PGAs Figure 2 17 and Figure 2 18 This happens because a large load capacitance decreases the internal amplifier s phase margin and bandwidth If the PGA drives a large capacitive load the circuit in Figure 6 2 can be used A small series resistor Riso at the improves the phase margin by making the load resistive at high frequencies It will not however improve the bandwidth FIGURE 6 2 Capacitive Loads PGA Circuit for Large For C gt 100 pF a good estimate for Rigo is 500 This value can be fine tuned on the bench Adjust Riso so that the step response overshoot and frequency response peaking are acceptable at all gains 6 3 Layout Considerations Good PC board layout techniques will help achieve the performance shown in the Electrical Characteristics and Typical Performance Curves It will also help minimize EMC Electro Magnetic Compatibility issues 6 3 1 COMPONENT PLACEMENT
19. can operate to 0 3V past either supply rail The input offset voltage is measured at both Vss 0 3V and 0 3V to ensure proper operation The transition between the two input stages occurs when Vin 7 Vpp 1 5V For the best distortion and gain linearity avoid this region of operation 4 2 3 RAIL TO RAIL OUTPUT The Maximum Output Voltage Swing is the maximum swing possible under a particular output load Accord ing to the specification table the output can reach within 60 mV of either supply rail when R 10 and Vngr Vpp 2 See Figure 2 21 for typical performance under other conditions 4 2 4 INPUT VOLTAGE AND PHASE REVERSAL The amplifier family is designed with CMOS input devices It is designed to not exhibit phase inversion when the input pins exceed the supply voltages Figure 2 34 shows an input voltage exceeding both supplies with no resulting phase inversion The maximum voltage that can be applied to the input pins is Vss 0 3V to Vpp 0 3V Voltages on the inputs that exceed this absolute maximum rating can cause excessive current to flow in or out of the input pins Current beyond 2 mA can cause possible reli ability problems Applications that exceed this rating must be externally limited with an input resistor as shown in Figure 4 2 CHX Vin O O Vour Maximum expected Ep 2 mA Minimum expected Ane 2mA FIGURE 4 2 Ry
20. gt 0 55 gt 1 2 CHO 0 3V G 5 D o 0 6V 6 1 CS g cs 5 0 50 55 5 10 o 5 Ld 5 gt 0 45 gt 0 8 0 040 4 o 06 Vout i E 03 2 6 2 0 35 0 4 o 0 30 0 2 0 25 0 0 Time 500 ns div Time 500 ns div FIGURE 2 27 Channel Select Timing FIGURE 2 30 Gain Select Timing 2003 Microchip Technology Inc DS21117A page 13 MCP6S21 2 6 8 Note Unless otherwise indicated Ta 25 C 5 0V Vss GND Vger Vss G 1 Input 0 3V G to CH7 0 3V R 10 to Vpp 2 and C 60 pF 1 0 r 1 10 Shutdown Shutdown err gt C Vp 55 E S uo E Vp 2 5 V E 08 ts CS 5 2 9 1 YA 5 05 S 5 0 4 o gt g 0 3 2 5 1 2 E t x 4 0 10 0 2 o 5 G 16 32 Vour is ON 0 1 C
21. limits the current flow into an input pin 4 3 Resistor Ladder The resistor ladder shown in Figure 4 1 Ap RE sets the gain Placing the gain switches in series with the inverting input reduces the parasitic capaci tance distortion and gain mismatch RLapis an additional load on the output of the PGA and causes additional current draw from the supplies In Shutdown mode Ap is still attached to the OUT and Vggr pins Thus these pins and the internal ampli fier s inverting input are all connected through Ap and the output is not high Z unlike the external op amp While Ap contributes to the output noise its effect is small Refer to Figure 2 12 4 4 Shutdown Mode These PGAs use a software shutdown command When the SPI interface sends a shutdown command the internal op amp is shut down and its output placed in a high Z state The resistive ladder is always connected between Vggr and Vour even in shutdown This means that the output resistance will be on the order of 5 kQ and there will be a path for output signals to appear at the input The Power on Reset POR circuitry will temporarily place the part in shutdown when activated See Section 5 4 Power On Reset for details 2003 Microchip Technology Inc DS21117A page 17 MCP6S21 2 6 8 5 0 DIGITAL FUNCTIONS The 521 2 6 8 PGAs use a standard SPI com patible serial interface to receive instructions from a con
22. through suggestion only and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any intellectual property rights DNV MSC The Netherlands DNV Certification Inc Accredited by the RvA ANSI RAB QMS 7 DNY ISO 9001 QS 9000 REGISTERED FIRM gt a A 9 m m The Microchip name and logo the Microchip logo KEELOQ MPLAB PIC PlCmicro PICSTART PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U S A and other countries FilterLab microID MXDEV MXLAB PICMASTER SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U S A Accuron Application Maestro dsPIC dsPICDEM dsPICDEM net ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC microPort Migratable Memory MPASM MPLIB MPLINK MPSIM PICC PICkit PICDE
23. vs FIGURE 2 10 Input Offset Voltage Drift Vggr Voltage 0 01 3 0 0100 Vour 0 3V to Vpp 0 3V 3 EVpp 45 5 V am 5 0 001 5 5 Vou G G 1 to 23 Vow LL 0 0010 ri i eser cca AA 0 0001 3 Go m Von G 6242 0 00001 0 0001 25 30 35 40 45 50 55 1 10 Power Supply Voltage V Output Voltage Swing Vp p FIGURE 2 8 DC Output Non Linearity vs FIGURE 2 11 DC Output Non Linearity vs Supply Voltage Output Swing 1000 12 11 F210 kHz 10 8 9 100 g 8 F o or 6 gt 5 22 5 Dc 10 5 4 2 2 5 1 0 1 1 10 100 Ik 10k 100k 1 2 4 5 8 10 16 32 Frequency Hz Gain V V FIGURE 2 9 Input Noise Voltage Density FIGURE 2 12 Input Noise Voltage Density vs Frequency vs Gain DS21117A page 10 2003 Microchip Technology Inc MCP6S21 2 6 8 Note Unless otherwise indicated Ta 25 C 5 0V Vss GND VREr Vss G 1 V V Input CHO 0 3V G CH1 to CH7 0 3V 10 to Vpp 2 and C 60 pF 120 110 100 90 80 Power Supply Rejection Ratio 70 50 25 0 25 50 75 100 125 Ambient Temperature C FIGURE 2 13 PSRR vs Ambient
24. 1 6F 3 18 20 Shinyokohama Kohoku Ku Yokohama shi Kanagawa 222 0033 Japan Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Microchip Technology Korea 168 1 Youngbo Bldg 3 Floor Samsung Dong Kangnam Ku Seoul Korea 135 882 Tel 82 2 554 7200 Fax 82 2 558 5934 Singapore Microchip Technology Singapore Pte Ltd 200 Middle Road 07 02 Prime Centre Singapore 188980 Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Microchip Technology Barbados Inc Taiwan Branch 11F 3 No 207 Tung Hua North Road Taipei 105 Taiwan Tel 886 2 2717 7175 Fax 886 2 2545 0139 EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A 4600 Wels Austria Tel 43 7242 2244 399 Fax 43 7242 2244 393 Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1 3 Ballerup DK 2750 Denmark Tel 45 4420 9895 Fax 45 4420 9910 France Microchip Technology SARL Parc d Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A ler Etage 91300 Massy France Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Microchip Technology GmbH Steinheilstrasse 10 D 85737 Ismaning Germany Tel 49 089 627 144 100 Fax 49 089 627 144 44 Italy Microchip Technology SRL Via Quasimodo 12 20025 Legnano MI Milan Italy Tel 39 0331 742611 Fax 39 0331 466781 United Kingdom Microchip Ltd 505 Eskdale Road Winnersh Triangle Wokingham Berkshire England RG41 5TU Tel 44 118 921 5869 Fax
25. 6 4 5 23 c 2 1 0 LA 10 100 1000 Capacitive Load pF FIGURE 2 18 Gain Peaking vs Capacitive Load 2003 Microchip Technology Inc DS21117A page 11 MCP6S21 2 6 8 Note Unless otherwise indicated Ta 25 C 5 0V Vss GND VREr Vss G 1 Input 0 3V G CH1 to CH7 0 3V 10 to Vpp 2 and C 60 pF J MS Gain dB og 100k 1M 10M 100M Frequency Hz FIGURE 2 19 Gain vs Frequency 100 420 Samples 90 1 Vpp 5 0 V 80 70 60 50 40 30 20 10 0 ooo oot Percentage of Occurrences Quiescent Current in Shutdown 1 2 1 1 1 0 p 0 9 Ss 7 0 8 0 7 0 6 Ta 125 0 5 Ta 85 Ta 25 C 0 4 0 3 Ta 40 C 0 2 Quiescent Current mA 0 1 0 0 DLL 0 0 0 5 1 0 15 20 25 30 35 4 0 45 5 0 5 5 Supply Vol
26. 6S28 has the highest There is about a 2 1 ratio in between these parts 4 2 Internal Op Amp The internal op amp provides the right combination of bandwidth accuracy and flexibility 4 2 1 COMPENSATION CAPACITORS The internal op amp has three compensation capaci tors connected to a switching network They are selected to give good small signal bandwidth at high gains and good slew rate full power bandwidth at low gains The change in bandwidth as gain changes is between 2 MHz and 12 MHz Refer to Table 4 1 for more information FIGURE 4 1 PGA Block Diagram TABLE 4 1 GAIN VS INTERNAL COMPENSATION CAPACITOR MON acad Capacitor 1 Large 12 4 0 0 30 12 2 Large 12 4 0 0 30 6 4 Medium 20 11 0 70 10 5 Medium 20 11 0 70 7 8 Medium 20 11 0 70 2 4 10 Medium 20 11 0 70 2 0 16 Small 64 22 1 6 5 32 Small 64 22 1 6 2 0 Note 1 FPBW is the Full Power Bandwidth These numbers are based on Vpp 5 0V 2 No changes DC performance e g Vos accompany a change in compensation capacitor 3 BW is the closed loop small signal 3 dB bandwidth DS21117A page 16 2003 Microchip Technology Inc MCP6321 2 6 8 4 2 2 RAIL TO RAIL INPUT The input stage of the internal op amp uses two differ ential input stages in parallel one operates at low VIN input voltage while the other operates at high Vi With this topology the internal inputs
27. 6V INL V A FIGURE 1 8 Output Voltage INL with the standard condition Vper Vss OV 2003 Microchip Technology Inc DS21117A page 7 MCP6S21 2 6 8 114 DIFFERENT Ver CONDITIONS Some of the plots in Section 2 0 Typical Performance Curves have the conditions VREr Vpp 2 Vpp The equations and figures above eas ily modified for these conditions The ideal becomes EQUATION Vo ideal Vggg t G Veep Vpp2 Vss OV The complete linear model is EQUATION Vo linear GU gp Vin p Vos 0 3V where the new Vin endpoints are EQUATION SY Viro Vin pu cc FpD 03V V Ree INR G VREF The equations for extracting the specifications do not change DS21117A page 8 2003 Microchip Technology Inc MCP6S21 2 6 8 2 0 TYPICAL PERFORMANCE CURVES Note The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only The performance characteristics listed herein are not tested or guaranteed In some graphs or tables the data presented may be outside the specified operating range outside specified power supply range and therefore outside the warranted range Note Unless otherwise indicated Ta 25 C 5 0V Vss GND Vggr Vas G 1 V V Input
28. 90 394 9 80 9 91 10 01 Chamfer Distance h 010 015 020 0 25 0 38 0 51 Foot Length E 016 033 050 0 41 0 84 1 27 Foot Angle 0 4 8 0 4 8 Lead Thickness 008 009 010 0 20 0 23 0 25 Lead Width B 013 017 020 0 33 0 42 0 51 Mold Draft Angle 0 12 15 0 12 15 Mold Draft Angle Bottom 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 012 Drawing No C04 108 DS21117A page 38 2003 Microchip Technology Inc MCP6S21 2 6 8 NOTES 2003 Microchip Technology Inc DS21117A page 39 MCP6321 2 6 8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO XX Examples Device Temperature Package a MCP6S21 I P One Channel PGA Range PDIP package b MCP6S21 I SN One Channel PGA SOIC package Device MCP6S21 One Channel PGA p MCP6S21T One Channel PGA c MCP6S21 I MS One Channel PGA Tape and Reel for SOIC and MSOP MSOP package MCP6S22 Two Channel PGA d MCP6S22 I MS Two Channel PGA MCP6S22T Two Channel PGA MSOP package Tape and Reel for SOIC and MSOP MCP6S26 Six Channel PGA MCP6S22T I MS Tape and Reel MCP6S26T Six Channel PGA Two Channel PGA MSOP package Tape and
29. HO 0 3V 6 1 0 1 0 0 10k 100k 1M 10M Time 1 us div Frequency Hz FIGURE 2 31 Output Voltage vs FIGURE 2 33 Output Voltage Swing vs Shutdown Mode Frequency 20 6 T 18 420 Samples Vin 5 0V o 5 5 16 H H 5 14 H H 4 8 12 Hon 5 5 10 H H HH gt 3 NE NE NE 5 5 6 HHHHHH 6 5 4 HHHHHHH g1 2 HHHHHHH 0 0 00 1 60 164 1 68 172 1 76 180 1 84 1 88 POR Trip Voltage V Time 1 ms div FIGURE 2 32 POR Trip Voltage FIGURE 2 34 The MCP6S21 2 6 8 family shows no phase reversal under overdrive __ ____ ____ __ DS21117A page 14 2003 Microchip Technology Inc MCP6321 2 6 8 3 0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3 1 TABLE 3 1 PIN FUNCTION TABLE 6521 MCP6S22 6526 6528 Symbol Description 1 1 1 1 Vout Analog Output 2 2 2 2 CHO Analog Input 3 3 3 CH1 Analog Input 4 4 CH2 Analog Input 5 5 CH3 Analog Input 6 6 CH4 Analog Input 7 7 CH5 Analog Input 8 CH6 Analog Input 9 CH7 Analog Input 3 8 10 VREF External Reference Pin 4 4 9 11 Vss Negative Power Supply 5 5 10 12 CS SPI Chip Select 6 6 11 13 SI SPI Serial Data Input 12 14 SO SPI Serial Data Output 7 7 13 15 SCK SPI Clock Input 14 16 Vpp Positive Power Supply
30. I SO Device 1 Device 2 1 Set CS low 2 Clock out the instruction and data Device 2 for Device 2 16 clocks to Device 1 Device 1 3 Device 1 automatically clocks out all 00100000 00000000 00000009 00000900 zeros first 16 clocks to Device 2 4 Clock out the instruction and data for Device 1 16 clocks to Device 1 5 Device 1 automatically shifts data Device 1 Device 2 from Device 01000001 00000111 00100000 00000000 clocks 6 Raise CS FIGURE 5 3 Daisy Chain Configuration DS21117A page 22 2003 Microchip Technology Inc MCP6321 2 6 8 4 23456 7 8 910111213141516 123456 7 8 910111213141516 SCK 5 5 5 5 5 zz 5 Instruction Byte Data Byte Instruction Byte Data Byte for Device 2 for Device 2 i for Device 1 for Device 1 za 0 first 16 bits out are always zeros 5 zz 5 Instruction Byte Data Byte for Device 2 for Device 2 FIGURE 5 4 Serial bus sequence for daisy chain configuration SPI 0 0 mode 123456 7 8 910111213141516 123456 7 8 910111213141516 5
31. Instrumentation Block Diagram Test Equipment Medical Instrumentation CHO Package Types CH1 y CH2 o MCP6S21 MCP6S22 CH3 D PDIP SOIC MSOP PDIP SOIC MSOP 9 MUX 2 Vour 1 7 8 81 8 CHO 2 7 SCK 2 7 SCK CH7 Gain 8 n b Vrer 3 6 SI CH1 3 6 SI Switches 8 CSH ZR Vss 4 5105 4 5 CS 5193 SPI SOc Logic gt SCK MCP6S26 MCP6S28 POR PDIP SOIC TSSOP PDIP SOIC Vour 4 Vo Vour 18 Vss VREF CHO 2 13 SCK 2 15 SCK CH1 3 12 SO CH1 3 14 SO CH2 4 11 SI CH2 4 13 SI CH3 5 10 CS CH3 5 12 CS CH4 6 9 Vss CH4 6 11 Vss CH5 7 8 5 7 10 VREF CH6 8 9 7 2003 Microchip Technology Inc DS21117A page 1 MCP6S21 2 6 8 1 0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function Absolute Maximum Ratings T Vout Analog Output 7 0 CHO CH7 Analog Inputs All inputs an
32. M PICDEM net PowerCal Powerlnfo PowerMate PowerTool rfLAB rfPIC Select Mode SmartSensor SmartShunt SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U S A and other countries Serialized Quick Turn Programming SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2003 Microchip Technology Incorporated Printed in the U S A All Rights Reserved gt Printed on recycled paper Microchip received QS 9000 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona in July 1999 and Mountain View California in March 2002 The Company s quality system processes and procedures are QS 9000 compliant for its PICmicro 8 bit MCUs KEELOQ code hopping devices Serial EEPROMs microperipherals non volatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is 150 9001 certified 2003 Microchip Technology Inc DS21117A page 41 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support 480 792 7627 Web Address http www microchip com Rocky Mountain 2355 West Chandler Blvd Chandler AZ 85224
33. MICROCHIP MCP6S21 2 6 8 Single Ended Rail to Rail I O Low Gain PGA Features Description Multiplexed Inputs 1 2 6 or 8 channels The Microchip Technology Inc MCP6S21 2 6 8 are 8 Gain Selections analog Programmable Gain Amplifiers PGA They 41 2 4 5 8 10 16 or 32 V V can be configured for gains from 1 V V to 32 V V and the input multiplexer can select one of up to eight chan Serial Peripheral Interface SPI nels through an SPI port The serial interface can also Rail to Rail Input and Output put the PGA into shutdown to conserve power These Low Gain Error 1 max PGAs are optimized for high speed low offset voltage Low Offset 275 uV max and single supply operation with rail to rail input and High Bandwidth 2 to 12 MHz typ output capability These specifications support single supply applications needing flexible performance or multiple inputs The one channel MCP6S21 and the two channel MCP6S22 are available in 8 pin PDIP SOIC and MSOP packages The six channel MCP6S26 is avail able in 14 pin PDIP SOIC and TSSOP packages The A D Converter Driver eight channel MCP6S28 is available in 16 pin PDIP e Multiplexed Analog Applications and SOIC packages All parts are fully specified from 40 C to 85 C Low Noise 10 nV VHz 10 kHz typ Low Supply Current 1 0 mA typ Single Supply 2 5V to 5 5V Typical Applications Data Acquisition Industrial
34. Reel for SOIC and TSSOP MCP6S28 Eight Channel PGA 0 eo Six Channel PGA MCP6S28T Eight Channel PGA package Tape and Reel for SOIC MCP6S26 I SN Six Channel PGA SOIC package Temperature Range 40 C to 85 C h MCP6S26T I ST Tape and Reel Six Channel PGA TSSOP package i MCP6S28T I SL Tape and Reel Package MS Plastic Micro Small Outline MSOP 8 lead P Plastic DIP 300 mil Body 8 14 and 16 lead Eight Channel PGA SOIC package SN Plastic SOIC 150 mil Body 8 lead SL Plastic SOIC 150 mil Body 14 16 lead ST Plastic TSSOP 4 4mm Body 14 lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom mended workarounds To determine if an errata sheet exists for a particular device please contact one of the following 1 Your local Microchip sales office 2 The Microchip Corporate Literature Center U S FAX 480 792 7277 3 The Microchip Worldwide Site www microchip com Please specify which device revision of silicon and Data Sheet include Literature you are using New Customer Notification System Register on our web site www microchip com cn to receive the most current information on our products 2002 Microchip Technology Inc DS21117A page 39 MCP6S21 2 6 8 NOTES DS21117A page 40 2002 Microchip Technology Inc Note the f
35. S22 has VREF tied internally to so Vss is coupled to the internal amplifier and the spec describes PSRR only We recommend the MCP6S22 s Vss pin be tied directly to ground to avoid noise problems 2 lg includes current in Ap typically 60 pA at 0 3V Both and la exclude digital switching currents 3 The output goes Hi Z and the registers reset to their defaults see Section 5 4 Power On Reset DS21117A page 2 2003 Microchip Technology Inc MCP6321 2 6 8 DC CHARACTERISTICS CONTINUED Electrical Specifications Unless otherwise indicated Ta 25 C 2 5V to 5 5V Vss GND VREr Vss 1 V V Input 0 3V G to CH7 0 3V R 10 to Vpp 2 SI SCK are tied low and CS is tied high Parameters Sym Min Typ Max Units Conditions Power Supply Supply Voltage Vpp 2 5 5 5 V Quiescent Current la 0 5 1 0 1 35 mA lo 0 Note 2 Quiescent Current Shutdown SHDN 0 5 1 0 lo 0 Note 2 mode Power On Reset POR Trip Voltage VPOR 1 2 1 7 2 2 V Note 3 POR Trip Voltage Drift AVpon AT 3 0 mV C Ta 40 C to 85 C Note 1 Rj ap RE Ra Figure 4 1 connects Veer and the inverting input of the internal amplifier The MCP6S22 has VREE tied internally to Vss so is coupled to the internal amplifier and the PSRR spec describes PSRR only We recommend
36. Vpp Vpor 0 1V to 0 1V 50 Vpp to 90 Vout point Note 1 Not tested in production Set by design and characterization 2 When using the device in the daisy chain configuration maximum clock frequency is determined by a combination of propagation delay time tpo lt 80 ns data input setup time tsy gt 40 ns SCK high time gt 40 ns SCK rise and fall times of 5 ns Maximum fgcx is therefore 5 8 MHz DS21117A page 4 2003 Microchip Technology Inc MCP6321 2 6 8 TEMPERATURE CHARACTERISTICS Electrical Specifications Unless otherwise indicated Vpp 2 5V to 5 5V Vas GND Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range TA 40 85 Operating Temperature Range Ta 40 125 Note Note Storage Temperature Range TA 65 150 Thermal Package Resistances Thermal Resistance 8L PDIP 85 C W Thermal Resistance 8L SOIC OJA 163 C W Thermal Resistance 8L MSOP OJA 206 C W Thermal Resistance 14L PDIP OJA 70 C W Thermal Resistance 14L SOIC OJA m 120 C W Thermal Resistance 14L TSSOP OJA 100 C W Thermal Resistance 16L PDIP OJA 70 C W Thermal Resistance 16L SOIC OJA 90 C W Note 1 The MCP6S21 2 6 8 family of PGAs operate
37. ad Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 045 058 070 1 14 1 46 1 78 Lower Lead Width B 014 018 022 036 0 46 0 56 Overall Row Spacing 8 eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom 5 10 15 5 10 15 Controlling Parameter Significant Characteristic Notes Dimensions D and 1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No 04 017 2003 Microchip Technology Inc DS21117A page 37 MCP6S21 2 6 8 16 Lead Plastic Small Outline SL a E1 E E i D 2 1 45 E MM L Wai Narrow 150 mil SOIC A2 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch 050 1 27 Overall Height A 053 061 069 1 35 1 55 1 75 Molded Package Thickness A2 052 057 061 1 32 1 44 1 55 Standoff 8 A1 004 007 010 0 10 0 18 0 25 Overall Width E 228 237 244 5 79 6 02 6 20 Molded Package Width 1 150 154 157 3 81 3 90 3 99 Overall Length D 386 3
38. andard marking consists of Microchip part number year code week code traceability code facility code mask rev and assembly code For marking beyond this certain price adders apply Please check with your Microchip Sales Office J MH M DS21117A page 28 2003 Microchip Technology Inc MCP6S21 2 6 8 Package Marking Information Con t 14 Lead PDIP 300 mil MCP6S26 r1 D XXXXXXXXXXXXXX YYWWNNN LI U LT LT LT U U 14 Lead SOIC 150 mil MCP6S26 XXXXXXXXXXX XXXXXXXXXXX O YYWWNNN 14 Lead TSSOP 4 4mm MCP6S26 Example 6826 0345256 LT LT LT LI LT LT U Example MCP6S26ISL A 0345256 Example 2003 Microchip Technology Inc DS21117A page 29 MCP6S21 2 6 8 Package Marking Information Con t
39. chip Technology Consulting Shanghai Co Ltd Chengdu Liaison Office Rm 2401 2402 24th Floor Ming Xing Financial Tower No 88 TIDU Street Chengdu 610016 China Tel 86 28 86766200 Fax 86 28 86766599 China Fuzhou Microchip Technology Consulting Shanghai Co Ltd Fuzhou Liaison Office Unit 28F World Trade Plaza No 71 Wusi Road Fuzhou 350001 China Tel 86 591 7503506 Fax 86 591 7503521 China Hong Kong SAR Microchip Technology Hongkong Ltd Unit 901 6 Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong N T Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 China Shanghai Microchip Technology Consulting Shanghai Co Ltd Room 701 Bldg B Far East International Plaza No 317 Xian Xia Road Shanghai 200051 Tel 86 21 6275 5700 Fax 86 21 6275 5060 China Shenzhen Microchip Technology Consulting Shanghai Co Ltd Shenzhen Liaison Office Rm 1812 18 F Building A United Plaza No 5022 Binhe Road Futian District Shenzhen 518033 China Tel 86 755 82901380 Fax 86 755 82966626 China Qingdao Rm 505 Fullhope Plaza No 12 Hong Kong Central Rd Qingdao 266071 China Tel 86 532 5027355 Fax 86 532 5027205 India Microchip Technology Inc India Liaison Office Marketing Support Division Divyasree Chambers 1 Floor Wing A A3 A4 No 11 O Shaugnessey Road Bangalore 560 025 India Tel 91 80 2290061 Fax 91 80 2290062 Japan Microchip Technology Japan K K Benex S
40. d Vss 0 3V to 0 3V Vss Negative Power Supply Difference Input voltage 5 Positive Power Supply Output Short Circuit continuous SCK SPI Clock Input Current at Input Pins 2 mA Sl SPI Serial Data Input Current at Output and Supply Pins 30 mA 50 SPI Serial Data Output Storage temperature 65 C to 150 C CS SPI Chip Select Junction temperature 150 C VREF External Reference Pin ESD protection on all pins HBM MM gt 2 200V T Notice Stresses above those listed under Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability DC CHARACTERISTICS Electrical Specifications Unless otherwise indicated Ta 25 C 2 5V to 5 5V Vss GND Vngr Vss G 1 V V Input CHO 0 3V G to CH7 0 3V 10 to Vpp 2 SI and SCK are tied low and CS is tied high Parameters Sym Min Typ Max Units Conditions Amplifier Input Inpu
41. e Unless otherwise indicated Ta 25 C 5 0V Vss GND Vggr Vas G 1 V V Input CHO 0 3V G CH1 to CH7 0 3V 10 to Vpp 2 and C 60 pF 20 420 Sampl es ET S 150 g 20 40 to 125 o 100 16 HH S 5 B 14 H H 5 9 12 H H 0 Von 2 5 109 Piaf ols Bw i 6 H H H H i 100 5 5 8 4 150 2 2 E 200 0 PE oe aes 00 05 10 15 20 25 30 35 40 45 50 55 NN m Veer Voltage Input Offset Voltage Drift uV C FIGURE 2 7 Input Offset Voltage
42. e bit n Value at POR W Writable bit Bit is set U Unimplemented bit read as 0 0 Bit is cleared Bit is unknown 2003 Microchip Technology Inc DS21117A page 21 MCP6S21 2 6 8 5 2 4 SHUTDOWN COMMAND The software Shutdown command allows the user to put the amplifier into a low power mode see Register 5 1 In this shutdown mode most pins are high impedance Section 4 4 Shutdown Mode and Section 5 1 SPI Timing cover the exceptions at pins VREF VouT and SO Once the PGA has entered shutdown mode it will remain in this mode until either a valid command is sent to the device other than NOP or Shutdown or the device is powered down and back up again The internal registers maintain their values while in shutdown Once brought out of shutdown mode the part comes back to its previous state see Section 5 4 for excep tions to this rule This makes it possible to bring the device out of shutdown mode using one command send a command to select the current channel or gain and the device will exit shutdown with the same state that existed before shutdown 5 3 Multiple devices can be connected in a daisy chain configuration by connecting the SO pin from one device to the SI pin on the next device and using common SCK and CS lines Figure 5 3 This approach reduces PCB layout complexity Daisy Chain Configuration The example in Figure 5 3 shows a daisy chain con
43. ew Rate SR 4 0 Vlus G 1 2 11 G 4 5 8 10 22 G 16 32 Noise Input Noise Voltage Eni 3 2 UVp p f 2 0 1 Hz to 10 kHz Note 2 26 f 0 1 Hz to 200 kHz Note 2 Input Noise Voltage Density ni 10 nV VHz f 10 kHz Note 2 Input Noise Current Density ini 4 fANHZ f 10 kHz Note 1 See Table 4 1 for a list of typical numbers 2 En and ej include ladder resistance noise See Figure 2 33 for ey vs G data 2003 Microchip Technology Inc DS21117A page 3 MCP6S21 2 6 8 DIGITAL CHARACTERISTICS Electrical Specifications Unless otherwise indicated Ta 25 C 2 5V to 5 5V Vss GND Vref Vss G 1 Input 0 3V G CH1 to CH7 0 3V 10 to Vpp 2 C 60 pF SI and SCK are tied low and CS is tied high Parameters Sym Min Typ Max Units Conditions SPI Inputs CS SI SCK Logic Threshold Low Vi 0 0 3Vpp Input Leakage Current LL 1 0 1 0 Logic Threshold High Vin 0 7Vpp Amplifier Output Leakage Current 1 0 1 0 In Shutdown mode SPI Output SO for MCP6S26 and MCP6S28 Logic Threshold Low VoL Vss Vss 0 4 lo 2 1 mA 5V Logic Threshold High Vou Vpp 0 5 Vpp V 400 pA SPI Timing Pin Capacitance 10 pF All digital pins Input R
44. fig uration with two devices although any number of devices can be configured this way The MCP6S21 and MCP6S22 can only be used at the far end of the daisy chain because they do not have a serial data out SO pin As shown in Figure 5 4 and Figure 5 5 both SI and SO data are sent in 16 bit 2 byte words These devices abort any command that is not a multiple of 16 bits When using the daisy chain configuration the maxi mum clock speed possible is reduced to 5 8 MHz because of the SO pin s propagation delay see Electrical Specifications The internal SPI shift register is automatically loaded with zeros whenever CS goes high a command is exe cuted Thus the first 16 bits out of the SO pin once CS line goes low are always zeros This means that the first command loaded into the next device in the daisy chain is a NOP This feature makes it possible to send shorter command and data byte strings when the far thest devices do not need to change For example if there were three devices on the chain and only the mid dle device needed changing only 32 bytes of data need to be transmitted for the first and middle devices and the last_device on the chain would receive a NOP when the CS pin is raised to execute the command cs SCK PlCmicro SO CS CS Microcontroller SCK SCK SI SO S
45. h Z Once the device is deselected CS goes high SO is forced low This feature supports daisy chaining as explained in Section 5 3 Daisy Chain Configuration 2003 Microchip Technology Inc DS21117A page 15 MCP6S21 2 6 8 4 0 ANALOG FUNCTIONS The 6521 2 6 8 family of Programmable Gain Amplifiers PGA are based on simple analog building blocks see Figure 4 1 Each of these blocks will be explained in more detail in the following sub sections Vpp CHO CH1 9 V CH2 QUT CH3 MUX CH5 0 S CH6 F CH7 Gain 8 Switches CS SI d SPI SO Logic SCK e jeppe7 Joysisoy POR Vss VREF MCP6S21 One input SO pin MCP6S22 Two inputs CH1 VREF tied internally to Vss no SO pin MCP6S26 Six inputs to 5 MCP6S28 Eight inputs CHO CH7 4 1 Input MUX The MCP6S21 has one input the MCP6S22 and MCP6S25 have two inputs the MCP6S26 has six inputs and the MCP6S28 has eight inputs see Figure 4 1 For the lowest input current float unused inputs Tying these pins to a voltage near the used channels also works well For simplicity they can be tied to Vss or Vpp but the input current may increase The one channel MCP6S21 has the lowest input bias current while the eight channel MCP
46. ise Fall Times CS SI SCK tRFI 2 us Note 1 Output Rise Fall Times SO tRFO 5 ns MCP6S26 and MCP6S28 CS high time tcsH 40 ns SCK edge to CS fall setup time teso 10 ns SCK edge when CS is high CS fall to first SCK edge setup time lcssc 40 ns SCK Frequency fsck 10 MHz Vpp 5V Note 2 SCK high time 1 40 ns SCK low time tio 40 ns SCK last edge to CS rise setup time tsccs 30 ns CS rise to SCK edge setup time 1 100 ns SCK edge when CS is high SI set up time tsu 40 ns SI hold time tup 10 ns SCK to SO valid propagation delay tpo 80 ns MCP6S26 and MCP6S28 CS rise to SO forced to zero tsoz 80 ns MCP6S26 and MCP6S28 Channel and Gain Select Timing Channel Select Time tcu 1 5 us CHx 0 6V CHy 0 3V 6 1 CHx to CHy select CS 0 7Vpp to Vout 90 point Gain Select Time tc 1 us CHx 0 3V G 510 G 1 select CS 0 7Vpp to Vout 90 point Shutdown Mode Timing Out of Shutdown mode CS goes ton 3 5 10 HS 5 07 to 90 point high to Amplifier Output Turn on Time Into Shutdown mode CS goes high torr 1 5 US CS 0 7Vpp to Vour 90 point to Amplifier Output High Z Turn off Time POR Timing Power On Reset power up time trey 30 US Vpp Vpon 0 1V to 0 1V 50 Vpp to 90 Vout point Power On Reset power down time tRPD 10 US
47. n 5 3 Daisy Chain Configuration Current Measurement Circuit 6 4 2 SHIFTED GAIN RANGE PGA Figure 6 4 shows a circuit using an MCP6021 at a gain V V of 10 in front of an MCP6S21 This changes the over INO JMCP6S28 all gain range to 10 V V to 320 V V from 1 V V to 32 V V FIGURE 6 6 PGA with Extended Gain Range VIN O MCP6021 Vout 6 4 4 MULTIPLE SENSOR AMPLIFIER B The multiple channel PGAs except the MCP6S21 allow the user to select which sensor appears on the e AAN output see Figure 6 7 These devices can also 10 0 change the gain to optimize performance for each 4M kQ sensor Sensor 0 FIGURE 6 4 PGA with Modified Gain Sensor 1 0 MCP6S26 V Range ss our It is also easy to shift the gain range to lower gains see Sensor 5 Figure 6 6 The MCP6021 acts as a unity gain buffer and the resistive voltage divider shifts the gain range FIGURE 6 7 PGA with Multiple Sensor down to 0 1 V V to 3 2 from 1 V V to 32 V V Inputs SS DS21117A page 26 2003 Microchip Technology Inc MCP6321 2 6 8 6 4 5 EXPANDED INPUT PGA Figure 6 8 shows cascaded MCP6S28s that provide up to 15 input channels Obviously Sensors 7 14 have a high total gain range available as explained in Section 6 4 3 Extended Gain Range These devices can be daisy chained Section 5 3 Daisy Chain
48. nt compensation capacitors are selected to optimize the bandwidth vs slew rate trade off see Table 4 1 REGISTER 5 2 GAIN REGISTER U x U x U x U x U x W 0 W 0 W 0 G2 G1 GO bit 7 bit O bit 7 3 Unimplemented Read as 0 reserved for future use bit 2 0 G2 G0 Gain Select Bits 000 Gain of 1 Default 001 Gain of 2 010 Gain of 4 011 Gain of 5 100 Gain of 8 101 Gain of 10 110 Gain of 16 111 Gain of 32 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown DS21117A page 20 2003 Microchip Technology Inc MCP6321 2 6 8 5 2 3 CHANGING THE CHANNEL If the instruction register is programmed to address the inputs of the 6522 MCP6S26 and 528 can be changed channel register the multiplexed per Register 5 3 REGISTER 5 3 CHANNEL REGISTER U x U x U x U x U x W 0 W 0 W 0 C2 C1 bit 7 bit O bit 7 3 Unimplemented Read as 0 reserved for future use bit 2 0 2 0 Channel Select Bits MCP6S21 MCP6S22 MCP6S26 MCP6S28 000 CHO Default CHO Default CHO Default CHO Default 001 CHO CH1 CH1 CH1 001 CHO CHO CH2 CH2 011 CHO CH1 CH3 CH3 100 CHO CHO CH4 CH4 101 CHO CH1 CH5 CH5 110 CHO CHO CHO CH6 111 CHO CH1 CHO CH7 Legend R Readabl
49. ollowing details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act Information contained in this publication regarding device applications and the like is intended
50. s over this extended temperature range but with reduced performance Operation in this range must not cause T to exceed the Maximum Junction Temperature 150 C cs 0 6V FIGURE 1 1 Channel Select Timing Diagram cs 1 ton torr Hi Z Hi Z V p _ Iss 1 0 mA typ 500 nA typ FIGURE 1 2 PGA Shutdown timing diagram must enter correct commands before CS goes high cs tc 1 5V Vi d 0 3V FIGURE 1 3 Gain Select Timing Diagram VPOR 0 1V Vpor 0 1V Vpon 0 1V tRPU Vour Hi Z Iss o 500 nA typ FIGURE 1 4 POR power up and power down timing diagram 2003 Microchip Technology Inc DS21117A page 5 MCP6S21 2 6 8 cs 7 tsccs tcs1 tcso a to tu 1 4 t ee ee 1 f tsu typ E om gt lt gt lt gt lt gt lt 50 X 7 first 16 bits out are always zeros FIGURE 1 5 Detailed SPI Serial Interface Timing SPI 0 0 mode lcsH CS J tcssc tsccs tcs1 teso Hi a a J SCK X 1f tsu tup sen 8 H Um dc M tbo tsoz M first 16 bits out are always zeros FIGURE 1 6 Detailed SPI Serial Interface Timing
51. ss 004 006 008 0 10 0 15 0 20 Lead Width B 010 012 016 0 25 0 30 0 40 Mold Draft Angle Top 7 7 Mold Draft Angle Bottom B 7 7 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side Drawing 04 111 2003 Microchip Technology Inc DS21117A page 33 MCP6S21 2 6 8 14 Lead Plastic Dual In line P 300 mil PDIP 1 3 3 D ra J 2 4 ID 9 Y ES n LT maza B Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch 100 2 54 Top to Seating Plane A 140 155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane Al 015 0 38 Shoulder to Shoulder Width E 300 313 325 7 62 7 94 8 26 Molded Package Width 1 240 250 260 6 10 6 35 6 60 Overall Length D 740 750 760 18 80 19 05 19 30 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 045 058 070 1 14 1 46 1 78
52. t Offset Voltage Vos 275 275 uV G 1 4 0V Input Offset Voltage Drift AVos ATA 4 40 to 85 C Power Supply Rejection Ratio PSRR 70 85 dB G 1 Note 1 Input Bias Current lg 1 pA CHx Vpp 2 Input Bias Current over lg 250 pA Ta 40 to 85 C Temperature CHx 7 Vpp 2 Input Impedance Zn 10131 15 Input Voltage Range Vive Vss 0 3 Vppt0 3 V Amplifier Gain Nominal Gains G 1 to 32 1 2 4 5 8 10 16 or 32 DC Gain Error G 1 0 1 0 1 Vout 0 3V to 0 3V gt 2 1 0 1 0 Vout 0 3V to 0 3V DC Gain Drift G 1 AG ATA 0 0002 40 to 85 C gt 2 AG ATA 0 0004 40 to 85 C Internal Resistance RLAD 3 4 49 6 4 kQ Note 1 Internal Resistance over ARLAD ATA 0 028 Note 1 Temperature Ta 40 to 85 C Amplifier Output DC Output Non linearity G 1 0 003 Yo of FSR Vout 0 3V to 0 3V Vpp 5 0V gt 2 0 001 Yo of FSR Vout 0 3V to Vpp 0 3V 5 0V Maximum Output Voltage Swing VoL Vss 20 Vpp 100 mV G 2 2 0 5V output overdrive Vss 60 Vpp 60 G 2 0 5V output overdrive Vrer Vpp 2 Short Circuit Current lo sc 30 mA Note 1 Rap Ra in Figure 4 1 connects VREF Vour and the inverting input of the internal amplifier The MCP6
53. t is important to use good PCB layout techniques Any parasitic coupling at high frequency might cause undesired peaking Filter ing high frequency signals i e fast edge rates can help To minimize high frequency problems Use complete ground and power planes Use HF surface mount components Provide clean supply voltages and bypassing Keep traces short and straight Try a linear power supply e g LDO 2003 Microchip Technology Inc DS21117A page 25 MCP6S21 2 6 8 6 4 Typical Applications y IN 6 4 1 GAIN RANGING O Figure 6 3 shows a circuit that measures the current lx MCP6021 It benefits from changing the gain on the PGA Just as 10 0 ka a hand held multimeter uses different measurement ranges to obtain the best results this circuit makes it V easy to set a high gain for small signals and a low gain OUT for large signals As a result the reguired dynamic range at the PGA s output is less than at its input by up 1 11 to 30 dB Lil s FIGURE 6 5 PGA with lower gain range Vout 6 4 3 EXTENDED GAIN RANGE PGA lx Figure 6 6 gives a 1 V V to 1024 V V gain range Rs which is much greater than the range for a single PGA 1 VN to 32 V V The first PGA provides input mul tiplexing capability while the second PGA only needs one input These devices can be daisy chained FIGURE 6 3 Wide Dynamic Range Sectio
54. tage V FIGURE 2 22 Supply Voltage Quiescent Current vs In Shutdown Mode 0 9 5 0 V Quiescent Current Shutdown pA e a 0 25 50 75 100 125 Ambient Temperature C FIGURE 2 20 Histogram of Quiescent FIGURE 2 23 Quiescent Current in Current in Shutdown Mode Shutdown Mode vs Ambient Temperature 100 40 gt t 3 9 35 8 5 5 g Vop 5 5V T 30 7 22 v i g 10 o t 20 125 C 2 5V Tat 85 9 2 2 15 Ta 25 C gt 7 Ta 40 C gt 10 5 gt 2 5 5 5 1 0 0 1 1 10 2 5 3 0 3 5 4 0 4 5 5 0 5 5 Output Current Magnitude mA Power Supply Voltage V FIGURE 2 21 vs Output Current Output Voltage Headroom FIGURE 2 24 vs Supply Voltage Output Short Circuit Current DS21117A page 12 2003 Microchip Technology Inc MCP6S21 2 6 8 Note Unless otherwise indicated Ta 25 C 5 0V Vss GND Vss G 1 Input CHO 0 3V G CH1 to CH7 0 3V R 10 to Vpp 2 and C 60 pF
55. tance h 010 015 020 0 25 0 38 0 51 Foot Length L 019 025 030 0 48 0 62 0 76 Foot Angle 0 4 8 0 4 8 Lead Thickness 008 009 010 0 20 0 23 0 25 Lead Width B 013 017 020 0 33 0 42 0 51 Mold Draft Angle Top 0 12 15 0 12 15 Mold Draft Angle Bottom 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 012 Drawing No C04 057 Ce DS21117A page 32 2003 Microchip Technology Inc MCP6S21 2 6 8 8 Lead Plastic Micro Small Outline Package MS MSOP 1 bo i D 2 n O 1 LS ne T 6 F r B Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch 026 0 65 Overall Height A 044 1 18 Molded Package Thickness A2 030 034 038 0 76 0 86 0 97 Standoff 8 A1 002 006 0 05 0 15 Overall Width E 184 193 200 4 67 4 90 5 08 Molded Package Width 1 114 118 122 2 90 3 00 3 10 Overall Length 114 118 122 2 90 3 00 3 10 Foot Length L 016 022 028 0 40 0 55 0 70 Footprint Reference F 035 037 039 0 90 0 95 1 00 Foot Angle 0 6 0 6 Lead Thickne
56. tegrated noise at the MCP6S28 s output and serves as an anti aliasing filter This filter may be designed using Microchip s FilterLab software available at www microchip com 2003 Microchip Technology Inc DS21117A page 27 MCP6S21 2 6 8 7 0 PACKAGING INFORMATION 7 1 Package Marking Information 8 Lead PDIP 300 mil MCP6S21 MCP6S22 Example MCP6S21 XXXXXNNN I P256 o Dryw 0345 LJ LI LIT LJ LI CA L 8 Lead SOIC 150 mil MCP6S21 MCP6S22 Example XXXXXXXX MCP6S21 XXXXYYWW I SN0345 256 8 Lead 6521 MCP6S22 Example XXXXX MCP6S211 YWWNNN 345256 Legend XX X Customer specific information YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code Note Inthe eventthe full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information St
57. the MCP6S22 s Vss pin be tied directly to ground to avoid noise problems 2 lg includes current Rj Ap typically 60 pA at Vour 0 3V Both lo and supw exclude digital switching currents 3 The output goes Hi Z and the registers reset to their defaults see Section 5 4 Power On Reset AC CHARACTERISTICS Electrical Specifications Unless otherwise indicated Ta 25 2 5V to 5 5V Vss GND Vngr Vss G 1 V V Input CHO 0 3V G CH1 to CH7 0 3V R 10 to Vpp 2 C 60 pF SI and SCK are tied low and CS is tied high Parameters Sym Min Typ Max Units Conditions Frequency Response 3 dB Bandwidth BW 2to 12 MHz All gains lt 100 mVp p Note 1 Gain Peaking GPK m 0 E dB All gains Vour lt 100 mVp p Total Harmonic Distortion plus Noise f 1kHz G 1V V THD N 0 0015 1 5V 1 0 5 0 BW 22 kHz f 1kHz G 4V V THD N 0 0058 1 5V 1 0 5 0 BW 22 kHz f 1kHz G 16 V V THD N 0 023 1 5V 1 0 5 0V BW 22 kHz f 20 kHz G 1 THD N 0 0035 Vout 1 5V 1 0Vpx 5 0 BW 80 kHz f 20 kHz G 4 VN THD N 0 0093 Vout 1 5V 1 0Vpx Vpp 5 0 BW 80 kHz f 20 kHz G 16 THD N 0 036 1 5V 1 0Vpx 5 0 BW 80 kHz Step Response Sl
58. troller This interface is configured to allow daisy chaining with other SPI devices There is an internal POR Power On Reset that resets the registers under low power conditions 5 4 SPI Timing Chip Select CS toggles low to initiate communication with these devices The first byte of each SI word two bytes long is the instruction byte which goes into the Instruction Register The Instruction Register points the second byte to its destination In a typical application CS is raised after one word 16 bits to implement the desired changes Section 5 3 Registers covers applications using multiple 16 bit words SO goes low after CS goes high it has a push pull output that does not go into a high Z state The MCP6S21 2 6 8 devices operate in SPI Modes 0 0 and 1 1 In 0 0 mode the clock idles in the low state Figure 5 1 and in 1 1 mode the clock idles in the high state Figure 5 2 In both modes SI data is loaded into the PGA on the rising edge of SCK and SO data is clocked out on the falling edge of SCK In 0 0 mode the falling edge of CS also acts as the first falling edge of SCK see Figure 5 1 There must be multiples of 16 clocks SCK while CS is low or commands will abort see Section 5 3 Registers
59. wn should not be used they are reserved for future use The device is brought out of Shutdown mode when a valid command other than or Shutdown is sent and CS is raised REGISTER 5 1 INSTRUCTION REGISTER W 0 W 0 W 0 U x U x U x U x W 0 M2 M1 MO AO bit 7 bit 0 bit 7 5 M2 M0 Command Bits 000 NOP Default Note 1 m 0017 PGA enters Shutdown Mode as soon as a full 16 bit word is sent and CS is raised Notes 1 and 2 010 7 Write to register 0117 reserved for future use Note 1 1XX NOP reserved for future use Note 1 bit 4 1 Unimplemented Read as 0 reserved for future use bit O AO Indirect Address Bit 1 Addresses the Channel Register 0 Addresses the Gain Register Default Note 1 All other bits in the 16 bit word including AO are don t cares 2 The device exits Shutdown mode when a valid command other than NOP or Shut down is sent and CS is raised that valid command will be executed Shutdown does not toggle Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2003 Microchip Technology Inc DS21117A page 19 MCP6S21 2 6 8 5 2 2 SETTING THE GAIN The amplifier can be programmed to produce binary and decimal gain settings between 1 V V and 32 V V Register 5 2 shows the details At the same time differ e
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MICROCHIP MCP6S21/2/6/8 Manual