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ANALOG DEVICES Low Voltage 1.15 V to 5.5 V 8-Channel Bidirectional Logic Level Translators ADG3308/ADG3308-1 handbook

1. Universal Added Figure dar is repe aereo ees 7 Updated Outline Dimensions eseeeen 19 Changes to Ordering Guide see 19 1 05 Revision 0 Initial Version Theory of Operation sits eR Re ERR 16 Level Translator Architecture ses 16 Input Driving Requirements see 16 Output Load Requirement asss 16 Enable Operation 16 Power Supplies tette ertet 16 Data Rate eee entente tei eei neis 17 Applications 18 Layout Guidelines ret t ette e tanen 18 Outline Dimensions ee EORR teens 19 Orderime Guide oett aa 20 Rev C Page 2 of 20 SPECIFICATIONS ADG3308 AD63308 1 Vecy 1 65 V to 5 5 V Vcca 1 15 V to GND 0 V specifications Tur to Tmax unless otherwise noted Table 1 Parameter Symbol Conditions Min Typ Max Unit LOGIC INPUTS OUTPUTS A Side Input High Voltage Vina Vcca 1 15 V Veca 0 3 V Vina VccA 1 2 V to 5 5 V 0 65 x VccA V Input Low Voltage Vita 0 35 xVeca V Output High Voltage Vy Vccy 20 pA see Figure 29 0 4 V Output Low Voltage Vora Vy OV lo 20 uA see Figure 29 0 4 V Capacitance f 1 MHz see Figure 34 10 Leakage Current ILa HicH z or Vcca EN 0 see Figure 31 1 uA Y Side Input High Voltage 0 65 x Vc V Input Low Voltage Viy
2. 0 high impedance state at Pin 1 to Pin Y8 Vinen Logic input high voltage at the EN pin Vien Logic input low voltage at the EN pin Cen Capacitance measured at EN pin Iren Enable EN pin leakage current ten Three state enable time for Pin A1 to Pin A8 Pin Y1 to Pin Y8 te asy Propagation delay when translating logic levels in the A gt Y direction tr Rise time when translating logic levels in the AY direction te asy Fall time when translating logic levels in the A gt Y direction Dmax Guaranteed data rate when translating logic levels in the gt direction under the driving and loading conditions specified in Table 1 tskew A Y Difference between propagation delays on any two channels when translating logic levels in the gt direction tppsKEW A gt Y Difference in propagation delay between any one channel and the same channel on a different part under same driving loading conditions when translating in the A gt Y direction te y gt a Propagation delay when translating logic levels in the gt direction tr Y gt a Rise time when translating logic levels in the Y gt A direction try Fall time when translating logic levels the Y gt A direction Dmax oa Guaranteed data rate when translating logic levels in the gt direction under the driving and loading conditions specified in Table 1 tskew Difference between propagation delays on an
3. 2 Vecy 5 5 V EN 0 0 1 1 uA 1 Temperature range is 40 C to 85 C B Version for the TSSOP the LFCSP the WLCSP and the backside coated WLCSP All typical values are at TA 25 C unless otherwise noted 3 Guaranteed by design not subject to production test Rev C Page 5 of 20 ADG3308 ADG3308 1 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 2 Parameter Rating Vcca to GND 0 3 V to 7 V Vccy to GND Vcca to 7 V Digital Inputs A 0 3 V to Vcca 0 3 V Digital Inputs Y 0 3 V to Vccy 0 3 V EN to GND 0 3 V to 7 V Operating Temperature Range Extended Industrial Range B Version Storage Temperature Range Junction Temperature Osa Thermal Impedance 20 Lead TSSOP 20 Lead LFCSP 20 Ball WLCSP 20 Ball Backside Coated WLCSP Lead Temperature Soldering 10 sec IR Reflow Peak Temperature 20 sec 40 C to 85 C 65 C to 150 C 150 C 78 C W 30 4 C W 100 C W 100 C W 300 C 260 C 0 C 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating
4. 25 Mbps Channel to Channel Skew tskew 2 5 ns Part to Part Skew tPPSKEW 15 ns Y gt A Level Translation Rs Rr 500 15 pF see Figure 38 Propagation Delay te YoA 14 35 ns Rise Time tR Y gt A 5 16 ns Fall Time tE Y gt A 2 5 6 5 ns Maximum Data Rate Dmax Y gt A 25 Mbps Channel to Channel Skew tskEw Y gt A 3 6 5 ns Part to Part Skew tPPSKEW Y5A 23 5 ns Rev C Page 4 of 20 ADG3308 AD63308 1 Parameter Symbol Conditions Min Typ Max Unit 2 5V 0 2V lt Veca lt Vecy Vecy 3 3 V 0 3 V A Y Level Translation Rs 500 50 pF see Figure 37 Propagation Delay tp AoY 7 10 ns Rise Time tg asy 2 5 4 ns Fall Time tE Asy 2 5 ns Maximum Data Rate Dmax A Y 60 Mbps Channel to Channel Skew tskEw A Y 1 5 2 ns Part to Part Skew tePskEW A Y 4 ns Y gt A Level Translation Rs 500 15 pF see Figure 38 Propagation Delay te YoA 5 8 ns Rise Time tR Y gt A 1 4 ns Fall Time tF Y gt A 3 5 ns Maximum Data Rate Dmax Y gt A 60 Mbps Channel to Channel Skew tskew YA 2 3 ns Part to Part Skew tPPSKEW YA 3 ns POWER REQUIREMENTS Power Supply Voltages Veca Vcca Vecy 1 15 5 5 V Vccv 1 65 5 5 V Quiescent Power Supply Current IccA Va or Vcca Vy O V or Vccy 0 17 1 uA Vcca Vecy 5 5 V EN Vccy Va OV or Veca Vy OV or Vecy 027 1 uA Vcca Vecy 5 5 V EN Vccy Three State Mode Power Supply Current HiGH ZA Vcca 5 5 V EN 0 0 1 1 uA
5. ADG3308 ADG3308 1 ADG3308 2 1MO SIGNAL SOURCE Y A DIRECTION ADG3308 ADG3308 1 ADG3308 2 SIGNAL SOURCE Vccv ov ov ov Vccv ov Veca Vecy 0v Vccv VccA ov NOTES 1 ten IS WHICHEVER IS LARGER BETWEEN ten AND tEN2 IN BOTH AY AND Y A DIRECTIONS 04865 050 Figure 36 Enable Time Rev C Page 13 of 20 ADG3308 ADG3308 1 ADG3308 ADG3308 1 SIGNAL ADG3308 2 uk SOURCE tF aay tg a gt Y 063308 ADG3308 1 m ADG3308 2 SIGNAL SOURCE tF tg Figure 38 Switching Characteristics YA Level Translation Rev C Page 14 of 20 04865 051 04865 052 ADG3308 AD63308 1 TERMINOLOGY Vina Logic input high voltage at Pin A1 to Pin 8 Vira Logic input low voltage at Pin A1 to Pin 8 Vona Logic output high voltage at Pin A1 to Pin A8 Vora Logic output low voltage at Pin A1 to Pin A8 Ca Capacitance measured at Pin A1 to Pin A8 EN 0 Tha mon z Leakage current at Pin A1 to Pin A8 when EN 0 high impedance state at Pin A1 to Pin A8 Viny Logic input high voltage at Pin Y1 to Pin Y8 Vuy Logic input low voltage at Pin Y1 to Pin Y8 Vony Logic output high voltage at Pin Y1 to Pin Y8 Vor Logic output low voltage at Pin Y1 to Pin Y8 Cy Capacitance measured at Pin Y1 to Pin Y8 EN 0 HIGH Z Leakage current at Pin Y1 to Pin Y8 when EN
6. 0 35 x Vcc V Output High Voltage Va 20 pA see Figure 30 Vecy 0 4 V Output Low Voltage Va OV lo 20 pA see Figure 30 0 4 V Capacitance C f 1 MHz EN see Figure 35 6 8 pF Leakage Current OVorVcy EN 0 see Figure 32 1 uA Enable EN Input High Voltage ADG3308 TSSOP LFCSP 0 65 x Vecy V ADG3308 1 ADG3308 2 WLCSP VccA 1 15 V Vcca 0 3 V VccA 1 2 V to 5 5 V 0 65 x VccA V Input Low Voltage ViLEN ADG3308 TSSOP LFCSP 0 35 xVcv V ADG3308 1 ADG3308 2 WLCSP 0 35 V Leakage Current Ven OV or Vccy Va see Figure 33 1 uA Capacitance Cen 45 pF Enable Time ten Rs Rr 500 Va O0Vor 1 1 8 us Vcca AY Vy or Vccy Y gt A see Figure 36 SWITCHING CHARACTERISTICS 3 3 V 0 3V lt Vc Vecy Vcv 5 V 0 5 V A Y Level Translation Rs 500 50 pF see Figure 37 Propagation Delay tracy 6 10 ns Rise Time tr asy 2 3 5 ns Fall Time tr asy 3 5 ns Maximum Data Rate 50 Mbps Channel to Channel Skew tskew aY 2 4 ns Part to Part Skew tPPSKEW AS Y 3 ns Y gt A Level Translation Rs 50 15 pF see Figure 38 Propagation Delay te oA 4 ns Rise Time tR Y gt A ns Fall Time tEY gt A 3 ns Maximum Data Rate Dmax Y gt A 50 Mbps Channel to Channel Skew YA 2 3 5 ns Part to Part Skew 5 gt 2 ns Rev C Page 3 of 20 AD63308 AD63308 1 Param
7. 1 25 C 1 CHANNEL 6 Vcca 3 3V 5V 5 4 3 2 1 0 13 23 33 43 53 CAPACITIVE LOAD pF Figure 14 Icca vs Capacitive Load at Pin A for Y gt A 5 V3 3 V Level Translation 25 C 9 1 CHANNEL DATA RATE 50kbps Veca 1 2V Vccy 1 8 8 7 6 5 4 1 8V Vecy 3 3 3 2 F Veca 3 3V 5V 1 0 13 23 33 43 53 63 73 LOAD pF 04865 021 04865 023 Figure 15 Rise Time vs Capacitive Load at Pin Y A gt Y Level Translation FALL TIME ns TA 25 C 1 CHANNEL DATA RATE 50kbps Vcca 1 2V Vecy 33 43 53 CAPACITIVE LOAD pF 63 73 04865 024 Figure 16 Fall Time vs Capacitive Load at Pin Y A gt Y Level Translation Rev C Page 9 of 20 AD63308 AD63308 1 12 TA 25 C TA 25 C 1 CHANNEL 1 CHANNEL Veca 1 2 Vecy 1 8V DATA RATE 50kbps 20 DATA RATE 50kbps T 5 gt 8 T lt gt gt 56 a lt 4 a 4 9 n 2 0 8 13 23 33 43 53 63 5 LOAD pF 3 LOAD pF 3 Figure 17 Rise Time vs Capacitive Load at Pin A YA Level Translation
8. 15 pF when translating in the Y gt A direction Rev C Page 17 of 20 AD63308 AD63308 1 APPLICATIONS The ADG3308 ADG3308 1 ADG3308 2 are designed for digital circuits that operate at different supply voltages therefore logic level translation is required The lower voltage logic signals are connected to the A pins and the higher voltage logic signals to the Y pins The ADG3308 ADG3308 1 ADG3308 2 can provide level translation in both directions A gt Y or YA on all eight channels eliminating the need for a level translator IC for each direction The internal architecture allows the ADG3308 ADG3308 1 ADG3308 2 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made It also allows simultaneous data flow in both directions on the same part for example when two channels translate the AY direction while the other two translate in the Y gt A direction This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation Figure 40 shows an application where a 3 3 V microprocessor can read or write data to and from a 1 8 V peripheral device using an 8 bit bus ADG3308 ADG3308 1 ADG3308 2 MICROPROCESSOR MICROCONTROLLER DSP PERIPHERAL DEVICE 04865 056 Figure 40 1 8 V to 3 3 V 8 Bit Level Translation Circuit When the application requires level translation betw
9. ADG3308 1 ADG3308 2 consist of eight bidirectional channels Each channel can translate logic levels in either the gt or the Y gt A direction They use a one shot accelerator architecture ensuring excellent switching charac teristics Figure 39 shows a simplified block diagram of a bidirectional channel VccA Vccv lt 04865 053 Figure 39 Simplified Block Diagram of an ADG3308 ADG3308 1 ADG3308 2 Channel The logic level translation in the gt direction is performed using a level translator U1 and an inverter U2 whereas the translation in the Y gt A direction is performed using the U3 inverter and U4 inverter The one shot generator detects a rising or falling edge present on either the A side or the Y side of the channel It sends a short pulse that turns on the PMOS transistors T1and T2 for a rising edge or the NMOS transistors T3 and T4 for a falling edge This charges discharges the capacitive load faster resulting in fast rise and fall times The inputs of the unused channels A or Y should be tied to their corresponding Vcc rail Vcca Vccy or to GND INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3308 ADG3308 1 ADG3308 2 the circuit that drives the input of the device should be able to ensure rise fall times of less than 3 ns when driving a load consisting of a 6 resistor in parallel with the input capacitance of the ADG3308 ADG3308 1 ADG3308 2 channel OUTPUT LOAD
10. the 1 15 V to 5 5 V supply range 3 No direction pin 4 Packages 20 lead TSSOP and 20 lead LFCSP ADG3308 20 ball WLCSP ADG3308 1 and backside coated 20 ball WLCSP ADG3308 2 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 2007 Analog Devices Inc All rights reserved AD63308 AD63308 1 TABLE OF CONTENTS Features eee HL uer 1 Applications teet ote 1 Functional Block Diagram 1 General Description o eR E yh daya 1 Product Highlights seen 1 Revision History 2 Specifications soient tiii atento 3 Absolute Maximum Ratings eerte 6 ESD Caution ceret n ER ROO 6 Pin Configurations and Function Descriptions 7 Typical Performance Characteristics 8 Test CITCUIU 5 12 Terminology i2 e Ee 15 REVISION HISTORY 9 07 Rev B to Rev C Updated Outline Dimensions sse 19 7 07 Rev A to Rev B Added Backside Coated WLCSP Package Universal Changes to Input Driving Requirements Section 16 Updated Outline Dimensions seen 19 Changes to Ordering Guide sse 20 7 06 Rev 0 to Rev A Added WLCSP
11. ANALOG DEVICES Low Voltage 1 15 V to 5 5 V 8 Channel Bidirectional Logic Level Translators ADG3308 ADG3308 1 FEATURES Bidirectional logic level translation Operates from 1 15 V to 5 5 V Low quiescent current lt 1 pA No direction pin APPLICATIONS Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communication devices Telecommunications equipment Network switches and routers Storage systems SAN NAS Computing server applications GPS Portable POS systems Low cost serial interfaces GENERAL DESCRIPTION The ADG3308 AD G3308 1 ADG3308 2 are bidirectional level translators containing eight bidirectional channels They can be used in multivoltage digital system applications such as a data transfer between a low voltage DSP controller and a higher voltage device The internal architecture allows the device to perform bidirectional level translation without an additional signal to set the direction in which the translation takes place The voltage applied to Vcca sets the logic levels on the A side of the device and Vccy sets the levels on the Y side For proper operation Vcca must always be less than Vccy The Vcca compatible logic signals applied to the A side of the device appear as Vccy compatible levels on the Y side Similarly Vccy compatible logic levels applied to the Y side of the device appear as Vcca compatible logic levels the A side The enable pin E
12. Figure 20 Propagation Delay tpi vs Capacitive Load at Pin Y A gt Y Level Translation 4 0 25 C Ta 25 3 5 1 CHANNEL 1 CHANNEL RATE 50kbps DATA RATE 50kbps 3 0 T gt 25 5 Veca 1 2V Vccy 1 8V 20 Veca 1 8V Vccy 3 3V 2 j lt lt 15 9 Veca 3 3 5V 5 1 0 V YCCY x 0 5 0 g 13 18 23 28 33 38 43 48 53 13 18 23 28 33 38 43 48 53 CAPACITIVE LOAD pF 5 CAPACITIVE LOAD pF 3 Figure 18 Fall Time vs Capacitive Load at Pin A Y2A Level Translation Figure 21 Propagation Delay vs Capacitive Load at Pin A YA Level Translation 14 25 25 1 CHANNEL 1 CHANNEL 12 DATA RATE 50kbps DATA RATE 50kbps i j Veca 12V 1 8V Veca 1 2V Vccy 1 8V T T 10 a 8 a z z o o amp O 4 x x 2 0 5 8 13 23 33 43 53 63 3 13 18 23 28 33 38 43 48 53 9 LOAD pF s CAPACITIVE LOAD pF Figure 19 Propagation Delay vs Capacitive Load Figure 22 Propagation Delay teu vs Capacitive Load at Pin Y A gt Y Level Translation at Pin A gt Level Translation Rev C Page 10 of 20 ADG3308 AD63308 1 TA 25 C DATA RATE 25Mbps C 50pF 1 CHANNEL 25 50 C 15pF 1 CHANNEL 400mV DIV 5ns DIV 8 E 8 400mV DIV 3ns DIV 5 Figure 23 Eye Diagram at Y Output Figure 26 Eye Diagr
13. N provides three state operation on both the side and the Y side pins When the EN pin is pulled low the terminals on both sides of the device are in the high impedance state For normal operation EN should be driven high Rev C Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM VccA Vecy ADG3308 ADG3308 1 ADG3308 2 x E B t O O O O I O Q O A8 Q lt Y8 EN O i GND Figure 1 ADG3308 is available in a compact 20 lead TSSOP and a 20 lead LFCSP the ADG3308 1 is available in a 20 ball WLCSP and the ADG3308 2 is available in a backside coated 20 ball WLCSP The EN pin is referred to the Vccy supply voltage for the ADG3308 and to the Vcc supply voltage for the ADG3308 1 and ADG3308 2 The ADG3308 ADG3308 1 ADG3308 2 are guaranteed to operate over the 1 15 V to 5 5 V supply voltage range and the extended 40 C to 85 C temperature range PRODUCT HIGHLIGHTS l Bidirectional logic level translation 2 Fully guaranteed over
14. REQUIREMENTS The ADG3308 ADG3308 1 ADG3308 2 level translators are designed to drive CMOS compatible loads If current driving capability is required it is recommended to use buffers between the ADG3308 ADG3308 1 ADG3308 2 outputs and the load ENABLE OPERATION The ADG3308 ADG3308 1 ADG3308 2 provide three state operation at the A I O pins and the Y I O pins by using the enable EN pin as shown in Table 4 Table 4 Truth Table EN Y I O Pins A I O Pins 0 High Z High Z 1 Normal operation Normal operation 1 High impedance state 2 n normal operation the ADG3308 ADG3308 1 ADG3308 2 perform level translation When EN 0 the ADG3308 ADG3308 1 ADG3308 2 enter into three state mode In this mode the current consumption from both the Vcca and Vccy supplies is reduced allowing the user to save power which is critical especially in battery operated systems The EN input pin can only be driven with Vccy compatible logic levels for the ADG3308 whereas the ADG3308 1 ADG3308 2 can be driven with either Vcca or Vccy compatible logic levels POWER SUPPLIES For proper operation of the device the voltage applied to the Vcca must always be less than or equal to the voltage applied to To meet this condition the recommended power up sequence is Vccy first and then Vcca The ADG3308 ADG3308 1 ADG3308 2 operate properly only after both supply voltages reach their nominal values It is not recommended to use
15. RUZ 40 C to 85 C 20 Lead Thin Shrink Small Outline Package TSSOP RU 20 ADG3308BRUZ REEL 40 to 85 C 20 Lead Thin Shrink Small Outline Package TSSOP RU 20 ADG3308BRUZ REEL7 40 C to 85 C 20 Lead Thin Shrink Small Outline Package TSSOP RU 20 ADG3308BCPZ REEL 409 to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP VQ CP 20 1 ADG3308BCPZ REEL7 409 to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 20 1 ADG3308BCBZ 1 RL7 40 C to 85 C 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 2 ADG3308BCBZ 1 REEL 40 C to 85 C 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 2 ADG3308BCBZ 2 RL7 40 to 85 C Backside Coated 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 3 ADG3308BCBZ 2 REEL 40 C to 85 C Backside Coated 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 3 17 RoHS Compliant Part 2005 2007 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D04865 0 9 07 C ANALOG DEVICES Rev C Page 20 of 20 www analog com
16. TE Mbps Y gt A Level Translation 04865 005 04865 004 04865 006 Rev C Page 8 of 20 lccv mA Iccy mA Icca mA 25 C 1 CHANNEL C 15pF 35 40 45 DATA RATE Mbps Figure 8 Iccy vs Data Rate YA Level Translation TA 25 C 1 CHANNEL Veca 1 2 1 8V 0 13 23 33 43 53 CAPACITIVE LOAD pF Figure 9 Iccy vs Capacitive Load at Pin Y for AY 1 2 V gt 1 8 V Level Translation Ta 25 C 1 CHANNEL Veca 1 2V Vecy 1 8V CAPACITIVE LOAD pF Figure 10 Icca vs Capacitive Load at Pin for Y gt A 1 8 V gt 1 2 V Level Translation 04865 007 04865 012 04865 013 Iccy mA Icca mA Iccy mA 25 C 1 CHANNEL Veca 1 8V Vecy 3 3V CAPACITIVE LOAD pF Figure 11 Iccy vs Capacitive Load at Pin Y for A gt Y 1 8 V gt 3 3 V Level Translation 25 C 1 CHANNEL Vcca 1 8V Vecy 3 3V CAPACITIVE LOAD pF Figure 12 lcca vs Capacitive Load at Pin A for Y gt A 3 3 V gt 1 8 V Level Translation Ta 25 C 1 CHANNEL CAPACITIVE LOAD pF Figure 13 Iccy vs Capacitive Load at Pin Y for AY 3 3 V gt 5 V Level Translation 04865 016 04865 017 04865 020 Icca mA RISE TIME ns 10 ADG3308 AD63308
17. am at A Output 1 2 V gt 1 8 V Level Translation 25 Mbps 3 3 V gt 1 8 V Level Translation 50 Mbps TA 25 C C 50pF 25 C DATA RATE 25Mbps 1 CHANNEL DATA RATE 50Mbps C 50pF 1 CHANNEL 04865 038 04865 041 3ns DIV Figure 24 Eye Diagram at A Output Figure 27 Eye Diagram at Y Output 1 8 V gt 1 2 V Level Translation 25 Mbps 3 3 V gt 5 V Level Translation 50 Mbps TA 25 C C 50pF DATA RATE 50Mbps 1 CHANNEL 25 C DATA RATE 50Mbps C 15pF 1 CHANNEL 500mV DIV 3ns DIV 800mV DIV 3ns DIV Figure 25 Eye Diagram at Y Output Figure 28 Eye Diagram at A Output 1 8 V gt 3 3 V Level Translation 50 Mbps 5 V53 3 V Level Translation 50 Mbps 04865 039 04865 042 Rev C Page 11 of 20 ADG3308 ADG3308 1 TEST CIRCUITS ADG3308 ADG3308 1 ADG3308 2 ADG3308 ADG3308 1 ADG3308 2 lt 04865 047 04865 043 ADG3308 ADG3308 1 ADG3308 2 ADG3308 ADG3308 1 ADG3308 2 CAPACITANCE METER 04865 048 04865 044 ADG3308 ADG3308 1 ADG3308 2 ADG3308 ADG3308 1 ADG3308 2 CAPACITANCE METER 04865 045 04865 049 Figure 31 Three State Leakage Current at Pin Figure 35 Capacitance at Pin Y ADG3308 ADG3308 1 ADG3308 2 04865 046 Figure 32 Three State Leakage Current at Pin Y Rev C Page 12 of 20 ADG3308 AD63308 1 AY DIRECTION
18. een a microprocessor and multiple peripheral devices the ADG3308 ADG3308 1 ADG3308 2 I O pins can be three stated by setting EN 0 This feature allows the ADG3308 ADG3308 1 ADG3308 2 to share the data buses with other devices without causing contention issues Figure 41 shows an application where a 3 3 V microprocessor is connected to 1 8 V peripheral devices using the three state feature 100nF i 100nF ADG3308 ADG3308 1 ADG3308 2 BE wo 93 wo a dg 5 O44 268 55 899 0 5 x VOWS Y6 a 25 1 5 Y7 2 z o ADG3308 ADG3308 1 ADG3308 2 PERIPHERAL DEVICE 2 04865 055 Figure 41 1 8 V to 3 3 V Level Translation Circuit Using the Three State Feature LAYOUT GUIDELINES As with any high speed digital IC the printed circuit board layout is important in the overall performance of the circuit Care should be taken to ensure proper power supply bypass and return paths for the high speed signals Each Vcc pin Vcca and Vccy should be bypassed using low effective series resistance ESR and effective series inductance ESI capacitors placed as close as possible to the and Vccy pins The parasitic induc tance of the high speed signal track can cause significant overshoot This effect can be reduced by keeping the length of the tracks as short as possible A solid copper plane for the return path GND is also recommended Rev C Pa
19. eter Symbol Conditions Min Typ Max Unit 1 8V 0 15 V lt Vca Vay Vc 3 3 V 0 3 V A Y Level Translation Rs Rr 500 C 50 pF see Figure 37 Propagation Delay tp acy 8 11 ns Rise Time tr asy 2 5 ns Fall Time tr Ady 2 5 ns Maximum Data Rate Dmax A Y 50 Mbps Channel to Channel Skew tskew A gt Y 2 4 ns Part to Part Skew tPPSKEW A gt Y 4 ns Y gt A Level Translation Rs 500 15 pF see Figure 38 Propagation Delay te y gt a 5 8 ns Rise Time tR Y gt A 2 3 5 ns Fall Time tr Y gt A 2 3 5 ns Maximum Data Rate Dmax 50 Mbps Channel to Channel Skew tskew Y gt A 2 3 ns Part to Part Skew tPpskew Y gt A 3 ns 1 15V to 1 3 V lt Vcca Vey Vecy 3 3 V 0 3 V A Y Level Translation Rs Rr 500 50 pF see Figure 37 Propagation Delay tracy 9 18 ns Rise Time tR Asy 3 5 ns Fall Time tE Ady 2 5 ns Maximum Data Rate Dmax A Y 40 Mbps Channel to Channel Skew tskew A gt Y 2 5 ns Part to Part Skew tePskEW A Y 10 ns Y gt A Level Translation Rs 500 15 pF see Figure 38 Propagation Delay te Y5A 5 9 ns Rise Time tg Y gt A 2 4 ns Fall Time tr Y gt A 2 4 ns Maximum Data Rate DwAX Y gt A 40 Mbps Channel to Channel Skew tskEW YA 2 4 ns Part to Part Skew tePSKEW YA 4 ns 1 15V to 1 3 V lt Vcca Vecy Vy 1 8 V 0 3 V A Y Level Translation Rs Rr 500 50 pF see Figure 37 Propagation Delay 12 25 ns Rise Time tR Asy 7 12 ns Fall Time te asy 3 5 ns Maximum Data Rate Dmax
20. ge 18 of 20 ADG3308 AD63308 1 OUTLINE DIMENSIONS 6 40 BSC Sy 075 0 30 gt lt 0 60 contanaaiy 0 19 SEATING 0 45 0 1 PLANE COMPLIANT TO JEDEC STANDARDS MO 153 AC Figure 42 20 Lead Thin Shrink Small Outline Package TSSOP RU 20 Dimensions shown in millimeters PIN 1 INDICATOR ABTS E BOTTOM VIEW 4 00 EE 1 00 Je 065 0 85 0 05 MAX a n 205 Y 0 02 SEATING o Z 0 30 4 POPEAMARITY PLANE 0 23 0 20 REF 0 1 082207 B COMPLIANT TO JEDEC STANDARDS MO 220 VGGD 1 Figure 43 20 Lead Lead Frame Chip Scale Package LFCSP VO 4mm x 4 Body Very Thin Quad CP 20 1 Dimensions shown in millimeters Rev C Page 19 of 20 AD63308 AD63308 1 A1 BALL IDENTIFIER TOP VIEW BALL SIDE DOWN 0 65 0 53 256 2 50 244 0 50 BSC 244 PITCH 0 28 024 618 wlo NI N BOTTOM VIEW BALL SIDE UP Figure 44 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 2 Dimensions shown in millimeters 0 645 070606 A Bde 0 585 dn 0 525 2 00 0 042 194 0 040 0 037 A1 BALL IDENTIFIER 2 56 2 50 244 0 50 5 Ee Ei PITCH TOP VIEW i BOTTOM VIEW BALL SIDE DOWN 0 24 BALL SIDE UP a 20 Figure 45 Backside Coated 20 Ball Wafer Level Chip Scale Package WLCSP CB 20 3 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADG3308B
21. may be applied at any one time ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage a may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev C Page 6 of 20 ADG3308 AD63308 1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL a1 INDICATOR ADG3308 TOP VIEW Not to Scale ADG3308 TOP VIEW Not to Scale THE EXPOSED PAD CAN BE TIED TO 04865 002 GND OR IT CAN LEFT FLOATING 5 DO NOT TIE IT TO Veca OR Vccy 8 AGIS 1 TOP VIEW 04865 057 Not to Scale BALLS AT THE BOTTOM Figure 2 20 Lead TSSOP Figure 3 20 Lead LFCSP Figure 4 20 Ball WLCSP Table 3 Pin Function Descriptions Pin Ball No TSSOP LFCSP WLCSP Mnemonic Description 1 19 a4 Veca Power Supply Power supply voltage input for the A1 I O pin to the A8 I O pin 1 15 V Vcca lt Vccy 2 20 a3 A1 Input Output A1 Referenced to Vcca 3 1 b4 A2 Input Output A2 Referenced to Vcca 4 2 b3 A3 Input Output A3 Referenced to Vcca 5 3 c4 A4 Input Output A4 Referenced to Vcca 6 4 c3 A5 Input Output A5 Referenced to Vcca 7 5 d4 6 Input Output A6 Referenced to Vcca 8 6 d3 A7 Input Output A7 Referenced to Vcca 9 7 e4 A8 In
22. put Output 8 Referenced to Vcca 10 8 e3 EN Active High Enable Input 11 9 e2 GND Ground 12 10 1 Y8 Input Output Y8 Referenced to Vccv 13 11 d2 Y7 Input Output Y7 Referenced to Vccv 14 12 di Y6 Input Output Y6 Referenced to Vccv 15 13 c2 Y5 Input Output Y5 Referenced to Vccv 16 14 ci Y4 Input Output Y4 Referenced to Vccv 17 15 b2 Y3 Input Output Referenced to Vccy 18 16 b1 Y2 Input Output Y2 Referenced to Vccv 19 17 a2 Y1 Input Output Y1 Referenced to 20 18 al Vecy Power Supply Power supply voltage input for the Y1 I O pin to the Y8 I O pin 1 65 lt lt 5 5 V Rev C Page 7 of 20 AD63308 AD63308 1 TYPICAL PERFORMANCE CHARACTERISTICS Icca mA lccy mA Icca mA 1 0 Ta 25 C 1 CHANNEL 50pF 0 8 VccA 3 3V 5V 07 0 6 0 5 0 4 Veca 1 8 3 3 0 3 0 2 0 1 VccA 1 2V 1 8V 0 0 5 10 15 20 25 30 35 40 45 DATA RATE Mbps Figure 5 Icca vs Data Rate AY Level Translation 25 1 CHANNEL 50 C 50pF VccA 1 8V Vccy 1 2V Vecy Figure 6 Iccy vs Data Rate A gt Y Level Translation 25 C 1 CHANNEL C 15pF 15 20 25 30 DATA RATE Mbps 35 40 45 50 Figure 7 lcca vs Data Rate 15 20 25 30 DATA RA
23. the part in a system where during power up may be greater than Vccy due to a significant increase in the current taken from the Vcca supply For optimum performance the and Vccy pins should be decoupled to GND as close as possible to the device Rev C Page 16 of 20 ADG3308 AD63308 1 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the Vcca and supply voltage combination and the load capacitance It represents the maximum frequency of a square wave that can be applied to the I O pins ensuring that the device operates within the data sheet specifications in terms of output voltage Vor and Vou and power dissipation the junction temperature does not exceed the value specified under the Absolute Maximum Ratings section Table 5 shows the guaranteed data rates at which the ADG3308 ADG3308 1 ADG3308 2 can operate in both directions gt level translation or YA level translation for various Vcca and Vccy supply combinations Table 5 Guaranteed Data Rates Vecy Vcca 1 8 V 1 65 V to 1 95 V 2 5 V 2 3 V to 2 7 V 3 3 V 3 0 V to 3 6 V 5V 4 5 V to 5 5 V 1 2 V 1 15 V to 1 3 V 25 Mbps 30 Mbps 40 Mbps 40 Mbps 1 8 V 1 65 V to 1 95 V 45 Mbps 50 Mbps 50 Mbps 2 5 V 2 3 V to 27 V 60 Mbps 50 Mbps 3 3 V 3 0 V to 3 6 V 50 Mbps 5V 4 5 V to 5 5 V 1 The load capacitance used is 50 pF when translating the A gt Y direction and
24. y two channels when translating logic levels in the Y gt A direction tppsKEW Y gt A Difference in propagation delay between any one channel and the same channel on a different part under same driving loading conditions when translating in the Y gt A direction Voca Vcca supply voltage Voc Vccy supply voltage Icca Vcca supply current Iccv Vccy supply current Iucu z4 Vcca supply current during three state mode EN 0 Iuran zv Vccy supply current during three state mode EN 0 Rev C Page 15 of 20 AD63308 AD63308 1 THEORY OF OPERATION The ADG3308 ADG3308 1 ADG3308 2 level translators allow the level shifting necessary for data transfer in a system where multiple supply voltages are used The device requires two supplies and Vccy Vcca Vccx These supplies set the logic levels on each side of the device When driving the A pins the device translates the Vcc compatible logic levels to compatible logic levels available at the Y pins Similarly because the device is capable of bidirectional translation when driving the Y pins the Vccy compatible logic levels are translated to the Voca compatible logic levels available at the A pins When EN 0 the A1 pin to the A8 pin and the pin to the Y8 pin are three stated When EN is driven high the ADG3308 ADG3308 1 ADG3308 2 go into normal operation mode and perform level translation LEVEL TRANSLATOR ARCHITECTURE The ADG3308

ANALOG DEVICES Low Voltage 1.15 V to 5.5 V 8-Channel Bidirectional Logic Level Translators ADG3308/ADG3308-1 handbook

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