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AMIC A29L800A Series 1M X 8 Bit 512K X 16 Bit CMOS 3.0 Volt-only Boot Sector Flash Memory

1. Pb Free TFBGA A29L800AUG 90U 90U 48 48balTFBGA TFBGA AZ9L800AUG 90UF 90UF 48 48 ball Pb Free TFBGA Pb Free TFBGA Note U is for industrial SS temperature range 40 C to 85 C 1 is for industrial operating temperature range 25 C to 85 C June 2005 Version 1 1 32 AMIC Technology Corp AMIC A29L800A Series Package Information SOP 44L Outline Dimensions unit inches mm 0 010 Detail F He Ae 4 Fc Seating Plane ae exe wuoe ox zez 277 e eom ome 0020 os 0o40 oso Co 110 s 279 a e 7 Cua pep fan gi epe paseo Py pee Yoo Tos fe elel le Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension S includes end flash June 2005 Version 1 1 33 AMIC Technology Corp i AMIC A29L800A Series Package Information TSOP 48L Type I Outline Dimensions unit inches mm D gt 1 487 Lu 24 25 Detail A Detail A Dimensions in inches n Nom Max min Nom wex peor pim eo oo 94s eo o
2. Logical Inhibit Write cycles are inhibited by holding any one of OE Vi CE Vin or WE Vin To initiate a write cycle CE and WE must be a logical zero while OE isa logical one Power Up Write Inhibit If WE CE Vi and OE Vin during power up the device does not accept commands on the rising edge of WE The internal state machine is automatically reset to reading array data on the initial power up AMIC Technology Corp i AMIC Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations The Command Definitions table defines the valid register command sequences Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data All addresses are latched on the falling edge of WE or CE whichever happens later All data is latched on the rising edge of WE or CE whichever happens first Refer to the appropriate timing diagrams in the AC Characteristics section Reading Array Data The device is automatically set to reading array data after device power up No commands are required to retrieve data The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm After the device accepts an Erase Suspend command the device enters the Erase Suspend mode The system can read array data using the standard read timings except that if it reads at
3. 100 000 cycles 3 The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum byte program time listed If the maximum byte program time given is exceeded only then does the device set I Os 1 See the section on I Os for further information 4 In the pre programming step of the Embedded Erase algorithm all bytes are programmed to 001 before erasure 5 System level overhead is the time required to execute the four bus cycle command sequence for programming See Table 5 for further information on command definitions 6 The device has a guaranteed minimum erase and program cycle endurance of 10 000 cycles June 2005 Version 1 1 28 AMIC Technology Corp AMIC A29L800A Series Latch up Characteristics Tasers a Input Voltage with respect to VSS on all I O pins VCC 1 0V VCC Current 100 mA 100 mA Input voltage with respect to VSS on all pins except I O pins 1 0V 12 5V including A9 OE and RESET Includes all pins except VCC Test conditions VCC 5 0V one pin at time TSOP and SOP Pin Capacitance mee reme tm we om ee 3 eee Notes 1 Sampled not 100 tested 2 Test conditions Ta 25 C f 1 0MHz Data Retention Minimum Pattern Data Retention Time June 2005 Version 1 1 29 AMIC Technology Corp AMIC A29L800A Series T
4. 20 E 15 2 5 8 gt 10 e e gt o 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note Addresses are switching at 1MHz Icc1 Current vs Time Showing Active and Automatic Sleep Currents lt E E 2 5 O gt 2 Q gt o Frequency in MHz Note T 25 C Typical Icc1 vs Frequency June 2005 Version 1 1 19 AMIC Technology Corp A29L800A Series AC Characteristics Read Only Operations Ta 0 C to 70 C or 40 C to 85 C for 0 25 C to 85 C for 1 Parameter Symbols Description Test Setup Ee 11114 pue Hun Output Enable Hold toEH Time Note 1 Toggle and Data Polling teHoz Chip Enable to Output High Z LE Notes 1 ES Output Enable to Output oe Z oe 1 Output Hold Time from Addresses CE or adi OE Whichever Occurs First Note 1 Notes 1 Not 10096 tested 2 See Test Conditions and Test Setup for test specifications Timing Waveforms for Read Only Operation Addresses X Addresses Stable tacc z L Output Valid db High Z SS RESET June 2005 Version 1 1 20 AMIC Technology Corp AMIC A29L800A Series AC Characteristics Hardware Reset RESET Ta 0 C to 70 C or 40 C to 85 C for U 25 C to 85 C for T SHE Description Test Setup All Speed Options RESET Pin Low During Embedded Algorithms to Read or Write See Note me EMI SUI A 8
5. CMOS Compatible Ta 0 C to 70 C or 40 C to 85 C for U 25 C to 85 C for Parameter P is inti En s Symbol arameter Description est Description Typ Input Load Current Vin VSStovcc vcc vccMax ao m A9 Input Load Current VCC VCC Max A9 12 5V eee Output Leakage Current Vour VSStovec vcc vccMax T ao wA CE Vi OE Vi Byte Mode ILir ILo VCC Active Read Current Notes 1 2 CE Vit OE Vin Word Mode 16 2 VCC Active Write Program Erase E AE Current Notes 2 3 4 CE Vu OE Vin Icc3 VCC Standby Current Note 2 CE Vin RESET VCC 0 3V Icca VCC Standby Current During Reset RESET VSS 0 3V Note 2 lccs Automatic Sleep Mode Note 2 4 5 Vin VCC 0 3V Vi VSS 0 3V Temporary Unprotect Sector IL IH ID OL Output Low Voltage lo 4 0mA VCC VCC Min OH2 VoH1 V Output High Voltage Notes 1 The Icc current listed is typically less than 2 mA MHz with OE at Vin Typical VCC is 3 0V 2 Maximum Icc specifications are tested with VCC VCC max 3 Icc active while Embedded Algorithm program or erase is in progress 4 Automatic sleep mode enables the low power mode when addresses remain stable for tacc 30ns Typical sleep mode current is 200nA 5 Not 10096 tested Vi Vi Vi Vi June 2005 Version 1 1 18 AMIC Technology Corp A29L800A Series DC Characteristics continued Zero Power Flash 25
6. actively erasing or programming This includes programming in the Erase Suspend mode If the output is high Ready the device is ready to read array data including during the Erase Suspend mode or is in the standby mode Table 6 shows the outputs for RY BY Refer to RESET Timings Timing Waveforms for Program Operation and Timing Waveforms for Chip Sector Erase Operation for more information l Oe Toggle Bit I Toggle Bit on l Oe indicates whether an Embedded Program or Erase algorithm is in progress or complete or whether the device has entered the Erase Suspend mode Toggle Bit may be read at any address and is valid after the rising edge of the final WE pulse in the command sequence prior to the program or erase operation and during the sector erase time out During an Embedded Program or Erase algorithm operation successive read cycles to any address cause l Oe to toggle The system may use either OE or CE to control the read cycles When the operation is complete I Os stops toggling After an erase command sequence is written if all sectors selected for erasing are protected l Oe toggles for approximately 100us then returns to reading array data If not all selected sectors are protected the Embedded Erase algorithm erases the unprotected sectors and ignores the selected sectors that are protected The system can use I Os and 02 together to determine whether a sector is actively erasing or is
7. an address within erase suspended sectors the device outputs status data After completing a programming operation in the Erase Suspend mode the system may once again read array data with the same exception See Erase Suspend Erase Resume Commands for more information on this mode The system must issue the reset command to re enable the device for reading array data if I Os goes high or while in the autoselect mode See the Reset Command section next See also Requirements for Reading Array Data in the Device Bus Operations section for more information The Read Operations table provides the read parameters and Read Operation Timings diagram shows the timing diagram Reset Command Writing the reset command to the device resets the device to reading array data Address bits are don t care for this command The reset command may be written between the sequence cycles in an erase command sequence before erasing begins This resets the device to reading array data Once erasure begins however the device ignores reset commands until the operation is complete The reset command may be written between the sequence cycles in a program command sequence before programming begins This resets the device to reading array data also applies to programming in Erase Suspend mode Once programming begins however the device ignores reset commands until the operation is complete The reset command may be written between the sequence cycle
8. circuitry Write cycles also internally latch addresses and data needed for the programming and erase operations Reading data out of the device is similar to reading from other Flash or EPROM devices Device programming occurs by writing the proper program command sequence This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper program margin Device erasure occurs by executing the proper erase command sequence This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation During erase the device automatically times the erase pulse widths and verifies proper erase margin The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four The host system can detect whether a program or erase operation is complete by observing the RY BY pin or by reading the l Oz Data Polling and l Oe toggle status bits AMIC Technology Corp AMIC A29L800A Series After a program or erase cycle has been completed the device is ready to read array data or accept another command The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors The A29L800A is fully erased when shipped from the factory The Eras
9. determine the status of the erase operation by using l Oz I Os or l Oz See Write Operation Status for information on these status bits When the Embedded Erase algorithm is complete the device returns to reading array data and addresses are no longer latched Figure 2 illustrates the algorithm for the erase operation See the Erase Program Operations tables in AC Characteristics for parameters and to the Chip Sector Erase Operation Timings for timing waveforms Sector Erase Command Sequence Sector erase is a six bus cycle operation The sector erase command sequence is initiated by writing two unlock cycles followed by a set up command Two additional unlock write cycles are then followed by the address of the sector to be erased and the sector erase command The Command Definitions table shows the address and data requirements for the sector erase command sequence The device does not require the system to preprogram the memory prior to erase The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase The system is not required to provide any controls or timings during these operations After the command sequence is written a sector erase time out of 50us begins During the time out period additional sector addresses and sector erase commands may be written Loading the sector erase buffer may be done in any sequence and the number of sectors may be from o
10. erase suspended When the device is actively erasing that is the Embedded Erase algorithm is in progress I Os toggles When the device enters the Erase Suspend mode I Os stops toggling However the system must also use 02 to determine which sectors are erasing or erase suspended Alternatively the system can use 1 07 see the subsection on 07 Data Polling I Os also toggles during the erase suspend program mode and stops toggling once the Embedded Program algorithm is complete The Write Operation Status table shows the outputs for Toggle Bit on I Os Refer to Figure 4 for the toggle bit algorithm and to the Toggle Bit Timings figure in the AC Characteristics section for the timing diagram The l O2 vs l Oe figure shows the differences between l O2 and l Oe in graphical form See also the subsection on I 02 Toggle Bit II 1 02 Toggle Bit Il The Toggle Bit II on I Oz when used with l Oe indicates whether a particular sector is actively erasing that is the Embedded Erase algorithm is in progress or whether that sector is erase suspended Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence 1 02 toggles when the system reads at addresses within those sectors that have been selected for erasure The system may June 2005 Version 1 1 15 A29L800A Series use either OE or CE to control the read cycles But l O2 cannot distinguish whether the sector is actively er
11. the status bits on 1 07 l Oo Standard read cycle timings and Icc read specifications apply Refer to Write Operation Status for more information and to each AC Characteristics section for timing diagrams Standby Mode When the system is not reading or writing to the device it can place the device in the standby mode In this mode current consumption is greatly reduced and the outputs are placed in the high impedance state independent of the OE input The device enters the CMOS standby mode when the CE amp RESET pins are both held at VCC 0 3V Note that this is a more restricted voltage range than Vin If CE and RESET are held at Vin but not within VCC 0 3V the device will be in the standby mode but the standby current will be greater The device requires the standard access time tce before it is ready to read data If the device is deselected during erasure or programming the device draws active current until the operation is completed Iccz and Icca in the DC Characteristics tables represent the standby current specification Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption The device automatically enables this mode when addresses remain stable for tacc 30ns The automatic sleep mode is independent of the CE WE and OE control signals Standard address access timings provide new data when addresses are changed While in sleep mode output data is latched and always av
12. A Series AC Characteristics Erase and Program Operations Ta 0 C to 70 C or 40 C to 85 C for U 25 C to 85 C for l tavay e wc fwrite Write Cycle Time Noted 1 Time Note 1 pamm o 3 Dee emm f e 8 o8 o Dee sw jpesweme o ow p os os ee T _ tors Output Enable Setup Time Enable Setup Time 00 00 SE Recover Time Before Write EA high to WE low teu tes CE CE SewpTime o O Time Write Pulse Width High B i twawi twewia Programming Operation Note 2 mE RI s eeew9emen ee 71 e i Notes 1 Not 100 tested 2 See the Erase and Programming Performance section for more information June 2005 Version 1 1 23 AMIC Technology Corp AMIC A29L800A Series Timing Waveforms for Program Operation Program Command Sequence last two cycles Read Status Data last two cycles twc tas ii V NV us mu tAH CE OE WE RY BY tvcs pa u VCC Note 1 PA program addrss PD program data Dout is the true data at the program address 2 Illustration shows device in word mode Timing Waveforms for Chip Sector Erase Operation June 2005 Version 1 1 24 AMIC Technology Corp A29L800A Series Erase Command Sequence last two cycles Read Status Data lt lt GC 0h Ga 555h for chip erage mu un u Data 10
13. A29L800A Series 1M X 8 Bit 512K X 16 Bit CMOS 3 0 Volt only Boot Sector Flash Memory Document Title 1M X 8 Bit 512K X 16 Bit CMOS 3 0 Volt only Boot Sector Flash Memory Revision History Rev History Issue Date Remark 0 0 Initial issue September 27 2004 Preliminary 1 0 Change voltage range from 2 7V 3 6V to 3 0V 3 6V January 10 2005 Final Final version release 1 1 Change voltage range from 3 0V 3 6V back to 2 7V 3 6V June 24 2005 Add 70U series products June 2005 Version 1 1 AMIC Technology Corp A29L800A Series 1M X 8 Bit 512K X 16 Bit CMOS 3 0 Volt only Features W Single power supply operation Full voltage range 2 7 to 3 6 volt read and write operations for battery powered applications WM Access times 70 90 max W Current 9 mA typical active read current 20 mA typical program erase current 200 nA typical CMOS standby 200 nA Automatic Sleep Mode current W Flexible sector architecture 16 Kbyte 8 KbyteX2 32 Kbyte 64 KbyteX15 sectors 8 Kword 4 KwordX2 16 Kword 32 KwordX15 sectors Any combination of sectors can be erased Supports full chip erase Sector protection A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector W Extended operating temperature range 40 C 85 C for U series 25 C 85 C for series W Unlock Bypass Program Command Reduces overall programming time when issuing multiple
14. A29L800A Series Block Diagram RY BY l Oo 1 015 A 1 vss Input Output Erase Voltage Buffers Generator State Control Command Voltage Register Generator Chip Enable O VCC Detector A0 A18 Address Latch d a oO o o a D O D m x Pin Descriptions Write Enable Output Enable Pin not connected internally June 2005 Version 1 1 4 AMIC Technology Corp AMIC Absolute Maximum Ratings Storage Temperature Plastic Packages 65 C to 150 C Ambient Temperature with Power Applied 55 C to 125 C Voltage with Respect to Ground VCC Note 1 ee o dci 0 5V to 4 0V A9 OE amp RESET Note 2 0 5 to 12 5V All other pins Note 1 0 5V to VCC 0 5V Output Short Circuit Current Note 3 200mA Notes 1 Minimum DC voltage on input or I O pins is 0 5V During voltage transitions input or I O pins may undershoot VSS to 2 0V for periods of up to 20ns Maximum DC voltage on input and I O pins is VCC 0 5V During voltage transitions input or I O pins may overshoot to VCC 2 0V for periods up to 20ns 2 Minimum DC input voltage on A9 OE and RESET is 0 5V During voltage transitions A9 OE and RESET may overshoot VSS to 2 0V for periods of up to 20ns Maximum DC input voltage on A9 is 12 5V which may overshoot to 14 0V for periods up to 20ns 3 No more th
15. Algorithms to Read or Write See Note tee RESETPuseWidh Mn 0 a eaaa Min 0 y w o tREADY tRP tRH RESET High Time Before Read See Note 0 RY BY Recovery Time RESET Low to Standby Mode Note Not 100 tested ns ns RESET Timings RY BY CE OE tRH RESET tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY BY t tRB Ni CE OE RESET ll June 2005 Version 1 1 21 AMIC Technology Corp AMIC A29L800A Series AC Characteristics Word Byte Configuration BYTE Ta 0 C to 70 C or 40 C to 85 C for 0 25 C to 85 C for 1 met CE to BYTE Switching Low or High rea BYTE Switching Low to Output High Z L w BYTE Switching High to Output Active i BYTE Timings for Read Operations BYTE Data Output Data Output Switching 1 O0 O14 26 0 O0 1 07 from word to byte mode 4 tFLoz M tELEH BYTE f 2 Data Output Data Output BYTE O0 W O24 l Oo I O7 NN 00 1034 Switching from byte to 00 BYTE Timings for Write Operations EE CE WE gt The falling edge of the last WE signal BYTE yu x tas NE tHoLp taH Note Refer to the Erase Program Operations table for tas and tan specifications June 2005 Version 1 1 22 AMIC Technology Corp AMIC A29L800
16. Bypass mode to facilitate faster programming Once the device enters the Unlock Bypass mode only two write cycles are required to program a word or byte instead of four The Word Byte Program Command Sequence section has details on programming data to the device using both standard and Unlock Bypass command sequence An erase operation can erase one sector multiple sectors or the entire device The Sector Address Tables indicate the address range that each sector occupies A sector address consists of the address inputs required to uniquely select a sector See the Command Definitions section for details on erasing a sector or the entire chip or suspending resuming the erase operation After the system writes the autoselect command sequence the device enters the autoselect mode The system can then read autoselect codes from the internal register which is separate from the memory array on 07 00 Standard read cycle timings apply in this mode Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information Icc2 in the DC Characteristics table represents the active current specification for the write mode The AC June 2005 Version 1 1 6 A29L800A Series Characteristics section contains timing specification tables and timing diagrams for write operations Program and Erase Operation Status During an erase or program operation the system may check the status of the operation by reading
17. CE and OE pins to Vit CE is the power control and selects the device OE is the output control and gates array data to the output pins WE should remain at Vin all the time during read operation The BYTE pin determines whether the device outputs array data in words and bytes The internal state machine is set for reading array data upon device power up or after a hardware reset This ensures that no spurious alteration of the memory content occurs during the power transition No command is necessary in this mode to obtain array data Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs The device remains enabled for read access until the command register contents are altered See Reading Array Data for more information Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms Icc1 in the DC Characteristics table represents the active current specification for reading array data Writing Commands Command Sequences To write a command or command sequence which includes programming data to the device and erasing sectors of memory the system must drive WE and CE to Vi and OE to Vin For program operations the BYTE pin determines whether the device accepts program data in bytes or words Refer to Word Byte Configuration for more information The device features an Unlock
18. ailable to the system Icca in the DC Characteristics table represents the automatic sleep mode current specification Output Disable Mode When the OE input is at Viu output from the device is disabled The output pins are placed in the high impedance state RESET Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data When the system drives the RESET pin low for at least a period of tme the device immediately terminates any operation in progress tristates all data output pins and ignores all read write attempts for the duration of the RESET pulse The device also resets the internal state machine to reading array data The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity Current is reduced for the duration of the RESET pulse When RESET is held at VSS 0 3V the device draws CMOS standby current Icca If RESET is held at Vii but not within VSS 0 3V the standby current will be greater The RESET pin may be tied to the system reset circuitry A system reset would thus also reset the Flash memory enabling AMIC Technology Corp AMIC the system to read the boot up firmware from the Flash memory If RESET is asserted during a program or erase operation the RY BY pin remains a O busy until the internal reset operation is complete which requires a time treapy durin
19. an one output is shorted at a time Duration of the short circuit should not be greater than one second Device Bus Operations This section describes the requirements and use of the device bus operations which are initiated through the internal command register The command register itself does not occupy any addressable memory location The register is composed of latches that store the commands along with the address and data information needed to execute the A29L800A Series Comments Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device These are stress ratings only Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended Exposure to the absolute maximum rating conditions for extended periods may affect device reliability Operating Ranges Commercial C Devices Ambient Temperature Ta 00005 0 C to 70 C Extended Range Devices Ambient Temperature Ta For 15 5 25 C to 85 C For U Setrles ice sso aea mde os 40 C to 85 C VCC Supply Voltages VCC for all devices 2 7V to 3 6V Operating ranges define those limits between which the functionally of the device is guaranteed command The contents of the register serve as inputs to the internal state machine The s
20. asing or is erase suspended l Oe by comparison indicates whether the device is actively erasing or is in Erase Suspend but cannot distinguish which sectors are selected for erasure Thus both status bits are required for sector and mode information Refer to Table 6 to compare outputs for I Oz and l Oe Figure 4 shows the toggle bit algorithm in flowchart form and the section l Oz Toggle Bit II explains the algorithm See also the I Os Toggle Bit I subsection Refer to the Toggle Bit Timings figure for the toggle bit timing diagram The 1 02 vs I Os figure shows the differences between 02 and l Oe in graphical form Reading Toggle Bits l Oe 1 02 Refer to Figure 4 for the following discussion Whenever the system initially begins reading toggle bit status it must read l Oz l Oo at least twice in a row to determine whether a toggle bit is toggling Typically a system would note and store the value of the toggle bit after the first read After the second read the system would compare the new value of the toggle bit with the first If the toggle bit is not toggling the device has completed the program or erase operation The system can read array data on 1 07 l Oo on the following read cycle However if after the initial two read cycles the system determines that the toggle bit is still toggling the system also should note whether the value of I Os is high see the section on l Os If it is the system should then determi
21. e Suspend Erase Resume feature enables the user to put erase on hold for any period of time to read data from or program data to any other sector that is not selected for erasure True background erase can thus be achieved June 2005 Version 1 1 2 The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data The RESET pin may be tied to the system reset circuitry A system reset would thus also reset the device enabling the system microprocessor to read the boot up firmware from the Flash memory The device offers two power saving features When addresses have been stable for a specified amount of time the device enters the automatic sleep mode The system can also place the device into the standby mode Power consumption is greatly reduced in both these modes AMIC Technology Corp AMIC A29L800A Series Pin Configurations SOP TSOP I A18 A17 On AUN n gt B o A29L800AV A29L800A L E l Oss A 1 7 1 I Os O13 VOs 1 012 1 04 m TFBGA TFBGA Top View Balls Facing Down O 5 6 o ORO an A2 gt Ae 91 gt Oo gt Pp H 9 N amp O ORO NC 8 NC A5 A1 gt N 9 N Q 2 8 2 o o Q Q O O June 2005 Version 1 1 AMIC Technology Corp AMIC
22. e system detects I O7 has changed from the complement to true data it can read valid data at I O7 00 on the following read cycles This is because 07 may change asynchronously with l Oo I Os while Output Enable OE is asserted low The Data Polling Timings During Embedded Algorithms in the AC Characteristics section illustrates this Table 6 shows the outputs for Data Polling on l Oz Figure 3 shows the Data Polling algorithm June 2005 Version 1 1 14 A29L800A Series Read l Oz I Oo Address VA 1 07 Data Read 1 07 l Oo Address VA 1 07 Data No Note 1 VA Valid address for programming During a sector erase operation a valid address is an address within any sector selected for erasure During chip erase a valid address is any non protected sector address 2 1 07 should be rechecked even if I Os 1 because 1 O7 may change simultaneously with I Os Figure 3 Data Polling Algorithm AMIC Technology Corp RYIBY Read Busy The RY BY is a dedicated open drain output pin that indicates whether an Embedded algorithm is in progress or complete The RY BY status is valid after the rising edge of the final WE pulse in the command sequence Since RY BY is an open drain output several RY BY pins can be tied together in parallel with a pull up resistor to VCC The RY BY pin is not available on the 44 pin SOP package If the output is low Busy the device is
23. est Conditions Test Specifications Output Load o OE Load 1 TTL gate Output Load Capacitance C including jig capacitance 30300 pF Test Setup 3 3V 2 7 KQ Device Under Test Diodes IN3064 or Equivalent June 2005 Version 1 1 30 AMIC Technology Corp AMIC A29L800A Series Ordering Information Top Boot Sector Flash Access Time Active Read Program Erase Standby ns Current Current Current Package Typ mA Typ mA Typ uA A29L800ATM 70F 44Pin Pb Free SOP 48 ball Pb Free TFBGA Note U is for industrial operating temperature range 40 C to 85 C A29L800ATG 70UF 48 ball Pb Free TFBGA 1 is for industrial operating temperature range 25 C to 85 C June 2005 Version 1 1 31 AMIC Technology Corp AMIC A29L800A Series Ordering Information continued Bottom Boot Sector Flash Access Time Active Read Program Erase Standby ns Current Current Current Typ mA Typ mA Typ uA A29L800AUM 70F 44Pin Pb Free SOP A29L800AUG 70U 48 ball TFBGA A29L800AUG 70UF 48 ball Pb Free TFBGA A29LB00AUM 90F 90F 44Pin 44pin Pb Free SOP Free SOP A29L800AUV 90 90 48152 TSOP A29L800AUV 90F 90F 48Pin 48Pin Pb Free TSOP Free TSOP 8291800800 900 90U agpintsop TSOP A29L800AUV 20UF 90UF 48Pin 48Pin Pb Free TSOP Free TSOP A29L800AUG 90 90 48 48balTFBGA TFBGA A29LB00AUG 90F 90F 48 48 ball Pb Free TFBGA
24. g Embedded Algorithms The system can thus monitor RY BY to determine whether the reset operation is complete If Table 2 A29L800A Top Boot Block Sector Address Table 2 2 2 2 2 2 2 XxX XxX X 1 1 1 0 0 1 1 Po fe e pa e Note 2 2 2 2 2 2 2 2 2 2 2 2 gt lt 2 2 2 X 4291 8004 Series RESET is asserted when a program or erase operation is not executing RY BY pin is 1 the reset operation is completed within a time of 8 not during Embedded Algorithms The system can read data tru after the RESET pin return to Vin Refer to the AC Characteristics tables for RESET parameters and diagram Sector Size Kbytes Kwords 64 32 Address Range in hexadecimal Byte Mode x 8 Word Mode x16 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 32 16 8 4 8 4 16 8 Address range is A18 A 1 in byte mode and A18 AO in word mode See Word Byte Configuration section June 2005 Version 1 1 7 AMIC Technology Corp AMIC Table 3 A29L800A Bottom Boot Block Sector Address Table x lt Sector Size Kbytes Kwords A29L800A Series Address Range in hexadecimal By
25. h for chip erase RY BY tvcs VCC Note 1 SA Sector Address for Sector Erase VA Valid Address for reading status data see Write Operaion Ststus 2 Illustratin shows device in word mode June 2005 Version 1 1 25 AMIC Technology Corp Pi AMIC A29L800A Series Timing Waveforms for Data Polling During Embedded Algorithms 4 1 NEC 9C tac tcE toE OE Lem 1 07 Complement j3 u NN f V 1 Oo l Oe High Z sas baa u NN tBuUsY Sa RY BY Note VA Valid Address Illustation shows first status cycle after command sequence last status read cycle and array data read cycle June 2005 Version 1 1 26 AMIC Technology Corp AMIC A29L800A Series Timing Waveforms for Toggle Bit During Embedded Algorithms tRC Addresses I tacc gt CE tce gt tCH toE OE tOEH tDF WE toH Y l Oe 2 High Z Mi Valid Status N N NN t first read second read RY BY Note VA Valid Address not required for I Os Illustration shows first two status cycle after command sequence last status read cycle and array data read cycle Timing Waveforms for I O2 vs 06 Enter C NX y Valid Bas N a e stop togging Embedded Erase Enter Erase Erase Suspend Suspend Program Resume Erasing WE u u uU N 0 _ Erase Erase Era
26. ining address bits that are don t care When all necessary bits have been set as required the programming equipment may then read the corresponding identifier code on 1 07 l Oo To access the autoselect codes in system the host system can issue the autoselect command via the command register as shown in the Command Definitions table This method does not require Vin See Command Definitions for details on using the autoselect mode Table 4 A29L800A Autoselect Codes High Voltage Method Device ID A29L800A Top Boot Block Device ID A29L800A Bottom Boot Block Continuation ID Hardware Data Protection The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes refer to the Command Definitions table In addition the following hardware data protection measures prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during Vcc power up transitions or from system noise The device is powered up to read array data to avoid accidentally writing data to the array Write Pulse Glitch Protection Noise pulses of less than 5ns typical on OE CE or WE do not initiate a write cycle June 2005 Version 1 1 9 A12 A10 x x A11 to L Logic Low Vit H Logic High Vin SA Sector Address X Don t Care Note The autoselect codes may also be accessed in system via command sequences
27. les in the AC Characteristics section for parameters and to the Sector Erase Operations Timing diagram for timing waveforms Erase Suspend Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from or program data to any sector not selected for erasure This command is valid only during the sector erase operation including the 50us time out period during the sector erase command sequence The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm Writing the Erase Suspend command during the Sector Erase time out immediately terminates the time out period and suspends the erase operation Addresses are don t cares when writing the Erase Suspend command When the Erase Suspend command is written during a sector erase operation the device requires a maximum of 20us to suspend the erase operation However when the Erase Suspend command is written during the sector erase time out the device immediately terminates the time out period and suspends the erase operation After the erase operation has been suspended the system can read array data from or program data to any sector not selected for erasure The device erase suspends all sectors selected for erasure Normal read and write timings and command definitions apply Reading at any address within erase suspended sectors produces status data on 1 07 l Oo The s
28. n 020 oa oars 12 00 1210 0 020 BASIC 0 50 BASIC 0020 0024 040 oso 060 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension S includes end flash June 2005 Version 1 1 34 AMIC Technology Corp AMIC A29L800A Series Package Information 48LD CSP 6 x 8 mm Outline Dimensions unit mm 48TFBGA TOP VIEW BOTTOM VIEW oouUummocr 2 uoummo r 2 2 OO OO OOo i 123456 Ball A1 CORNER SIDE VIEW lt i C SEATING PLANE i E Dimensions in mm Symbol eee b oa 040 o ss 600 so b Le F E 75 2 00 17 June 2005 Version 1 1 35 AMIC Technology Corp
29. n accepted Table 6 shows the outputs for I Os Read l Oz l Oo Note 1 Toggle Bit Toggle Yes Read 1 07 I Oo Twice Notes 1 2 Toggle Bit Toggle v Program Erase Operation Not Program Erase Commplete Write Operation Complete Reset Command Notes 1 Read toggle bit twice to determine whether or not it is toggling See text 2 Recheck toggle bit because it may stop toggling as 1 Os changes to 1 See text Figure 4 Toggle Bit Algorithm June 2005 Version 1 1 16 AMIC Technology Corp Table 6 Write Operation Status 1 02 Note 1 No toggle A29L800A Series RYIBY 0 0 Standard Embedded Program Algorithm Mode Embedded Erase Algorithm 0 Erase Reading within Erase 1 Suspend Suspended Sector Mode Reading within Non Erase Suspended Sector Dela Data Erase Suspend Program Toggle Notes 1 1 07 and l O2 require a valid address when reading status information Refer to the appropriate subsection for further details 2 I Os switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits See 1 05 Exceeded Timing Limits for more information Maximum Negative Input Overshoot 0 8V 0 5V Maximum Positive Input Overshoot VCC42 0V p 43 VCC 0 5V 2 0V June 2005 Version 1 1 17 AMIC Technology Corp AMIC A29L800A Series DC Characteristics
30. ne again whether the toggle bit is toggling since the toggle bit may have stopped toggling just as I Os went high If the toggle bit is no longer toggling the device has successfully completed the program or erase operation If it is still toggling the device did not complete the operation successfully and the system must write the reset command to return to reading array data The remaining scenario is that the system initially determines that the toggle bit is toggling and I Os has not gone high The system may continue to monitor the toggle bit and l Os through successive read cycles determining the status as described in the previous paragraph Alternatively it may choose to perform other system tasks In this case the system must start at the beginning of the algorithm when it returns to determine the status of the operation top of Figure 4 I Os Exceeded Timing Limits l Os indicates whether the program or erase time has exceeded a specified internal pulse count limit Under these conditions I Os produces a 1 This is a failure condition that indicates the program or erase cycle was not successfully completed The l Os failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0 Only an erase operation can change a 0 back to a 1 Under this condition the device halts the operation and when the operation has exceeded the timing limits I Os produces a Ln Under bo
31. ne sector to all sectors The time between these additional cycles must be less than 50us otherwise the last address and command might not be accepted and erasure may begin It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted The interrupts can be re enabled after the last Sector Erase command is written If the time between additional sector erase commands can be assumed to be less than 50us the system need not monitor I O3 Any command other than Sector Erase or Erase Suspend during the time out period resets the device to reading array data The system must rewrite the command sequence and any additional sector addresses and commands The system can monitor l Os to determine if the sector erase timer has timed out See the I Os Sector Erase Timer AMIC Technology Corp AMIC section The time out begins from the rising edge of the final WE pulse in the command sequence Once the sector erase operation has begun only the Erase Suspend command is valid All other commands are ignored When the Embedded Erase algorithm is complete the device returns to reading array data and addresses are no longer latched The system can determine the status of the erase operation by using l Oz I Os or I Oz Refer to Write Operation Status for information on these status bits Figure 2 illustrates the algorithm for the erase operation Refer to the Erase Program Operations tab
32. ng array or autoselect data all bus cycles are write operation 4 Data bits I O15 I Os are don t care for unlock and command cycles 5 6 7 Autoselect Note 8 Address bits A18 A11 are don t cares for unlock and command cycles unless SA or PA required No unlock or command cycles required when reading array data The Reset command is required to return to reading array data when device is in the autoselect mode or if I Os goes high while the device is providing status data 8 The fourth cycle of the autoselect command sequence is a read cycle 9 The data is OOh for an unprotected sector and O1h for a protected sector See Autoselect Command Sequence for more information 10 The Unlock Bypass command is required prior to the Unlock Bypass Program command 11 The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode 12 The system may read and program in non erasing sectors or enter the autoselect mode when in the Erase Suspend mode 13 The Erase Resume command is valid only during the Erase Suspend mode June 2005 Version 1 1 13 AMIC Technology Corp AMIC Write Operation Status Several bits I Os I Os I Os I Oz RY BY are provided in the A29L800A to determine the status of a write operation Table 6 and the following subsections describe the functions of these status bits 1 07 I Os and RY BY each offer a method for determining whethe
33. program command sequence W Top or bottom boot block configurations available W Embedded Algorithms Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors General Description The A29L800A is an 8Mbit 3 0 volt only Flash memory organized as 1 048 576 bytes of 8 bits or 524 288 words of 16 bits each The 8 bits of data appear on I Oo I 07 the 16 bits of data appear on l Oo l O1s The A29L800A is offered in 48 ball TFBGA 44 pin SOP and 48 Pin TSOP packages This device is designed to be programmed in system with the standard system 3 0 volt VCC supply Additional 12 0 volt VPP is not required for in system write or erase operations However the A29L800A can also be programmed in standard EPROM programmers The A29L800A has the first toggle bit I Os which indicates whether an Embedded Program or Erase is in progress or it is in the Erase Suspend Besides the l Oe toggle bit the A29L800A has a second toggle bit I O2 to indicate whether the addressed sector is being selected for erase The A29L800A also offers the ability to program in the Erase Suspend mode The standard A29L800A offers access times of 70 and 90ns allowing high speed microprocessors to operate without wait states To eliminate bus contention the device has separate chip enable CE write enable WE and output enable OE controls The device requires only a single 3 0 volt power
34. r a program or erase operation is complete or in progress These three bits are discussed first I 07 Data Polling The Data Polling bit l Oz indicates to the host system whether an Embedded Algorithm is in progress or completed or whether the device is in Erase Suspend Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence During the Embedded Program algorithm the device outputs on 07 the complement of the datum programmed to 1 07 This O7 status also applies to programming during Erase Suspend When the Embedded Program algorithm is complete the device outputs the datum programmed to 1 07 The system must provide the program address to read valid status information on l Oz If a program address falls within a protected sector Data Polling on I O7 is active for approximately 2us then the device returns to reading array data During the Embedded Erase algorithm Data Polling produces a 0 on 07 When the Embedded Erase algorithm is complete or if the device enters the Erase Suspend mode Data Polling produces a 1 on l Or This is analogous to the complement true datum output described for the Embedded Program algorithm the erase function changes all the bits in a sector to 1 prior to this the device outputs the complement or O The system must provide an address within any of the sectors selected for erasure to read valid status information on 1 O7 When th
35. r erase command sequences 2 See I O3 Sector Erase Timer for more information Figure 2 Erase Operation AMIC Technology Corp A29L800A Series Table 5 A29L800A Command Definitions Gunimand Bus Cycles Notes 2 5 Sequence pal eun Fou Fh Note 1 Addr Data Addr Datal Addr Data Data Addr Exe Reset Reset Note7 si 7 11 Xxx FO Ex peee teje LL aiae a Dan Top Boot Block S AA ES 55 Bottom Boot Bloc Byte 555 xo2 9B Continuation ID AA 55 7F Word 555 2AA 555 ol T Word E 2AA ce Taaa sss 55 Aaa ee ee eee aS Wor 555 n E ET Byte e Wor 555 Sector Erase E Byte EI Erase Suspend Note 12 er EMEN ET a eM pem ESSE EE EIE Si Legend X Don t care RA Address of the memory location to be read RD Data read from location RA during read operation PA Address of the memory location to be programmed Addresses latch on the falling edge of the WE or CE pulse whichever happens later PD Data to be programmed at location PA Data latches on the rising edge of WE or CE pulse whichever happens first SA Address of the sector to be verified in autoselect mode or erased Address bits A18 A12 select a unique sector Note 1 See Table 1 for description of bus operations 2 All values are in hexadecimal 3 Except when readi
36. s in an autoselect command sequence Once in the autoselect mode the reset command must be written to return to reading array data also applies to autoselect during Erase Suspend If I Os goes high during a program or erase operation writing the reset command returns the device to reading array data also applies during Erase Suspend June 2005 Version 1 1 10 A29L800A Series Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes and determine whether or not a sector is protected The Command Definitions table shows the address and data requirements This method is an alternative to that shown in the Autoselect Codes High Voltage Method table which is intended for PROM programmers and requires Viv on address bit A9 The autoselect command sequence is initiated by writing two unlock cycles followed by the autoselect command The device then enters the autoselect mode and the system may read at any address any number of times without initiating another command sequence A read cycle at address XXOOh retrieves the manufacturer code and another read cycle at XXO3h retrieves the continuation code A read cycle at address XX01h returns the device code A read cycle containing a sector address SA and the address 02h in returns 01h if that sector is protected or OOh if it is unprotected Refer to the Sector Address tables for valid sector addresses The
37. se Suspend Suspend fase Suspend Erase Erase Read p Read Complete Program I O2 and l Oe toggle with OE and CE Note Both l Ose and l O2 toggle with OE or CE See the text on I Os and 1 02 in the section Write Operation Status for more information June 2005 Version 1 1 27 AMIC Technology Corp AMIC A29L800A Series Timing Waveforms for Alternate CE Controlled Write Operation PA for program 555 for program _ 5 for sector erase 2AA for erase 555 for chip erase Data Polling u eem A 8 E O 7 Xj tAH twH ac OE I tBUsY CE tcPH tws tps tDH Data tRH lt AO for program PD for program 55 for erase 30 for sector erase 10 for chip erase u RESET RY BY u Note 1 PA Program Address PD Program Data SA Sector Address I O 7 Complement of Data Input D out Array Data 2 Figure indicates the last two bus cycles of the command sequence Erase and Programming Performance Typ Note a max Note Commens 000 o oe fo oa ses Es oon pegemmina Byte Programming Time Word Programming Time ue Chip Programming Time Byte Mode 11 33 sec overhead Note 5 Note 3 Word Mode 7 2 21 6 sec Notes 1 Typical program and erase times assume the following conditions 25 C 3 0V VCC 10 000 cycles Additionally programming typically assumes checkerboard pattern 2 Under worst case conditions of 90 C VCC 2 7V
38. supply for both read and write functions Internally generated and regulated voltages are provided for the program and erase operations June 2005 Version 1 1 1 Boot Sector Flash Memory Embedded Program algorithm automatically writes and verifies data at specified addresses W Typical 100 000 program erase cycles per sector 20 year data retention at 125 C Reliable operation for the life of the system W Compatible with JEDEC standards Pinout and software compatible with single power supply Flash memory standard Superior inadvertent write protection W Data Polling and toggle bits Provides a software method of detecting completion of program or erase operations mW Ready BUSY pin RY BY Provides a hardware method of detecting completion of program or erase operations not available on 44 pin SOP W Erase Suspend Erase Resume Suspends a sector erase operation to read data from or program data to a non erasing sector then resumes the erase operation W Hardware reset pin RESET Hardware method to reset the device to reading array data W Package options 44 pin SOP or 48 pin TSOP I or 48 ball TFBGA The A29L800A is entirely software command set compatible with the JEDEC single power supply Flash standard Commands are written to the command register using standard microprocessor write timings Register contents serve as input to an internal state machine that controls the erase and programming
39. system must write the reset command to exit the autoselect mode and return to reading array data Word Byte Program Command Sequence The system may program the device by word or byte depending on the state of the BYTE pin Programming is a four bus cycle operation The program command sequence is initiated by writing two unlock write cycles followed by the program set up command The program address and data are written next which in turn initiate the Embedded Program algorithm The system is not required to provide further controls or timings The device automatically provides internally generated program pulses and verify the programmed cell margin Table 5 shows the address and data requirements for the byte program command sequence When the Embedded Program algorithm is complete the device then returns to reading array data and addresses are longer latched The system can determine the status of the program operation by using 1 07 I Os or RY BY See White Operation Status for information on these status bits Any commands written to the device during the Embedded Program Algorithm are ignored Note that a hardware reset immediately terminates the programming operation The Byte Program command sequence should be reinitiated once the device has reset to reading array data to ensure data integrity Programming is allowed in any sequence and across sector boundaries A bit cannot be programmed from a 0 back to a 1 At
40. tate machine outputs dictate the function of the device The appropriate device bus operations table lists the inputs and control levels required and the resulting output The following subsections describe each of these operations in further detail Table 1 A29L800A Device Bus Operations Operation RESET AO A18 l Oo I 07 Note 1 Read I Os 035 BYTE V BYTE V An 1 Os l O14 High Z AN 1 O15 A 1 CMOS Standby VCC 0 3V on VCC 0 3 V X Legend L Logic Low Vit H Logic High Vin Vip 12 0 0 5V X Don t Care Din Data In Dour Data Out Ain Address In Notes 1 Addresses are A18 A0 in word mode BYTE Vy A18 A4 in byte mode BYTE Vi 2 See the Sector Protection Unprotection section and Temporary Sector Unprotect for more information June 2005 Version 1 1 5 AMIC Technology Corp AMIC Word Byte Configuration The BYTE pin determines whether the I O pins 1 O15 I Oo operate in the byte or word configuration If the BYTE pin is set at logic 1 the device is in word configuration O15 I Oo are active and controlled by CE and OE If the BYTE pin is set at logic O the device is in byte configuration and only l Oo I Oz are active and controlled by CE and OE Os l O14 are tri stated and l Oss pin is used as an input for the LSB A 1 address function Requirements for Reading Array Data To read array data from the outputs the system must drive the
41. te Mode x 8 Word Mode x16 i x lt m 2 XxX 2 X x Xx Note ojlejo ejojej joj e 2 XK 26 2 26 2 2 25 X 1 o e 2 2 2 2 2 x Xx 64 32 40000h 4FFFFh 64 32 50000h 5FFFFh 28000 2FFFF 20000 27FFF XKqox x x X 2 25 2 64 32 64 32 64 32 D0000h DFFFFh 68000 6FFFF E0000h EFFFFh F0000h FFFFFh 78000 7FFFF 70000 77FFF Address range is A18 A4 in byte mode and A18 AO in word mode See Word Byte Configuration section June 2005 Version 1 1 AMIC Technology Corp AMIC Autoselect Mode The autoselect mode provides manufacturer and device identification through identifier codes output on 07 l Oo This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm However the autoselect codes can also be accessed in system through the command register When using programming equipment the autoselect mode requires Vip 11 5V to 12 5 V on address pin A9 Address pins A6 A1 and AO must be as shown in Autoselect Codes High Voltage Method table In addition when verifying sector protection the sector address must appear on the appropriate A29L800A Series highest order address bits Refer to the corresponding Sector Address Tables The Command Definitions table shows the rema
42. tempting to do so may halt the operation and set l O5 to 1 or cause the Data Polling algorithm to indicate the operation was successful However a succeeding read will show that the data is still 0 Only erase operations can convert a 0 to a 1 AMIC Technology Corp Write Program Command Sequence Data Poll from System Verify Data No Yes Last Address Yes Programming Completed Embedded Program algorithm in progress Increment Address Note See the appropriate Command Definitions table for program command sequence Figure 1 Program Operation Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence The unlock bypass command sequence is initiated by first writing two unlock cycles This is followed by a third write cycle containing the unlock bypass command 20h The device then enters the unlock bypass mode A two cycle unlock bypass program command sequence is all that is required to program in this mode The first cycle in this sequence contains the unlock bypass program command AOh the second cycle contains the program address and data Additional data is programmed in the same manner This mode dispenses with the initial two unlock cycles required in the standard program command sequence resulting in faster total programming time Table 5 shows
43. th these conditions the system must issue the reset command to return the device to reading array data AMIC Technology Corp i33 AMIC A29L800A Series 1 03 Sector Erase Timer After writing a sector erase command sequence the system may read l Os to determine whether or not an erase operation START has begun The sector erase timer does not apply to the chip erase command If additional sectors are selected for erasure the entire time out also applies after each additional sector erase command When the time out is complete 1 03 switches from 0 to 1 The system may ignore I Os if the system can guarantee that the time between additional sector erase commands will always be less than 50us See also the Sector Erase Command Sequence section After the sector erase command sequence is written the system should read the status on l Oz Data Polling or I Os NE Read l O7 l Oo Toggle Bit I to ensure the device has accepted the command sequence and then read l Os If I Os is 1 the internally controlled erase cycle has begun all further commands other than Erase Suspend are ignored until the erase operation is complete If I Os is O the device will accept additional sector erase commands To ensure the command has been accepted the system software should check the status of I Os prior to and following each subsequent sector erase command If I O3 is high on the second status check the last command might not have bee
44. the requirements for the command sequence During the unlock bypass mode only the Unlock Bypass Program and Unlock Bypass Reset commands are valid To exit the unlock bypass mode the system must issue the two cycle unlock bypass reset command sequence The first cycle must contain the data 90h the second cycle the data OOh June 2005 Version 1 1 11 A29L800A Series Addresses are don t care for both cycle The device returns to reading array data Figure 1 illustrates the algorithm for the program operation See the Erase Program Operations in AC Characteristics for parameters and to Program Operation Timings for timing diagrams Chip Erase Command Sequence Chip erase is a six bus cycle operation The chip erase command sequence is initiated by writing two unlock cycles followed by a set up command Two additional unlock write cycles are then followed by the chip erase command which in turn invokes the Embedded Erase algorithm The device does not require the system to preprogram prior to erase The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase The system is not required to provide any controls or timings during these operations The Command Definitions table shows the address and data requirements for the chip erase command sequence Any commands written to the chip during the Embedded Erase algorithm are ignored The system can
45. ystem can use l Oz or l Oe and l O2 together to determine if a sector is actively erasing or is erase suspended See Write Operation Status for information on these status bits After an erase suspended program operation is complete the system can once again read array data within non suspended sectors The system can determine the status of the program operation using the l Oz or l Oe status bits just as in the standard program operation See Write Operation Status for more information June 2005 Version 1 1 12 A29L800A Series The system may also write the autoselect command sequence when the device is in the Erase Suspend mode The device allows reading autoselect codes even at addresses within erasing sectors since the codes are not stored in the memory array When the device exits the autoselect mode the device reverts to the Erase Suspend mode and is ready for another valid operation See Autoselect Command Sequence for more information The system must write the Erase Resume command address bits are don t care to exit the erase suspend mode and continue the sector erase operation Further writes of the Resume command are ignored Another Erase Suspend command can be written after the device has resumed erasing Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress Erasure Completed Note 1 See the appropriate Command Definitions table fo

AMIC A29L800A Series 1M X 8 Bit 512K X 16 Bit CMOS 3.0 Volt-only Boot Sector Flash Memory

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