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Xicor XM28C040 Data Sheet

1. A47 amp A4 8 select one of four devices on the module DATA AA ADDR 5555 Ag A16 2AAA 80 AA 5555 5555 55 20 2AAA 5555 E E STANDARD OPERATING MODE 3873 FHD F16 Figure 9 Software Sequence to Deactivate Software Data Protection WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 3873 FHD F17 In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer the following six step algo rithm will reset the internal protection circuit After twc the device will be in standard operating mode SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be Will be steady steady May change Will change ES from LOW from LOW to HIGH to HIGH May change Will change ON from HIGH from HIGH to LOW to LOW Don t Care Changing OUI Changes State Not Allowed Known N A Center Line yk is High Impedance 28 040 SYSTEM CONSIDERATIONS Because the XM28C040 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where mul tiple I O pins share
2. The XM28C040 provides the same high endurance and data retention as the X28C010 PIN CONFIGURATION X28C010 Ag A16 l Og l Oz OE WE CE 8 25 XM28C040 9 24 X28C010 Ag 16 l Og Oz OE AE CE 3873 FHD F02 3873 FHD F01 1 Characteristics subject to change without notice 28 040 PIN DESCRIPTIONS Addresses Ag A4g The Address inputs select an 8 bit memory location during a read or write operation Chip Enable CE The Chip Enable input must be LOW to enable all read write operations When CE is HIGH power consumption is reduced see Note 4 Output Enable OE The Output Enable input controls the data output buffers and is used to initiate read operations Data In Data Out l Og 1 O Data is written to or read from the XM28C040 through the I O pins Write Enable WE The Write Enable input controls the writing of data to the XM28C040 PIN NAMES Symbol Description Ao A18 Address Inputs l Oo l Os Data Input Output WE Write Enable CE Chip Enable OE Output Enable Vcc 45V Vss Ground NC No Connect 3873 PGM TO1 28 040 DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW The read operation is terminated by either CE or OE returning HIGH This 2 line control architecture elimi nates bus contention in a system environment The data bus will be in a high impedance state when either OE or CE is HIGH Write
3. 1 V VoL Output LOW Voltage 0 4 V lo 2 1mA VoH Output HIGH Voltage 2 4 V 400u A 3873 PGM T02 2 POWER UP TIMING Symbol Parameter Typ t Units teun 2 Power up to Initiation of Read Operation 100 ms tpuw Power up to Initiation of Write Operation 5 ms 3873 CAPACITANCE T4 25 f 1MHz Vcc 5V Symbol Parameter Max Units Test Conditions Col Input Output Capacitance 50 pF OV Cin Input Capacitance 50 pF Vin OV Notes 1 Typical values are for TA 25 C and nominal supply voltage 2 This parameter is periodically sampled and not 100 tested 3873 104 1 28 040 A C CONDITIONS OF TEST MODE SELECTION Input Pulse Levels OV to 3V CE OE WE Mode Power Input Rise and L L H Read Dour Active Fall Times 10ns L H L Write Din Active Input and Output X X Standby and Write Inhibit High Z Standby Timing Levels 1 5V X L X Write Inhibit Output Load 1 TTL Gate and X X H Write Inhibit EN C 100pF 3873 PGM TO6 3873 105 1 A C CHARACTERISTICS XM28C040 TA 0 C to 75 C Vcc 5V 10 unless otherwise specified XM28C0401 TA 40 C to 85 C Voc 5V 10 unless otherwise specified XM28C040M 55 C to 125 C Vcc 5V 10 unless otherwise specified Read Cycle Limits
4. XM28C040 20 XM28C040 25 XM28C040 Symbol Parameter Min Max Min Max Min Max Units tRC Read Cycle Time 200 250 300 ns Chip Enable Access Time 200 250 300 ns taa Address Access Time 200 250 300 ns Output Enable Access Time 80 100 100 ns ttz CE Low to Active Output 0 0 0 ns to z OE Low to Active Output 0 0 0 ns tuz CE High to High Z Output 100 100 100 ns touz OE High to High Z Output 100 100 100 ns toH Output Hold From Address Change 0 0 0 ns 3873 107 Read Cycle gt ADDRESS CE OE oma I 00000 AA 3873 FHD F03 Note 3 thz and topz are measured from the point when CE or OE return high whichever occurs first to the time when the outputs are no longer driven 11 28 040 Write Cycle Limits ADDRESS DATA IN DATA OUT CY p WM WE Controlled Write CE Controlled Write 4 Symbol Parameter Min Min Max Units twc Write Cycle Time ms tas Address Setup Time 0 0 ns Address Hold Time 125 125 ns tcs Write Setup Time 25 0 ns tcH Write Hold Time 0 25 ns tcw CE Pulse Width 125 100 ns toes OE High Setup Time 10 10 ns toEH OE High Hold Time 10 35 ns twP WE Pulse Width 100 125 ns twPH WE High Recovery 100 100 ns tov Data Valid us tps Data Setup 50 50 ns tDH Data Hold 10 35 ns tpw Delay to Next Write 10 10 us tBL
5. C 65 to 150 C Respect to Ves Bede 1V to 47V D C Output Current 5mA Lead Temperature Soldering 10 seconds 300 C D C OPERATING CHARACTERISTICS COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating condi tions for extended periods may affect device reliability XM28C040 0 C to 70 C Vec 5V 10 unless otherwise specified 28 0401 T4 40 C to 85 C Voc 5V 10 unless otherwise specified XM28C040M 55 C to 125 C Vcc 5V 10 unless otherwise specified Limits Symbol Parameter Min Max Units Test Conditions lcc Vcc Current Active 80 mA Vii WE Vin TTL Inputs All I O s Open 1 Device Active Address Inputs TTL Levels f 5MHz IsB Vcc Current Standby 5 mA CE A17 A18 Vcc 0 3V All other inputs All Os OPEN Iu Input Leakage Current 10 uA Vss to 66 Output Leakage Current 10 uA Vout Vss to Vcc CE VIL Input LOW Voltage 1 0 8 V Input HIGH Voltage 2 Vcc
6. such an occurence Xicor s products are not authorized for use in critical components in life support devices or systems 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness 17
7. the same bus To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input Both OE and WE would then be common among all devices in the array For a read operation this assures that all deselected devices are in their standby mode and that only the selected device s is outputting data on the bus Because the XM28C040 has two power modes standby and active proper decoupling of the memory array is of prime concern Enabling CE will cause transient current spikes The magnitude of these spikes is dependent on the output capacitive loading of the I Os Therefore the larger the array sharing a common bus the larger the transient spikes The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors As a minimum it is recommended that a 0 1uF high fre quency ceramic capacitor be used between Vcc and Vss at each device Depending on the size of the array the value of the capacitor may have to be larger In addition it is recommended that a 4 7uF electrolytic bulk capacitor be place between Vcc and Vss for every two modules employed in the array This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces 28 040 ABSOLUTE MAXIMUM RATINGS Temperature under Bias Storage Temperature Voltage on any Pin with 65 to 135
8. C Byte Load Cycle 0 3 0 3 100 us 3873 108 1 WE Controlled Write Cycle two Ds gt lt HIGH Z 3873 FHD F04 Note 4 Due to the inclusion of the decoder IC on board the module the WE and CE write controlled timings will vary When utilizing the CE controlled write operation all the hold timings must be extended by the worst case propagation delay of the decoder For a WE controlled write operation CE must be a minimum 125ns to accommodate the additional setup time required 28 040 E Controlled Write Cycle two ADDRESS ____ KOO tas ee NONNA oman XXX ROO ips DH DATA OUT 3873 FHD F05 Page Write Cycle BYTE 0 BYTE 1 BYTE 2 BYTEn BYTE n 1 BYTE n 2 twe For each successive write within the page write operation A7 A48 should be the same or writes to an unknown address could occur 3873 FHD F06 28 040 DATA Polling Timing Diagram mores XXIX E 0 CE WE tOEH loEs OE 07 or or Dout X CES Pour X lt tw 3873 FHD F07 Toggle Bit Timing Diagram Xe Os HIGH 2 twc Starting and ending state of I Og will vary depending upon actual two 3873 FHD F08 28 040 MultiPlane Architecture The design of the XM28C040 h
9. Commercial 0 C to 70 Industrial 40 C to 85 C Military 55 C to 125 C MHR Military High Rel Blank 32 Lead Ceramic Module LIMITED WARRANTY Devices sold by Xicor Inc are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only Xicor Inc makes no warranty express statutory implied or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement Xicor Inc makes no warranty of merchantability or fitness for any purpose Xicor Inc reserves the right to discontinue production and change specifications and prices at any time and without notice Xicor Inc assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor Inc product No other circuits patents licenses are implied U S PATENTS Xicor products are covered by one or more of the following U S Patents 4 263 664 4 274 012 4 300 212 4 314 265 4 326 134 4 393 481 4 404 475 4 450 402 4 486 769 4 488 060 4 520 461 4 533 846 4 599 706 4 617 652 4 668 932 4 752 912 4 829 482 4 874 967 4 883 976 Foreign patents and additional patents pending LIFE RELATED POLICY In situations where semiconductor component failure may endanger life system designers using this product should design the system with appropriate error detection and correction redundancy and back up features to prevent
10. Write operations are initiated when both CE and WE are LOW and OE is HIGH The XM28C040 supports both a CE and WE controlled write cycle That is the address is latched by the falling edge of either CE or WE whichever occurs last Similarly the data is latched internally by the rising edge of either CE or WE which ever occurs first A byte write operation once initiated will automatically continue to completion typically within 5ms see Note 4 Page Write Operation The page write feature of the XM28C040 allows the entire memory to be written in 10 seconds Page write allows two to 256 bytes of data to be consecutively written to the XM28C040 prior to the commencement of the internal programming cycle The host can fetch data from another device within the system during a page write operation change the source address but the page address Ag through A4g for each subsequent valid write cycle to the part during this operation must be the same as the initial page address The page write mode can be initiated during any write operation Following the initial byte write cycle the host can write an additional one to 255 bytes in the same manner as the first byte was written Each successive byte load cycle started by the WE HIGH to LOW transition must begin within 100us of the falling edge of the preceding WE If a subsequent WE HIGH to LOW transition is not detected within 100us the internal automatic programming cycle will commen
11. array comprised of multiple XM28C040 memories that is frequently up dated The timing diagram in Figure 4 illustrates the sequence of events on the bus The software flow diagram in Figure 5 illustrates a method for testing the Toggle Bit 28 040 HARDWARE DATA PROTECTION The XM28C040 provides three hardware features that protect nonvolatile data from inadvertent writes Noise Protection A WE pulse less than 10ns will not initiate a write cycle Default Vcc Sense Alll functions are inhibited when Vec is 3V Write Inhibit Holding OE LOW will prevent an inad vertent write cycle during power up and power down SOFTWARE DATA PROTECTION The XM28C040 does provide the Software Data Protec tion SDP feature The module is shipped from Xicor with the Software Data Protection NOT ENABLED that is the module will be in the standard operating mode In this mode data should be protected during power up down operations through the use of external circuits The host system will then have open read and write access of the module once Vcc is stable The module canbe automatically protected during power up down without the need for external circuits by em ploying the SDP feature The internal SDP circuit is enabled after the first write operation utilizing the SDP command sequence When this feature is employed it will be easiest to incorporate in the system software if the module is viewed as a subsystem compos
12. as implemented a mul tiplane architecture That is there are four independent 128K x 8 memory spaces or planes each selected by its own chip enable input via the on board decoder chip This architecture can be utilized in a number of ways Separate Data and Program Memory Spaces The multiplane concept allows the system to write to one plane of the module and still be able to read continue executing code from the module utilizing any plane not performing a write operation This concept of separate data and program spaces can be expanded by providing a simple off module circuit that will disable writes to predetermined portions of memory A very basic version is shown in the Functional Diagram Whenever Aj is HIGH the WE input is forced HIGH write protecting one half the module This half would be reserved for read only program store while the other half would be available for read and write data store Expanded Sequential Page Lengths A standard system implementation would be decoding externally the module s chip enable and then wiring each address of the module to its corresponding ad dress line in the system This would effectively provide the system a memory organized as four separate memory planes with a sequential page address space of 256 bytes In an application such as data logging the most efficient method of logging the data is in a sequential manner If the data come in bursts that exceed 256 bytes in length alon
13. ce There is no page write window limitation Effectively the page write window is infinitely wide so long as the host continues to access the device within the byte load cycle time of 100us Write Operation Status Bits The XM28C040 provides the user two write operation status bits These can be used to optimize a system write cycle time The status bits are mapped onto the I O bus as shown in Figure 1 DATA Polling l O Figure 1 Status Bit Assignment N RESERVED TOGGLE BIT DATA POLLING 3873 FHD F09 The XM28C040 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed DATA Polling allows a simple bit test operation to determine the status of the XM28C040 eliminating additional interrupt inputs or external hardware During the internal programming cycle any attempt to read the last byte written will produce the complement of that data on 1 05 i e write data xxxx read data 1xxx xxxx Once the programming cycle is complete 1 05 will reflect true data Note Ifthe XM28C040 is inthe protected state and an illegal write operation is attempted DATA Polling will not operate Toggle Bit I Og The XM28C040 also provides another method for deter mining when the internal write cycle is complete During the internal programming cycle l Og will toggle from 1 to 0 and 0 to 1 on subsequent attempts to read the
14. ed This is accomplished by issuing a series of six write operations each write operation must conform to the data and address sequence illustrated in Figures 8 and 9 This is a nonvolatile operation and the host will have to wait a minimum twc before attempting to write new data 28 040 SOFTWARE DATA PROTECTION Figure 6 Timing Sequence Byte or Page Write DATA AA 55 AO ADDR 5555 2AAA 5555 Ag A16 A17 amp Aig select one of four devices on the module WRITES ae ae oe lt tBLC MAX gt BYTE Voc lt ov gt WRITE WG PROTECTED 3873 FHD F14 Figure 7 Write Sequence for Software Data Protection WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA TO ADDRESS 5555 BYTE PAGE LOAD ENABLED WRITE DATA XX TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS AFTER two RE ENTERS DATA PROTECTED STATE 3873 FHD F15 Regardless of whether the device has previously been protected or not once the software data protected algorithm is used and data has been written the device will automatically disable further writes unless another command is issued to cancel it If no further commands are issued the device will be write protected during power down and after any subsequent power up 28 040 RESETTING SOFTWARE DATA PROTECTION Figure 8 Reset Software Data Protection Timing Sequence
15. ed of four discrete memory devices with an address decoder see Func tional Diagram In this manner system memory map ping will extend onto the module That is the discrete memory ICs and decoder should be considered memory board components and SDP can be implemented at the component level as described in the next section SOFTWARE COMMAND SEQUENCE A4 and A4g are used by the decoder to select one of the four LCCs Therefore only one of the four memory devices can be accessed at one time In order to protect the entire module the command sequence must be issued separately to each device Enabling the software data protection mode requires the host system to issue a series of three write operations each write operation must conform to the data and address sequence illustrated in Figures 6 and 7 Because this involves writing to a nonvolatile bit the device will become protected after tyc has elapsed After this point in time devices will inhibit inadvertent write operations Once in the protected mode authorized writes may be performed by issuing the same command sequence that enables SDP immediately followed by the address data combination desired The command sequence opens the page write window enabling the host to write from one to 256 bytes of data Once the data has been written the device will automatically be returned to the protected state In order to facilitate testing of the devices the SDP mode can be deactivat
16. ger page might be desirable By swapping address lines externally the effective page length can be ex panded to 1024 bytes Refer to the table below for a matrix illustrating the various page length options TABLE 1 ADDRESS TRANSLATION MATRIX Module Address Inputs Effective Ao A7 Ag A16 A17 A18 Page Size No of Planes System 7 A8 A16 A17 A18 256 4 Address A0 A7 A9 A17 A8 A18 512 2 Lines A0 A7 A10 A18 A8 A9 1024 1 3873 PGM T09 Note The user should be aware the overall Icc of the module will increase as more individual components on the module are activated 28 040 PACKAGING INFORMATION 32 PIN DUAL IN LINE MODULE USING STRETCHED CERAMIC LEADLESS CHIP CARRIERS ON SIDE BRAZED CERAMIC SUBSTRATE PIN 1 1 610 40 89 1 590 40 39 L 0 020 0 51 S 100 005 0 016 0 41 2 54 13 P 1 508 38 30 1 492 37 90 TOL NON ACCUM 0 604 15 34 0 596 15 14 NOTES 1 ALL DIMENSIONS IN INCHES IN PARENTHESES IN MILLIMETERS 2 DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 ILL F47 28 040 ORDERING INFORMATION XM28C040 512K X 8 CMOS E PROM Module XM28C040 X X Device Access Time 20 200ns 25 250ns Blank 300ns Temperature Range Blank
17. last byte written When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations 28 040 DATA POLLING I O Figure 2 DATA Polling Bus Sequence LAST VIH WE S gt HIGH Z c Vou lt lt lt 4 E m READY 3873 FHD F10 Figure 3 DATA Polling Software Flow WRITE DATA NO WRITES COMPLETE YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS 107 COMPARE YES 3873 FHD F11 DATA Polling can effectively halve the time for writing to the XM28C040 The timing diagram in Figure 2 illus trates the sequence of events on the bus The software flow diagram in Figure 3 illustrates one method of implementing the routine 28 040 THE TOGGLE BIT I O Figure 4 Toggle Bit Bus Sequence LAST 6 We WRITE gt lt 0 Beginning and ending state of I Og will vary uez 1 READY 3873 FHD F12 Figure 5 Toggle Bit Software Flow COMPARE ACCUM WITH ADDR COMPARE OK LAST WRITE LOAD ACCUM FROM ADDR n YES READY 3873 FHD F13 The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling This can be especially helpful in an
18. z amp 18X 28C 040 Ny R3 4 Megabit Module XM28C040 512K x 8 Bit 5 Volt Byte Alterable E2PROM TYPICAL FEATURES High Density 4 Megabit 512K x 8 Module Access Time of 200ns at 55 C to 125 C Base Memory Component Xicor X28C010 Pinout Conforms to JEDEC Standard for 4 Megabit E7PROM Fast Write Cycle Times 256 Byte Page Write Early End of Write Detection DATA Polling Toggle Bit Polling Software Data Protection Three Temperature Ranges Commercial 0 C to 75 Industrial 40 to 85 C Military 55 to 125 High Rel Modules all Components are MIL STD 883 Compliant Endurance 100 000 Cycles FUNCTIONAL DIAGRAM X28C010 Ag A16 00 05 OE WE CE X28C010 Ag A16 l Og l Oz OE WE CE Xicor Inc 1991 1997 Patents Pending 3873 1 7 6 13 97 1 0 00 SH DESCRIPTION The XM28C040 is a high density 4 Megabit E PROM comprised of four X28C010 s mounted on a co fired multilayered ceramic substrate Individual components are 10096 tested prior to assembly in module form and then 10096 tested after assembly The XM28C040 is configured 512K x 8 bit The module supports a 256 byte page write operation This com bined with DATA Polling or Toggle Bit Polling effectively provides a 39us byte write cycle enabling the entire array to be rewritten in 10 seconds

Xicor XM28C040 Data Sheet

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