samsung KM29V64000TS/RS FLASH MEMORY handbook
Contents
1. 2nd half Page Register amp S A 64M 2M Bit NAND Fiash ARRAY 512 16 Byte x 16384 Latches amp Decoders Command C 1st half Page Register amp S A Y Gating amp High Voltage Generator Register I O Buffers amp Latches Vcc CE1 CE2 dem Control Logic RE Global Buffers WE CLE ALE WP RST Figure 2 ARRAY ORGANIZATION 1 Block 216 Row BK 256Byte 1 Page 528 Byte 1 Block 528B x 16 Pages 8K 256 Bytes 1 Device 528B x 16Pages x 1024 Blocks 64M 16K Rew 1024 Block 512B Column Matt tat woo vot Note Column Address Starting Address of the Register 00H Command Read Defines the starting Address of the 1st half of the Register 01H Command Read Defines the starting Address of the 2nd half of the Register A8 is initially set to Low or High by the or 01H Command X can be High or Low Column Address Row Address Page Address Advance information KM29V64000TS RS FLASH MEMORY PRODUCT INTRODUCTION The KM29V64000 a 66Mbit 69 206 016 bit memory organized as 16 384 rows by 528 columns A spare sixteen columns are located from column address of 512 to 527 A 528 byte data register is connected to memory cell arrays accommodating data transfer between the buffers and memory during page read and page program operations The memory array is made up2. A22 528 Byte Data Fail BLOCK ERASE The Erase operation can erase on a block BKByte basis Block address loading is accomplished in two cycles initiated by an Erase Setup command 80H Only address A13 to A22 is valid while to A12 is ignored The address of the block to be erased to FFH The Erase Confirm command DOH following the block address loading initiates the internal erasing process This two step sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noises conditions At the rising edge of WE after the erase confirm command input the internal write controller handles erase erase verity and pulse repetition where required If an erase operation error is detected the internal verity is halted and erase operation is terminated When the erase operation is complete the Write Status 0 be checked Figure 9 detail the sequence Figure 9 Block Erase Operation BERS DB OT et Pass VO 0 7 Add Input 2Cycle Block Add A9 A22 ERASE SUSPEND ERASE RESUME The Erase Suspend allows interruption during any erase operation in order to read or program data to or from another block of memory Once an erase process begins writing the Erase Suspend command to the command register suspends the internal erase process and the Ready Busy signal return to 1 Erase Suspend Status bit will be also set to 1 when the Status R
3. Sequential Row Read 1 Operation AG 0 7 CO0 Start Add 1st 2nd Nth 1H x 7 amp AQ 22 528Byte 528Byte SE L Command SE L 01H vod SE H 00H Command ist half array 2nd half arra Data Field Spare Field Data Field Spare Field Data Field Spare Field Advance Information KM29V64000TS RS FLASH MEMORY Figure 6 Sequential How Read 2 Operation SE fixed iow M O 0 7 Start Add 3Cycle Data Output 1st Nith amp AB A21 16Byte 16 A4 A7 Don t Care isthaif array 2nd half array Data Field Spare Field Figure 7 Gap less Sequential Read Operation SE fixed low emet iioii ie VO 0 7 Start Add 3Cycle Data Output 1st page end page Nth page A7 amp A9 A22 Data Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis but it does allow partial page program a byte or consecutive bytes up to 528 in a single page program cycle The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten The addressing may be done in random order in a block A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register followed by a nonvolatile programming period where th
4. Wi 3 Erase Suspend input to Ready 1 _ RE access time Read ID IREADD s RST pin low width Hardware reset 39 Device Resetting Time Read ProgranvErase atter erase suspend tRST A 5 10 500 5 Met E ware KC NE UNE 3 50 Co a o 50 tr R B 2 e Note 1 If CE goes high within 30ns after the rising edge of the last RE will not transition to VoL 2 The time to Ready depends on the value of the pull up resistor tied to R B pin 3 To break the sequential read cycle CE must be held high for longer than tCEH Program Erase Characteristics Parameter Program Time 384 Advance Information KM29V64000TS RS FLASH MEMORY Sequential Out Cycle after Read CLE L WE H ALE L Note Transition is measured 200mV from steady state voltage with load This parameter is sampled and not 100 tested Status Read Cycle CE ai 4 WE RE vo 0 7 c d ue 385 Advance Information KM29V64000TS RS FLASH MEMORY READ1 OPERATION READ ONE PAGE CLE _ ee tCEH CE ADF T pes pga Sigel 9950 1 007 7 01h Column Page Row Address Address ALE ZA 100ns y R B Busy READ1 OPERATION INTERCEPTED BY CE CLE WE tCHZ gt tAR2 ALE ya EU Os ZA og orem Aem j pouss Douna 0 7 E Page Row Address
5. the required Read Command or 50H should be input before serial page read cycle Table 2 STATUS REGISTER DEFINITION gt Led Reserved for Future em S VOS Erase Suspend READ ID The KM29V64000 contains a product identification mode initiated by writing 90H to the command register followed by an address input of OOH Two read cycles sequentially outputs the manufacturer code ECH and the device code E6H respectively The command register remains in Read ID mode until further commands are issued to it Figure 11 shows the operation sequence Program Erase Figure 11 Read ID Operation CLE CE Dui WE ALE RE tREADID 00 7 C Add 1 cycle Maker code Device code Advance Information KM29V64000TS RS FLASH MEMORY RESET The KM29V64000 offers a reset feature executed by writing FFH to the command register When the device is in Busy state during random read program or erase modes the reset operation will abort these operation The contents of memory cells being altered are no longer valid as the data will be partially programmed or erased Internal address registers are cleared to 076 and data registers to 1 s The command register is cleared to wait for the next command and the Status Register is cleared to value COH when WP is high Refer to table 3 for device status after reset operation I
6. 12 4 EE bo w whe Stand by Current CMOS 1882 CE Voc 0 2 WP SE OV Voc VIL VOL 3 gt 3 NENNEN Input Low Voltage Allinputs Vt 24 OutputLow Voltage Level Vo im 21mA O O Output Low Current R B 380 Advance Information KM29V64000TS RS FLASH MEMORY AC TEST CONDITION Note Ta 0 C to 70 C Vec 3 3Vt 1096 unless otherwise noted Input Pulse Level Input Rise and Fall Times 5 ns Input and Output Timing Levels 0 8V and 2 0V Output Load 1 GATE and CL 100 pF CAPACITANCE 25 C Voc 3 3V f 1 0 MHz Input Output mme Input Capacitance CIN VIN OV Note Capacitance is pericdically sampled and not 100 tested MODE SELECTION jour we vo rm px c i URL OR OC X H Ac u tsrseomatosos Dos Data Input Active Active Sequential Read amp Data Output Activa Active erate ali hy ts Pepa pot aos e Active px X X X X x x ne During Program Busy Notes 1 can be 2 WP should be biased to CMOS high or CMOS low for standby 3 When SE is high spare area is deselected Advance Information KM29V64000TS RS FLASH MEM
7. 257 Advance Information KM29V64000TS RS FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Temperature Under Bias Storage Temperature Short Circuit Output Current Notes 1 Minimum DC voltage is 0 3V an input output pins During transitions this level may undershoot to 2 0V for periods lt 30ns Maximum DC voltage on input output pins is Vcc40 5V which during transitions may overshoot to Vec 2 0V for periods 20ns 2 Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet Exposure to absolute maximum rating conditions for extended periods may affect device reliability RECOMMENDED OPE Parameter Supply Voltage DC AND OPERATING CHARACTERISTICS Recommended operating conditions otherwise noted Operating Sequential del tcycle 50ns Current Read tcycle 1 us Command lcc3 tcycle 50ns Address Input Data Input dec4 Hegister Head 1665 tcycle 50ns lout OMA p a m CE o a E 204 t coat tel eee ee Bt 1 5 CR i e Pr M 2 rod FEM tee aus M vn the wey one z NE 4 x 2
8. Address Advance Information KM29V64000TS RS FLASH MEMORY READ2 OPERATION READ ONE PAGE GLE CE WE twB a ZA ____ _ Vo LER Ae Ae erem rie HIM R B M Address Valid Address Selecied A4 A7 Don t Row 912 16 SEQUENTIAL ROW READ OPERATION Start address M CLE R B Busy Busy M LLL di utput E e Y 387 Advance Information KM29V64000TS RS FLASH MEMORY GAP LESS SEQUENTIAL READ OPERATION CLE M MM 1 I T3 output 1st Output PAGE PROGRAM OPERATION CLE CE tPROG ALE VO Keone ern OK Xen S Sequential Data Column 1 Input Command Address 22 up to 528 Byte Data rogram Read Status ess Sequential Input Command Command R B 1fQ0 0 Successful Program 1 O0 1 Error in program im Advance Information KM29V64000TS RS FLASH MEMORY BLOCK ERASE OPERATION ERASE ONE BLOCK E ALE ae RE CHA LY 1 LH L T R B Auto Black Erase Setup Erase Command Read Slatus Command Command VOOz1 Error in erase SUSPEND amp RESUME OPERATION DURING BLOCK ERASE WE CG 2 ALE RE tid Git Ov 2 2 Block Address tSF twa Program Read Suspend Functionare Resume acceptable ex 9 Successtut
9. Advance Information KM29V64000TS RS FLASH MEMORY 8M x 8 Bit NAND Flash Memory FEATURES GENERAL DESCRIPTION Single 3 3 volt Supply The KM29V64000TS RS is a 8M 8 388 608 x8 bit NAND Organization Flash memory with a spare 256K 262 144 x8 bit Its NAND Memory Cell Array 8M 128K bit x 8bit cell provides the most cost effective solution for the mass Data Register 512 16 bit x 8bit solid state storage market A program operation programs Automatic Program and Erase the 528 byte page in typically 200us and an erase Page Program 512 16 Byte operation can be performed in typically 4ms on either a Block Erase 8K 256 Byte 8K byte block Data in the page can be read out at 50ns Status Register cycle time per byte The I O pins serve as the ports for 528 Byte Page Read Operation address and data input output as well as command inputs Random Access 515 The on chip write controller automates all program and Serial Page Access 50 ns erase system functions including pulse repetition where Gap less Sequential read required and internal verify and margining of data Each Fast Write Cycle Time block can be programmed and erased a minimum of ten Program time 200us thousand cycles Howeven the write intensive systems can Block Erase time 4ms take advantage of the KM29V64000TS RS s extended Commnd Address Data Multiplexed I O port reliability of 1 000 000 program erase cycles by providing Hardware Data P
10. Erase operation however only the two row address cycles are used Device operations are selected by writing specific commands into the command register Table1 defines the specific commands of the KM29V64000 Table 1 COMMAND SETS Fun tion E MM Page Program Block Erase 60h Erase Suspend Note 1 The 00h Command defines starting Address on the 1st half of Registers The 01h Command defines starting Address on the 2nd of Registers After data access on the 2nd half of register by the 01H command the status pointer is automatically moved to the 1st half register OOH on the next cycle 2 The 50H command is valid only When the SE pin 40 is low level 378 Advance information KM29V64000TS RS FLASH MEMORY PIN DESCRIPTION Command Latch Enable CLE The CLE input controls the path activation for commands sent to the command register When active high commands are latched into the command register through the I O ports on the rising edge of the WE signal Address Latch Enable ALE The ALE input controls the path activation for address and input data to the internal address data registers Addresses are latched on the rising edge of WE with ALE high and input data is latched when ALE is low When the device is in the busy state during program or erase CE high does not return the device to standby mode Chip Enable CE The CE input is the device selection control When CE go
11. Frase Advance information KM29V64000TS RS FLASH MEMORY DEVICE OPERATION PAGE READ Upon initial device power up the KM29V64000 defaults to Read1 mode This operation is also initiated by writing to the command register along with three address cycles Once the command is latched it does not need to be written for the following page read operation Three types of operations are available random read serial page read and sequential row read The random read mode is enabled when the page address is changed The 528 bytes of data within the selected page are transferred to the data registers in less than 5us tR The CPU can detect the completion of this data transfer by analyzing the output of Ready Busy pin Once the data a page is loaded into the registers they may be read out in 50 5 cycle time by sequentially pulsing RE with CE staying low High to low transitions of the RE clock output the data starting from the selected column address up to the last column address column 511 or 527 depending on state of SE pin After the data of last column address is clocked out the next page is automatically selected for sequential row read Waiting 5us again allows for reading of the selected page By 02H command and 00H column address the KM29V64000 also support gab less sequential read operation that similar operation with normal sequential row read except do not need to wait tR 5us for reading the next page The sequential r
12. ORY A C Characteristics for Command Address Data Input Parameter WE High Hold Time 222210 ns Command Latch Cycle CLE c Z WE eee ALE m 22222222 109 tDH 382 Advance Information KM29V64000TS RS FLASH MEMORY Address Latch Cycle CLS CS two WE a tALS 105 tD tDS tDH AA ALE Input Data Latch Cycle tCLH tALS ALE JN pem tWP A WE NS voor KR KE an Advance Information KM29V64000TS RS FLASH MEMORY A C Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay Read register read na VS Vs vet as TRES ONE lei EM aet El ow A5 H tor 4 TI ane 4 Tjerk 4 Y Pe oki 100 RE Pulse Width tRC Read Cycle Time T Eno opan f em w Tompu o FE iw _ Last RE High to Busy at sequential rea _ TE High to Ready n case ot mercepsonoy cE tread CE High Hold Time at the last serial read ALE Setup Time Register Read ms FE Low to Status Output mso 5 Low to Status WE High to o
13. e toaded data is programmed into the appropriate cell The serial data loading period begins by inputting the Serial Data Input command 80H followed by the three cycle address input and then serial data loading The bytes other than those to be programmed do not need to be loaded The Page Program confirm command 10H initiates the programming process Writing 10H alone without previously entering the serial data will not initiate the programming process The internal write controller automatically executes the algorithms and timings necessary for program and verify thereby freeing the CPU for other tasks Once the program process starts the Read Status Register command may be entered with RE and CE low to read the status register The CPU can detect the completion of a program cycle by monitoring the Ready Busy output or the Status bit I O 6 of the Status Register Only the Read Status command and Reset command are valid while programming is in progress When the Page Program is complete the Write Status 0 may be checked Figure The internal write verify detects only errors for 1 s that are not successfully programmed to 0 5 The command register remains in Read Status command mode until another valid command is written to the command register Advance Information KM29V64000TS RS FLASH MEMORY Figure 8 Program amp Read Status Operation VO 0 7 Add amp Data Input 10H od Pass 7 amp A9
14. egister is read At this time blocks other than the suspended block can be read or programmed The Status Register and Ready Busy operation will function as usual After the Erase Resume command is written to it the erase process is restarted from the beginning of the erasing period The Erase Suspend Status bit and Ready Busy will return to 0 Refer to Figure 10 for operation sequence Figure 10 Erase Suspend amp Erase Resume Operation R B 7 08 Block Address input Erase Function Erase Function Erase Function Start Suspend Resume Advance information KM29V64000TS RS FLASH MEMORY READ STATUS The KM29V64000 contains a Status Register which can be read to find out whether program or erase operation is complete and whether the program or erase operation compteted successfully After writing 70H command to the command register a read cycle outputs the contents of the Status Register to the I O pins on the falling edge of CE or whichever occurs last This two line control allows the system to poll the progress of each device in multiple memory connections even when R B pins are common wired RE or CE does not need to be toggled for updated status Refer to table 2 for specific Status Register definitions The command register remains in Status Read mode until further commands are issued to it Therefore if the Status Register is read during a random read cycle
15. es high during a read operation the device is returned to standby mode However when the device is in the busy state during program or erase CE high is ignored and does not return the device to standby mode Write Enable WE The WE input controls writes to the I O port Commands address and data are latched on the rising edge of the WE pulse Read Enable RE The RE input is the serial data out control and when active drives the data onto the I O bus Data is valid tREA after the falling edge of RE which also increments the internal cotumn address counter by one Spear Area Enable SE The SE input is the spear area control and when high deselects the spare area during Read1 Sequential data input and Page program Port 0 7 The pins are used to input command address and data and to outputs data during read operations The pins float to high z when the chip ts deselected or the outputs are disabled Write Protected WP The WP pin provides inadvertent write erase protection during power transitions The internal high voltage generator is reset when the WP pin is active low Ready Busy R B The R B output indicates the status of the device operation When low it indicates that a program erase or random read operation is in process and return to high state upon completion It is an open drain output and does not float to high z condition when the chip is deselected or outputs are disabled
16. f the device is already in reset state a new reset command will not be accepted to by the command register The Ready Busy pin transitions to low for tRST after the Reset command is written Reset command is not necessarily for normal operation Refer to Figure 12 below Figure 12 RESET Operation tRST RR 00 7 Table 3 DEVICE STATUS Address Register 0 1 Data Register Al 1 Operation Mode Head 1 Waiting for next command READY BUSY The KM29V64000 has a Ready Busy output that provides a hardware method of indicating the completion of a page program erase and random read completion The R B is normally high but transitions to low after program or erase command is written to the command register or random read is begin after address loading It returns to high when the internal controller has finished the operation The pin is an open drain driver thereby allowing two or more Ready Busy outputs to be Or tied appropriate pull up resister is required for proper operation and the value may be calculated by following equation Vcc Max Va Max 3 2V loc 210 8 2 where 1 is the sum of the input currents of all devices tied to the Ready Busy pin Ready Busy open drain output i I L Device Advance information KM29V64000TS RS FLASH MEMORY DATA PROTECTION The KM29V64000 has a write protect pin WP to provide protection from any accidental w
17. of 16 cells that are serially connected to form a NAND structure Each of the 16 cells reside in a different page A block consists of the 16 pages formed by one NAND structures totaling 528 NAND structures of 16 cells The array organization is shown in Figure 2 The program and read operations are executed on a page basis while the erase operation is executed on block basis The memory array consists of 512 separately or grouped erasable 8K byte blocks It indicate that the bit by bit erase operation is prohibited on the KM29V64000 The KM29V64000 has addresses multiplexed into 8 I O s This scheme dramatically reduces pin counts and allows system upgrades to future higher densities by maintaining consistency in system board design Command address and data are all written through I O s by bringing WE to low while CE is low Data is latched on the rising edge of WE Command Latch Enable CLE and Address Latch Enable ALE are used to multiplex and address respectively via the I O pins All commands require one bus cycle except for Block Erase command which requires two cycles a cycle for erase setup and another for erase execution after block address loading The 8M byte physical space requires 23 addresses thereby requiring three cycles for byte level addressing column address low row address and high row address in that order Page Read and Page Program need the same three address cycles following the required command input In Block
18. ow read operation is terminated by bringing CE high The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area The spare area of bytes 512 to 527 may be selectively accessed by writing the Head 2 command with SE pin low level Address AO to A3 set the starting address of the spare area while addresses A4 to A7 are ignored Unless the operation is aborted the page address is automatically incremented for sequential row read as in Read 1 operation and spare sixteen bytes of each page may be sequentially read The Read 1 command 00H 01H is needed to move the pointer back to the main area Figure 3 thru 6 show typical sequence and timings for each read operation Figure 3 Read 1 Operation ALE 4 DE ROME VO 0 7 Start Add 3Cycle Data Output Sequential 01H 0 7 8 A9 A22 00H Command 01H Command 1st half array 2nd half array 1st half array 2nd half array gt Data Field Spare Field Data Field Spare Field After data access on 2nd half array by 01H command the start pointer is automatically moved to 1st half array OOH at next cycle Advance Information KM29V64000TS RS FLASH MEMORY Figure 4 Read 2 Operation CLE ALE R B RT s RELL 0 7 Start Add 3Cycle Data Output Sequential amp A9 22 Spare Field AT Don t Care Data Field Spare Field Figure 5
19. rite operation during power transition During device power up the WP should be at Vil until Vcc reaches approximately 3 0 during power down should be at when Vcc falls below 3 0V Refer to Figure 14 below Figure 14 AC WAVEFORMS for POWER TRANSITIONS 3 3V 10 3 0V 3 0 VCC High WP gt RE High or Low 7 WE Litt gt ALE Don t care Don t care CLE 396 PACKAGE DIMENSIONS Unit mm inch 44 40 TSOP2 400F 11 76 2 0 20 0 463 0 008 11 6 0 20 0 463 0 008 0 10 0 15 005 0094 9 006 002 443
20. rotection either ECC Error Checking and Correction or real time Program Erase Lockout During Power Transitions mapping out algorithm These algorithms have been Reliable CMOS Floating Gate Technology implemented in many mass storage applications and also Endurance 1M Program Erase Cycles the spare 16 bytes of a page combined with the other 512 Data Retention 10 years bytes can be utilized by system level ECC Command Register Operation The KM29V64000TS RS is an optimum solution for large 44 40 Lead TSOP Type II 400 mil 0 8 mm pitch nonvolatile storage application such as solid state storage digital voice recorder digitai still camera and other portable applications requiring nonvolatility PIN CONFIGURATION 10 7 Vss 2 CE r7 2 CLE 3 FRE 3 ALE 4 8 4 WE 5 5 WP 6 N C 6 7 N C 7 N C 8 N C 8 N C 9 N C 9 aj N C N C NC NC e N C N C N C N C N C N C 07 106 LW 1 5 04 Lo OS vec vss 44 40 TSOP II 44 40 TSOP II STANDARD TYPE REVERSE TYPE Notes Connect all Vcc and Vss pins of each device to power supply outputs Do NOT leave Vcc or Vss disconnected PSN SUNG Advance Information KM29V64000TS RS FLASH MEMORY sl Lu Figure 1 FUNCTIONAL BLOCK DIAGRAM Vcc Vss 9 A22 X Buffers Latches amp Decoders A0 A7 Y Buffers E
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samsung KM29V64000TS/RS FLASH MEMORY handbook