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BSI BS62UV2006 Ultra Low Power/Voltage CMOS SRAM 256K X 8 bit

1. Vcc 0 2V or CE2 lt 0 2V 2 Vec 0 2VorVin 0 2V TYP MAX Vcc for Data Retention CE1 Vcc 0 2VorCE2 0 27 EENEG Vin Vec 0 2VorVin 0 2V Chip Deselect to Data Retention Time See Retention Waveform Operation Recovery Time 1 Vcc 1 0V Ta 25 C 2 tko Read Cycle Time 3 IccDR is 0 7UA at TA 70 C E LOW Vec DATA RETENTION WAVEFORM 1 CE1 Controlled Data Retention Mode gt Vec y Vor gt 1 0V SE k Le y SE CE1 gt Vcc 0 2V Sr EE E LOW Vec DATA RETENTION WAVEFORM 2 CE2 Controlled lt Data Retention Mode gt Vcc Veco Vor 1 0V Ver t CDR lt t R CE2 E vu CE2 lt 0 27 Vu R0201 BS62UV2006 3 Revision 1 1 Jan 2004 TE d BSI BAC TEST CONDITIONS Test Load and Input Output Reference m AC ELECTRICAL CHARACTERISTICS TA 40 C to 85 C Input Pulse Levels Vcc OV Input Rise and Fall Times 1V ns Input and Output Timing Reference Level 0 5Vcc Output Load 100pF 1TTL CL 30pF 1TTL BS62UV2006 m KEY TO SWITCHING WAVEFORMS WAVEFORM MUST BE STEADY MAY CHANGE FROMH TOL MAY CHANGE FROML TOH DON T CARE ANY CHANGE PERMITTED DOES NOT APPLY INPUTS OUTPUTS MUST BE STEADY WILL BE CHANGE FROMH TOL WILL BE CHANGE FROML TOH CHANGE STATE UNKNOWN C
2. 10 0 10 A W El OS lolala eZl BI WITH PLATING Seating Plane aly p BASE METAL bl SECTION A A SOP 32 R0201 BS62UV2006 9 Revision 1 1 Jan 2004
3. Revision 1 1 Jan 2004 TE SIT BSI m DC ELECTRICAL CHARACTERISTICS TA 40 C to 85 C PARAMETER NAME PARAMETER TEST CONDITIONS BS62UV2006 VIL Guaranteed Input Low Voltage Vec 2 0V Vec 3 0V VIH Guaranteed Input High Voltage Vec 2 0V Vec 3 0V Input Leakage Current Vcc Max Vin OV to Vcc Output Leakage Current Vcc Max CE1 Mm or CE2 Vi or OE Vm Vio OV to Vcc Vcc Max lo 0 14mMA Vec 2 0V Output Low Voltage Vcc Max lo 2 0mA Vec 3 0V Vcc Min lon 0 1MA Vec 2 0V Output High Voltage Vcc Min lon 1 0mMA Vec 3 0V Operating Power Supply Current Vcc Max CE1 Vi CE2 Vin loa OMA F Fmax Vec 2 0V Vec 3 0V Vcc Max CE1 Vu or CE2 Vi lba OMA Vcc Max CE1 Vcc 0 2V or CE2 lt 0 2V Vcc 0 2V or Vin lt 0 2V Vec 2 0V Standby Current TTL Vec 3 0V Vec 2 0V Iccsp1 Standby Current CMOS Vec 3 0V 1 Typical characteristics are at TA 25 C 2 These are absolute values with respect to device ground and all overshoots due to system or tester notice are included 3 Fmax 1 ta 4 IecsB1 is 2 0UA 3 0UA at Vec 2 0V 3 0V and TA 70 C 5 1 5V for pulse width less than 30ns m DATA RETENTION CHARACTERISTICS TA 40 C to 85 C SYMBOL PARAMETER TEST CONDITIONS
4. STSOP and 8mmx20mm TSOP e Automatic power down when chip is deselected e Three state outputs and TTL compatible e Fully static operation m PRODUCT FAMILY SPEED POWER DISSIPATION STANDBY Operating e E il 9 DI weem EE SEH Vec 3 0V Vec 2 0V Vec 3 0V Vec 2 0V BS62UV2006DC DICE BS62UV2006TC o o 3 0 11 Si mA 8mA BS62UV2006STC eS pet 831190 STSOP 32 BS62UV2006SC BS62UV2006DI BS62UV2006TI o o BS62UV2006STI 40 C to 85 C 1 9V 3 6V 85 100 STSOP 32 BS62UV2006SI m PIN CONFIGURATIONS E BLOCK DIAGRAM A11 10 32h OE A9 31 Aug A8 30H CET o4 A134 29 0 7 WE CS 2815 DQ6 o4 CE2 Clg 271 pas Address Memory Array A15 o7 BS62UV2006TC 26 DQ4 o Row vec CIS BS62UV2006STC 255 DQ3 Input A17 o9 BS62UV2006TI 2415 GND o 1024 x 2048 Aug 10 BS62UV2006STI 23H paz O Buffer Decoder A14 11 22 pai Ken A12 12 21 pao D A7 13 201 AO o oe 3 A4 6 17 A3 8 Column I O A17 10 32 vec Beste A16 2 31 A15 A14 3 CE2 A12 4 SG WE 3 256 A7 AG 2 SS a Column Decoder AS 7 BS62UV2006SC 26 AQ i A4 8 BS62UV2006SI 25 A11 9 24 OE Control A2 10 23 A10
5. in the output state Then the data input signals of opposite phase to the outputs must not be applied to them 10 The parameter is guaranteed but not 100 tested 11 Tcowis measured from the later of CE1 going low or CE2 going high to the end of write OO N DD R0201 BS62UV2006 7 Revision 1 1 Jan 2004 m ORDERING INFORMATION BS62UV2006 X X Z YY Note BS62UV2006 SPEED 85 85ns 10 100ns PKG MATERIAL Normal G Green P Pb free GRADE C 0 C 70 C 40 C 85 C PACKAGE S SOP T TSOP 8mm x 20mm ST Small TSOP 8mm x 13 4mm D DICE BSI Brilliance Semiconductor Inc assumes no responsibility for the application or use of any product or circuit described herein BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death including life support systems and critical medical instruments m PACKAGE DIMENSIONS R0201 BS62UV2006 STSOP 32 1 Ce GAUGE PLANE Bac INCH MM A 0 0433 0 004 1 10 0 10 Al 0 0044 0 002 0 10 0 05 A2 0 039 0 002 1 00 0 05 0 009 0 002 0 224 0 05 0 008 0 001 0 20 0 03 e 0004 0 008 0 10 0 21 10 0
6. 04 0 006 0 10 0 16 D 10 4654 0 004 11 80 0 10 E 0 3154 0 004 8 004 0 10 e 0020 0 004 0 504 0 10 HD 0 528 0 008 13 404 0 20 L 0 0197 2008 0 50 797 0 0315 0 004 0 804 0 10 y 0 004 Max 0 1 Max e o 9 o 8 KR Sange pue 1 9 A DATAIL VIEW WITH PLATING HE een SECTION A A BASE METAL Revision 1 1 Jan 2004 BS62UV2006 m PACKAGE DIMENSIONS continued 004334 0 004 1 10 0 10 0 004 0 002 0 10 0 05 0 035 0002 1 00 0 05 0 009 0 002 0 224 0 05 0 008 0 001 Want 0 03 0 004 0 008 010 021 0 004 0 006 _ 0 10 0 16 0 724 0 004 18 40 0 10 0 315 0 004 Sot 0 10 0 026 0 004 Want 0 10 0 787 0 008 120 00 0 20 0 0197 208 1050 302 L1 0 0315E 0 004 30 0 10 0 004 Max 0 1 Max o 8 0 8 was HO DEJ INCH MM A Al A2 b bl c cl D E e HD L LA DETAIL VIE WITH PLATING BASE METAL bl SECTION A TSOP 32 WNT INCH MM 0 111 0 007 2 821 0 176 0 009 0 005 0 22910 127 0 1055 0 0055 2 680 0 140 0 014 0 020 0 35 0 50 0 014 0 018 0 35 0 46 0 006 0 012 0 15 0 32 0 006 0 011 0 15 0 28 0 805 0 005 20 44740 127 0 445 0 005 11 30340 127 0 555 0 012 14 097 0 305 0 050 0 006 1 27040 152 0 033 0 010 0 83410 25 0 055 0 008 1 397 0 203 0 004 Max 0 1 Max 0
7. 2576 BS62U V 2006 hy B S Ultra Low Power Voltage CMOS SRAM 256K X 8 bit BS62UV2006 SIT E FEATURES Wide Vcc operation voltage Data retention supply voltage as low as 1 C grade 1 8V 3 6V Easy expansion with CE2 CE1 and OE options I grade 1 9V 3 6V E DESCRIPTION Vcc_min 1 65V at 25 C Ultra low power consumption The BS62UV2006 is a high performance ultra low power CMOS Vcc 2 0V C grade 8mA Max operating current Static Random Access Memory organized as 262 144 words by 8 bits f l grade d 40mA Max operating current and operates from a wide range of 1 8V to 3 6V supply voltage 0 20uA Typ CMOS standby current Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of Vcc 3 0V C grade 11mA Max operating current 0 2uA at 2 0V 25 C and maximum access time of 85ns at 85 C grade 13mA Max operating current 0 30uA Typ CMOS standby current Easy memory expansion is provided by an active LOW chip High speed access time enable CE1 an active HIGH chip enable CE2 and active LOW 85 85ns Max output enable OE and three state output drivers 10 100ns Max The BS62UV2006 has an automatic power down feature reducing the power consumption significantly when chip is deselected The BS62UV2006 is available in DICE form JEDEC standard 32 pin 450mil Plastic SOP 8mmx13 4mm
8. ENTER LINE IS HIGH IMPEDANCE OFF STATE READ CYCLE PARAMETER sg pore te DESCRIPTION eseu NAME MIN TYP MAX MIN TYP MAX Read Cycle Time 100 VE Address Access Time 100 85 ns E Les Chip Select Access Time CE1 100 Se de 85 Lee tees Chip Select Access Time CE2 10 85 ns Eat Le Output Enable to Output Valid 45 40 ns mg toon Chip Select to Output Low Z CE1 15 15 ns LEES ti Chip Select to Output Low Z CE2 15 15 ns LES L Output Enable to Output in Low 2 15 10 ae LS Chip Deselect to Output in High 2 CE1 40 35 ns Las Chip Deselect to Output in High 2 CE2 40 a 2 35 ns Tones L Output Disable Output in High 2 35 30 ns ton Data Hold from Address Change 15 15 Se ns R0201 BS62UV2006 Revision 1 1 Jan 2004 o a BS62UV2006 m SWITCHING WAVEFORMS READ CYCLE READ CYCLE 1 1 2 4 ADDRESS X t on READ CYCLE2 1 3 4 t acs gt V SA t acsz gt 5 t cnz oss Kt az gt D our READ CYCLE3 1 4 tro d ADDRESS X ta Xo 22222222 C te AEN E ei gt pe xX P NOTES 1 WE is high in read Cycle 2 Device is contin
9. Ports These 8 bi directional ports are used to read data from or write data into the RAM Vcc Power Supply Gnd E TRUTH TABLE MODE Ground UO OPERATION CURRENT Not selected High Z 106584 Power Down Output Disabled High Z Read Dour Write DIN ABSOLUTE MAXIMUM RATINGS m OPERATING RANGE SYMBOL PARAMETER AMBIENT RATING RANGE TEMPERATURE Vcc Terminal Voltage with VTERM Respect to GND 0 5 to Vec 0 5 Commercial 0 C to 70 C 1 8V 3 6V TBIAS Temperature Under Bias 40 to 85 Industrial 40 C to 85 C 1 9V 3 6V TSTG Storage Temperature 60 to 150 PT Power Dissipation 1 0 m CAPACITANCE TA 25 C f 1 0 MHz DC Output Current 1 Stresses greater than those listed under ABSOLUTE MAXIMUM CIN Input VIN 0V 6 pF RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 20 SYMBOL PARAMETER CONDITIONS MAX UNIT Capacitance CDQ Input Output E Capacitance 8 pF sections of this specification is not implied Exposure to absolute 1 This parameter is guaranteed and not 100 tested maximum rating conditions for extended periods may affect reliability R0201 BS62UV2006 2
10. g Kt wre AW 3 K t WP gt WE tas 4 10 ES SE gt gt gt DH 7 Dw 7 R0201 BS62UV2006 6 Revision 1 1 Jan 2004 d SIT BSI BS62UV2006 WRITE CYCLE2 6 t we ADDRESS Ka X 11 t Cw 5 CE1 SR 72 CE2 6 11 KS Va K lt t wr 2 3 t aw t WP ee 2 WE KE Ea 4 10 K NOTES 1 WE must be high during address transitions 2 The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low All signals must be active to initiate a write and any one signal can terminate a write by going inactive The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write 3 Twr is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle 4 During this period DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied 5 If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition output remain in a high impedance state OE is continuously low OE Vi Dout is the same phase of write data of this write cycle Dour is the read data of next address If CE1 is low and CE2 is high during this period DQ pins are
11. o Address Input Buffer A1 11 CET ao E 12 o gt 11411111 20 Ges o gt A11 A9 88 A3 A2 A1 A0 A10 DQ2 15 DQ4 GND 16 17 DQ3 Brilliance Semiconductor Inc reserves the right to modify document contents without notice R0201 BS62UV2006 1 Revision 1 1 Jan 2004 BSI m PIN DESCRIPTIONS Name BS62UV2006 Function A0 A17 Address Input These 18 address inputs select one of the 262 144 x 8 bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH Both chip enables must be active when data read from or write to the device If either chip enable is not active the device is deselected and is in a standby power mode The DQ pins will be in the high impedance state when the device is deselected WE Write Enable Input The write enable input is active LOW and controls read and write operations With the chip selected when WE is HIGH and OE is LOW output data will be present on the DQ pins when WE is LOW the data present on the DQ pins will be written into the selected memory location E Output Enable Input The output enable input is active LOW If the output enable is active while the chip is selected and the write enable is inactive data will be present on the DQ pins and they will be enabled The DQ pins will be in the high impedance state when OE is inactive DQO0 DQ7 Data Input Output
12. uously selected when CE1 Vit and CE2 Vin 3 Address valid prior to or coincident with CE1 transition low and or CE2 transition high A O zz Mu 5 The parameter is guaranteed but not 100 tested R0201 BS62UV2006 5 Revision 1 1 Jan 2004 d SIT BSI m AC ELECTRICAL CHARACTERISTICS TA 40 C to 85 C WRITE CYCLE BS62UV2006 JEDEC CYCLE TIME 100ns CYCLE TIME 85ns PARAMETER PARAMETER DESCRIPTION Veo 1 9 3 6V Vee 1 9 3 6V UNIT NAME MIN TYP MAX MIN TYP MAX ty AX twe Write Cycle Time 100 g 85 wad ns Lon tew Chip Select to End of Write 100 85 ng to tig Address Setup Time 0 m 0 a SS ng taw Address Valid to End of Write 100 85 a ns La me tw Write Pulse Width 50 40 ns Tia Write recovery Time CE1 WE 0 2 0 H ns ae twee Write recovery Time CE2 0 0 Ss ns kig twuz Write to Output in High Z 40 2 35 nS La tow Data to Write Time Overlap 40 S 35 z z ns ec ton Data Hold from Write Time 0 os X 0 Ve 2 ns ta Le Output Disable to Output in High 2 as 40 E 35 ns tynox tow End of Write to Output Active 10 Ss 10 me m SWITCHING WAVEFORMS WRITE CYCLE WRITE CYCLE1 D t we 3 K t WRI 7 11 K t cw gt 5 CE1 Be CEs 222222 7 AA gee N

BSI BS62UV2006 Ultra Low Power/Voltage CMOS SRAM 256K X 8 bit

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