MAXIM MAX9856 handbook
Contents
1. HP GAIN 5 5dB 8 HP GAIN 5 508 E HP GAIN 5 508 5 R 320 160 R 32Q E 10 10 20kHz EM 1 1 1 e I 2 a 01 04 x 01 5mW 0 01 0 01 0 01 10kHz 10kHz 2011 0 001 0 001 0 001 0 5 10 15 20 25 3 35 40 0 10 20 30 40 50 6 10 0 100840 1053 00E 3 OUTPUT POWER mW OUTPUT POWER mW FREQUENCY Hz TOTAL HARMONIC DISTO2. POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIO FFT DAC TO LINE OUT 48kHz vs FREQUENCY DAC TO HP vs FREQUENCY DAC TO LINE OUT SYNCHRONOUS SLAVE MODE OdBFS 0 0 20 a V 100mVp E 100 MCLK 12 288MHz E RIPPLE mVP P RIPPLE P P 4 LRCLK 48kHz 1 8 20 2 20 PCLK 2 20 40 2 2 e 40 ES hr a 60 5 60 60 80 80 8 lt 100 100 100 m 120 120 140 10 100 k 0k 100k 10 00 1k 10k 100k 000 0 453 8 3 1289 1688 205 pa aan 282 623 01083 1463 183 REQUENCY Hz REQUENCY Hz FREQUENCY He FFT DAC TO LINE OUT 48kHz FFT DAC TO LINE OUT 48kHz FFT DAC TO LINE OUT 48kHz SYNCHRONOUS SLAVE MODE 60dBFS ASYNCHRONOUS MASTER MODE OdBFS ASYNCHRONOUS MASTER MODE 60dBFS 20 2 20 20 CLK 12 288MHz 5 CLK 11 2890MHz MCLK 11 2896MHz 5 0 LRCLK 48kHz 1 18 0 LRCLK 48kHz 1 8 0 LRCLK 48kHz L 2 PCLK 2 PCLK 2 PCLK 2 20 20 20 2 e 8 0 40 40 a a a P 60 60 P 60 80 80 80 lt lt lt 100 100 100 1
3. FFT LINE IN T0 ADC 48kHz FFT LINE IN T0 ADC 48kHz FFT LINE IN T0 ADC 48kHz SYNCHRONOUS MASTER 60dBFS ASYNCHRONOUS MASTER MODE 04 5 ASYNCHRONOUS MASTER MODE GOdBFS 20 20 8 20 MCLK 12 288MHz 2 MCLK 11 2896MHz 2 MCLK 11 2896MHz 2 LRCLK 48kH2 4 0 LRCLK 48kHz 5 0 LRCLK 48kHz 5 PCLK 2 PCLK 2 PCLK 2 20 20 20 2 a s 40 s 40 40 5 6 60 60 80 a lt lt lt 100 10 10 120 12 12 140 14 14 20k 0 5k 10k 15k 20k FREQUENCY 2 FREQUENCY Hz FREQUENCY Hz FFT LINE IN TO ADC 48kHz FFT LINE IN TO ADC 48kHz WIDEBAND FFT DAC TO HP AMP 48kHz ASYNCHRONOUS SLAVE MODE OdBFS ASYNCHRONOUS SLAVE MODE 60dBFS SYNCHRONOUS MASTER MODE OdBFS 20 3 20 10 MCLK 11 2896MHz MCLK 11 2896MHz C1 4 TuF j LRCLK 48kHz E LRCLK 48kHz 8 4 PCLK 2 PCLK 2 20 20 0 2 Q 8 40 amp 40 5 50 60 p 00 7 80 80 90 100 100 110 120 120 130 140 140 150 0 5k 10k 15k 20k 0 20k 10 100 1k 10k 100k 10M FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz WIDEBAND F
4. TOTAL HARMONIC DISTORTION NOISE DYNAMIC RANGE AUTOMATIC GAIN CONTROL THRESHOLDS vs MCLK FREQUENCY OdBFS vs MCLK FREQUENCY 60dBFS 10 s 8 DAC PLAYBACK M0DE 48kHz 8 DAC PLAYBACK MODE 48kHz _ 710 o 20 8 5 3 5 04 5 z 0 50 60 70 0 01 400 80 0 0 20 0 20 10 11 12 13 14 15 16 17 18 19 20 20 MICROPHONE INPUT dBV FREQUENCY MHz FREQUENCY MHz 14 MAKLM LINEIN1 LINEIN2 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Pin Description FUNCTION Line 1 Input AC couple signal to LINEIN1 with a 1uF capacitor Line 2 Input AC couple signal to LINEIN2 with a 1uF capacitor AUXIN Auxiliary Input Input for beep and sound effect signals or can be used for DC measurements EG Positive Internally Regulated Supply 1 6V 3596 Bypass to AGND with 1uF capacitor EG LGNDSNS egative Internally Regulated Supply 1 15V 5 Bypass to AGND with 1uF capacitor nternal Microphone Bias Regulator Output 1 23V 5 Bypass to AGND with a 1uF capacitor Converter Reference 1 23V 5 Bypass to AGND with a 1uF capacitor Line Output Ground Sense Feedback path to line out amplifiers for noise reduction Connect to the ground pin of the line output jack Connect directly to AGND if ground sense is not required LOUTL Left Channel Line Output Ground refer
5. DWCI AWCI 1 DBCI ABCI 1 DDLY ADLY 0 WS 0 PCM 0 LEF RIGHT D15 D14 D13 212 011 010 D9 D8 D D4 D3 D2 D1 D15 D14 D13 D12 D11 D10 D9 D8 07 D6 D5 D4 D3 D2 D1 DO UU UU UU UU UU DWCI AWCI 0 DBCI ABCI 0 DDLY ADLY 1 WS 1 PC LEF GH Di7 D1q D15 014 013 012 011 ptg 08 De 07 06 25 04 03 02 01 pti 08 07 06 05 04 4UUUUUUUUUUUUUUU I DBCI ABCI 0 DDLY ADLY 0 WS 0 PCM LEFT oer oe DIGITAL AUDIO INTERFACE MASTER MODE DWCI AWCI 0 DBCI ABCI 0 DDLY ADLY 0 WS 0 PCM 0 LEFT RIGHT 015 014 013 012 11 10 09 7 D6 05 04 03 D2 1 00 e ppprs orz prr oro 09 08 07 06 05 04 ps 02 01 DWCI AWCI 0 DBCI ABCI 0 DDLY ADLY 1 WS 2 0 PCM 0 LEFT RIGHT D15 D14 D13 D12 011 010 D9 D8 07 D6 05 D4 D3 D2 D1 DO D15 D14 DI3D12 D11 D10 D9 D8 D7 06 05 D4
6. D using the specified divide ratio In mode the MAX9856 expects an LRCLK D as specified by the divide ratio id for slave mode only A digital PLL locks on to any externally supplied LRCLK D signal regardless of the MCLK frequency DHF must set high for sample rates above 50 2 MCLK MHz PSCLK 8kHz 16kHz 11 2896 DAC LRCLK Divider When DPLLEN is set low the frequency of LRCLK D is determined by DACNI See Table 6 for common DACNI values DACNI 65536 x 96 x fLRCLK_D fPCLK for DHF 0 DACNI 65536 x 48 x fLRCLK_D fPCLK for DHF 1 fi RCLK D LRCLK D frequency fPcLK Prescaled MCLK internal clock frequency PCLK Table 6 Common DACNI and ADCNI Values LRCLK 44 1kHz 48kHz 88 2kHz DAC ONLY 96kHz DAC ONLY 12 12 288 13 16 9344 Note Values in bold are exact integers that provide maximum full scale performance MAXI 23 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers DIGITAL AUDIO INTERFACE SLAVE MODES LRCLK SHOULD TRANSITION THE UNUSED BCLK EDGE DWCI AWCI 0 DBCI ABCI 0 DDLY ADLY 0 WS 0 PCM 0 LEF RIGHT D15 D14 D13 D12 D11D10 D9 108 06 D5 D4 D3 D2 101100 121011 010109 D8 D7 D6 D5 D4 D3 02 01 AL UU UU UUUUUUUUUUU
7. MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD VCPVDD VDVDDS2 1 8V RHP 320 RLINE 10kQ C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG AvPRE 20dB CmIcBIAS AvMICPGA 0dB MCLK 11 2896MHz DRATE 00 TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS ADC DAC DATA RATE ACCURACY LRCLK_D and LRCLK_A Output Average Sample Rate Deviation Note 8 Master Mode Any MCLK LRCLK_D Output Sample Rate PCLK LRCLK 1536 1024 768 512 384 Deviation Master Mode 256 192 or 128 LRCLK Input Sample Rate Range LRCLK_A LRCLK_D DHF 0 Slave Mode LRCLK_D DHF 1 LRCLK_D and LRCLK_A PLL Lock Time Any allowable LRCLK and PCLK rates LRCLK_D and LRCLK_A Allowable LRCLK period change from Acceptable Jitter for Maintaining nominal for slave PLL mode at any PLL Lock All Slave Modes allowable LRCLK and PCLK rates HEADPHONE AMPLIFIERS f 2 1kHz THD 196 RL 160 TA 25 C RL 32Q OdBFS DAC Output Voltage OdB volume setting Line In to HP Out Voltage Gain 4 5dB volume setting OdB PGA setting Output Offset Voltage TA 25 40dB volume setting Total Harmonic Distortion Plus RL 320 Pour 25mW f 1kHz Noise RL 160 Pour 25mW f 1kHz Output Power 5 5dB volume setting DAC i
8. 0 3V single layer 210 CPGND 0 3V to CPVDD 0 3V 40 Pin TQFN derate 37mW C above 70 C 0 3V to AVDD 0 3V multilayer 2963 SVSS 0 3V to 0 3V Operating Temperature Range 40 C to 85 C 0 3V to 4V Storage Temperature Range 65 C to 150 C 0 3V to 4V Lead Temperature soldering 10s 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS VAVDD VCPVDD 2 1 8V RHP 320 RLINE 10kQ C1 4 7uF C2 4 7uF CREF CPREG CNREG AvPRE 200 5 1uF AvMIGPGA MCLK 11 2896MHz DRATE 00 TA Tmin to Tmax unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS AVDD CPVDD inferred from HP output PSRR DVDD DVDDS2 inferred from CODEC performance tests Su
9. D3 D2 D1 DO Figure 1 Digital Audio Interface Data Format Examples 24 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers DAI STEREO SERIAL INTERFACE TIMING DIAGRAM SLAVE MODE SDIN LRCLK INPUTS BCLK BCI 0 INPUT BCLK BCI 1 INPUT SDOUT OUTPUT Figure 2 Digital Audio Interface Timing Diagrams ADC Interface The stereo ADC is capable of outputting data at any sample rate from 8kHz to 48kHz Data can be output in common formats including left justified 125 and PCM Figure 1 Figure 2 shows the digital timing in both slave and master modes Table 7 ADC Interface Registers DAI STEREO SERIAL INTERFACE TIMING DIAGRAM MASTER MODE SDIN INPUT tsu BCLK OUTPUT If the DAC and ADC operate at the same sample rate only the D is needed allowing the LRCLK pin to be reassigned as a GPIO When configured as a general purpose output LRCLK A can be set high or low by the APIN bits When configured as a general purpose input the status is reported in register 0 00 Table 7 lists and describes the ADC interface registers REG B B B Bi AWCI APIN nv o o 0 APLLEN ADCNI 14 8 ADCNI 7 0 AGAIN ANTH ADC Interface Register Bit Description REGISTER FUNCTION When PCM 0 When 1 ADC Word Clock LRCLK A Invert O Left channel data is
10. DirectDrive Headphone Amplifiers Audio Input Register Bit Description FUNCTION Programmable Gain Adjust for Digital Audio Input DIGITAL AUDIO INPUT PGA SETTINGS SETTING GAIN dB SETTING GAIN dB 0 00 0 0x93 15 0x07 0 5 0x96 15 5 0 99 16 0 15 0x9C 16 5 0x1C 0x9F 17 0x22 2 17 5 0 29 OxA5 18 Ox2F 7 0 35 OxAC Ox40 OxAE 0x45 OxB3 Ox4A OxB7 0x50 OxBB 0x55 OxBF 0x59 0 2 Ox5E 0xC6 0x63 0xC9 0x67 0xCC 0x6B 0xCF 0x70 0xD2 0 74 10 0xD4 0x78 0xD6 Ox7C Ox7F 0x83 0x86 Ox8D 0x90 32 MAXIM Low Power Audio with DirectDrive Headphone Amplifiers Audio Input Register Bit Description continued FUNCTION Programmable Gain Adjust for Line Inputs LINE INPUT PGA SETTINGS SETTING GAIN dB SETTING GAIN dB 0x00 30 0x10 0x01 28 0x11 0x02 26 0x12 0x03 24 0x13 0x04 0x14 PGAAUX 0x05 0x15 PGAL1 0x06 0x16 pan 0x07 0x17 0x08 0x18 0x09 0x19 MAXIM 33 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Audio Input Register Bit Description continued BITS FUNCTION Left Right Programmable Gain Adjustment for Microphone Inputs When AGC is enabled the PGAML and PGAMR bits cannot be manually programmed The PGAML register can
11. SYMBOL ICBIAS AvMICPGA 0dB MCLK 11 2896MHz DRAT at TA 25 C Note 1 CONDITIONS Gain Error Full Scale Conversion Channel Gain Mismatch fin 1kHz line input PGA ADC DYNAMIC SPECIFICATIONS Dynamic Range Note 4 Total Harmonic Distortion fs 8kHz to 32kHz BW 22 2 to fs 2 fs 44 1kHz BW 22Hz to 20kHz A weighted fs 48kHz BW 22Hz to 20kHz A weighted 1kHz OdBFS 8kHz 1kHz OdBFS S 48kHz Signal to Noise Ratio 1kHz OdBFS 5 8kHz BW 22Hz to 20kHz A weighted 1kHz OdBFS 5 48kHz BW 22Hz to 20kHz A weighted Channel Crosstalk Driven channe fs 8kHz at 1dBFS fin 1kHz Power Supply Rejection Ratio Note 7 VAVDD 1 71V to 3 6V f 1kHz VnippLE 100mV f 2 10kHz VRIPPLE 100mV ADC DIGITAL FILTER PATH Passband Cutoff 0 2dB from peak 0 44 Passband Ripple Stopband Cutoff f lt fp 0 1 0 56 Stopband Attenuation f gt fs 60 Attenuation at fs 2 ADC HIGHPASS FILTER 6 02 3dB Corner Frequency fs 44 1kHz P 000 Disabled P 001 P 010 011 LK 1598 LK 798 LK 398 28 55 P 100 LRCLK 197 P 101 110 LRCLK 97 LRCLK 47 P 111 LRCLK 22 DC Attenuation DC Output Offset DCATTEN P 000 P anything other than 000
12. alerting that a jack has been inserted The JKMIC bit can be configured to create a hardware interrupt that alerts the microcontroller of jack removal and insertion events Impedance Detection The MAX9856 is able to detect the type of load con nected by applying a 2mA pullup current to HPL HPR and JACKSNS To minimize click and pop the current is ramped up and down over a 24ms period The 2mA current can be individually applied to HPL HPR and JACKSNS by appropriately configuring the EN bits When the 2mA current has finished ramping HSDETL HSDETR and JSDET are updated to reflect the mea sured impedance EN must be cleared and reset to re measure the impedance Figure 7 and Table 15 illustrate the impedance detection process MICBIAS JACKSNS IMPEDANCE DETECTION SET EN BITS TO 0 COMPLETE 10 24ms tr 24ms Figure 7 Current on HPL or JACKSNS During Impedance Detection MAXI 37 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Table 14 Headset Detect Control Register com qr 20 1 o so p 7 SN l Table 15 Impedance Detection Routine Disable the headphone amplifiers Set EN 111 to enable the detection circuitry IRQ set high Indicates that the detection current has reached its final value and the impedance has been stored in HSDETL HSDETR and JSDET Once the impedance of HPL HPR and JACKSNS has been read set EN
13. 000 to shut down the detection circuitry IRQ set high Indicates that the detection circuitry is completely shut down and the headphone amplifiers can be reenabled Headset Detection Register Bit Description FUNCTION Jack Detection Enable Sleep Mode Enables pullups on HPL and JACKSNS to detect jack insertion LSNS and JKSNS are not valid unless JDETEN 1 and SHDN 0 Normal Mode Enables the comparator circuitry on JACKSNS to detect voltage changes JKMIC is not valid unless JDETEN 1 and the microphone circuitry is enabled JDETEN Impedance Detection Enable Enables the impedance detection circuitry for HPL HPR and JACKSNS When EN 000 HSDETL HSDETR and JSDET are set to 11 See Table 2 Status Register Bit Description for details on reading the load impedance IMPEDANCE DETECTION ENABLE DESCRIPTION EN DESCRIPTION Disabled JACKSNS pin impedance sense enabled HPR pin impedance sense enabled HPL pin impedance sense enabled 38 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers saving power Table 16 shows the power management register and a register bit description Power Management and Control The MAX9856 has comprehensive power management that allows unused features to be disabled thereby Table 16 Power Management Register REGISTER B7 B6 B5 B4 B3 2 B1 SHON o DIGEN LOUTEN DALEN DAREN ADLEN ADREN P
14. 29 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Analog Mixers Each mixer is configurable independently for left and The MAX9856 has two main analog mixers The first right channels See Table 11 for audio mixer control feeds signals into the headphone and line output registers and register bit description amplifiers while the second supplies the ADC input Table 11 Audio Mixer Control Registers MOUT MXOUTR Audio Mixer Register Bit Description FUNCTION ADC INPUT MIXER DESCRIPTION MXINL OR MXINR SELECTED INPUT SOURCE 00000 No input source selected LINEIN1 selected LINEIN2 selected MICL selected XXXX1 MICR selected AUDIO OUTPUT MIXER DESCRIPTION No input source selected MXOUTL MXOUTR MIC L R PGA output selected LINEIN1 selected LINEIN2 selected DAC output selected 30 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Analog Inputs The MAX9856 features various analog inputs All inputs have independent gain control for maximum flexibility AUXIN is a mono auxiliary input that can be used for mixing alarms beeps and sound effects into the head phone outputs or ADC input The AUXIN signal has a dedicated PGA for gain adjustment and can be mixed into the headphone output signal directly bypassing the output mixer and volume control AUXIN can also serve as an input for making precise measurements in the syst
15. 80 Automatic Gain Control The MAX9856 AGC continuously adjusts the analog microphone PGAs to maintain constant signal level When the AGC is enabled manual control of the input PGA is not possible The PGA includes zero cross detection which prevents gain changes from being audible The AGC process consists of three main sections When the AGC threshold is exceeded the gain is reduced exponentially with a time constant referred to as the attack time Once the large signal has passed Table 10 Automatic Gain Control Registers the AGC waits the specified hold time before reducing the gain The time required to reduce the gain from maximum attenuation to minimum attenuation is known as the release time The AGC circuitry only operates on the PGA in the micro phone path but the digital level detector is based on the mixed signal Only use the AGC when input signals from the LINEIN and AUXIN are excluded or attenuated Table 10 lists the AGC registers and shows the AGC register bit description B4 B3 B2 B1 AGCRLS AGCATK AGCHLD AGC Register Bit Description 0 AGCSRC AGCSTH FUNCTION 000 78ms 001 156ms 010 312ms recommended 011 625ms 100 1 25s 101 2 55 110 5s 111 10s AGCRLS 28 AGC Release Time The release time is the time it takes for the gain to return to its normal level after
16. 9 DRAWING CONFORMS 0220 EXCEPT FOR 0 4mm LEAD PITCH PACKAGE T4866 1 BDALLAS MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY TRE 12 NUMBER OF LEADS SHOWN FOR REFERENCE ONLY PACKAGE DUTLINE 13 ALL DIMENSIONS APPLY BOTH LEADED 2 AND PKG CODES 36 40 48L THIN QFN 6x6x0 8mm AX COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS 10 WARPAGE SHALL NOT EXCEED 010 APPROVAL DOCUMENT CONTROL NO REV DRAWING NOT TO SCALE pe 21 0141 PACKAGE TYPE PACKAGE CODE DOCUMENT NO 40 TDFN EP T4066 5 21 0141 MAXIM 45 9S86XVMI 9856 Low Power Audio with DirectDrive Headphone Amplifiers Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 m 3 08 Initial release 1 9 08 Added new Note 1 to EC table 2 10 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 46 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2008 Maxim Integrated Products MAXIM a registered trademark of Maxim Integrated Products Inc
17. Note 5 DRATE 10 Signal to Noise Ratio Driven channel at 1dBFS fiy 1 2 s 8kHz 217Hz VRIPPLE 100mV AvPGA 10kHz VRIPPLE 100mV AvPGA 088 DAC DIGITAL FILTER 8x interpolation FIR fs 7 8kHz to 50kHz Passband Cutoff fP 0 2dB from peak Passband Ripple f lt 0 44 x fs Stopband Cutoff fs Stopband Attenuation f gt fs Attenuation at fs 2 DAC DIGITAL FILTER 4x interpolation FIR fs 50kHz to 100 2 Passband Cutoff fp 0 2dB from peak Passband Ripple f lt 0 23 x fs Stopband Cutoff fs 0 5 Stopband Attenuation gt fs 54 Attenuation at fs 2 60 DAC HIGHPASS FILTER Crosstalk Power Supply Rejection Ratio PSRR DACHP 000 Disabled DACHP 001 LRCLK 1598 28 DACHP 010 LRCLK 798 55 Corner Frequency DACHP 011 LRCLK 398 fs 44 1kHz DACHP 100 LRCLK 197 DACHP 101 LRCLK 97 DACHP 110 LRCLK 47 DACHP 111 LRCLK 22 DC Attenuation z 000 MAXIM 3 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD 52 1 8V RHP 320 RLINE 10kQ C1 4 7uF C2 4 7uF CREF CMBIAS CPREG E 00 TA TMIN to TMAX unless CNREG 1 AvPRE 200 C otherwise noted Typical values are PARAMETER STEREO ADC Note 6
18. Off 011 BCLK 48 x LRCLK_A 101 BCLK PCLK 4 110 BCLK PCLK 8 111 BCLK PCLK 16 MAXUM MCLK Prescaler Set PSCLK to appropriately divi Master Mode Selects between master and slave operation 0 Slave mode LRCLK_D and LRCLK_A are inputs LRCLK_A are outputs BCLK Select Configures BCLK when operating in master mode Set BSEL to be a sufficiently high frequency to fully clock in all data bits for both the DAC and ADC if operating at different sample rates 010 BCLK 48 x LRCLK_D recommended if the DAC and ADC operate at the same rate 100 BCLK PCLK 2 recommended if the DAC and ADC are not operating at the same rate 21 9S86XVMI 9856 Low Power Audio with DirectDrive Headphone Amplifiers The MAX9856 DAC is capable of supporting any sam DRATE control bits The h DAC Interface There are two speed set tings for the DAC set by the ighest rate runs the modulator ple rate from 8kHz to 96kHz in either master or slave at an internal clock rate between 5MHz and 10MHz mode including all common sample rates 8kHz and provides the highest audio performance The low 11 025kHz 12kHz 16kHz 22 05kHz 24kHz 32kHz rate runs the modulator between 2 5MHz and 5MHz for 44 1kHz 48kHz 88 2kHz and 96kHz reduced power consumption A 15 bit clock divider coefficient must be programmed The digital audio interface offers full functionality for into the device to set
19. be monitored to determine the gain set by the AGC MICROPHONE SETTINGS SETTING GAIN dB SETTING GAIN dB 20 0x0B 4 0x01 0x0C 4 PGAMU 0x02 4 PGAMR 0x03 0x0E 4 0 04 0 05 0x10 0x06 0 11 Ox07 0x12 0x08 Ox13 0x09 0x14 to 0x1F 1 i 1 1 X L N 0110 O Left Right Microphone Preamplifier Enable Enables the microphone circuitry and sets the preamplifier gain 00 Microphones disabled PAENL PAENR 01 0dB 10 20dB 11 30dB Microphone Mute Enable MICBIAS Voltage Select 0 MICBIAS 1 5V 1 MICBIAS 2 4V use only when AVDD gt 2 7V Left Microphone Input Select LMICDIF 0 MICL MICGND pseudo differential input 1 INLP INLN differential input 34 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Audio Outputs signals and microphone signals The sharing of ground The MAX9856 features stereo headphone amplifiers and can result in interference that is audible The MAX9856 s line output amplifiers with DirectDrive technology ground sense provides a path for the interfering signal to DirectDrive eliminates the need for bulky and expensive be input and combined with the output audio signal to DC blocking capacitors on the outputs The DirectDrive reduce the audibility of the interference Connect HGND biasing scheme is illustrated in Figu
20. capable of operating at a different sample rate than the ADC Both master and slave modes are available when operating the interface in left justified 125 PCM data format The incoming data can be level shifted and highpass filtered in the digital domain The highpass fil tering allows only reproducible frequencies to be con verted saving power and improving sound quality MAX9856 features stereo DirectDrive headphone amplifiers and line outputs which eliminate the need for large output coupling capacitors The audio output path includes high quality mixing amplifiers to allow flexibility in choosing from the DAC output and the stereo analog line inputs Volume control amplifiers provide adjustable gains between 5 5dB and 74dB for the headphones The line outputs are capable of generating 1VRMs out put signal from a full scale digital input The digital audio signals of the internal 18 bit sigma delta ADC outputs are converted from the analog micro phone and line input paths The ADC is capable of operating at a sample rate ranging from 8kHz to 48kHz with any master clock frequency between 10MHz and 60MHz The ADC is capable of operating at a different sample rate than the DAC Both master and slave modes are available when operating the interface in left justified 125 or PCM data formats The outgoing data can be level shifted and highpass filtered in the digital 18 domain The highpass filtering allows
21. its own When AGC is enabled the noise gate reduces the output level only when the AGC has set the gain to the maximum setting Choose a threshold between 28dB and 48dB when used in conjunction with the AGC When the AGC is enabled the effective noise gate thresholds are increased by 20dB due to the microphone PGA being set to maximum gain by the AGC ADC NOISE GATE THRESHOLD LEVELS VALUE THRESHOLD dB 0x0 to 0x5 Disabled 0x6 7 0 8 0x9 0xB 0xC 0xD Digital Filters energy sent to speakers incapable of low The MAX9856 digital audio interface includes digital frequencies The ADC filter ADCHP can reduce low first order highpass filters Table 8 for both the DAC frequency noise such as wind noise from being con input and the ADC output The corner frequency for verted The cutoff frequency depends on sample rate each filter is selectable from 5Hz to 4kHz The DAC fil and is shown in Table 9 ter DACHP can be used to reduce the low frequency Table 8 Digital Highpass Filters REG B7 B6 B5 B4 B3 B2 B1 BO MAXIM 27 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Table 9 Digital Highpass Filter Cutoff Frequencies LRCLK kHz 010 Hz 011 Hz ADCHP DACHP 100 Hz 101 Hz 110 Hz 111 Hz 10 20 41 82 170 364 28 114 501 30 124 545 40 165 727 55 60
22. reduction of wind noise from microphone inputs Three microphone inputs are available One fully differ ential input can be used with internal microphones while a pair of single ended inputs can be used with an external mono or stereo headset microphone Selectable gain of OdB 2088 and 30dB can be applied to the input signals in addition to 0 to 2088 input PGA The MAX9856 features AGC on the micro phone input path to automatically compensate for vary ing input signal levels and the limited dynamic range of most microphones The integrated noise gate provides low level audio noise quieting to lower the audible noise floor An auxiliary input is available for sending externally generated beeps and sound effects directly to the headphones The auxiliary input can also be used to make DC measurements with the ADC by providing a direct path to the ADC HPL HPR and JACKSNS provide a headset detection feature which can both detect the insertion of a jack and measure the load impedance Jack detection can be done in both shutdown and powered on mode The headphone and line outputs feature ground sensing to reduce ground noise Reduced output offset voltage and extensive click and pop suppression circuitry on headphone amplifiers eliminate audible clicks and pops at startup and shutdown I2C Register Address and Definitions The MAX9856 has 28 internal registers used for config uration and status reporting Table 1 lists all t
23. the DAC sample rate relative to several digital audio formats including left justified 125 the prescaled MCLK input PCLK This allows high and PCM modes Figure flexibility in both the MCLK and LRCLK D frequencies timing for various modes In slave mode the interface accepts any LRCLK D sig nal between 7 8kHz to 100kHz DACNI and ADCNI values Table 5 DAC Interface Registers 1 Figure 2 shows the digital Table 5 shows the DAC inter face registers and descriptions Table 6 lists the common DWCI DPLLEN DDLY DACNI 14 8 DACNI 7 0 DAC Interface Register Bit Descriptions REGISTER FUNCTION DAC Word Clock LRCLK D Invert When PCM 0 O Left channel data is transmitted while LRCLK D is low 1 Right channel data is transmitted while LRCLK D is low When PCM 1 O Start of a new frame is signified by the falling edge of the LRCLK D pulse 1 Start of a new frame is signified by the rising edge of the LRCLK D pulse 22 DAC BCLK Invert O SDIN is accepted on the rising edge of BCLK 1 SDIN is accepted on the falling edge of BCLK In master mode O LRCLK D transitions occur on the falling edge of BCLK 1 LRCLK D transitions occur on the rising edge of BCLK DAC Modulator Rate 00 Low power mode 01 Reserved 10 High performance mode 11 DAC clock disabled DAC Data Delay 0 most significant bit of an audio word is latched at the fi LRCL
24. transfer the bus master retries communication The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when in read mode An acknowledge is sent by the master after each read byte to allow data transfer to continue A not acknowledge is sent when the master reads the final byte of data from the MAX9856 followed by a STOP condition CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION ST FA LP f f NOT ACKNOWLEDGE ACKNOWLEDGE soa Y Figure 10 Acknowledge MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Write Data Format A write to the MAX9856 includes transmission of a START condition the slave address with the R W bit set to 0 1 byte of data to configure the internal register address pointer 1 or more bytes of data and a STOP condition Figure 11 illustrates the proper frame format for writing 1 byte of data to the MAX9856 Figure 12 illustrates the frame format for writing n bytes of data to the MAX9856 The slave address with the R W bit set to O indicates that the master intends to write data to the MAX9856 The MAX9856 acknowledges receipt of the address byte during the master generated 9th SCL pulse The second byte transmitted from the master config ures the MAX9856 s internal register address pointer ACKNOWLEDGE FROM MAX9856 7 The pointer tells the MAX9856 where to write the next byte of data An acknowledge pulse is sent by
25. 0F 0x1D 0x02 4 5 0x10 1 0x03 4 0x11 1 0 04 3 5 0 12 0 20 HPVOLL HPVOLR 0x05 3 0x13 0x21 0x06 2 5 0x14 0x22 5 6 7 8 0x07 2 0x1 0x23 0x08 0x1 0x24 0x09 1 0x25 OxOA Ox1 28 0x26 0x27 0x0C 1 32 0 28 to Mute 0x0D 0x1B 34 Volume Slewing Enable Enables volume slewing so that when a volume change is made the actual volume control steps though all intermediate settings to give a smooth sounding change Auxiliary Input DC Measurement Mode 0 AUXIN connected to the input PGA for audio signals 1 AUXIN directly connected to the ADC input for DC measurements Set MXINL to 10000 for proper operation Auxiliary Input Connected to Headphone Amplifiers AUXMIX O AUXIN not connected to the headphone amplifiers 1 AUXIN mixed directly into the headphone amplifiers bypassing the output mixer Headphone Output Mode 00 Shutdown 01 Standard mono mode HPL mono HPR shutdown 10 Dual mono mode HPL HPR mono 11 Stereo mode HPMODE 36 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Headset Detection The MAX9856 features headset detection that can detect the insertion and removal of a jack as well as the loaq type When a jack is detected an interrupt on IRQ can be triggered to alert the microcontroller of the event Figure 6 shows the typical configuration for jack dete
26. 19 1288 1 9 08 TION KIT ALUA AVAILABL AVLAZCIL AVI Low Power Audio CODEC with DirectDrive Headphone Amplifiers General Description The 9856 is a high performance low power stereo audio CODEC designed for MP3 personal media play ers PMPs or other portable multimedia devices Using on board stereo DirectDrive headphone ampli fiers the CODEC can output 30mW into stereo 320 headphones while operating from a single 1 8V power supply Very low 9mW playback power consumption makes it an ideal choice for battery powered applica tions The MAX9856 provides microphone input ampli fiers plus flexible input selection signal mixing and automatic gain control AGC Comprehensive load impedance sensing allows the MAX9856 to autodetect most common audio and audio video headset and jack plug types Outputs include stereo DirectDrive line outputs and DirectDrive headphone amplifiers The stereo ADC can convert audio signals from either internal or external microphones that can be configured for single ended or differential signal inputs Line inputs can be config ured as stereo differential or mono and fed through one channel of the microphone path The analog inputs selected can be gain ranged or mixed with other input sources prior to conversion to digital The ADC path also features programmable digital highpass filters to remove DC offset voltages and wind noise The MAX9856 supports all common
27. 20 120 120 140 140 140 0000 4663 8 1263 1693 20633 0000 49 88301283 16 3 2053 000 0 46 3 853 12553 1683 2053 23 683 1083 14E 3 183 2E 3 0688 1083 143 183 2E 3 683 01083 1453 183 FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz FFT DAC TO LINE OUT 48kHz FFT DAC TO LINE OUT 48kHz FFT LINE IN TO ADC 48kHz ASYNCHRONOUS SLAVE MODE OdBFS ASYNCHRONOUS SLAVE MODE 604 5 SYNCHRONOUS MASTER MODE 04 5 20 2 MCLK 11 2896MHz MCLK 11 2898 MCLK 12 288MHz 2 0 LRCLK 48kHz 4 2 LRCLK 48kHz ls LRCLK 48kHz jJ PCLK 2 PCLK 2 PCLK 2 20 gt 40 a e e 80 z lt lt 100 120 140 140 0000 4663 3 12 3 1693 20633 0000 4 883 1283 163 2063 0 20k 2E 3 6F3 1083 43 183 23 6F3 1083 143 183 FREQUENCY Hz FREQUENCY Hz 12 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Typical Operating Characteristics continued VAVDD VCPVDD VDVDDS2 VDVDD 1 8V RHP 320 RUNE 10kQ C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG 1HF VAVPRE 20dB CMICBIAS 1UF VAVMICPGA 0dB MCLK 12 288 2 DRATE 10 TA 25 C unless otherwise noted
28. 30dB LINEIN2 b is RIGHT AUDIO OUTPUT 32dB 30dB MIXER PGA AUXAC AUXDC CL LRCLK_A DIGITAL MAXIM FILTERING AND MAX9856 GAIN LRCLK_D 0702048 DIGITAL AUDIO XAG BCLK INTERFACE gt a Fi INPUT LN2 PREAMPLIFIER SDIN MEM cL DIGITAL CR FILTERING AND 20dB UXAC 01702048 3008 SDOUT GAIN RIGHT ADC INPUT MIXER PREAMPLIFIER TIMING AND CONTROL LOGIC ATIC GAIN CONTRO MICROPHONE JACKSNS BIAS AND JACK DETECTION I2C SERIAL CHARGE PORT INTERNAL REGULATORS PUMP MICBIAS DGND CPGND REF PVSS MAXIN 17 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Detailed Description The MAX9856 is a high performance low power stereo audio CODEC designed to provide a complete audio solution Operating from a 1 8V supply the MAX9856 achieves high performance and reasonable output power while consuming only 9mW in DAC playback mode The internal 18 bit sigma delta DAC accepts stereo di gital audio signals and converts them to stereo audio outputs that be mixed with line inputs and or micro phone inputs The DAC is capable of operating at sam ple rates ranging from 8kHz to 96kHz with any master clock frequency between 10MHz and 60MHz The DAC is
29. C microphone inputs AC grounded Note 8 In master mode operation the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate 1 8V unless otherwise noted Note 9 To enable the line input make sure the desired input is selected by either the audio output mixer or the ADC input mixer Note 10 CB is in pF 10 MAXIM VAVDD VCPVDD VDVDDS2 1 8V RHP 320 RLINE 10kQ C1 4 7 C2 4 7 CREF 1yF VAVPRE 20dB CMICBIAS VAVMICPGA 12 288MHz DRAT TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HP Low Power Audio CODEC with DirectDrive Headphone Amplifiers Typical Operating Characteristics CmBIAS CPREG CNREG TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER DAC TO HP E 10 TA 25 C unless otherwise noted TOTAL HARMONIC DISTORTION NOISE vs FREQUENCY DAC TO HP
30. Clock Frequency SCL Bus Free Time Between STOP and START Conditions Hold Time Repeated START Condition SCL Pulse Width Low SCL Pulse Width High Setup Time for a Repeated START Condition Data Hold Time 0 Data Setup Time 100 SDA and SCL Receiving Rise Note 10 20 0 1CB SDA and SCL Receiving Fall Time BUF D STA Note 10 20 0 1 1 8V Note 10 20 0 1CB VDVDD 3 6V Note 10 20 0 05Cp Setup Time for STOP Condition tsu STO 0 6 Bus Capacitance Pulse Width of Suppressed Spike tsP TA 25 C SDA Transmitting Fall Time tf Note 1 All devices are 100 production tested at room temperature All temperature limits are guaranteed by design Note 2 Supply current measurements taken with no applied input signal to line and microphone inputs A digital zero audio signal used for all digital serial audio inputs Speaker and headphone outputs are loaded as stated in the global conditions Note 3 DAC performance measured at headphone outputs Note 4 Dynamic range measured using method The input is applied at GOdBFS fin 1kHz The is THD N referred to OdBFS Note 5 Signal to noise ratio measured using an all zeros input signal and is relative to OdB full scale The DAC is not muted for the SNR measurement Note 6 Performance measured from line inputs unless otherwise noted Note 7 Microphone amplifiers connected to AD
31. DIGITAL INPUTS BCLK LRCLK_A LRCLK_D SDIN SDA SCL nput Voltage High VIH 0 7 x DVDD nput Voltage Low VIL 0 3 x DVDD nput Hysteresis 200 nput Leakage Current lL 10 nput Capacitance 10 CMOS DIGITAL OUTPUTS BCLK LRCLK_A LRCLK_D SDOUT Output Low Voltage VOL loL 3mA Output High Voltage VoH 3mA DVDD 0 4 OPEN DRAIN DIGITAL OUTPUTS IRQ SDA Output High Current loH Vout DVDD Output Low Voltage VOL IOL 3mA DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS tBCLKS Slave operation BCLK Cycle Time tBCLKM Master operation tBCLKH Slave operation BCLK Low Time tBCLKL Master operation BCLK or LRCLK A D Rise and Fall Time tr tf Master operation 15pF MAXIM 9 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS continued VDVDD Vpvpps2 1 8V TA TMIN to Tmax unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS SDIN or LRCLK_A D to BCLK BCI 0 see the 2 Register Address Map Rising Setup Time Definitions section SDIN or LRCLK_A D to BCLK t BCI 0 see the 2 Register Address Map Rising Hold Time RB and Definitions section BCI 0 see the 2 Register Address Map and Definitions section CL SDOUT Delay Time DLY 12C INTERFACE TIMING CHARACTERISTICS Serial
32. FT DAC TO HP AMP 48kHz SUPPLY CURRENT SYNCHRONOUS MASTER MODE 60dBFS vs SUPPLY VOLTAGE DAC DIGITAL FILTER FREQUENCY RESPONSE 10 20 8 3 N CT 47yF 5 STEREO DAC PLAYBACK MODE 48kHz 4 18 F SUPPLY CURRENT lypp Ipvpos2 2 1 1 30 2 2 o 8 E 4 S 70 5 10 E 5 ie zc 3 i E 110 2 S A 4 5 130 2 6 150 0 7 10 100 10k 100k 1M 10M 10 15 20 25 30 35 40 0 Bk Ak 20k 28 FREQUENCY Hz SUPPLY VOLTAGE V FREQUENCY Hz MAXIM 13 9S86XVMI MAX9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Typical Operating Characteristics continued VAVDD VCPVDD 52 1 8V RHP 320 RLINE 10kQ C1 4 7yF C2 CREF 5 CPREG CNREG 1HF VAVPRE 20dB CMICBIAS VAVMICPGA 0dB MCLK 12 288 2 DRATE 10 TA 25 C unless otherwise noted ADC DIGITAL FILTER FREQUENCY RESPONSE CLICK POP DAC SOFT START 3 9856 10029 MAX9856 toc30 2 s 050 SCL 1 1V div 1V div 0 E DA ov 8 2 lt 5 3 HPL LINEOUTL 5mV div 1V div 5 6 7 0 5k 10k 25k TIME 200ms div TIME 4ms div FREQUENCY Hz
33. K D transition 1 The most significant bit of an audio word is latched at the s LRCLK D transition DDLY 1 28 mode rst BCLK edge after the econd BCLK edge after the MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers DAC Interface Register Bit Descriptions continued REGISTER FUNCTION PCM PCM ode Select PCM determines the format of the LRCLK D and LRCLK A signal 0 LRCLK D and LRCLK signals have 50 duty cycle Left channel audio is ransmitted during one state of and right channel audio during the other state 1 LRCLK D and LRCLK A are pulses that indicate the start of a frame of audio data consisting of two channels Following the frame sync pulse 16 bits of left channel data is immediately followed by 16 bits of right channel data The DDLY and WS bits are ignored when 4 DAC High Sample Rate Mode O LRCLK D is less than 50kHz 8x FIR interpolation filter used 1 LRCLK D is greater than 50 2 4x FIR interpolation filter used DPLLEN Word Size This bit controls both the DAC and ADC 0 16 bits 1 18 bits The DAC interface can accept higher than 18 bit words but the additional least significant bits are ignored DAC 0 val bits slave 1 val PLL Enable id for slave and master mode The frequency of LRCLK D is set by the DACNI divider n master mode MAX9856 generates
34. LD ISLD 0 IHPOCL IHPOCR IJDET IGPI Clock Control The MAX9856 can work with a master clock supplied from any system clock MCLK within the range of 10MHz to 60MHz range A clock prescaler divides by 1 2 or 4 to create an internal clock PCLK in the 10 2 to 20MHz range There are two clock generation circuits that operate independently for the ADC and DAC path allowing the ADC and DAC to be operated at different sample rates BCLK services the LRCLK signals for both the ADC and Table 4 Clock Control Register REG B5 DAC When the ADC and DAC operate at different LRCLK rates BCLK should be set appropriately for the higher sample rate The number of clock cycles per frame must be greater than or equal to the configured bit depth The MAX9856 digital audio interface can operate in either master or slave mode In master mode the MAX9856 generates the BCLK and LRCLK signals which control the data flow on the digital audio inter face In slave mode the external master device gener ates the BCLK and LRCLK signals See Table 4 0x03 0 5 Clock Control Register Bit Description 000 Disable clock input 001 10MHz lt MCLK lt 16MHz PCLK 010 16MHz lt MCLK lt 20MHz PCLK 011 20MHz lt MCLK lt 32MHz PCLK 100 32 2 lt MCLK lt 40MHz PCLK 101 40MHz lt MCLK lt 60MHz PCLK 110 Reserved 111 Reserved 1 Master mode BCLK LRCLK D and 000 Off 001
35. OLUME CONTROL Headphone Volume Control Range 5 5dB to 2dB Headphone Volume Control Step 2 5dB to 2dB Size 2dB to 46dB 468B to 74dB Headphone Mute Attenuation f 1kHz CHARGE PUMP Charge Pump Oscillator Frequency TA 25 MICROPHONE AMPLIFIERS PALEN PAREN 01 Preamplifier Gain MICL MICR PALEN PAREN 10 PALEN PAREN 11 PGAML R 0x20 IC PGA Gain A VMICPGA l 5GAMUR 0x00 IC PGA Gain Step Size IC Mute Attenuation f 1kHz INL VIN 100mVp p at 217Hz 20dB INL MICL MICR AvPRE 30dB MIC Input Resistance RIN_MIC or MICR AvpRE 20dB INL MICL or MICR AvpRE MIC Input Resistance Matching RMATCH INL to INL or MICL MICR to AGND MIC Input Bias Voltage VCML Measured at INL MICR MICL and AGND V Input Voltage Noise f 1kHz AypnE 30dB nV NHz Common Mode Rejection Ratio 6 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD VcPVDD VDVDDS2 1 8V RHP 320 RLINE 10 C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG AvPRE 20dB CmIcBIAS AvMICPGA 0dB MCLK 11 2896MHz DRATE 00 TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS RE AvMICPGA VIN 500mVp p f 1kHz A
36. RING AND MIXERS ANALOG MIXERS DIGITAL INTERFACE Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 9S86XVMI MAX9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers ABSOLUTE MAXIMUM RATINGS Voltages with respect to AGND LRCLK A LRCLK D BCLK AVDD DVDD DVDDS2 CPVDD 0 3V to 4V SDIN SBOLDT 0 3V to DVDDS2 0 3V PMSS SVS Sienan aonet Capacitor connection only Continuous Current Into Out of HPR HPL DGND CPGND 0 3V to 0 3V A SVSS 0 3V to AVDD 0 3 CPVDD CPGND C1P C1N PVSS HGNDSNS LGNDSNS 0 3V to 0 3V Any Other uu a a a JACKSNS SVSS 0 3V to AVDD 0 3V Duration of HPR HPL LOUTL LOUTR Short Circuit LOUTL LOU SVSS 0 3V to AVDD 0 3V to AVDD AGND CPVDD CPGND Continuous LINEIUNT LINEIN2 AUXIN u uu uuu sa 2V to 2V Continuous Power Dissipation TA 70 CL MICR INLP INRM 2V to 2V 40 Pin TQFN derate 26 3mW C above 70 C PVSS 0 3V to CPGND
37. RTION NOISE TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY DAC TO HP vs FREQUENCY DAC TO LINE OUT vs FREQUENCY LINE IN TO ADC 10 10 EG GANT SS 08 8 8 8 160 5 E E E E 1 1 1 5 01 01 01 5mW 001 001 001 20mW 0 001 0 001 0 001 1060 10050 1E 10E 3 100E 3 1080 100E 0 1053 00E 3 10 00 1k 10k 100k FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE POWER OUT vs FREQUENCY INTMIC TO ADC vs FREQUENCY INTMIC TO ADC vs HEADPHONE LOAD 10 5 10 100 5 3dBFS 5 ADCout 3dBFS 2 THD N 10 N 1kHz MIC PREAMP 200 MIC PREAMP 300 5 MIC GAIN 008 MIC GAIN 008 1 lt THD N 1 5 01 0 o 10 553 a 0 01 0 0 0 001 0 00 1 10 00 0k 00k 10 00 1k 10k 100k 1 0 100 1000 FREQUENCY 2 FREQUENCY Hz HEADPHONE LOAD Q 11 MAXIM 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Typical Operating Characteristics continued VAVDD VCPVDD 52 1 8V RHP 320 RUNE 10kQ C1 4 7yF C2 CREF 5 CPREG CNREG 1yF VAVPRE 20dB CMICBIAS 1uF VAVMICPGA OdB MCLK 12 288 2 DRATE 10 TA 25 C unless otherwise noted
38. T MODE EN 2 0 111 JACKSNS HPL HPR High Threshold VtH2 HPL HPR disabled JSDET HSDETL HSDETR AVMATCH tGLITCH Pulses shorter than tGLiTCH are eliminated 12 JACKSNS HPL HPR Low Threshold HPL HPR disabled JSDET HSDETL HSDETR JACKSNS HPL HPR Sense Current HPL HPR disabled JSDET HSDETL HSDETR 8 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD VpvDDS2 1 8V RHP 320 RLINE 10 C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG 1pF AvPRE 20dB CMICBIAS 1UF AvMICPGA MCLK 11 2896MHz DRATE 00 TA TMIN to unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS SLEEP MODE JDETEN 1 SHDNB 0 JACKSNS HPL Resistance MICBIAS GND 400 JACKSNS HPL Sense Voltage AVDD JACKSNS HPL Sleep Threshold AVDD AVDD AVDD JKSNS LSNS 0 8V 040 0 15 DIGITAL ELECTRICAL CHARACTERISTICS VDVDDS 1 8V TA to Tmax unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX MCLK INPUT CHARACTERISTICS nput Voltage High VIH 0 x DVDD Voltage Low VIL 0 4 nput Leakage Current lL nput Capacitance CLK Input Frequency CLK Duty Cycle aximum MCLK Input Jitter For guaranteed performance limits 100
39. TOP condition Figure 13 illustrates the frame format for reading 1 byte from the MAX9856 Figure 14 illustrates the frame format for reading multi ple bytes from the MAX9856 NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9856 ACKNOWLEDGE FROM MAX9856 1 ACKNOWLEDGE FROM MAX9856 71 SLAVE ADDRESS REGISTER ADDRESS Figure 13 Reading 1 Indexed Byte of Data from the MAX9856 ACKNOWLEDGE FROM MAX9856 ACKNOWLEDGE FROM 9856 TT T T T SLAVE ADDRESS DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER ACKNOWLEDGE FROM MAX9856 T T T T T T SLAVE ADDRESS Figure 14 Reading n Bytes of Indexed Data from the MAX9856 42 T T1 T T T SLAVE ADDRESS T T T T T T T T ES DATA BYTE n W 1BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers PCB Layout and Bypassing Proper layout and grounding are essential for optimum performance Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance Proper grounding improves audio performance minimizes crosstalk between chan nels and prevents any switching noise from coupling into the audio signal Connect AGND DGND CPGND and PGND together at a single point on the PCB using the star grounding technique Route DGND CPGND and all traces that carry switching tran
40. an open drain output A pullup resistor typi cally greater than 5000 is required on SDA SCL oper ates only as an input A pullup resistor typically greater than 5000 is required SCL if there are mul tiple masters on the bus or if the single master has an open drain SCL output Series resistors in line with SDA and SCL are optional Series resistors protect the digital inputs of the MAX9856 from high voltage spikes on the bus lines and minimize crosstalk and under shoot of the bus signals gt SCL tup STA 9 CONDITION Figure 8 2 Wire Interface Timing Diagram SMBus is a trademark of Intel Corp MAXI START CONDITION 1 lgur 9 1 i REPEATED STOP START CONDITION CONDITION 39 9S86XVMI MAX9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Bit Transfer One data bit is transferred during each SCL cycle The data on SDA must remain stable during the high period of the SCL pulse Changes in SDA while SCL is high are control signals see the START and STOP Conditions section START and STOP Conditions SDA and SCL idle high when the bus is not in use A master initiates communication by issuing a START con dition A START condition is a high to low transition on SDA with SCL high A STOP condition is a low to high transition on SDA while SCL is high Figure 9 A START condition from the master signals the beginning of a transmi
41. ction and Table 14 shows the headset detect control register and bit description Sleep Mode Jack Detection When the MAX9856 is in shutdown and the power sup ply is available sleep mode jack detection can be enabled to detect jack insertion Sleep mode applies a 2uA pullup current to JACKSNS and HPL which forces the voltage on JACKSNS and HPL to AVDD when no load is applied When a jack is inserted either JACK SNS HPL or both are loaded sufficiently to reduce the output voltage to nearly OV and clear the JKSNS or LSNS bits respectively The change in the LSNS and JKSNS bits sets JDET and triggers an interrupt on IRQ if IJDET is set The interrupt signals the microcontroller that a jack has been inserted allowing the microcon troller to respond as desired Powered On Jack Detection When the MAX9856 is in normal operation and the microphone interface is enabled jack insertion and 51515 P Figure 6 Example Jack Configuration for Jack Detection READ HSDETL HSDETR SET EN BITS TO 1 JSDET removal can be detected through the JACKSNS pin As shown in Figure 6 Vmic is pulled up by MICBIAS When a microphone is connected is assumed to be between OV and 95 of VMICBIAS If the jack is removed increases to VMICBIAS This event caus es JKMIC to be set alerting the system that the head set has been removed Alternatively if the jack is inserted VMIC decreases to below 95 of VMICBIAS and JKMIC is cleared
42. dress with the R W bit set to 1 to initi ate a read operation The MAX9856 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse A START command followed by a read command resets the address pointer to reg ister OxOO The first byte transmitted from the MAX9856 is the contents of register 0 00 Transmitted data is valid on the rising edge of SCL The address pointer autoincrements after each read data byte This auto increment feature allows all registers to be read sequentially within one continuous frame A STOP con dition can be issued after any number of read data bytes If a STOP condition is issued followed by anoth er read operation the first data byte to be read is from register OxOO The address pointer can be preset to a specific register before a read command is issued The master presets the address pointer by first sending the MAX9856 s slave address with the R W bit set to O followed by the register address A REPEATED START condition is then sent followed by the slave address with the R W bit set to 1 The MAX9856 then transmits the contents of the specified register The address pointer autoincrements after transmitting the first byte The master acknowl edges receipt of each read byte during the acknowl edge clock pulse The master must acknowledge all correctly received bytes except the last byte The final byte must be followed by a not acknowledge from the master and then a S
43. e high side of microphone or connect to the positive line signal AC couple to the signal when using with a single ended line or microphone input MICL Left Channel Single Ended Microphone Input AC couple to the microphone with a 1 capacitor MICGND MICBIAS Microphone Ground Allows the common return signal of a stereo microphone pair to be connected to the inverting input differential amps in a pseudo differential configuration Alternatively MICGND can be grounded for single ended microphone applications Right Channel Single Ended Microphone Input AC couple to the microphone with a 1uF capacitor Low Noise Bias Voltage Outputs a 1 5V or 2 4V microphone bias An external resistor in the 2 2kQ to 4700 range should be used to set the microphone current AGND Analog Ground and Chip Substrate JACKSNS 16 Jack Sense Detects the presence or absence of a jack and can be configured to detect the impedance range of the external load See the Headset Detection section Exposed Pad The exposed pad lowers the package s thermal impedance by providing a direct heat conduction path from the die to the PCB The exposed pad is internally connected to the substrate Connect the exposed thermal pad to AGND MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Functional Diagram 1 71V TO 3 6V 1 71V TO 3 6V AVDD 32dB 30dB LEFT AUDIO MIXER 32dB
44. eadphone Amplifiers Status Registers Status registers 0x00 and 0x01 are read only registers that report the status of various device functions The the status register and are set the next time the event occurs Table 2 lists the status registers bit location and description MAX9856 status register bits are cleared upon a read operation of Table 2 Status Registers Bit Location B7 B6 B4 B3 B2 B1 JKMIC HPOCL HPOCR HSDETR JDET JSDET CLD SLD LSNS JKSNS ETL Status Register Bit Description BIT FUNCTION CLD Clip Detect Flag Indicates that a signal has become clipped in the ADC Slew Level Detect Flag When volume or gain changes are made the slewing circuitry smoothly steps through all intermediate settings When SLD is set high all slewing has completed and the volume or gain is at its final value Digital PLL Unlock Flag Indicates that the digital audio PLL for the DAC or ADC has become unlocked and digital signal data is not reliable Jack Microphone Flag Indicates JACKSNS has been pulled up to the MICBIAS voltage The microphone bias must be enabled for this bit to function properly HPOCL Headphone Output Left Right Current Overload Flags Indicate that the headphone output amplifiers have HPOCR exceeded the rated current JDET Headset Configuration Change Flag Indicates a change in JKMIC LSNS or JKSNS GPI GPI State Indicates the state of LRCLK A when configured as general pu
45. el signals cause maximum gain the PGA 1dB of attenuation for every 2dB signal amplitude decrease from NG threshold NG Threshold Level NG Attenuation MAXIM 7 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD VCPVDD 52 1 8V RHP 320 RLINE 10kQ C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG AvPRE 20dB CmIcBIAS AvMICPGA 0dB MCLK 11 2896MHz DRATE 00 TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS LINEIN1 LINEIN2 INPUTS Line Input Full Scale Input Voltage Input DC Bias Voltage Line Input Resistance PGA 0dB Note 9 LINEIN1 to LINEIN2 or LINEIN2 to LINEIN1 f 1kHz Crosstalk Line Channel to Channel Gain Matching PGA Gain Range PGA Gain Step Size B to 30dB AUXIN INPUT AUXIN Full Scale Input Voltage DC 0 Input DC Voltage Range 1 Input DC Bias Voltage DC 0 DC 0 DC 1 AVMATCH AUXIN Input Resistance RIN Line Channel to Channel Gain Matching PGA Gain Range PGA Gain Step Size 32dB to 30dB JACK SENSE OPERATION EN 2 0 000 JACKSNS High Threshold 092x 095x 098x JKMIC Ten A MICBIAS MICBIAS MICBIAS JACKSNS Deglitch Period JKMIC JACKSNS Voltage JKMIC JDETEN 1 HEADSET IMPEDANCE DETEC
46. em In this mode the is bypassed increasing the impedance of the input and is directly connected to the ADC Three microphone inputs are available Two are pseudo differential inputs with a shared ground connected to the MICBIAS JACKSNS meme MICGND inverting input of the microphone preamplifier The third is a fully differential input Stereo microphones that share a common return path can take advantage of the pseudo differential configuration by connecting the com mon return to the MICGND canceling common mode noise Figure 3 shows the typical application circuit for both single ended and differential microphones The microphone preamplifier and PGA provide a wide range of gain options The microphone inputs can also be used as additional line inputs when the gain is set to A single low noise bias voltage output is available MICBIAS to bias microphones from a clean supply with an external bias resistor There are two selectable microphone bias voltages that can be selected depending on the power supply voltage Table 12 lists the audio input control registers and bit description MICBIAS JACKSNS Figure 3 Typical Microphone Connections a Pseudo Differential b Differential Table 12 Audio Input Control Registers B2 PGAAUX PGAL1 PGAL2 PGAML MAXIM PGAMR MBSEL LMICDIF 31 9S86XVMI 9856 Low Power Audio CODEC with
47. enced DirectDrive output LOUTR Right Channel Line Output Ground referenced DirectDrive output Headphone Ground Sense Feedback path to headphone amplifiers for noise reduction Connect to the ground pin of the headphone jack Connect directly to AGND if ground sense is not required Analog Power Supply Bypass to AGND with 10 and 0 1uF capacitors Left Headphone DirectDrive Output Right Headphone DirectDrive Output Negative Power Supply Input Connect to PVSS and bypass to CPGND with 4 7uF capacitor Internally Generated Negative Supply Connect to SVSS Charge Pump Flying Capacitor Negative Terminal Connect 4 7yF capacitor between and Charge Pump Ground Charge Pump Flying Capacitor Positive Terminal Connect a 4 7uF capacitor between and Charge Pump Positive Supply Bypass to CPGND with a 4 7uF capacitor MAXIM 12 Serial Clock Input Connect a 10kQ pullup resistor to DVDD 12 Serial Data Input Output Connect a 10kQ pullup resistor to DVDD Hardware Interrupt Output IRQ can be programmed to pull low when bits in the status register 0 00 change state Read status register 0x00 to clear IRQ once set Repeat faults have no effect on IRQ until it is cleared by reading the 12 status register 0x00 Connect 10kQ pullup resistor to DVDD for full output swing Digital Audio Left Right Clock Input Output LRCLK D is the audio sample rate clock that deter
48. he regis ters their addresses and power on reset POR states Registers 0 00 and 0x01 are read only while all the other registers are read write Write zeros to all unused bits in the register table when updating the register unless otherwise noted MAXIM Low Power Audio with DirectDrive Headphone Amplifiers Table 1 Register Map REGISTER POWER ON REGISTER RESET ADDRESS STATE Status 0x00 Status LSNS HSDETR Interrupt Enable ICLD IHPOCL IHPOCR CLOCK CONTROL Clock Rates DAC INTERFACE System DWCI nterface DPLLEN DACNI 14 8 nterface DACNI 7 0 ADC INTERFACE System AWCI ADLY nterface APLLEN ADCNI 14 8 nterface ADCNI 7 0 Level DIGITAL FILTER Highpass Filters AUTOMATIC GA AGC Control AGCATK AGCHLD AGC Threshold AGCSRC AGCSTH ANALOG MIXER ADC Mixer ADC Mixer Output Mixer MXOUTR AUDIO INPUTS Digital Input Gain AUXIN Gain PGALT LINEIN2 Gain PGAL2 0 14 0 00 ICL Gain PGAML 0x15 0x00 ICR Gain PGAMR IC Mode 0 MMIC MBSEL 0 LMICDIF Ox17 0 00 AUDIO OUTPUTS HPL Volume H HPR Volume HPVOLR 0x19 0x00 Output Mode EN AUXDC AUXMIX 0 0 HPMODE Ox1A 0x00 HEADSET DETECT System 0 0 0 JDETEN EN Ox1B 0x00 POWER MANAGEMENT System SHDN DIGEN LOUTEN DALEN EN ADLEN ADREN MAXIM 19 9S86XVMI Low Power Audio CODEC with DirectDrive H
49. mines whether the audio data on SDIN is routed to the left or right channel LRCLK D is an input when the MAX9856 is in slave mode and an output when in master mode D is also used with SDOUT if LRCLK A is configured as a GPIO 15 9S86XVMI MAX9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Pin Description continued FUNCTION SDIN D Audio Bit Clock Input Output BCLK is an input when the MAX9856 is in slave mode and an output w in master mode D io Serial Data ADC Output Audio Serial Data DAC Input DVDDS2 LRCLK_A D Digital Audio Interface I O Power Supply Bypass to DGND with 1uF capacitor D Audio Left Right Clock Input Output LRCLK A is the audio sample rate clock that determines whether the audio data on SDOUT is routed to the left or right channel When only one LRCLK is needed ADC and DAC are at the same sample rate LRCLK A can be reprogrammed as a general purpose input output GPIO Master Clock Input CMOS Input Acceptable Input frequency range 10MHz to 60MHz Digital Power Supply Supply for the digital core and 12C interface Bypass to DGND with a 1 0uF capacitor Digital Ground Inverting Left Differential Input AC couple to the low side of microphone or connect to the negative line signal AC couple to ground when using with a single ended line or microphone input INLP Noninverting Left Differential Input AC couple to th
50. ncy of LRCLK A is set by the ADCNI divider bits In master mode the MAX9856 generates LRCLK A using the specified divide ratio In slave mode the 9856 expects an LRCLK A using specified divide ratio 1 Valid for slave mode only A digital PLL locks on to any externally supplied LRCLK signal regardless of the MCLK frequency ADC LRCLK Divider If APIN z 01 use DACNI for both the DAC and ADC When APLLEN is set low the frequency of A is determined by ADCNI See Table 6 for common ADCNI values ADCNI 65536 x 96 x fLRCLK_A fPCLK fLRCLK A LRCLK A frequency fPcLK Prescaled MCLK internal clock frequency PCLK ADC Output Gain Specifies the gain applied to the digital output of the ADC prior to being output from the device VALUE GAIN dB 0 0 3 0 1 2 0 2 0x3 0x4 0x5 0x6 7 0 8 0 9 OxB OxC OxD OxE OxF 26 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers ADC Interface Register Bit Description continued REGISTER FUNCTION ADC Noise Gate Threshold The MAX9856 features a noise gate that reduces the audible noise at low signal levels The noise gate attenuates the output at a rate of 1dB for each 2dB the signal is below the threshold ANTH specifies the noise gate threshold level relative to the final ADC output signal level The noise gate can be used in conjunction with AGC or on
51. nput at fs 44 1kHz Note 4 VAVDD 1 71V to 3 6V Power Supply Rejection Ratio VRIPPLE 100mVp p f 217Hz VRIPPLE 100mVp p f 10kHz Capacitive Drive No sustained oscillations Pour 1 6mW f 1kHz HPL to HPR or HPR to HPL Dynamic Range Crosstalk Channel Gain Matching AVMATCH Peak voltage Into shutdown Click and Pop Level A weighted 32 samples per second Out of shutdown LINE AMPLIFIERS OdBFS DAC Output Voltage Line In to Line Out Voltage Gain OdB input PGA setting Output Offset Voltage TA 25 C MAXIM 5 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD VCPVDD VDVDDS2 1 8V RHP 320 RLINE 10kQ C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG AvPRE 20dB 5 AvMICPGA 0dB MCLK 11 2896MHz DRATE 00 TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS Total Harmonic Distortion Plus Noise Signal to Noise Ratio SNR THD N Vout 1 f 1kHz VAVDD 1 71V to 3 6V Power Supply Rejection Ratio PSRR VRIPPLE 100mVp p f 217Hz VRIPPLE 100mVp p f 10kHz Capacitive Drive CL No sustained oscillations Vour 2Vp p f 1kHz LOUTL to LOUTR or LOUTR to LOUTL Crosstalk Channel Gain Matching AVMATCH V
52. ower Management Register Bit Description BITS FUNCTION SHDN Shutdown Overrides all settings and forces the entire device into a shutdown state Digital Core Enable Set high to use either the DAC or ADC Line Output Enable Left DAC Enable Right DAC Enable Left ADC Enable Right ADC Enable I2C Serial Interface The MAX9856 features an 12C SMBus compatible 2 wire serial interface consisting of a serial qata line SDA and serial clock line SCL SDA SCL facil itate communication between the MAX9856 and the master at clock rates up to 400 2 Figure 8 shows the 2 wire interface timing diagram The master generates SCL and initiates data transfer on the bus The master device writes data to the MAX9856 by transmitting the proper slave address followed by the register address and then the data word Each transmit sequence is framed by a START S or REPEATED START Sr con dition and a STOP P condition Each word transmitted to the MAX9856 is 8 bits long and is followed by an acknowledge clock pulse A master reading data from the MAX9856 transmits the proper slave address followed by a series of nine SCL pulses The MAX9856 transmits data on SDA in sync with the master generated SCL pulses The master acknowledges receipt of each byte of data Each read sequence is framed by a START or REPEATED START condition a not acknowl edge and a STOP condition SDA operates as both an input and
53. pply Voltage Range DAC playback mode lAVDD ICPVDD fs 44 1kHz analog DVDD lDVDDS2 Line only playback mode lAVDD ICPVDD DAC line input playback mode fs 44 1kHz lAVDD ICPVDD IDVDD IDVDDS2 Total Supply Current Note 2 Full operation fs 44 1kHz DAC AUXIN Ipuppso l 37 45 lAVDD ICPVDD DVDD IDVDDS2 DAC playback fs 44 1kHz ADC record fs 8kHz IDVDD IDVDDS2 5 ADC record lAVDD ICPVDD 15 44 1kHz IDVDD IDVDDS2 lAVDD ICPVDD Shutdown Supply Current IDvDD 52 Shutdown to Full Operation 2 MAXI Low Power Audio CODEC with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS continued VAVDD VCPVDD 2 VpvDD 1 8V RHP 320 RLINE 10 C1 4 7uF C2 4 7uF CREF CMBIAS CPREG CNREG AvPRE 20dB 5 AvMICPGA 0dB MCLK 11 2896MHz DRATE 00 TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS STEREO DAC Note 3 Gain Error Channel Gain Mismatch DAC DYNAMIC SPECIFICATIONS s 44 1kHz A weighted DRATE 10 Dynamic Range Note 4 s 8kHz to 96kHz DRATE 00 A weighted DRATE 10 Total Harmonic Distortion IN 1kHz fs 8kHz to 96kHz 0dBFS S 8kHz to 96kHz DRATE 00 A weighted
54. re 4 The SNS directly to the ground terminal of the headphone jack phone outputs have separate left right volume controls to enable ground sense on the Figure 5 while the line outputs produce a fixed level signal Similarly connect LGNDSNS directly to the ground termi nal of a line output jack to enable ground sense on the line outputs If ground sense is not required connect HGNDSNS and LGNDSNS to AGND Table 13 lists the audio output control registers and bit description The audio outputs feature ground sensing which is intended to reduce the effect of ground noise In many systems the ground return for line outputs and head phone jacks is used by other functions such as video AVDD 2 CONVENTIONAL AMPLIFIER BIASING SCHEME DirectDrive AMPLIFIER BIASING SCHEME Figure 4 Traditional Amplifier Output vs MAX9856 DirectDrive Output HPR HGNDSNS Figure 5 Ground Sense Connection MAXI 35 9S86XVMI 9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Table 13 Audio Output Control 2 1 REGISTER B7 HPVOLL 0x19 HPVOLR Ox1A VSEN AUXDC AUXMIX HPMODE Audio Output Register Bit Description BITS FUNCTION HPMUTE Headphone Mute Enable Headphone Volume Control HEADPHONE VOLUME CONTROL SETTINGS SETTING GAIN dB SETTING GAIN dB SETTING GAIN dB 0x00 5 5 0x0E 8 0x1C 0x01 5 0x
55. rpose input Headphone Sense LSNS is set when the internal pullup current forces the voltage at HPL to exceed AVDD 0 4V This indicates headphone jack insertion or removal has occurred HPMODE must be set to 00 and JDETEN set to 1 for this bit to function Jack Sense JKSNS is set when the internal pullup current forces the voltage on JACKSNS to exceed AVDD 0 4V This indicates jack insertion or removal has occurred JDETEN must be set for this bit to function Load Impedance Sense Indicates the approximate load connected to HPR HPL or JACKSNS These bits are updated once each time the appropriate EN bits are set high and cause an undefeatable hardware interrupt HEADPHONE OR JACKSNS LOAD 2000 load open 50Q load 2000 0 lt load lt 500 Idle state HSDETL HSDETR JSDET 20 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Interrupt Enables Hardware interrupts are reported on the open drain IRQ pin When an interrupt occurs IRQ remains low until the interrupt is serviced by reading status register 0x00 If a flag is set it is reported as a hardware interrupt only if Table 3 Interrupt Enable Bit Locations the corresponding interrupt enable is set Each bit enables interrupts for the status flag in the respective bit location in register 0x00 Table 3 lists the interrupt enable bit locations and description REG B B B m p IC
56. sample rates from 8kHz to 48kHz in both master and slave mode The ser ial digital audio interfaces support a variety of formats including 125 left justified and PCM modes The 9856 uses a thermally efficient space saving 40 pin 6mm x 6mm x 0 8mm TQFN package Applications MP3 Players Personal Media Players Handheld Gaming Consoles Cellular Phones Pin Configuration appears at end of data sheet DirectDrive is a registered trademark of Maxim Integrated Products Inc MAXIM Features 1 71V to 3 6V Single Supply Operation Stereo 30mW DirectDrive Headphone Amplifier Stereo 1VRMs DirectDrive Line Outputs Vpp 1 8V and Stereo Line Inputs Low Noise Stereo and Mono Differential Microphone Inputs with Automatic Gain Control and Noise Quieting 9mW Playback Power Consumption Vpp 1 8V 91dB 96kHz 18 Bit Stereo DAC 85dB 48kHz 18 Bit Stereo ADC Supports Any Master Clock Frequency from 10MHz to 60MHz ADCs and DACs Can Run at Independent Sample Rates Flexible Audio Mixing and Volume Control Clickless Popless Operation Headset Detection Logic 2 Control Interface Ordering Information PART TEMP RANGE PIN PACKAGE MAX9856ETL 40 C to 85 C 40 TQFN EP Denotes lead free ROHS compliant package EP Exposed pad Simplified Block Diagram DVDD AND DVDDS2 1 71V TO 3 6V AVDD AND CPVDD 1 71V TO 3 6V MAXIM MAX9856 DIGITAL FILTE
57. sients or digital signals separately from AGND and the analog audio signal paths Ground all components associated with the charge pump to CPGND CPVSS bypassing and CPVDD bypassing Connect all digital I O termination to DGND including DVDD and DVDDS2 bypassing Bypass REF and MICBIAS to AGND Pin Configuration TOP VIEW rS jw cap moe qm maa ex og REEL pine qe T eee nee Qa 179110911411 Dry 0291 O I MAXIM MAX9856 LINEINI LINEIN2 S LGNDSNS gt THIN QFN 6mm x 6mm MAXIM Connect PVSS and SVSS together at the device and place the charge pump hold capacitor C2 as close to SVSS as possible and ground to CPGND Bypass CPVDD with a 1uF capacitor to CPGND and place the bypass capacitor as close to the device as possible The MAX9856 thin QFN package features an exposed thermal pad on its underside This pad lowers the pack age s thermal resistance by providing a direct heat conduction path from the die to the PCB Connect the exposed thermal pad to AGND An evaluation kit EV Kit is available to provide an example layout for the MAX9856 The EV Kit allows quick setup of the MAX9856 and includes easy to use software allowing all internal registers to be controlled Chip Information PROCESS BiCMOS 43 9S86XVMI MAX9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Package Informa
58. ssion to the MAX9856 The master terminates transmission and frees the bus by issuing a STOP con dition The bus remains active if a REPEATED START condition is generated instead of a STOP condition Early STOP Conditions The MAX9856 recognizes a STOP condition at any point during data transmission except if the STOP con dition occurs in the same high pulse as a START condi tion For proper operation do not send a STOP condition during the same SCL high pulse as the START condition Figure 9 START STOP and REPEATED START Conditions 40 Slave Address The MAX9856 is preprogrammed with a slave address of 0x20 or 0010000 The address is defined as the 7 most significant bits MSBs followed by the read write bit Setting the read write bit to 1 configures the MAX9856 for read mode Setting the read write bit to O configures the MAX9856 for write mode The address is the first byte of information sent to the MAX9856 after the START condition Acknowledge The acknowledge bit ACK is a clocked 9th bit that the MAX9856 uses to handshake receipt of each byte of data when in write mode see Figure 10 The MAX9856 pulls down SDA during the entire master generated 9th clock pulse if the previous byte is successfully received Monitoring ACK allows for detection of unsuc cessful data transfers An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred In the event of an unsuccessful data
59. the MAX9856 upon receipt of the address pointer data The third byte sent to the MAX9856 contains the data that is written to the chosen register An acknowledge pulse from the MAX9856 signals receipt of the data byte The address pointer autoincrements to the next register address after each received data byte This autoincrement feature allows a master to write to sequential registers within one continuous frame Figure 12 illustrates how to write to multiple registers with one frame The master signals the end of transmission by issuing a STOP condition Register addresses greater than Ox1C are reserved Do not write to these addresses ACKNOWLEDGE FROM MAX9856 JE B1 T T T T T SLAVE ADDRESS Figure 11 Writing 1 Byte of Data to the MAX9856 ACKNOWLEDGE FROM MAX9856 ACKNOWLEDGE FROM MAX9856 ACKNOWLEDGE FROM MAX9856 7 B7 Bs B4 B3 B1 180 ACKNOWLEDGE FROM T T T REGISTER ADDRESS DATA BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER ACKNOWLEDGE FROM MAX9856 PEPPER T 1 1 1 T1 1 1 SLAVE ADDRESS 0 REGISTER ADDRESS Figure 12 Writing n Bytes of Data to the MAX9856 MAXIM DATA BYTE n AJP 1 BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER 41 9S86XVMI MAX9856 Low Power Audio CODEC with DirectDrive Headphone Amplifiers Read Data Format Send the slave ad
60. the input signal has fallen below the threshold and the hold time has passed MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers AGC Register Bit Description continued FUNCTION AGCATK AGCHLD AGCSRC AGC Attack Time The attack time is the time it takes to reduce the gain after the input signal has exceeded the threshold level The gain attenuation during attack is exponential and the attack time is defined as one time constant rather than the time it takes to reach the final gain 00 3ms 01 12ms 10 50ms recommended 11 200ms AGC Hold Time Hold time is the delay before the AGC release begins The hold time counter starts whenever the signal drops below the AGC threshold and is reset by any signal that exceeds the threshold 00 disabled 01 50ms 10 100ms recommended 11 400ms and Noise Gate Signal Source Selects the audio signal that the and noise gate circuitry monitors O Left channel ADC output 1 Left channel right channel ADC output results in 3dB lower threshold for coherent signals AGCSTH MAXIM AGC Threshold Sets the signal level at which the AGC begins gain reduction The signal is monitored after the ADC output gain has been applied AGC THRESHOLD LEVELS AGCSTH LEVEL dB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
61. tion For the latest package outline information go to www maxim ic com packages QFN THIN EPS A o 10 PIN 110 0 35x45 A R 15 OPTIONAL DDALLAS AVIALXL VI TITLE PACKAGE OUTLINE 36 40 48L THIN QFN 6x6x0 8mm DRAWNG NOT TO SCALE HA SEATING PLANE 44 MAXIM Low Power Audio CODEC with DirectDrive Headphone Amplifiers Package Information continued For the latest package outline information and land patterns go to www maxim ic com packages COMMON DIMENSIONS EXPOSED PAD VARIATIONS T3666N 1 T3666MN roa s sca aso azn aon 425 14866 1 _ 4 40 4 50 4 60 4 40 4 50 4 60 1 4 40 4 50 4 60 4 40 4 50 4 60 4866 2 4 40 4 50 4 60 4 40 4 50 4 60 NOTES 1 DIMENSIONING 8 TOLERANCING CONFORM TO ASME 14 5 1994 2 ALL DIMENSIONS ARE IN MILLIMETERS ANGLES ARE IN DEGREES 3 N IS THE TOTAL NUMBER OF TERMINALS THE TERMINAL 1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95 1 5 012 DETAILS OF TERMINAL 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED THE TERMINAL 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0 25mm AND 0 30mm FROM TERMINAL 6 ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY 7 DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION
62. transmitted while LRCLK A is low 1 Right channel data is transmitted while LRCLK is low 0 Start of a new frame is signified by the falling edge of the LRCLK pulse 1 Start of a new frame is signified by the rising edge of the LRCLK pulse ADC BCLK Invert timing MAXIM 0 SDOUT is valid on the rising edge of BCLK 1 SDOUT is valid on the falling edge of BCLK If operating in master mode the ABCI bit has no effect The DBCI bit controls BCLK to LRCLK A 25 9S86XVMI Low Power Audio CODEC with DirectDrive Headphone Amplifiers ADC Interface Register Bit Description continued REGISTER FUNCTION LRCLK A GPIO Configuration 00 General purpose input 01 Word clock for the ADC 10 2 General purpose output low 11 General purpose output high When APIN z 01 LRCLK D is used as the word clock for both the DAC and ADC AWCI ABCI and ADLY are still active and independent from the DAC mode bit settings when operating with a shared LRCLK D ADC Data Delay 0 The most significant bit of an audio word is valid at the first BCLK edge after the LRCLK transition 1 The most significant bit of an audio word is valid at the second BCLK edge after the LRCLK A transition 1 for I S compatible mode MAX9856 ADC PLL Enable This bit only applies when APIN 01 When z 01 use DPLLEN for both the DAC and ADC 0 Valid for slave and master mode The freque
63. weighted Total Harmonic Distortion Plus 20dB 098 Noise ViN 50mVp p f 1kHz A weighted 30dB AvMICPGA VIN 18mVp p f 1kHz A weighted VAVDD 1 71V to 3 6V TA 25 MIC Power Supply Rejection Ratio PPLE 100mV at 1 2 input referred VRIPPLE 100 at 10kHz input referred MICROPHONE BIAS VAVDD 1 8V MBSEL 0 register setting VAVDD 3 0V MBSEL 1 register setting BIAS Load Regulation IMICBIAS 0 to 2mA AS Capacitive Load Minimum capacitive load AS Short Circuit Current To GND VAVDD 1 71V to 3 6V MBSEL 0 AS Power Supply Rejection TA 25 C VRIPPLE 100 at 1kHz VRIPPLE 100mV at 10kHz VNOISEMIC f 10Hz to 20kHz MBSET or 1 BIAS f 1 2 CBIAS Output Voltage VMICBIAS MICBIAS Noise Voltage AUTOMATIC GAIN CONTROL Threshold Level Set by AGCSTH 3 0 Attack Time Set by AGCATK 1 0 Release Time Set by AGCRLS 2 0 Hold Time Set by AGCHLD 1 0 30dB 30 to 50 Gain Adjustment Range 20dB 20 to 40 01020 ADC LOW LEVEL QUIETING Full 12dB quieting at 1dB of attenuation gain for every 2dB NG Attack and Release Time decrease increase of signal level immediate release if PGA lt 20dB gain when AGC is enabled ANTH 3 0 setting range AGC off AGC on adjusts these values by 2088 since low lev
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MAXIM MAX9856 handbook