MAXIM MAX17000 handbook
Contents
1. 100 STANDBY MODE 00 FSTANDEY MODE E io E NOB MOL 5 4 MOD gg STANDBY MODE 80 3 80 4 80 ES 70 70 T 7 2 lt 7 Sc 8 60 5 6 5060 a SKIP MODE ee a SKIP MODE B amp 7 S 50 S 50 WM MODE S 8 T T p 3 SKIP MODE PWM MODE 40 40 0 30 30 30 20 2 20 Vin 7V Vin 12V Vin 20V 10 10 10 0 01 0 1 10 0 01 4 1 0 001 4 1 0 LOAD CURRENT LOAD CURRENT A LOAD CURRENT A SMPS 1 8V OUTPUT VOLTAGE SMPS SWITCHING FREQUENCY SMPS VALLEY CURRENT LIMIT vs LOAD CURRENT vs LOAD CURRENT vs INPUT VOLTAGE 1 82 350 10 50 8 8 RgENSE 2mQ 5 300 2 F i 3 181 SKIP MODE 10 25 x 25 2 amp m S 200 gt 180 E 10 00 5 150 ODE E 5 5 PWM M a 1 79 975 50 Vin 12 Vin 12V Vout 1 8V 1 78 9 50 0 001 0 01 0 1 1 0 0 2 4 6 8 10 4 8 12 16 20 24 2 LOAD CURRENT A LOAD CURRENT A INPUT VOLTAGE V NO LOAD SUPPLY CURRENT PRESET 1 5V OUTPUT vs INPUT VOLTAGE VOLTAGE DISTRIBUTION 100 z NO LOADS SAMPLE SIZE 150 85 C E PWM MODE Icc 100 gt r 17 EI 40 E 10 E PWM MODE MODE Icc Ipp 30 Lu 1 e DBY MODE Icc Ipp amp 55 a a a 5 SKIP MODE2. DL high DL low DL Gate Driver On Resistance RDL DH Gate Driver Source Sink Current DL Gate Driver Source IDL SRC DL forced to 2 5V Sink Current IDL SNK DL forced to 2 5V DL rising 25 C DL falling TA 25 C Internal BST Switch IBST 10mA On Resistance Vpp 5V internal design target Vest Vix 26V SHDN AGND TA 25 C IDH DH forced to 2 5V BST LX forced to 5V Dead Time LX BST Leakage Current INPUTS AND OUTPUTS SHDN STDBY SKIP OVP rising edge hysteresis 300mV 600mV min max SHDN STDBY SKIP or Vcc Ta 25 C Logic Input Threshold Logic Input Current Input Leakage Current CSH 0 or Voc TA 25 C Input Bias Current CSL 0 or Vcc 5 000Z LXVIW 17000 Complete DDR2 and Memory Power Management Solution ELECTRICAL CHARACTERISTICS ViN 12V Voc Vpp VSHDN VREFIN 5V Vcsr 1 8V STDBY SKIP AGND TA 40 C to 85 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS PWM CONTROLLER VIN VDD Input Voltage Range FB AGND Output Voltage Accuracy VCSL FB FB Adj RTON 96 75kQ 600kHz 167ns nomina RTO 200kQ 300kHz 333n nomina RTO 303 25 200kHz 500n nomina 12V 2 1 2
3. PGOOD1 Leakage Current IPGOOD1 Rising edge PWM disabled below this level hysteresis 200mV TON POR Thresh VPOR IN FAULT DETECTION VTT PGOOD Upper Trip Threshold Hysteresis 25mV PGOOD2 Lower Trip Threshold Hysteresis 25mV VTTS forced 50mV beyond PGOOD2 trip threshold VTTS forced 50mV beyond PGOOD2 trip threshold PGOOD Output Low Voltage ISINK 3mA VTTS VngriN PGOOD2 high impedance PGOOD2 forced to 5V Ta 25 PGOOD2 Propagation Delay tPGOOD2 PGOOD2 Fault Latch Delay PGOOD2 Leakage Current IPGOOD2 FAULT DETECTION Thermal Shutdown Threshold TSHDN Hysteresis 15 C Vcc Undervoltage Lockout Threshold CSL Discharge MOSFET OVP Vcc Rising edge IC disabled below this level VUVLOUCO hysteresis 200mV 4 MAXIM Complete DDR2 DDR3 Memory Power Management Solution ELECTRICAL CHARACTERISTICS continued ViN 12V Vcc Vpp VSHDN VREFIN 5V VosL 1 8V STDBY SKIP AGND 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS CURRENT LIMIT Valley Current Limit Threshold Vumir Vest 17 20 25 Current Limit Threshold T Negative VCSH VCSL SKIP Vcc 23 mV Current Limit Threshold Zero Crossing VcsH VCSL 1 mV SMPS GATE DRIVERS DH Gate Driver On Resistance BST LX forced to 5V 1 5 5 0 1 5 5 0 Q
4. 000Z LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution Valley Current Limit Protection The MAX17000 uses the same valley current limit pro tection employed on all Maxim Quick PWM controllers If the current exceeds the valley current limit threshold the PWM controller is not allowed to initiate a new cycle The actual peak current is greater than the valley cur rent limit threshold by an amount equal to the inductor ripple current Therefore the exact current limit charac teristic and maximum load capability are a function of the inductor value and battery voltage When combined with the undervoltage protection circuit this current limit method is effective in almost every circumstance In forced PWM mode the MAX17000 also implements a negative current limit to prevent excessive reverse inductor currents when Vour is sinking current The negative current limit threshold is set to approximately 115 of the positive current limit See Figure 5 lu gt a ILIM VAL h HR Figure 5 Valley Current Limit Threshold Point Power Good Outputs PGOOD1 and PGOOD2 The MAX17000 features two power good outputs PGOOD1 is the open drain output for a window com parator that continuously monitors the SMPS output PGOOD1 is actively held low in shutdown and during soft start and soft shutdown After the soft start termi nates PGOOD1 b
5. 17000 Complete DDR2 and DDR3 Memory Power Management Solution Applications Information PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and clean stable operation The switching power stage requires particular attention If possible mount all the power components on the topside of the board with their ground terminals flush against one another Follow these guidelines for good PCB layout e Keep the high current paths short especially at the ground terminals This practice is essential for sta ble jitter free operation e Keep the power traces and load connections short This practice is essential for high efficiency Using thick copper PCBs 20z vs 10z can enhance full load efficiency by 1 or more Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters where a single millionm of excess trace resistance causes a measurable efficiency penalty e Minimize current sensing errors by connecting CSH and CSL directly across the current sense resistor RSENSE e When trade offs in trace lengths must be made it is preferable to allow the inductor charging path to be made longer than the discharge path For example it is better to allow some extra distance between the input capacitors and the high side MOSFET than to allow distance between the inductor and the low side MOSFET or between the inductor and the out put filter capac
6. 2 DDR3 Memory Power Management Solution The maximum ESR to meet ripple requirements is Vin X fsw xL Vin Vout x Vout Resr lt X VRIPPLE where fsw is the switching frequency With most chemistries polymer tantalum aluminum electrolytic the actual capacitance value required relates to the physical size needed to achieve low ESR and the chemistry limits of the selected capacitor tech nology Ceramic capacitors provide low ESR but the capacitance and voltage rating after derating are determined by the capacity needed to prevent VSAG and VsoAR from causing problems during load tran sients Generally once enough capacitance is added to meet the overshoot requirement undershoot at the rising load edge is no longer a problem Thus the out put capacitor selection requires carefully balancing capacitor chemistry limitations capacitance vs ESR vs voltage rating and cost PWM Output Capacitor Stability Considerations For Quick PWM controllers stability is determined by the in phase feedback ripple relative to the switching frequen Cy which is typically dominated by the output ESR The boundary of instability is given by the following equation fow 5 1 x 2nxRgrp x CouT Resr Acs RSENSE where Cour is the total output capacitance REsR is the total equivalent series resistance of the output capaci ors RSENSE is the effective current sense resistance see Figure 8
7. 2 MAXIM Complete DDR2 DDR3 Memory Power Management Solution ELECTRICAL CHARACTERISTICS continued VIN 12V Vcc Vpp VSHDN VREFIN 5V Vcs 1 8V STDBY SKIP AGND TA 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS Minimum Off Time toFF MIN No B forced above 1 0V STDBY AGND or cc TA 25 C F V FB forced above 1 0V SMPS VTT and VTTR blocks STDBY 2 Vcc F b Quiescent Supply Current Vpp Quiescent Supply Current Vcc B forced above 1 0V ultra skip and VTTR ocks STDBY AGND Shutdown Supply Current SHDN AGND Ta 25 C Vcc CC IDD A SHDN AGND VIN 26V Vpp or 5V Ta 25 C TON Pin Shutdown Current LINEAR REGULATOR VTT VTTI Input Voltage Range VTTI VTTI Supply Current VTTI 2 8V REFIN 1 4 no load Shutdown Current DN AGND Ta 25 C FIN Input Bias Current 1 4V Ta 25 C FIN Range VREFIN FIN Disable Threshold High side on resistance source lyr 0 1A VTT Internal MOSFET Low side on resistance sink 0 1A 1V VREFIN 5mV or 500A Vcs_ 2 5mV to VTIS VTT VI 0 5V to 1 5V 300 1V VREFIN 5mV H Output Accuracy Vcsu 2 5mV k Load VTTS VTT VTTS 0 5V to 1 5V
8. AVLAZCLAVI 9 000Z LXVIW 17000 Complete 2 and DDR3 Memory Power Management Solution Typical Operating Characteristics continued MAX17000 Circuit of Figure 1 Vin 12V Vpp Vcc 5V SKIP GND TA 25 C unless otherwise noted VTT VOLTAGE VTT OFFSET VOLTAGE DISTRIBUTION OUTPUT OVERLOAD WAVEFORM vs SOURCE SINK LOAD CURRENT AT 300mA LOAD 17000 toc15 0 79 8 SAMPLE SIZE 150 85 0 8 DL i 8 25 0 xu 8 E 2 40 E VDDQ VIT 076 3 PGOOD2 5 PGOOD1 gt 075 TE gt 0 74 5 10 0 73 Vit 18V 0 72 0 400 5 20 15 10 05 0 05 10 15 20 150 125 100 45 5 0 DL 5V div PGOOD 2V div LOAD CURRENT A OFFSET VOLTAGE mV VDDQ 1V div PGOOD1 2V div VIT 1V div 10A div 1V div VTT OVERLOAD FAULT WAVEFORMS VTT SOURCE CURRENT LIMIT VTT SINK CURRENT LIMIT bms TIMER 50 MAX17000 toc20 SAMPLE SIZE 150 85 C 2 SAMPLE SIZE 150 B 425 C mm 8 8 DL 40 3 2040 lx Co co 30 30 2 VDDQ ER 20 20 a a 1 VITR 10 1 10 PGOOD1 PGOOD2 0 0 2 0 25 30 35 40 40 35 3 0 25 2 0 1ms div CURRENT LIMIT A CURRENT LIMIT A DL 5V div 1V div lx 2A div PGOODI 2
9. Minimum Off Time toFF MIN Note 2 FB forced above 1 0V PWM VTT and VTTR blocks STDBY Vcc Quiescent Supply Current Vcc lcc FB forced above 1 0V ultra skip and VTTR blocks STDBY AGND LINEAR REGULATOR VTT VTTI Input Voltage Range VyTTI VTTI Supply Current 2 8V REFIN 1 4V no load REFIN Range VREFIN REFIN Disable Threshold High side on resistance source Internal MOSFET Low side on resistance sink lvrr 0 1A VTT Load Regulation 50pA to 1A lt Iyrr 50pA to 1A 6 MAXIM Complete DDR2 DDR3 Memory Power Management Solution ELECTRICAL CHARACTERISTICS continued ViN 12V Vcc Vpp VSHDN VREFIN 5V Vcsr 1 8V STDBY SKIP AGND TA 40 C to 85 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS REFERENCE BUFFER VTTR VTTR Output Accuracy Adj EFIN to VTTR VTTR Output Accuracy Preset Vcsu 2 to VITR FAULT DETECTION SMPS PGOOD1 Output Low Voltage ISINK 3mA FAULT DETECTION VTT PGOOD Output Low Voltage ISINK 3mA FAULT DETECTION Vcc Undervoltage Lockout Threshold CURRENT LIMIT Valley Current Limit Threshold VLIMIT VcsH VCSL SMPS GATE DRIVERS DH Gate Driver On Resistance RDH BST LX forced to 5V DL high DL low DL rising DL falling Rising edge IC disabled below this level hysteresis 200mV VUVL
10. and Acs is the current sense gain of 2 For a standard 300kHz application the effective zero frequency must be well below 95kHz preferably below 50kHz With these frequency requirements standard tantalum and polymer capacitors already commonly used have typical ESR zero frequencies below 50kHz allowing the stability requirements to be achieved with out any additional current sense compensation In the standard application circuit Figure 7 the ESR needed to support 15mVp p ripple is 15mV 10A x 0 3 5mQ Two 330uF polymer capacitors in parallel provide 4 5mQ max ESR and 1 2x x 330yF x 9mQ 53kHz ESR zero frequency Ceramic capacitors have a high ESR zero frequency but applications with sufficient current sense compen sation can still take advantage of the small size low ESR and high reliability of the ceramic chemistry By the inductor current DCR sensing applications with 26 ceramic output capacitors can be compensated using either a DC compensation or AC compensation method The DC coupling requires fewer external com pensation capacitors but this also creates an output load line that depends on the inductor s DCR parasitic resistance Alternatively the current sense information can be AC coupled allowing stability to be dependent only on the inductance value and compensation com ponents and eliminating the DC load line see Figure 9 When only using ceramic output capacitors out
11. and enters the low current 1 shutdown state When discharge mode is enabled by OVP OVP high the CSL and VTT internal 16Q discharge MOSFETs are enabled in shutdown When discharge mode is disabled by OVP OVP low LX VTT and VTTR are high impedance in shutdown A rising edge on SHDN clears the fault OV protection latch Exposed Pad Connect backside exposed pad to AGND 13 000Z LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution Standard Application Circuits The MAX17000 standard generates the VDDQ VTT and VTTR rails for DDR Table 1 Componen COMPONENT Input Capacitor application circuit Figure 1 Vout 1 5V TO 1 8V AT 10A Vin 7V TO 20V 300kHz 2x 10uF 25V Taiyo Yuden TMK432BJ106KM DDR2 or DDR3 in a notebook computer See Table 1 for component selections Table 2 lists the component man ufacturers Table 3 is the operating mode truth table t Selection for Standard Applications VoUT 1 5V TO 1 8V AT 6A VIN 7V TO 16V 500kHz 10yF 25V Taiyo Yuden TMK432BJ106KM Output Capacitor 2x 3 2 5V 12mQ C2 case SANYO 2R5TPE330MCC2 2x 220yF 2 5V 21mQ B2 case SANYO 2R5TPE220MLB Inductor Current Sensing Resistor 1 4uH 12A 3 4mQ typ Sumida CDEP105 L NP 1R4 2mQ 0 5W 2010 Vishay WSL20102LOO0FEA 14H 12A 3 4mQ typ Sumida CDEP105 L NP 1R4 3mQ 0 5W 2010 Vishay WSL20103LOO0
12. lower parasitic capacitance For the low side MOSFET NL the worst case power dissipation always occurs at maximum input voltage PD NL Resistive 1 x Rog on VIN MAX The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD MAX but are not quite high enough to exceed the current limit and cause the fault latch to trip To pro tect against this possibility the circuit can be over designed to tolerate zl AlNDUCTOR LOAD VALLEY MAX _ xX LIR 5 27 0004 LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution where IVALLEY MAX is the maximum valley current allowed by the current limit circuit including threshold tolerance and on resistance variation The MOSFETs must have a good size heatsink to handle the overload power dissipation Choose a Schottky diode DL with a forward voltage low enough to prevent the low side MOSFET body diode from turning on during the dead time Select a diode that can handle the load current during the dead times This diode is optional and can be removed if effi ciency is not critical Setting the PWM Output Voltage Preset Output Voltages 17000 Dual Mode operation allows the selection of common voltages without requiring external components Connect FB to AGND for a fixed 1 5V out put to Vcc for a fixed 1 8V output
13. DDR2 and DDR3 Memory Power Management Solution Table 3 Operating Mode Truth Table OPERATION PS output ramps up in skip mode with a 1 4ms typ ramp time PGOOD I is held low until the PS output is in regulation ramp up to the final voltage based on 1 2 or VREFIN 2 is held low until T is in regulation PS output ramps up in skip mode with a 1 4ms ramp time PGOOD is held low until the SMPS put is in regulation ce CSL or FB is in regulation the PWM block turns off and enters standby mode T remains off throughout since STDBY is low PGOOD2 stays low throughout The VTT discharge T is enabled if OVP is high but disabled if OVP is low TR ramps up to the final voltage based on Vcsi 2 or VREFIN Ultra skip and standby modes are exited and the full current capability of the MAX17000 is available VTT ramps up after the internal SMPS block is ready VTT ramps to the final voltage based on 1 2 or VREFIN PGOOD2 goes high when VTT is in regulation SMPS output is in forced PWM mode VTT and VTTR are enabled PGOOD1 is high when the SMPS output is in regulation PGOOD2 is high when VTT is in regulation SMPS output is in normal skip mode VTT and VTTR are enabled PGOOD1 is high when the SMPS output is in regulation PGOOD2 is high when VTT is in regulation SMPS output is in ultra skip mode VTT is off and is high impedance PGOOD2 is for
14. Iin wn be lt 01 e Lt 10 STANDBY MODE T 0 01 0 4 8 12 16 20 24 2 1490 1495 1500 1505 1510 INPUT VOLTAGE V OUTPUT VOLTAGE V 8 Complete 2 DDR3 Memory Power Management Solution Typical Operating Characteristics continued MAX17000 Circuit of Figure 1 Vin 12V Vpp Vcc 5V SKIP GND TA 25 C unless otherwise noted STARTUP WAVEFORM SHUTDOWN WAVEFORM HEAVY LOAD DISCHARGE MODE ENABLED STANDBY TRANSITION WAVEFORM MAX17000 toc09 MAX17000 toc10 17000 0611 22 STBY SHDN VDDQ VTT VDDQ TON VTT DL PGOOD1 DL lx ___ 200us div 400us div 2 2ms div SHDN 5V div PGOOD1 2V div Rigap 0 2522 DL 5V div PGOOD 5V div STBY 5V div DL 5V div VDDQ 500mV div 5A div SKIP GND VDDQ 2V div PGOOD 5V div VDDQ 1V div LX 10V div VIT 500mV div DL 5V div VIT 1V div SHDN 10V div VIT 1V div lix 2A div 500mV div VTTR 1V div lix 2A div TON 10V div SMPS LOAD TRANSIENT RESPONSE SMPS LOAD TRANSIENT RESPONSE STANDBY TRANSITION WAVEFORM SKIP MODE SKIP MODE MAX17000 toc12 17000 toc13 17000 toc14 VDDQ VDDQ LX LX lLOAD lx uu 200us div 20us div 20us div STBY 5V div LX 10V div VDDQ 50mV div lLoap SA div VDDQ 50mV div lLoap SA div VDDQ 2V div lux 10A div LX 10V div lx 5A div LX 10V div lux 5A div VIT 1V div DL 5V div TON 10V div
15. VIT 160 FET CSL 169 FET Po Figure 6 MAX17000 Startup Shutdown Timing when OVP Is Enabled Soft shutdown begins after SHDN goes low an outpu undervoltage fault occurs or a thermal fault occurs A fault on the SMPS UV fault for more than 200us typ or fault on the VTT output that persists for more than 5ms typ triggers shutdown of the whole IC During soft shutdown the output is ramped down to OV in 2 8ms reducing negative inductor currents that can cause negative voltages on the output At the end of soft shutdown DL is driven low AVLAZCLA When OVP is enabled OVP Vcc the internal 160 discharging MOSFETs on CSL and VTT are enabled until startup is triggered again by a rising edge of SHDN When OVP is disabled OVP AGND the CSL and VTT internal 160 discharging MOSFETs are not enabled in shutdown Output Fault Protection The MAX17000 provides overvoltage undervoltage fault protections for the PWM output Drive OVP to enable and disable fault protection as shown in Table 4 21 000Z LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution Table 4 Fault Protection and Shutdown Setting Truth Table ov won REACTION DRIVER STATE COMMENT DL immediately pulled low Shutdown VTTR tracks the SMPS output during soft shutdown CSL and VTT i prie E SHDN low high impedance at the end of soft shutdown 16 discharge NE MOSFETs disabl
16. VTTI is the input power supply to the VTT linear regulator Normally connected to the output of the SMPS regulator for DDR applications 12 External Reference Input REFIN sets the feedback regulation voltage VTTR VREFIN of the 17000 Connect REFIN to Vcc to use the internal Vcsi 2 divider Connect 0 5V to 1 5V voltage input to set the adjustable output for VTT VTTS VTTR Feedback Input for SMPS Output Connect to Vcc for a fixed 1 8V output or to AGND for a fixed 1 5V output For an adjustable output 1 0V to 2 7V connect FB to a resistive divider from the output voltage FB regulates to 1 0V Negative Input of the PWM Output Current Sense and Supply Input for Connect CSL to the negative side of the output current sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing CSL is also the path for the internal 16 discharge MOSFET when Vcc UVLO occurs with OVP enabled Positive Input of the PWM Output Current Sense Connect CSH to the positive side of the output current sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing MAXIM Complete DDR2 DDR3 Memory Power Management Solution Pin Description continued FUNCTION Switching Frequency Setting Input An external resistor between the input power source and this pin sets the switching
17. after soft shutdown Discharge Enabled DL immediately latched high DH forced low OVP High SMPS OVP PGOOD1 PGOOD2 immediately forced low SMPS latched fault enabled VTT and VTTR blocks immediately shut down Internal 160 condition discharge MOSFETs on CSL and VTT enabled SMPS UVP PGOOD2 immediately pulled low Soft shutdown initiated if fault persists for more than 5ms typ DH not used in soft shutdown DL low after soft shutdown completed VTTR tracks the SMPS output during soft shutdown Internal 160 discharge MOSFETs on CSL and VTT enabled after soft shutdown VTT latched fault condition if fault persists for more than 5ms typ VTT 90 or VIT gt 110 DL and DH immediately pulled low OVP Enabled Vcc UVLO PGOOD1 and PGOOD2 immediately forced low Discharge Enabled falling edge VTT and VTTR blocks immediately disabled OVP High Internal 16Q discharge MOSFETs on CSL and VTT enabled immediately 22 MAXIM Complete DDR2 DDR3 Memory Power Management Solution Table 4 Fault Protection and Shutdown Setting Truth Table continued MODE REACTION DRIVER STATE DL and DH immediately pulled low PGOOD1 and PGOOD2 immediately forced low VTT and VTTR blocks immediately disabled high impedance no 16Q discharge on outputs Activate INT_REF once Vcc rises above UVLO and SHDN high Once REFOK is valid high initiate the soft start sequence DL
18. frequency per phase according to the following equation Tsw CroN x RTON 6 5kQ where CTON 16 26pF TON is high impedance in shutdown High Side Gate Driver Output Swings from LX to BST DH is low when in shutdown or UVLO Inductor Connection Connect LX to the switched side of the inductor as shown in Figure 1 Boost Flying Capacitor Connection Connect to an external 0 1uF 6V capacitor as shown in Figure 1 The MAX17000 contains an internal boost switch Synchronous Rectifier Gate Driver Output DL swings from Vpp to PGND1 Supply Voltage Input for the DL Gate Driver and 3 3V Reference Analog Supply Connect to the system supply voltage 4 5V to 5 5V Bypass Vpp to power ground with a 1uF or greater ceramic capacitor Power Ground Ground connection for the low side MOSFET gate driver Analog Ground Connect backside exposed pad to AGND Pulse skipping Control Input This input determines the mode of operation under normal steady state conditions and dynamic output voltage transitions High gt 2 4V Forced PWM operation Low AGND Pulse skipping mode Controller Supply Voltage Connect to a 4 5V to 5 5V source Bypass Vcc to AGND with a 1pF or greater ceramic capacitor Shutdown Control Input Connect to Vcc for normal operation When SHDN is pulled low the MAX17000 slowly ramps down the output voltage to ground When the internal target voltage reaches 25mV the controller forces DL low
19. or connect FB directly to OUT for a fixed 1 0V output Adjustable Output Voltage The output voltage can be adjusted from 1 0V to 2 7V using a resistive voltage divider Figure 8 The MAX17000 regulates FB to a fixed reference voltage 1 0V The adjusted output voltage is Vout Pees where VFB is 1 0 LX DL PGND1 MAXIM VTTI Input Capacitor Stability Considerations The value of the VTTI bypass capacitor is chosen to limit the amount of ripple noise at VTTI and the amount of voltage dip during a load transient Typically VTTI is connected to the output of the buck regulator which already has a large bulk capacitor Nevertheless a ceramic capacitor of equivalent value to the VTT output capacitor must be used and must be added and placed as close as possible to the VTTI pin This value must be increased with larger load current or if the trace from the VTTI pin to the power source is long and has significant impedance Setting VTT Output Voltage The VTT output stage is powered from the VTTI input The output voltage is set by the REFIN input REFIN sets the feedback regulation voltage VTTR VTTS VREFIN of the MAX17000 Connect a 0 1V to 2 0V volt age input to set the adjustable output for VTT VTTS and VTTR If REFIN is tied to Vcc the internal CSL 2 divider is used to set VTT voltage hence VTT tracks the VcsL voltage and is set to Vcsi 2 This feature makes the MAX17000 ideal for memory a
20. remains low until switching soft start begins COMMENT Thermal fault Active fault condition General Shutdown and Fault Conditions Vcc UVLO rising edge Vcc POR rising edge Vcc POR DL Don t care Vcc less than 2VT is not sufficient to turn on the falling edge MOSFETs DL forced low SMPS Overvoltage Protection OVP If the output voltage of the SMPS rises 115 above its nominal regulation voltage while OVP is enabled OVP Vcc the controller sets its overvoltage fault latch pulls PGOOD1 and PGOOD2 low and forces DL high The VTT and VTTR block shut down immediately and the internal 16Q discharge MOSFETs on CSL and are turned on If the condition that caused the overvolt age persists such as a shorted high side MOSFET the battery fuse blows Cycle Vcc below 1V or toggle SHDN to clear the overvoltage fault latch and restart the controller OVP is disabled when OVP is connected to GND Table 4 PGOOD upper threshold remains active at 115 of nominal regulation voltage even when OVP is disabled and the 160 discharge MOSFETs on CSL and VTT are not enabled in shutdown SMPS Undervoltage Protection UVP If the output voltage of the SMPS falls below 8596 of its regulation voltage for more than 200us typ the controller sets its undervoltage fault latch pulls PGOOD1 and PGOOD2 low and begins soft shutdown pulsing DL DH remains off during the soft shutdown sequence initiated by an undervolt
21. 0FEA Table 2 Componen SUPPLIER INDUCTORS 30V 20A n channel MOSFET high side Fairchild FDMS8690 30V 40A n channel MOSFET low side Fairchild FDMS8660S t Suppliers 30V 20A n channel MOSFET high side Fairchild FDMS8690 30V 40A n channel MOSFET low side Fairchild FDMS8660S WEBSITE Dale Vishay 402 563 6866 www vishay com NEC TOKIN America Inc Panasonic Corp Sumida Corp 510 324 4110 65 23 1 3226 Singapore 408 982 9660 408 749 9714 USA www nec tokinamerica com www panasonic com www sumida com TOKO America Inc 858 675 8013 www tokoam com CAPACITORS AVX Corp 843 448 9411 USA WWW avxcorp com KEMET Corp 408 986 0424 USA www kemet com Panasonic Corp SANYO Electric Co Ltd 65 231 3226 Singapore 408 749 9714 USA 81 72 870 6310 Japan 619 661 6835 USA www panasonic com www sanyodevice com Taiyo Yuden 03 3667 3408 Japan 408 573 4150 USA www t yuden com Corp SENSING RESISTORS Vishay 847 803 6100 USA 81 3 5201 7241 Japan 402 563 6866 USA www component tdk com www vishay com MOSFET Fairchild Semiconductor DIODES 800 341 0392 USA www fairchildsemi com Central Semiconductor Corp 631 435 1110 www centralsemi com Nihon Inter Electronics Corp 14 81 3 3343 84 3411 Japan www niec co jp MAXIM Complete
22. 19 4125 0 5 08 MAKII Complete DDR2 and DDR3 Memory Power Management Solution General Description The MAX17000 pulse width modulation PWM con troller provides a complete power solution for notebook DDR DDR2 and DDR3 memory It comprises a step down controller a source sink LDO regulator and a ref erence buffer to generate the required VDDQ VTT and VTTR rails The VDDQ rail is supplied by a step down converter using Maxim s proprietary Quick PWM controller The high efficiency constant on time PWM controller han dles wide input output voltage ratios low duty cycle applications with ease and provides 100ns response to load transients while maintaining a relatively constant switching frequency The Quick PWM architecture cir cumvents the poor load transient timing problems of fixed frequency current mode PWMs while also avoid ing the problems caused by widely varying switching frequencies in conventional constant on time and con stant off time PWM schemes The controller senses the current to achieve an accurate valley current limit pro tection It is also built in with overvoltage undervoltage and thermal protections The MAX17000 can be set to run in three different modes power efficient SKIP mode low noise forced PWM mode and standby mode to support memory in notebook computer stand by operation The switching frequency is programma ble from 200kHz to 600kHz to allow small components and high effi
23. 2 ZERO CROSSING SMPS RUN VALLEY CURRENT LIMIT SOFT START S VTT WINDOW MAXUM INT_REF MAX17000 COMPARATOR Figure 2 MAX17000 Functional Diagram MAXUM SMPS RUNOK STDBY VIT CURRENT LIMIT VIT SS CURRENT LIMIT VIT VITNEG PGND2 CURRENT LIMIT VIT EN 17 000Z LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution 5V Bias Supply Vcc The MAX17000 requires an external 5V bias supply in addition to the battery Typically this 5V bias supply is the notebook s 95 efficient 5V system supply Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers If stand alone capability is needed the 5V supply can be generated with an external linear regulator such as the MAX1615 The 5V bias supply powers both the PWM controller and internal gate drive power so the maximum current drawn is IBIAS IQ fswQG MOSFETs 2mA to 20 typ where lQ is the current for the PWM control circuit fsw is the switching frequency and QG MOSFETs is the total gate charge specificat
24. 300mA VTT Output Accuracy Source Load T Load Regulation 50pA to 1A 1 50pA to 1A 1 0V lt VTTI lt 2 8V lyrr x100mA Source Sink With respect to internal VTT EN signal OVP 25 T Line Regulation T Current Limit T Current Limit Soft Start Time T Discharge MOSFET TS Input Current 3 000Z LXVIN 17000 Complete DDR2 and DDR3 Memory Power Management Solution ELECTRICAL CHARACTERISTICS continued 12V Vcc VoD VSHDN VREFIN 5V VosL 1 8V STDBY SKIP AGND TA 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS REFERENCE BUFFER VTTR VTTR Output Accuracy Adj EFIN to VTTR VTTR Output Accuracy Preset 91 2 to VTTR VTTR Maximum Recommended Current FAULT DETECTION SMPS SMPS OVP and PGOOD1 Upper Trip Threshold SMPS OVP and PGOOD1 Upper Trip Threshold FB forced 25mV above trip threshold Fault Propagation Delay SMPS Output Undervoltage Fault Propagation Delay SMPS PGOOD1 Lower Trip Threshold PGOOD1 Lower Trip Threshold FB forced 50mV below PGOOD 1 trip Propagation Delay threshold PGOOD Output Low Voltage ISINK 3mA FB 1V PGOOD1 high impedance PGOOD1 forced to 5V Ta 25 C Source sink Measured at FB hysteresis 25mV tPGOOD1
25. O VCC DL Gate Driver On Resistance RDL Dead Time tDEAD INPUTS AND OUTPUTS SHDN STDBY SKIP OVP rising edge hysteresis 300mV 600mV min max Note 1 Limits are 100 production tested at Ta 25 C Maximum and minimum limits over temperature are guaranteed by design and characterization Note 2 On time and off time specifications are measured from 50 point at the DH pin with LX GND Vest 5V and a 250pF capacitor connected from DH to LX Actual in circuit times might differ due to MOSFET switching speeds 7 OOOZELXVIN 17000 Complete 2 and DDR3 Memory Power Management Solution SMPS 1 8V EFFICIENCY vs LOAD CURRENT Typical Operating Characteristics MAX17000 Circuit of Figure 1 Vin 12V Vpp Vcc 5V SKIP GND TA 25 C unless otherwise noted SMPS 1 8V EFFICIENCY vs LOAD CURRENT SMPS 1 8V EFFICIENCY vs LOAD CURRENT
26. V div VDDQ 2V div PGOOD 2V div VIT 1V div 10 MAXIM Complete DDR2 and DDR3 Memory Power Management Solution Typical Operating Characteristics continued MAX17000 Circuit of Figure 1 Vin 12V Vpp Vcc 5V SKIP GND TA 25 C unless otherwise noted VTT LOAD TRANSIENT RESPONSE SOURCE VTT LOAD TRANSIENT RESPONSE lyrr BETWEEN 10mA AND 1 5A SINK MAX17000 toc21 17000 toc22 VIT ac VDDQ 18V 20us div 20us div 1A div lyrr 1A div VIT 20mV div VIT 20mV div VTT LOAD TRANSIENT RESPONSE VTTR OUTPUT VOLTAGE SOURCE SINK vs LOAD CURRENT MAX17000 toc23 0 79 5 0 78 8 077 3 076 lt 075 0 74 zZ 5 073 lt gt 0 72 071 VDDQ 1 8V 0 70 20us div 6 4 2 0 2 4 6 lr 1A div LOAD CURRENT A VIT 20mV div 11 000Z LXVIW 17000 Complete 2 and DDR3 Memory Power Management Solution Pin Description FUNCTION OVP Mode Control This input selectively enables disables the SMPS OV protection feature and output discharge mode When enabled the SMPS OV protection feature is enabled Connect OVP to the following voltage levels for the desired function High gt 2 4V Enable SMPS OV protection and SMPS and VTT discharge FETs Low GND Disable SMPS OV protection and SMPS and VTT discharge FETs PGOOD1 Open Drain Power Good Output PGOOD is low when the SMPS
27. VLO circuitry inhibits switching until Vcc reaches 4 1V typ When Vcc rises above 4 1V the controller activates the PWM controller and initializes soft start When Vcc drops below the UVLO threshold falling edge the controller stops DL is pulled low and the internal 160 discharge MOSFETs on the CSL and VTT outputs are enabled if OVP is enabled Soft Start and Soft Shutdown Soft start and soft shutdown for the MAX17000 PWM block is voltage based Soft start begins when SHDN is driven high During soft start the PWM output is ramped up from OV to the final set voltage in 1 4ms This reduces inrush current and provides a predictable ramp up time for power sequencing The MAX17000 always uses skip mode during startup regardless of the SKIP and STDBY setting The SKIP and STDBY con trols take effect after soft start is done The MAX17000 VTT LDO regulator uses a current limited soft start function When the VTT block is enabled the internal source and sink current limits are linearly increased from zero to the full scale limit in 160 Full scale current limit is available when the VTT output is in regulation or after 160us whichever is earlier The reference buffer does not have any soft start control AVLAZCLA Complete DDR2 and DDR3 Memory Power Management Solution UTPUT R OUTPUT CURRENT LIMIT PGOOD1 PGOOD2 271
28. age fault After soft shutdown has com pleted the MAX17000 forces DL and DH low and enables the internal 160 discharge MOSFETs on CSL and VTT Cycle Vcc below 1V or toggle SHDN to clear the undervoltage fault latch and restart the controller VTT Overvoltage and Undervoltage Protection If the output voltage of the VTT regulator exceeds 10 of its regulation voltage for more than 5ms typ the controller sets its fault latch pulls PGHOOD1 and PGOOD2 low and begins soft shutdown pulsing DL DH remains off during the soft shutdown sequence initi ated by an undervoltage fault After soft shutdown has AVLAZCLA completed the MAX17000 forces DL and DH low and enables the internal 160 discharge MOSFETs on CSL and VTT Cycle Vcc below 1V or toggle SHDN to clear the undervoltage fault latch and restart the controller Thermal Fault Protection The MAX17000 features a thermal fault protection cir cuit When the junction temperature rises above 160 C a thermal sensor activates the fault latch pulls PGOOD1 and PGOOD low and shuts down using the shutdown sequence Toggle SHDN or cycle Vcc power below Vcc POR to reactivate the controller after the junction temperature cools by 159 Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point ripple current ratio The pri mary design trade off lies in choosing a good switching
29. aking higher frequencies more practical e Inductor Operating Point This choice provides trade offs between size vs efficiency and transient response vs output noise Low inductor values pro vide better transient response and smaller physical size but also result in lower efficiency and higher output noise due to increased ripple current The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc tion where the inductor current just touches zero with every cycle at maximum load Inductor values lower than this grant no further size reduction bene fit The optimum operating point is usually found between 20 and 50 ripple current Inductor Selection The switching frequency and operating point 96 ripple current or LIR determine the inductor value as follows 2 Vin Vour few lt ILOAD MAX X LIR VIN Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions Ferrite cores are often the best choice although powdered if 2122 INPUT Vin Y Cin MAXI MAX17000 DL PGND1 CSH iron is inexpensive and can work well at 200kHz The core must be large enough not to saturate at the peak inductor current IPEAK LIR LOAD MAX 1 Setting the Valley Current Limit The minimum current limit threshold must be high enough to support the maximum load current when the current limit is at the minimum
30. ced low TR is active and regulates to Vcsi 2 or VREFIN Ultra skip or skip mode is exited as the MAX17000 ramps the output down to zero TR tracks 51 2 or VREFIN during shutdown After the SMPS output reaches 25mV DL goes low Ultra skip or skip mode is exited as the MAX17000 ramps the output down to zero TR tracks 1 2 or VREFIN during shutdown After the SMPS output reaches 25mV DL goes low VTT is not enabled throughout soft shutdown low Internal16Q discharge MOSFETs on CSL and VTT enabled if OVP is high but disabled if P is low 15 000Z LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution 45V gt R3 R2 100kQ 100kQ PGOOD1 PGOOD2 PGND1 CSL MAXI 17000 SLP_S3 ON OFF AGND NZ PGND Figure 1 MAX17000 Standard Application Circuit Detailed Description The MAX17000 complete DDR solution comprises a step down controller a source sink LDO regulator and a reference buffer Maxim s proprietary Quick PWM pulse width modulator in the MAX17000 is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages The Quick PWM architecture circumvents the poor load tran sient timing problems of fixed frequency current mode PWMs while also avoiding the problems caused by widely varying
31. ciency The VDDQ output voltage can be set to a preset 1 8V or 1 5V or be adjusted from 1 0V to 2 5V by an external resistor divider This output has 1 accuracy over line and load operating range The MAX17000 includes a 2 source sink LDO regu lator for the memory termination VTT rail This VTT regu lator has a 5mV deadband that either sources or sinks ideal for the fast changing load burst present in memory termination applications This feature also reduces output capacitance requirements The VTTR reference buffer sources and sinks 3mA providing the reference voltage needed by the memory controller and devices on the memory bus The MAX17000 is available in a 24 pin 4mm x 4mm Thin QFN package Applications Notebook Computers DDR DDR2 and DDR3 Memory Supplies SSTL Memory Supplies Quick PWM is a trademark of Maxim Integrated Products Inc MAKIM Features SMPS Regulator VDDQ Quick PWM with 100ns Load Step Response Output Voltages Preset 1 8V 1 5V or Adjustable 1 0V to 2 5V 1 Vout Accuracy Over Line and Load 26V Maximum Input Voltage Rating Accurate Valley Current Limit Protection 200kHz to 600kHz Switching Frequency Source Sink Linear Regulator VTT 2A Peak Source Sink Low Output Capacitance Requirement Output Voltages Preset VDDQ 2 or REFIN Adjustable from 0 5V to 1 5V Low Quiescent Current Standby State Soft Start Soft Shutdown SMPS Power Good Window Comparator VTT Power Good Window C
32. d high side and larger low side power MOSFETs This is consistent with the low duty factor seen in note book applications where a large VIN Vour differential exists The high side gate driver DH sources and sinks 1 2A and the low side gate driver DL sources 1 0A and sinks 2 4A This ensures robust gate drive for high cur rent applications The DH floating high side MOSFET dri ver is powered by an internal boost switch charge pump at BST while the DL synchronous rectifier driver is pow ered directly by the 5V bias supply Vpp PWM Output Capacitor Selection The output filter capacitor must have low enough effec tive series resistance ESR to meet output ripple and load transient requirements yet have high enough ESR to satisfy stability requirements In core and chipset converters and other applications where the output is subject to large load transients the output capacitor s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient Ignoring the sag due to finite capacitance VsTEP Resr Recp lt LOAD MAX In low power applications the output capacitor s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage The output ripple voltage of a step down controller equals the total inductor ripple current multiplied by the output tor s ESR 25 000Z LXVIW 17000 Complete
33. e cycle of ringing after the initial step response undervoltage overshoot Input Capacitor Selection The input capacitor must meet the ripple current requirement IRMS imposed by the switching currents The IRMS requirements can be determined by the fol lowing equation IRMS Vn Vour The worst case RMS current requirement occurs when operating with Vin 2Vour At this point the above equation simplifies to IRMS 0 5 X MAXIM Complete DDR2 and DDR3 Memory Power Management Solution For most applications nontantalum chemistries ceramic aluminum or OS CON are preferred due to their resis tance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input If the Quick PWM controller is operated as the second stage of a two stage power conversion system tanta lum input capacitors are acceptable either configu ration choose an input capacitor that exhibits less than 10 C temperature rise at the RMS input current for optimal circuit longevity MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load current capability when using high voltage gt 20V AC adapters Low current applications usually require less attention The high side MOSFET NH must be able to dissipat the resistive losses plus the switching losses at bot VIN MIN and ViN MAX Calculate both these sums Ideal
34. ecomes high impedance as long as the SMPS output voltage is between 115 typ and 85 typ of the regulation voltage When the SMPS output voltage exceeds the 115 85 regulation win dow the MAX17000 pulls PGOOD low Any fault con dition on the SMPS output forces PGOOD1 and PGOOD2 low and latches off until the fault latch is cleared by toggling SHDN or cycling Vcc power below 1V Detection of an OVP event immediately pulls PGOOD low regardless of the OVP state OVP enabled or disabled 20 PGOOD2 is the open drain output for a window com parator that continuously monitors the VTT output PGOOD2 is actively held low in standby shutdown and during soft start PGOOD2 becomes high imped ance as long as the VTT output voltage is within 10 of the regulation voltage When the VTT output exceeds the 10 threshold the MAX17000 pulls PGOOD low If PGOOD2 remains low for 5ms typ the MAX17000 latches off with the soft shutdown sequence For logic level output voltages connect an external 100kQ pullup resistor from PGOOD1 and PGOOD to Vpp POR UVLO Power on reset POR occurs when rises above approximately 2V resetting the fault latch and soft start circuit and preparing the controller for power up When OVP protection is enabled a rising edge on POR turns on the 160 discharge MOSFET on CSL and VTT When OVP is disabled the internal 160 discharge MOSFETs on CSL and VTT also remain off Vcc undervoltage lockout U
35. ed DL immediately pulled low VTTR tracks the SMPS output during soft shutdown CSL and VTT SMPS latched fault are high impedance at the end of soft shutdown 16 discharge condition MOSFETs disabled SMPS OVP Controller remains active normal operation Only PGOOD1 pulled disabled Note An OVP detection still pulls PGOOD1 low low fault not latched PGOOD2 immediately pulled low VTT latched fault VTT lt 90 or Soft shutdown initiated if fault persists for more than 5ms typ DH condition if fault VTT gt 110 not used in soft shutdown DL low after soft shutdown completed persists for more VTTR tracks the SMPS output soft shutdown than 5ms typ SMPS UVP OVP Disabled Discharge Disabled OVP Low DL and DH immediately pulled low Vcc UVLO PGOOD1 and PGOOD2 immediately forced low VTT and VTTR falling edge blocks immediately disabled high impedance no 16 discharge on outputs Soft shutdown initiated 160 discharge Shutdown DL high after soft shutdown completed MOSFETs on CSL SHDN low VITR tracks the SMPS output during soft shutdown Internal 160 and VTT enabled in discharge MOSFETs on CSL and VTT enabled after soft shutdown shutdown Soft shutdown initiated DH not used in soft shutdown DL low after soft shutdown completed SMPS latched fault VTTR tracks the SMPS output during soft shutdown Internal 16Q condition OVP Enabled discharge MOSFETs on CSL and VTT enabled
36. ense Configurations Sheet 2 of 2 For the best current sense accuracy and overcurrent protection use a 1 tolerance current sense resistor between the inductor and output as shown in Figure 7a This configuration constantly monitors the inductor cur rent allowing accurate current limit protection However the parasitic inductance of the current sense resistor cause current limit inaccuracies especially when using low value inductors and current sense resistors This parasitic inductance LESL can be can celled by adding an RC circuit across the sense resis tor with an equivalent time constant LESL RSENSE CEQ x REQ Alternatively low cost applications that do not require highly accurate current limit protection could reduce the overall power dissipation by connecting a series RC circuit across the inductor Figure 7b with an equiva lent time constant R2 CS DOR R Cm LHP R2 where Rcs is the required current sense resistance and RpcR is the inductor s series DC resistance Use the worst case inductance and Rpcn values provided by the inductor manufacturer adding some margin for the inductance drop over temperature and load AVLAZCLA FOR THERMAL COMPENSATION R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN FILM RESISTOR MOSFET Gate Drivers DH DL The DH and DL drivers are optimized for driving moder ate size
37. frequency STDBY AGND overrides the SKIP pin setting forcing the MAX17000 into standby The MAX17000 switches to forced PWM mode during shutdown regardless of the state of SKIP and STDBY levels Standby Mode STDBY It should be noted that standby mode in the MAX17000 corresponds to computer system standby operation and is not referring to the MAX17000 shutdown status When standby mode is enabled STDBY AGND the MAX17000 switches over from the fast internal PWM block to a low quiescent current mode using a low power valley comparator to initiate an on time pulse The zero crossing comparator is enabled so that the MAX17000 only operates in discontinuous mode reducing the maximum available output current by 1 6 The system is NOT expected to have any fast load tran sients in such a state While in standby VTT is disabled high impedance but VTTR remains active SKIP is ignored when standby mode is enabled When standby mode is disabled STDBY Vcc the MAX17000 reenables its fast internal PWM block Once the internal SMPS block is ready the VTT block is enabled and the VTT output capacitor is charged The VTT soft start current limit increases linearly from zero to its maximum current limit in 160us typ keeping the input VTTI inrush low See Figure 4 PS OUTPUT TR OUTPUT T OUTPUT T CURRENT LIMIT PGOOD1 PGOOD2 Figure 4 MAX17000 Standby Mode Timing AVLAZCLA
38. frequency and inductor operating point and the follow ing four factors dictate the rest of the design Input Voltage Range The maximum value VIN MAX must accommodate the worst case input supply voltage allowed by the notebook s AC adapter voltage The minimum value VIN MIN must account for the lowest input voltage after drops due to connectors fuses and battery selec tor switches If there is a choice at all lower input voltages result in better efficiency e Maximum Load Current There are two values to consider The peak load current OAD MAX deter mines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection inductor saturation rating and the design of the current limit circuit The continu ous load current ILOAD determines the thermal 23 000Z LXVIW 17000 Complete DDR2 and DDR3 Memory Power Management Solution stresses and thus drives the selection of input capacitors MOSFETs and other critical heat con tributing components Most notebook loads gener ally exhibit ILOAD MAX X 80 Switching Frequency This choice determines the basic trade off between size and efficiency The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and V N2 The opti mum frequency is also a moving target due to rapid improvements in MOSFET technology that are m
39. g those of electrolytic and tantalum types can be connected in parallel to the ceramic capacitor if desired to further suppress noise or volt age ripple at the output VTTR Output Capacitor Selection The VTTR buffer is a scaled down version of the regulator with much smaller output transconductance Its compensation capacitor can therefore be smaller and its ESR larger than what is required for its larger counterpart For typical applications requiring load cur rent up to 4mA a ceramic capacitor with a minimum value of 0 33uF is recommended Rgsn lt 0 30 Connect this capacitor between VTTR and the analog ground plane Power Dissipation Power loss in the MAX17000 is the sum of the losses of the PWM block the VTT LDO block and the VTTR ref erence buffer PD PWM x 5V 40mA x 0 2W PD VTT 2A x 0 9V 1 8W PD VTTR 3mA x 0 9V 2 7mW AVLAZCLA PD Total 2W The 2W total power dissipation is within the 24 pin multilayer board power dissipation spec of 2 22W The typical application does not source or sink continuous high currents VTT current is typically 100mA to 200mA in the steady state VTTR is down in the uA range though the Intel spec requires 3mA for DDR1 and 1mA for DDR2 True worst case power dissi pation occurs on an output short circuit condition with worst case current limit The MAX17000 does not employ any foldback current limiting and relies on the internal ther
40. ion limits at Vas 5V for the internal MOSFETs Free Running Constant On Time PWM Controller with Input Feed Forward The Quick PWM control architecture is a pseudo fixed frequency constant on time current mode regulator with voltage feed forward This architecture utilizes the output filter capacitor s ESR to act as a current sense resistor so the output ripple voltage can provide the PWM ramp signal In addition to the general Quick PWM the MAX17000 also senses the inductor current through DCR method or with a sensing resistor Therefore it is less dependent on the output capacitor ESR for stability The control algorithm is simple the high side switch on time is determined solely by a one shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage Another one shot sets a minimum off time 250ns typ The on time one shot is triggered if the error compara tor is low the low side switch current is below the valley current limit threshold and the minimum off time one shot has timed out On Time One Shot The heart of the PWM core is the one shot that sets the high side switch on time This fast low jitter adjustable one shot includes circuitry that varies the on time in response to battery and output voltages The high side switch on time is inversely proportional to the battery voltage as measured by the VIN input and proportional to the output voltage 18 An exte
41. itor e Route high speed switching nodes BST LX DH and DL away from sensitive analog areas REFIN FB CSH and CSL 30 1 Layout Procedure Place the power components first with ground ter minals adjacent low side MOSFET source CIN and anode of the low side Schottky If possi ble make all these connections on the top layer with wide copper filled areas Mount the controller IC adjacent to the low side MOSFET preferably on the backside opposite the MOSFETs to keep LX GND DH and the DL gate drive lines short and wide The DL and DH gate traces must be short and wide 50 mils to 100 mils wide if the MOSFET is from the controller IC to keep the driver impedance low and for proper adaptive dead time sensing Group the gate drive components BST diode and capacitor bypass capacitor together near the controller IC Make the DC DC controller ground connections as shown in Figures 1 and 9 This diagram can be viewed as having two separate ground planes power ground where all the high power compo nents go and an analog ground plane for sensitive analog components The analog ground plane and power ground plane must meet only at a single point directly at the IC Connect the output power planes directly to the out put filter capacitor positive and negative terminals with multiple vias Place the entire DC to DC con verter circuit as close as is practical to the load MAKLM Com
42. ly the losses at VIN MIN Should be roughly equal to losses at VIN MAX with lower losses in between If the losses at VIN MIN are significantly higher than the losses at VIN MAX consider increasing the size of NH reducing RDS ON but with higher CGATE Conversely if the loss es at VIN MAX are significantly higher than the losses at VIN MIN Consider reducing the size of NH increasing RDS ON to lower CGATE If Vin does not vary over a wide range the minimum power dissipation occurs where the resistive losses equal the switching losses Choose a low side MOSFET that has the lowest possi ble on resistance RDS ON Comes in a moderate sized package one or two 8 SOs or D PAK and is reasonably priced Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate to drain capacitor caused by the high side MOSFET turning on otherwise cross conduction problems can occur see the MOSFET Gate Drivers DH DL section MOSFET Power Dissipation Worst case conduction losses occur at the duty factor extremes For the high side MOSFET the worst case power dissipation due to resistance occurs at the minimum input voltage PD Resistive je X Hps oN Generally a small high side MOSFET is desired to reduce switching losses at high input voltages However the RDS ON required to
43. mal shutdown for protection Both the VTT and VTTR output stages are powered from the same VTTI input Their output voltages are referenced to the same REFIN input The value of the VTTI bypass capac itor is chosen to limit the amount of ripple noise at VTTI or the amount of voltage dip during a load transient Typically VTTI is connected to the output of the buck regulator which already has a large bulk capacitor Boost Capacitors The boost capacitors CBsT must be selected large enough to handle the gate charging requirements of the high side MOSFETs Typically 0 1uF ceramic capacitors work well for low power applications driving medium sized MOSFETs However high current appli cations driving large high side MOSFETs require boost capacitors larger than 0 1uF For these applications select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high side MOSFETs gates _ QGATE 200 where QGATE is the total gate charge specified in the high side MOSFET s data sheet For example assume the FDS6612A n channel MOSFET is used on the high side According to the manufacturer s data sheet a sin gle FDS6612A has a maximum gate charge of 13nC Vas 5V Using the above equation the required boost capacitance would be 13nC BST 0 065uF Selecting the closest standard value this example requires a O 1uF ceramic capacitor 29 000Z LXVIW
44. omparator Selectable Overvoltage Protection Undervoltage Thermal Protections 3mA Reference Buffer VTTR 9 9 9 o Ordering Information PART TEMP RANGE MAX17000ETG 40 C to 85 C Denotes a lead free package PIN PACKAGE 24 Thin QFN Pin Configuration TOP VIEW MAXIM MAX17000ETG THIN QFN 4mm x 4mm Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 000Z LXVIW 17000 Complete 2 and DDR3 Memory Power Management Solution ABSOLUTE MAXIMUM RATINGS TON to 0 3V to 28V VTTI to PGND2 0 3V to 6V VDD to PGND1 ss ee 0 3V to 46V VTT to 2 0 3V to Vrri 0 3V Vcc to 0 3V to 0 3V VTTS to 0 3V to Vcc 0 3V OVP to AGND iicet tete 0 3V to 46V VTTR to 0 3V to 0 3V SHDN STDBY SKIP to 0 3V to 6V PGND1 PGND2 to 0 3V to 0 3V REFIN FB PGOOD1 Continuous Power Dissipation Ta 70 C PGOOD2 to AGND 0 3V to Vcc 0 3V 24 Pin 4mm x 4mm Thin QFN CSH CSL to AGND 0 3V to Vcc 0 3V derated 27 8mW C above 70 2222mW DL to PGND1 0 3V to Vpp 4 Opera
45. output voltage is more than 15 typ beyond the normal regulation point during soft start and in shutdown After the soft start circuit has terminated PGOOD1 becomes high impedance if the SMPS output is in regulation PGOOD2 Open Drain Power Good Output 2 is low when the VTT output voltage is more than 10 typ beyond the normal regulation point in shutdown and in standby After the SMPS soft start circuit has terminated PGOOD2 becomes high impedance if the VTT output is in regulation Standby Control Input When SHDN is high and STDBY is low the MAX17000 enters a low quiescent current mode putting the SMPS in ultra skip operation and turning off the VTT output high Z This mode helps save converter power loss in computer standby operation When STDBY is high normal SMPS operation resumes and the VTT output is enabled Sense Pin for Termination Supply Output Normally connected to the VTT pin to allow accurate regulation to VcsL 2 or the REFIN voltage Termination Reference Buffer Output VTTR tracks Vcsi 2 when REFIN is connected to Voc VITR tracks VREFIN when a voltage between 0 5V to 1 5V is set at REFIN Decouple VTTR to AGND with a ceramic capacitor Power Ground for VTT Connect PGND2 externally to the underside of the exposed pad Termination Power Supply Output Connect VTT to VTTS to regulate the VTT voltage to the VTTS regulation setting Termination Power Supply Input
46. plete DDR2 and DDR3 Memory Power Management Solution KELVIN SENSE VIAS UNDER THE INDUCTOR POWER STAGE LAYOUT TOP SIDE OF PCB SEE EVALUATION KIT OUTPUT POWER GROUND KELVIN SENSE VIAS TO INDUCTOR PAD INDUCTOR DCR SENSING CONNECT AGND AND PGND1 TO THE CONTROLLER AT THE CONNECT THE EXPOSED PAD EXPOSED PAD TO ANALOG GROUND Vpp BYPASS CAPACITOR BYPASS CAPACITOR a FE VIA TO POWER GROUND BYPASS CAPACITOR VIT BYPASS CAPACITOR X RAY VIEW IC MOUNTED ON BOTTOM SIDE OF PCB IC LAYOUT Figure 9 PCB Layout Example Chip Information Package Information TRANSISTOR COUNT 7856 For the latest package outline information go to k PROCESS BiCMOS www maxim ic com packages PACKAGE TYPE PACKAGE CODE DOCUMENT NO Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 31 2008 Maxim Integrated Products MAXIM is registered trademark of Maxim Integrated Products Inc 000Z LXVI
47. pplications in which the termination supply must track the supply voltage VTT Output Capacitor Selection A minimum value of 9uF is needed to stabilize a 300mA VTT output This value of capacitance limits the regula tor s unity gain bandwidth frequency to approximately 1 2MHz typ to allow adequate phase margin for stabil ity To keep the capacitor acting as a capacitor within the regulator s bandwidth it is important that ceramic capacitors with low ESR and ESL be used CSH MAX17000 Figure 8 Setting VOUT with a Resistive Voltage Divider Dual Mode is a trademark of Maxim Integrated Products Inc 28 MAKLM Complete DDR2 DDR3 Memory Power Management Solution Since the gain bandwidth is also determined by the transconductance of the output FETs which increases with load current the output capacitor might need to be greater than 20yF if the load current exceeds 1 5A but can be smaller than 20uF if the maximum load current is less than 1 5A As a guideline choose the minimum capacitance and maximum ESR for the output capaci tor using the following LOAD 1 5A Cour MIN 20uF x Cour needs to be increased by a factor of 2 for low dropout operation 5mQ x ESR _ 15 value is measured at the unity gain bandwidth frequency given by approximately ae 36 1 5A Once these conditions for stability are met additional capacitors includin
48. put overshoot VSOAR typically determines the minimum output capacitance requirement Their relatively low capacitance value can allow significant output over shoot when stepping from full load to no load condi tions unless a small inductor value and high switching frequency are used to minimize the energy transferred from inductor to capacitor during load step recovery Unstable operation manifests itself in two related but distinctly different ways double pulsing and feedback loop instability Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal This fools the error comparator into triggering a new cycle immediately after the minimum off time period has expired Double pulsing is more annoying than harmful resulting in nothing worse than increased output ripple However it can indicate the possible presence of loop instability due to insufficient ESR Loop instability can result in oscillations at the output after line or load steps Such perturbations are usually damped but can cause the output voltage to rise above or fall below the tolerance limits The easiest method for checking stability is to apply a very fast zero to max load transient and carefully observe the output voltage ripple envelope for over shoot and ringing It can help to simultaneously monitor the inductor current with an AC current probe Do not allow more than on
49. put ripple so the actual DC output volt age is higher than the trip level by 50 of the output ripple voltage In discontinuous conduction SKIP AGND and lour lt ILOAD SKIP the output voltage has a DC regulation level higher than the error comparator threshold by approximately 1 596 due to slope compen sation However the internal integrator corrects for most of it resulting in very little load regulation STDBY AGND overrides the SKIP pin setting forcing the MAX17000 into standby MAKLM Complete DDR2 DDR3 Memory Power Management Solution The MAX17000 always uses skip mode during startup regardless of the SKIP and STDBY setting The SKIP and STDBY controls take effect after soft start is done See Figure 3 Forced PWM Mode SKIP Vcc The low noise forced PWM mode SKIP Vcc disables the zero crossing comparator which controls the low side switch on time This forces the low side gate drive waveform to constantly be the complement of the high side gate drive waveform so the inductor current reverses at light loads while DH maintains a duty factor of VouT VIN The benefit of forced PWM mode is to keep a fairly constant switching frequency However forced PWM operation comes at a cost the no load 5V bias Al Vw Vout L ON TIME Figure 3 Pulse Skipping Discontinuous Crossover Point DBY PS_RUNOK current remains between 2mA to 20mA depending on the switching
50. rnal resistor between the input power source and TON pin sets the switching frequency per phase according to the following equation t X RroN 6 5 x Vcs 0 075V ON MN f Cron x Rron 6 5kQ where CTON 16 26pF and 0 075V is an approxima tion to accommodate for the expected drop across the low side MOSFET switch This algorithm results in a nearly constant switching frequency despite the lack of a fixed frequency clock generator For loads above the critical conduction point where the dead time effect is no longer a factor the actual switch ing frequency is Vout Vois ton X Vin where Vpis is the sum of the parasitic voltage drops in the inductor discharge path including synchronous rectifier inductor and PCB resistances VCHG is the sum of the parasitic voltage drops in the charging path including the high side switch inductor and PCB resis tances and ton is the on time calculated by the MAX17000 Automatic Pulse Skipping Mode SKIP AGND In skip mode SKIP AGND an inherent automatic switchover to PFM takes place at light loads This switchover is affected by a comparator that truncates the low side switch on time at the inductor current s zero Crossing DC output accuracy specifications refer to the thresh old of the error comparator When the inductor is in continuous conduction the MAX17000 regulates the valley of the out
51. stay within package power dissipation often limits how small the MOSFET AVLAZCLA can be Again the optimum occurs when the switching losses equal the conduction RDS ON losses High side switching losses do not usually become an issue until the input is greater than approximately 15V Calculating the power dissipation in high side MOSFET due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn on and turn off times These factors include the internal gate resistance gate charge threshold voltage source inductance and PCB layout characteristics The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation preferably including verification using a thermocouple mounted on NH Qa sw PD NH Switching Xll X fsw GATE 2 Coss x Vin x few 2 where Coss is the NH MOSFET s output capacitance Qa sw is the charge needed to turn on the NH MOS FET and IGATE is the peak gate drive source sink cur rent 2 2A typ Switching losses in the high side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the C x VIN x fsw switching loss equation If the high side MOSFET chosen for adequate lt at low battery voltages becomes extraordinarily hot when biased from VIN MAX consider choosing another MOSFET with
52. switching frequencies in conventional con stant on time and constant off time PWM schemes Figure 1 is the MAX17000 standard application circuit and Figure 2 is the MAX17000 functional diagram 16 VIN 7V TO 20V 4 it Cin PGND L1 VDDQ RSENSE 41 8V OR 1 5V Cour PGND FB OPTIONS 1 CONNECT FB TO 5V FOR FIXED 1 8V 2 CONNECT FB TO GND FOR FIXED 1 5V 3 USE FB RESISTOR DIVIDER FOR ADJUSTABLE OUTPUT VOLTAGES 1V TO 2 5 VIT VDDQ 2 VDDQ 2 The MAX17000 includes a 2A source sink LDO regu lator for the memory termination rail The source sink regulator features a dead band that either sources or sinks ideal for the fast changing short period loads presenting in memory termination applications This feature also reduces the VTT output capacitance requirement down to 1uF though load transient response can still require higher capacitance values between 10uF and 20uF The reference buffer sources and sinks 3mA generating a reference rail for use in the memory controller and memory devices MAKLM Complete DDR2 and DDR3 Memory Power Management Solution ON TIME COMPUTE lOFF MIN TRIG 1 SHOT STDBY EA PS FAULT ECTION POWER GOO PGOOD1 VIT FAULT PGO0D2 POWER GOOD
53. ting Temperature Range BST to PGND1 Junction Temperatur eiiiai nets BST Storage Temperature Range DH Lead Temperature soldering 105 300 51 Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device These stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS VIN 12V Vpp VSHDN VREFIN 5V Vcs 1 8V STDBY SKIP AGND TA 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS PWM CONTROLLER VIN Vcc VDD Input Voltage Range FB AGND Output Voltage Accuracy VcsL FB Adj Output Voltage Range VCSL Load Regulation Error VcsH Vcsr OmV to 18mV SKIP Vcc Line Regulation Error 4 5V to 5 5V VIN 4 5V to 26V Soft Start Ramp Time tssrART Rising edge of SHDN Soft Stop Ramp Time tsstop Falling edge of SHDN Soft Stop Threshold RTON 96 75kQ 6 2 167ns nominal VIN 12V RTON 200kQ 300kHz VcsL 1 2V 333ns nominal RTON 303 25kQ 200kHz 500ns nominal On Time Accuracy Note 2
54. tolerance value The val ley of the inductor current occurs at lLOAD MAX minus half the ripple current therefore LIR gt x 17 75 where ILIMIT LOW equals the minimum current limit threshold voltage divided by the output sense element inductor DCR or sense resistor The valley current limit is fixed at 17mV min across the CSH to CSL differential input Special attention must be made to the tolerance and thermal variation of the on resistance in the case of DCR sensing Use the worst case maximum value for RDCR from the inductor data sheet and add some margin for the rise in RpcR with temperature A good general rule is to allow 0 596 additional resistance for each C of temperature rise which must be included in the design margin unless the design includes an NTC thermistor in the DCR network to thermally compensate the current limit threshold The current sense method Figure 7 and magnitude determine the achievable current limit accuracy and power loss The sense resistor can be determined by RSENSE VLIMIT ILIMIT SENSE RESISTOR RSENSE CSL A OUTPUT SERIES RESISTOR SENSING Figure 7a Current Sense Configurations Sheet 1 of 2 24 MAKLM Complete DDR2 and DDR3 Memory Power Management Solution ME INPUT Vin L MAXIM MAX17000 DL PGND1 CSH INDUCTOR 1 1 c la CSL B LOSSLESS INDUCTOR SENSING Figure 7b Current S
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