Sipex SP7650 handbook
Contents
1. gt P O L D2 Z DV UUU U U UO U SRN e le jer 26 Pin DFN 0 000 0 050 Bottom View 2 000 2 100 1 830 0 500 BSC 3 950 4 000 4 050 Note Dimensions in mm Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 12 ORDERING INFORMATION Part Number Temperature Package SP7650ER TR iccca aaa 40 C to 85 C E EENAA 26 Pin 7 X 4 DFN SP7650ER L TR i 40 C to 85 C Lead Free 26 Pin 7 X 4 DFN ITR Tape and Reel Pack quantity is 3 000 DFN CLICK HERE TO ORDER SAMPLES 4e Cinav VIA ANALOGEXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas CA 95035 TEL 408 934 7500 FAX 408 935 7600 Sipex Corporation reserves the right to make changes to any products described herein Sipex does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 132. cuit detection In the event that either a thermal short circuit or UVLO fault is detected the SP7650 is forced into an idle state where the output drivers are held off for a finite period before a restart is attempted Soft Start Soft Start is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source cur rent In a modern step down converter ramping up the positive terminal of the error amplifier controls soft start As a result excess source current can be defined as the current required to charge the output capacitor Ivin Cour DVour DT sorr START The SP7650 provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND The selection of this capacitor is based on the 10uA pull up current present at the SS pin and the 0 8V reference voltage Therefore the excess source can be redefined as IVin Cour DVour 10pA Css 0 8V Under Voltage Lock Out UVLO The SP7650 contains two separate UVLO com parators to monitor the bias Vcc and conver sion Vin voltages independently The Vcc UVLO threshold is internally set to 4 25V whereas the Vin UVLO threshold is program mable through the UVIN pin When the UVIN pin is greater than 2 5V the SP7650 is permitted to start up pending the removal of all other faults Both the Vcc and Viy UVLO compara tors have been designed with hysteresis to pre
3. vent noise from resetting a fault Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator THEORY OF OPERATION Thermal and Short Circuit Protection Because the SP7650 is designed to drive large output current there is a chance that the power converter will become too hot Therefore an internal thermal shutdown 145 C has been included to prevent the IC from malfunctioning at extreme temperatures A short circuit detection comparator has also been included in the SP7650 to protect against an accidental short at the output of the power converter This comparator constantly monitors the positive and negative terminals of the error amplifier and if the Veg pin falls more than 250mV typical below the positive reference a short circuit fault is set Because the SS pin overrides the internal 0 8V reference during soft start the SP7650 is capable of detecting short circuit faults throughout the duration of soft start as well as in regular operation Handling of Faults Upon the detection of power UVLO thermal or short circuit faults the SP7650 is forced into an idle state where the SS and COMP pins are pulled low and both switches are held off In the event of UVLO fault the SP7650 remains in this idle state until the UVLO fault is removed Upon the detection of a thermal or short circuit fault an internal 200ms timer is activated Inthe event of a short circuit fault a re start is at tempted imme
4. 27 N L Cour When the output capacitors are of a Ceramic Type the SP7650 Evaluation Board requires a Type III compensation circuit to give a phase boost of 180 in orderto counteract the effects of an under damped resonance of the output filter at the double pole frequency Type Ill Voltage Loop Compensation Gayp S Gain Block V r SRz2Cz2 1 SR1Cz3 1 PWM Stage Output Stage Grwm Gain Gour S Gain Block Block Vin SResrCoutt 1 T_ gt Volts _ SR1Cz2 SRz3Cz3 1 SRz2Cp1 1 Roc Output Inductor DC Resistance Condition Cz2 gt gt Cp1 amp R1 gt gt Rz3 Output Load Resistance gt gt Resp amp Roc VFBK Volts VRAMP_PP Notes Resp Output Capacitor Equivalent Series Resistance Vrame_pp SP6132 Internal RAMP Amplitude Peak to Peak Voltage Voltage Feedback Gain Block R4 Ro gt gt Vout SA2LCoyr S Resa Roo Court 1 Volts VREF Vout or SP7650 Voltage Mode Control Loop with Loop Dynamic Definitions Resp Output Capacitor Equivalent Series Resistance Rpc Output Inductor DC Resistance Rramp_pp SP7650 internal RAMP Amplitude Peak to Peak Voltage Conditions Cz2 gt gt Cpl and R1 gt gt Rz3 Output Load Resistance gt gt Resr and Rpc Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation APPLICATIONS INFORMATION Error Amplifier Gain Bandwi
5. 28V BST LX 5V LX GND OV UVIN 3 0V CVcc 1uF Ccomp 0 1uF Css 50nF Typical measured at Vcc 5V The denotes the specifications which apply over the full temperature range unless otherwise specified PARAMETER MIN TYP max UNITS CONDITIONS CONTROL LOOP PWM COMPARATOR RAMP amp LOOP DELAY PATH 25 RAMP COMP Maximum Duty Ratio Maximum Controllable Duty Ratio Measured just before pulsing begins Maximum Duty Ratio oo a Valid for 20 cycles nerastro 40 ow oo we TIMERS SOFTSTART SS Discharge Current 1 ma fe Fault Present SS 0 2V PROTECTION Short Circuit amp Thermal Short Circuit Threshold Voltage oe oa oa v e oo Ver 0 8V FB Number of Allowable Clock Cycles Minimum GL Pulse After 20 Cycles o cycles Vig 0 7V Thermal Shutdown Temperature Te Veg 0 7V OUTPUT POWER STAGE sn SOS e me es iia rese fe fw lh a i Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 3 PIN DESCRIPTION rar mme fee Ground connection for the synchronous rectifier Ground Pin The control circuitry of the IC and lower power driver are 4 8 19 21 GND referenced to this pin Return separately from other ground traces to the terminal of Cout Feedback Voltage and Short Circuit Detection pin It is the inverting input of the Error Amplifier and serves as the o
6. Preliminary SP7650 Wide Input Voltage Range 3A 300kHz Power iui Buck Regulator FEATURES SP7650 DFN PACKAGE EH 2 5V to 28V Step Down Achieved Using Dual Input 7mm x 4mm E Output Voltage down to 0 8V Penp i SElLX E 3A Output Capability Penp 2 TOP VIEW BEILX E Built in Low Roson Power Switches 40 MQ typ Penola poeem Padi palLx BM Highly Integrated Design Minimal Components anpla B3 Lx EH 300 kHz Fixed Frequency Operation VEB IE BalVcc EH UVLO Detects Both Vcc and Vin comP g SI IGND E Over Temperature Protection UvINEZ Connect o GND 20 GND HH Short Circuit Protection with Auto Restart GND 5 191GND E Wide BW Amp Allows Type II or III Compensation ssty 18 BST E Programmable Soft Start Vin 10 F7INC E Fast Transient Response Vin aa Connect 16 LX E High Efficiency Greater than 95 Possible Vin 12 15 Lx BM Asynchronous Start Up into a Pre Charged Output Vin 3 14 LX E Small 7mm x 4mm DFN Package Now Available in Lead Free Packaging DESCRIPTION The SP7650 is a synchronous step down switching regulator optimized for high efficiency The part is designed to be especially attractive for dual supply 12V or 24V distributed power systems step down with 5V used to power the controller This lower Vcc voltage minimizes power dissipation inthe part and is used to drive the t
7. Thermal Resistance Wyc 65 C to 150 C Internally Limited via OTP 2kV HBM ELECTRICAL SPECIFICATIONS Unless otherwise specified 40 C lt Tams lt 85 C 40 C lt Tj lt 125 C 4 5V lt Voc lt 5 5V 3V lt Vin lt 28V BST LX 5V LX GND OV UVIN 3 0V CVcc 1uF Ccomp 0 1uF Css 50nF Typical measured at Vcc 5V The denotes the specifications which apply over the full temperature range unless otherwise specified PARAMETER Min typ max UNITS CONDITIONS QUIESCENT CURRENT Soc in e fm ff BST Supply Current No switching oz os ma v 09V st Gren emma a e pm fe PROTECTION UVLO mos pews ef TT DS CRE oe we onsas REN ae ame yo 200 300 400 mv i a UVIN 3 0V X Gain Config Measure Vegi Voc 9 V T 25 C lt FB Error Amplifier Reference 0 792 0 800 0 808 Error Amplifier Reference 0 788 0 800 0 812 Over Line and Temperature lt Error Amplifier Transconductance Error Amplifier Gain COMP Sink Current WA V 0 9V COMP 0 9V WA V 0 7V COMP 2 2V nA v V 3 0 7V TA 25 C COMP Source Current 3 3 COMP Clamp Temp Coefficient Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 2 ELECTRICAL SPECIFICATIONS Unless otherwise specified 40 C lt Tamp lt 85 C 40 C lt Tj lt 125 C 4 5V lt Voc lt 5 5V 3V lt Vin lt
8. diately after the 200ms timeout expires Whereas when a thermal fault is de tected the 200ms delay continuously recycles and a re start cannot be attempted until the thermal fault is removed and the timer expires Error Amplifier and Voltage Loop Since the heart of the SP7650 voltage error loop is a high performance wide bandwidth transconductance amplifier Because of the amplifier s current limited 150uA transconductance there are many ways to com pensate the voltage loop or to control the COMP pin externally If a simple single pole single Copyright 2005 Sipex Corporation zero response is desired then compensation can be as simple as an RC to ground If a more complex compensation is required then the amplifier has enough bandwidth 45 at 4 MHz and enough gain 60dB to run Type II compen sation schemes with adequate gain and phase margins at cross over frequencies greater than 50kHz The common mode output of the error amplifier is 0 9V to 2 2V Therefore the PWM voltage ramp has been set between 1 1V and 2 2V to ensure proper 0 to 100 duty cycle capability The voltage loop also includes two other very important features One is an asynchronous start up mode Basically the synchronous rectifier can not turn on unless the high side switch has attempted to turn on or the SS pin has exceeded 1 7V This feature prevents the controller from dragging down the output voltage during startup or in fault m
9. dth Product Condition C22 gt gt CP1 R1 gt gt RZ3 20 Log RZ2 R1 6 28 RZJ OP See ee SS 1 6 28 RZ3 CZ3 3 IN gt N RR Frequency oO D Hz vy T T amp EE 2 AS 6 g Bode Plot of Type III Error Amplifier Compensation i RZ RZ2 i 3 CZ3 pl NA e RI 68 1k 1 VEB Hag i COMP CF1 _0 8V vV Reet 54 48 Vout 0 8 k9 Type III Error Amplifier Compensation Circuit Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 10 TYPICAL PERFORMANCE CHARACTERISTICS SP7650 Effi v s lout Plots SP7650 Vout v s lout Plots Vin 12V and Vout 3 3V 95 0 3 34 Vin 12V and Vout 3 3V 30 9 S 3 33 z gt 85 0 S S g 3 32 2 80 0 z u 3 3 31 75 0 9 70 0 3 3 0 5 1 0 1 5 2 0 2 5 3 0 0 0 5 1 0 1 5 2 0 2 5 3 0 Load Current A Load Current A SP7650 Effi v s lout Plots SP7650 Vout v s lout Plots Vin 12V and Vout 5 0V 4 9 Vin 12V and Vout 5 0V 94 0 9710 920 4 9700 90 0 s S 88 0 9 4 9690 lt 86 0 84 0 3 4 9680 Oo gt 820 4 9670 i 80 0 8 78 0 4 9660 Len 4 9650 74 0 0 5 10 15 20 25 3 0 0 os 10 dee ae 30 Load Current A Load Current A Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 11 PACKAGE 26 PIN DFN 7x 4mm Top View ii kl Al Side View gt e lt
10. e SP7650 can be set to different output voltages The relationship in the following formula is based on a voltage divider from the output to the feedback pin VFB which is set to an internal reference voltage of 0 80V Standard 1 metal film resistors of surface mount size 0603 are recommended Vout 0 80V R1 R2 1 gt R2 R1 Vout 0 80V 1 Where R1 68 1KS and for Vout 0 80V setting simply remove R2 from the board Furthermore one could select the value of R1 and R2 combination to meet the exact output voltage setting by restricting R1 resistance range such that 50KQ lt R1 lt 100KQ for overall system loop stability Copyright 2005 Sipex Corporation Inductor Selection There are many factors to consider in selecting the inductor including core material inductance vs frequency current handling capability effi ciency size and EMI In a typical SP7650 cir cuit the inductor is chosen primarily for value saturation current and DC resistance Increasing the inductor value will decrease output voltage ripple but degrade transient response Low in ductor values provide the smallest size but cause large ripple currents poor efficiency and more output capacitance to smooth out the larger ripple current The inductor must be able to handle the peak current at the switching fre quency without saturating and the copper resis tance in the winding should be kept as low as possible to minimize resistive powe
11. ltage rating The input capacitor must meet the ripple current requirement imposed by the switching current In continuous conduction mode the source cur rent of the high side MOSFET is approximately a square wave of duty cycle Vour Vin More accurately the current wave form is trapezoidal given a finite turn on and turn off switch tran sition slope Most of this current is supplied by the input bypass capacitors The RMS current handling capability of the input capacitors is determined at maximum output current and under the assumption that the peak to peak inductor ripple current is low it is given by Tonens Lai VD 1 D The worse case occurs when the duty cycle D is 50 and gives an RMS current value equal to Iour 2 Select input capacitors with adequate ripple current rating to ensure reliable operation The power dissipated in the input capacitor is 2 E cin 7 I CIN rms R espccmny This can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency The input voltage ripple primarily depends on the input capacitor ESR and capacitance Ignoring the inductor ripple current the input voltage ripple can be deter mined by Copyright 2005 Sipex Corporation R Tourmax V our Vin Vour AV iy ESR CIN 2 FSC Vy wins The capacitor type suitable for the output capac itors can also be used for the input capacitors However exercise extra caution when
12. nsation schemes A precision 0 8V reference present on the positive terminal of the error amplifier per mits the programming of the output voltage down to 0 8V via the Vps pin The output of the error amplifier COMP compared to a 1 1V peak to peak ramp is responsible for trailing edge PWM control This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM fre quency to 300kHz Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator THEORY OF OPERATION The SP7650 contains two unique control fea tures that are very powerful in distributed appli cations First asynchronous driver control is enabled during start up to prohibit the low side switch from pulling down the output until the high side switch has attempted to turn on Sec ond a 100 duty cycle timeout ensures that the low side switch is periodically enhanced during extended periods at 100 duty cycle This guar antees the synchronized refreshing of the BST capacitor during very large duty ratios The SP7650 also contains a number of valuable protection features Programmable Viy UVLO allows the user to setthe exact value at which the conversion voltage can safely begin down con version and an internal Vec UVLO which en sures that the controller itself has enough volt age to properly operate Other protection fea Copyright 2005 Sipex Corporation tures include thermal shutdown and short cir
13. odes The second feature is a 100 duty cycle timeout that ensures synchro nized refreshing of the BST capacitor at very high duty ratios In the event that the high side NFET is on for 20 continuous clock cycles a reset is given to the PWM flip flop half way through the 21st cycle This forces GL to rise for the cycle in turn refreshing the BST capacitor The boost capacitor is used to generate a high voltage drive supply for the high side switch which is 5V above Vin Power MOSFETs The SP7650 contains a pair of integrated low resistance N channel switches designed to drive up to 3A of output current Care should be taken to de rate the output current based on the ther mal conditions in the system such as ambient temperature airflow and heat sinking Maxi mum output current could be limited by thermal limitations of a particular application by taking advantage of the integrated over temperature protective scheme employed in the SP7650 The SP7650 incorporates a built in over tem perature protection to prevent internal overheat ing Date 2 18 05 THEORY OF OPERATION VBST GH Voltage VSWN V Vec GL Voltage V VIN SWN Voltage 0V V Diode v l V Vin V Vec BST Voltage V Vec TIME SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Setting Output Voltages Th
14. op switch The SP7650 is designed to provide a fully integrated buck regulator solution using a fixed 300kHz frequency PWM voltage mode architecture Protection features include UVLO thermal shutdown and output short circuit protection The SP7650 is ilable in th ing DFN k i TYPICAL APPLICATION CIRCUIT U1 SP7650 L1 1 Pono ix Atala o OVOUT Lai ix 28 ii 4 7uH Irate 4 78A 3 3V a sa MES Lo di OOF 4 ono xai AE R1 ale vola 6 3V 1023 68 1k 1 8 comp ono 2 Leyec TROPP CF1 ENABLE 0 T uvin an 2 ER i 1000F 8 fono ono 2 DBST gee di DI 10 SD101AWS IETA TR de le ea CBST S ii 2 by u 6800pF VIN 5 vin ui 5V VCC 12V fs 300Khz Tei Notes 22uF 1 U1 Bottom Side Layout should 16V has three contacts isolated from one another Vin SWNODE and GND GND _ 2 RSET 54 48 Vout 0 8V KOhm Sg Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator Copyright 2005 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied Exposure to absolute maximum rating conditions for extended periods of time may affect reliability GH SWN All other pins Storage Temperature Power Dissipation ESD Rating
15. r loss A good compromise between size loss and cost is to set the inductor ripple current to be within 20 to 40 of the maximum output current The switching frequency and the inductor oper ating point determine the inductor value as fol lows Vour Vin max Vour Vig in DE SE IN max L OUT max where fs switching frequency Kr ratio of the AC inductor ripple current to the maximum output current The peak to peak inductor ripple current is Vour Vin max Vour j Vina FL IN max I Once the required inductor value is selected the proper selection of core material is based on peak inductor current and efficiency require ments The core must be large enough not to saturate at the peak inductor current Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator APPLICATIONS INFORMATION Ipp OUT max 2 I I PEAK and provide low core loss at the high switching frequency Low cost powdered iron cores have a gradual saturation characteristic but can intro duce considerable AC core loss especially when the inductor value is relatively low and the ripple currentis high Ferrite materials although more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is ex ceeded Nevertheless they are preferred at high switching frequencies because they present very low core loss while the designer is only requi
16. r must supply all the addi tional current demanded by the load until the SP7650 adjusts the inductor current to the new value In order to maintain Vout the capacitance must be large enough so that the output voltage is helped up while the inductor current ramps to the value corresponding to the new load current Additionally the ESR in the output capacitor causes a step in the output voltage equal to the current Because of the fast transient response and inherent 100 0 duty cycle capability provided by the SP7650 when exposed to output load transient the output capacitor is typically chosen for ESR not for capacitance value The output capacitor s ESR combined with the inductor ripple current is typically the main contributor to output voltage ripple The maxi mum allowable ESR required to maintain a specified output voltage ripple can be calculated by Resr AVout IPK PK where AV our Peak to Peak Output Voltage Ripple Ipx px Peak to Peak Inductor Ripple Current The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows 2 AVour ees DN IppResr CourFs Date 2 18 05 SP7650 Wide Input Voltage Range 3A 300kHz Buck Regulator APPLICATIONS INFORMATION Fs Switching Frequency D Duty Cycle Cour Output Capacitance Value Input Capacitor Selection The input capacitor should be selected forripple current rating capacitance and vo
17. red to prevent saturation In general ferrite or molypermalloy materials are a better choice for all but the most cost sensitive applications Optimizing Efficiency The power dissipated in the inductor is equal to the sum of the core and copper losses To mini mize copper losses the winding resistance needs to be minimized but this usually comes at the expense of a larger inductor Core losses have a more significant contribution at low output cur rent where the copper losses are at a minimum and can typically be neglected at higher output currents where the copper losses dominate Core loss information is usually available from the magnetic vendor Proper inductor selection can affect the resulting power supply efficiency by more than 15 The copper loss in the inductor can be calculated using the following equation 2 Prw It ceus Rymowe where r rms is the RMS inductor current that can be calculated as follows I Ipp i Irrms Loutimaxy 1 3 ca max Copyright 2005 Sipex Corporation Output Capacitor Selection The required ESR Equivalent Series Resis tance and capacitance drive the selection of the type and quantity of the output capacitors The ESR must be small enough that both the resis tive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage During an output load transient the output capacito
18. tantalum capacitors are used Tantalum capacitors are known for catastrophic failure when exposed to surge current and input capacitors are prone to such surge current when power supplies are connected live to low impedance power sources Although tantalum capacitors have been successfully em ployed at the input it is generally not recom mended Loop Compensation Design The open loop gain of the whole system can be divided into the gain of the error amplifier PWM modulator buck converter output stage and feedback resistor divider In order to cross over at the desired frequency cut off FCO the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency The goal of loop compensation is to manipulate loop frequency response such that its cross over gain at Odb results in a slope of 20db dec APPLICATIONS INFORMATION The first step of compensation design is to pick the loop cross over frequency High cross over frequency is desirable for fast transient response but often jeopardizes the power supply stability Cross over frequency should be higher than the ESR zero but less than 1 5 of the switching frequency or 60kHz The ESR zero is contrib uted by the ESR associated with the output capacitors and can be determined by 1 2x Cour Resr fz sk The next step is to calculate the complex conju gate poles contributed by the LC output filter 1 feao
19. utput voltage feedback point for 5 v the Buck Converter The output voltage is sensed and can be adjusted FB through an external resistor divider Whenever V drops 0 25V below the positive reference a short circuit fault is detected and the IC enters hiccup mode Output of the Error Amplifier It is internally connected to the inverting input COMP of the PWM comparator An optimal filter combination is chosen and connected to this pin and either ground or V to stabilize the voltage mode loop UVLO input for Vin voltage Connect a resistor divider between V and 7 UVIN sani IN UV to set minimum operating voltage Soft Start Connect an external capacitor between SS and GND to set the SS soft start rate based on the 104A source current The SS pin is held low via a 1mA min current during all fault conditions 10 13 v Input connection to the high side N channel MOSFET Place a decoupling IN capacitor between this pin and PGND 14 16 23 26 Connect an inductor between this pin and Vour Input for external 5V bias supply General Overview The SP7650 is a fixed frequency voltage mode synchronous PWM regulator optimized for high efficiency The part has been designed to be especially attractive for high voltage applica tions utilizing SV to power the controller and 2 5V to 28V for step down conversion The heart of the SP7650 is a wide bandwidth transconductance amplifier designed to accom modate Type II and Type III compe
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Sipex SP7650 handbook