MAXIM MAX17019 High-Input-Voltage Quad-Output Controller handbook
Contents
1.2. 100 E 505 po 8 100 95 BV E 91 144011 11411 14 3 5 00 5 9 Vin 2 5 z 85 jo 5 85 80 Vin 20V gt 80 Vin 3 3V ce pi amp 75 Vin 12V Sg 490 amp 75 o 5 o Vin 5V 70 z 70 E 2 485 65 o 65 480 d 55 55 50 475 50 0 001 0 01 0 1 1 0 0 05 1015 20 25 30 35 40 45 50 0 001 0 01 0 1 1 LOAD CURRENT LOAD CURRENT A LOAD CURRENT A SMPS REGULATOR B OUTPUT VOLTAGE SMPS REGULATOR C EFFICIENCY vs LOAD CURRENT vs LOAD CURRENT 1 82 z 90 B 85 VIN 2 5V ES 80 Vin 5V 2 8 75 Vin 3 3V 2 S 177 amp 70 5 Vin 2 5V ly z i 65 Vin 5V Vin 3 3V 60 55 1 72 50 0 05 10 15 20 25 30 0 001 0 01 0 1 1 10 LOAD CURRENT A LOAD CURRENT A SMPS REGULATOR C OUTPUT VOLTAGE REGULATOR D VOLTAGE vs LOAD CURRENT vs SOURCE SINK LOAD CURRENT 0 930 5 z 0 925 2 E 920 3 _ 0 915 z 0 910 0905 c g 0 900 5 gt 0 895 890 0 885 880 0 05 10 15 20 25 30 35 40 45 50 20 15 1 0 05 0 05 10 15 20 LOAD CURRENT A LOAD CURRENT A MAX17019 toc03 610Z 17019 High Input Voltage Quad Output Controller Typical Operating Characteristics continued TA 25 C Circuit of Figure 1 unless otherwise noted REG A STARTUP WAVEFORM REG B STARTUP WAVEFORM HEAVY LOAD REG A SHUTDOWN WAVEFORM HEAVY LOAD 17019
3. 0 to 4A 0 duty cycle Note 2 FBC Line Regulation LXC Peak Current Limit 7 61041 17019 High Input Voltage Quad Output Controller ELECTRICAL CHARACTERISTICS continued Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V VIND 1 8V VSHDN Vona VONB Vonc VoND 5V IREF Ii pos loUTD no load FREQ GND UP DN Vcc TA 40 C to 125 C Note 1 PARAMETER SYMBOL CONDITIONS REGULATOR D Source Sink Linear Regulator and VTTR Buffer IND Input Voltage Range VIND IND Supply Current REFIND Input Range OUTD Output Voltage Range VEBD with respect to VREFIND OUTD FBD lourD 50pA source load FBD Output Accuracy with respect to VREFIND OUTD FBD lourD 50pA sink load FBD Load Regulation OUTD Linear Regulator Current urce load Limit ink load High side on resistance Internal MOSFET On Resistance cut resistance Low side on resistance VTTR Output Accuracy REFIND to lyrTR x8mA FAULT PROTECTION Upper threshold rising edge hysteresis 50mV SMPS POK and Fault Thresholds Lower threshold falling edge hysteresis 50mV Upper threshold rising edge VTT LDO POKD and Fault hysteresis 50 Threshold Lower threshold falling edge hysteresis 50mV POK Output Low Voltage ISINK GENERAL LOG
4. 17019 High Input Voltage Quad Output Controller Pin Description continued FUNCTION Feedback Input for the Internal 3A Step Down Converter FBB regulates to 0 75V Switching Regulator B Enable Input When ONB is pulled low LXB is high impedance When ONB is driven high the controller enables the 3A internal switching regulator External Synchronization Input Used to override the internal switching frequency Switching Regulator A Enable Input When ONA is pulled low DLA and DHA are pulled low When ONA is driven high the controller enables the step up step down converter Input for Regulators B and C Power INBC from a 2 5V to 5 5V supply Internally connected to the drain of the high side MOSFETs for both regulator B and regulator C Bypass to PGND with 2x 10pF or greater ceramic capacitors to support the RMS current 5V Bias Supply Input for the Internal Switching Regulator Drivers Bypass with a 1 or greater ceramic capacitor Provides power for the BSTB and BSTC driver supplies Open Drain Power Good Output for the Internal Source Sink Linear Regulator POKD is low if FBD is more than 10 typ above or below the REFIND regulation threshold POKD is held low during soft start and in shutdown POKD becomes high impedance when FBD is in regulation Source Sink Linear Regulator Regulator D and Reference Buffer Enable Input When OND is pulled low OUTD is high impedance When OND
5. AVAILABL UUE LUATION KIT MAALIVI High Input Voltage Quad Output Controller General Description The MAX17019 is a high input voltage quad output con troller up to 38V The MAX17019 provides a compact low cost controller capable of providing four indepen dent regulators a main stage a 3Ap p internal step down a 5Ap p internal step down and 2A source sink linear regulator The input voltage is up to 38V This makes it an excellent choice for automotive applications The internal switching regulators include 5V synchronous MOSFETs that can be powered directly from a single Li cell or from the main 3 3V 5V power stages Finally the linear regulator is capable of sourcing and sinking 2A to support DDR termination requirements or to generate a fixed output voltage The step down converters use a peak current mode fixed frequency control scheme an easy to implement architecture that does not sacrifice fast transient response This architecture also supports peak current limit protection and pulse skipping operation to maintain high efficiency under light load conditions Separate enable inputs and independent open drain power good outputs allow flexible power sequencing A soft start function gradually ramps up the output volt age to reduce the inrush current Disabled regulators enter high impedance states to avoid negative output voltage created by rapidly discharging the output through the low sid
6. 5V 0 4A TO 2 0A LXB 5V div LOAD TRANSIENT lig 1A div loyrg 2A div REG D LOAD TRANSIENT SINK MAX17019 toc18 20us div Vino 1 8V VggriNp 0 9V Cour 2 x 10uF LOAD TRANSIENT IS FROM 0 TO 1A SINKING OUTD 10mV div 1001 1A div REG C LOAD TRANSIENT 0 8A TO 3A MAX17019 toc16 OUTC LXC 20us div 5V 0 8A TO 3 0A LOAD TRANSIENT OUTC 50mV div LXC 5V div 2A div loyrc 2A div REG D LOAD TRANSIENT SOURCE MAX17019 toc19 20us div OUTD 10mV div loyrp 1A div Vinn 1 81 1 0 9V Cour 2 x 10uF LOAD TRANSIENT IS FROM 0 TO 1 SOURCING 11 61041 17019 High Input Voltage Quad Output Controller Pin Description FUNCTION Open Drain Power Good Output for the Internal 5A Step Down Converter POKC is low if FBC is more than 12 typ above or below the nominal 0 75V feedback regulation threshold POKC is held low during startup and in shutdown POKC becomes high impedance when FBC is in regulation Boost Flying Capacitor Connection for the Internal 5A Step Down Converter The MAX17019 includes an internal boost switch diode connected between Vpp and BSTC Connect to an external capacitor as shown in Figure 1 Inductor Connection for the Internal 5A Step Down Converter Connect LXC to the switched side of the inductor Source Sink Linear Regulator Output Bypass with 2x 10uF or greater ceramic capacitors to grou
7. AT 2 Vin x Dax Your Cour VsaG where Dmax is the maximum duty factor see the Electrical Characteristics table T is the switching peri od 1 fosc and AT equals VouT VIN x T when in PWM mode or L x lipLE VIN VoUT when in pulse skipping mode The amount of overshoot voltage VsoAR that occurs after load removal due to stored inductor ener 9y can be calculated as 2 L 2CoutVout VSOAR When using low capacity ceramic filter capacitors capacitor size is usually determined by the capacity needed to prevent VsoAR from causing problems during load transients Generally once enough capacitance is added to meet the overshoot requirement undershoot at the rising load edge is no longer a problem 22 Input Capacitor Selection The input capacitor must meet the ripple current requirement InMS imposed by the switching currents The IRMS requirements of an individual regulator can be determined by the following equation IRMS Wout Vin Vour The worst case RMS current requirement occurs when operating with Vin 2Vour At this point the above equation simplifies to IRMS 0 5 x ILOAD However the MAX17019 uses an interleaved fixed frequency archi tecture which helps reduce the overall input RMS cur rent on the INBC input supply For the MAX17019 system INA supply nontantalum chemistries ceramic aluminum or OS CON are pre ferred due to their r
8. PARAMETER SYMBOL CONDITIONS ONA OND Vcc ONB ONC GND does not include switching losses measured from Vcc Vcc Supply Current Main Step Down and Regulator D INA Supply Current Step Down Vcc UP DN Vcc step down 5V LINEAR REGULATOR LDO 5 5V to 38V l pos to 50mA P GND LDO5 Short Circuit Current Limit LDOS5 BYP GND ViNLDO 5 5V 1 25V REFERENCE Reference Output Voltage No load LDO5 Output Voltage Reference Load Regulation IREF 1 to 50 OSCILLATOR Oscillator Frequency FREQ GND Maximum Duty Cycle All Switching Regulators REGULATOR A Main Step Down Output Voltage Adjust Range ep down configuration UP DN Vcc ep down configuration FBA R tion Volt inu CSPA VCSNA OmV 90 duty cycle ep down configuration UP DN Vcc CSPA Vesna 0 to 20mv 90 duty cycle FBA Regulation Voltage Overload S V S V FBA Line Regulation ep down UP DN Vcc Current Sense Input Common Mode Range Vesa Current Limit Threshold Positive VILIMA REGULATOR B Internal 3A Step Down Converter FBB Regulation Voltage ILXB 0 duty cycle Note 2 FBB Regulation Voltage Overload ILXB 0 to 2 5A 0 duty cycle Note 2 FBB Line Regulation LXB Peak Current Limit IPKB REGULATOR C Internal 5A Step Down Converter FBC Regulation Voltage ILxc OA 0 duty cycle Note 2 FBC Regulation Voltage Overload VFBC
9. that has conduction losses equal to the switching losses Choose a low side MOSFET NL that has the lowest possible on resistance RDS ON comes in a moder ate sized package i e 8 pin SO DPAK or D PAK High Input Voltage Quad Output Controller and is reasonably priced Ensure that the MAX17019 DLA gate driver can supply sufficient current to support the gate charge and the current injected into the para sitic drain to gate capacitor caused by the high side MOSFET turning on otherwise cross conduction prob lems might occur Switching losses are not an issue for the low side MOSFET since it is a zero voltage switched device when used in the step down topology Power MOSFET Dissipation Worst case conduction losses occur at the duty factor extremes For the high side MOSFET the worst case power dissipation due to resistance occurs at minimum input voltage V PD NyResistive E RDS ON Generally use a small high side MOSFET to reduce switching losses at high input voltages However the RDS ON required to stay within package power dissi pation limits often limits how small the MOSFET can be The optimum occurs when the switching losses equal the conduction RDS ON losses High side switching losses do not become an issue until the input is greater than approximately 15V Calculating the power dissipation in high side MOSFETs NH due to switching losses is difficult s
10. 008 MAX17019 toc09 17019 toc10 400us div 400us div 400us div 5V div RLoap 1 69 ONA 5V div Rioap 2 52 ONB 5V div 1 01 OUTA 5V div OUTA 5V div OUTB 2V div POKA 5V div POKA 5V div POKB 5V div LA SA div ILA SA div lg 2A div LXA 10V div LXA 10V div LXB 5V div REG C STARTUP WAVEFORM REG B SHUTDOWN WAVEFORM HEAVY LOAD REG C SHUTDOWN 17019 0611 17019 toc12 17019 toc13 ONC OUTC POKC lic LXC 2 400us div 400us div 100us div ONB 5V div Roan 0 82 ONC 5V div 0 250 ONC 5V div Rioap 0 250 OUTB 2V div OUTC 1V div OUTC 1V div POKB 5V div POKC 5V div POKC 5V div lg 2A div Lc SA div ILe SA div LXB 5V div LXC 5V div LXC 5V div 10 MAXIM OUTA LXA OUTD lourD High Input Voltage Quad Output Controller REG A LOAD TRANSIENT 1A TO 3 2A MAX17019 toc14 OUTB LXB ILB lora 20us div OUTA 100mV div Viya 12V LOAD TRANSIENT LXA 10V div IS FROM 1A TO 3 2A lj A 2A div louta 2A div REG D LOAD TRANSIENT SOURCE SINK MAX17019 toc17 OUTD louTD 20us div OUTD 20mV div 1001 1A div Vino 1 8V 0 9V Cour 2 x 10uF LOAD TRANSIENT IS FROM 1A SOURCING TO 1A SINKING Typical Operating Characteristics continued TA 25 C Circuit of Figure 1 unless otherwise noted REG B LOAD TRANSIENT 0 4A TO 2A MAX17019 toc15 20us div OUTB 50mV div
11. The MAX17019 uses a direct summing configuration approaching ideal cycle to cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it Frequency Selection FREQ The FREQ input selects the PWM mode switching fre quency Table 1 shows the switching frequency based on the FREQ connection High frequency FREQ GND operation optimizes the application for the small est component size trading off efficiency due to higher switching losses This might be acceptable in ultra portable devices where the load currents are lower Low frequency FREQ 5V operation offers the best overall efficiency at the expense of component size and board space SLOPE COMPENSATION Figure 3 PWM Comparator Functional Diagram AVLAZCLA HIGH SPEED LEVEL TRANSLATOR AND BUFFER UNCOMPENSATED 1 OUTPUT DRIVER VBIAS 610Z LXVIW High Input Voltage Quad Output Controller Table 1 FREQ Table REG A AND REG C REG B STARTUP BLANKING TIME STARTUP BLANKING TIME SWITCHING FREQUENCY SWITCHING FREQUENCY SOFT START SOFT START TIME TIME REG A 1200 fswa 1500 fswa fswB 1800 fswB 3000 fswB fswa AND fswc MAX17019 REG C 900 fswc REG A 4 8ms REG C 3 6ms 500kHz REG A 3 2ms REG C 2 4ms REG A 2 4ms REG C 1 8ms 375kHz 500kHz 750kHz 0 5 x fSYNC Light Load Opera
12. Vcc FREQ Input Voltage Levels Low GND FREQ Input Bias Current TA 25 C SYNC Input Logic Threshold ELECTRICAL CHARACTERISTICS Circuit of Figure 1 ViNLDO 12V Vina VINBC VoD Vcc VBYP VCSPA VCSNA SV ViND 1 8V VSHDN VONA VONB Vonc VoND 5V IREF IL pos 410010 no load FREQ GND UP DN Vcc Ta 40 C to 125 C Note 1 PARAMETER SYMBOL CONDITIONS Input Voltage Range UP DN LDO5 INLDO INA LDO5 UP DN LDOS INA Vcc rising edge hysteresis 160mV A Undervoltage Threshold VINA UVLO SUPPLY CURRENTS ViNLDO Shutdown Supply Current lIN SHDN LDO 5 5V to 38V SHDN GND LDO 5 5V to 38V ON GND DN INLDO ViNLDO Suspend Supply Current lIN SUS A Shutdown Current Vcc ONB O ot include switch Supply Current Main Step Down Only Supply Current Main Step Down and Regulator B NB OND G Vcc Supply Current ing losses Main Step Down and Regulator C ured from 6 MAXUM High Input Voltage Quad Output Controller ELECTRICAL CHARACTERISTICS continued Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V 1 8V VSHDN Vona VONB Vonc VoND 5V IREF ILDO5 loUTD no load FREQ GND UP DN Vcc Ta 40 C to 125 C Note 1
13. L R3 40 2kQ 196 0402 22uF 50V R4 4mQ 5 1206 5V 20 4022 150uF 35mQ 6V B2 CASE Pwr 12 7A 14mQ R5 14 0kQ 1 0402 C14 1000pF 50V 0402 13 AGND 7 7A 14mQ R7 4 02kQ R8 1 0402 10 0kQ 1 0402 C15 2200pF 50V AGNDNZ 0402 AGNDNZ C10 10uF 6V 0805 PWR C11 C12 2x 10uF 6V 0805 PWR AGND OuF 15mQ 2 5V B2 CASE PWR 330uF 15mQ 2 5V B2 CASE PWR 15 61041 17019 High Input Voltage Quad Output Controller REG D PWR REG D ANALOG 7N PGOOD AND FAULT PROTECTION REFIND FAULTX REF ENAB MAXIM MAX17019 UP DN BUCK LOW BUCK MODE ONB INBC_OK INBC_OK ONC INBC_OK ED BY SHDN BOOST REF ENABLED BY ONA SSDA ONLY USED IN STEP UP MODE SSDA HIGH IN STEP DOWN MODE Figure 2 MAX17019 Block Diagram 16 REG B ANALOG EN UVLO INBC REG C ANALOG EN b L1 7 MAXIM High Input Voltage Quad Output Controller LDO5 Bootstrap Switchover When the bypass input BYP exceeds the 005 boot strap switchover threshold for more than 500us internal 1 5Q typ p channel MOSFET shorts BYP to LDOS
14. is driven high the controller enables the source sink linear regulator Switching Regulator C Enable Input When ONC is pulled low LXC is high impedance When ONC is driven high the controller enables the 5A internal switching regulator Feedback Input for the Internal 5A Step Down Converter FBC regulates to 0 75V Power Ground The source of the low side MOSFETs REG B and REG C the drivers for all switching regulators and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad Connect the exposed backside pad to system power ground planes through multiple vias Detailed Description The MAX17019 standard application circuit Figure 1 provides a 5V 5Ap p main stage a 1 8V 3Ap p VDDQ and 0 9A 2A VTT outputs for DDR and a 1 05V 5Ap p chipset supply The MAX17019 supports four power outputs one high voltage step down controller two internal MOSFET step down switching regulators and one high current source sink linear regulator The step down switching regulators use a current mode fixed frequency architec ture compensated by the output capacitance An inter nal 50mA 5V linear regulator provides the bias supply and driver supplies allowing the controller to power up from input supplies greater than 5 5V Fixed 5V Linear Regulator LDO5 An internal linear regulator produces a preset 5V low current output from INLDO LDO5 powers the gate dri vers for the external MOSFETs and provide
15. linear regulator sources up to 50mA max guaranteed When BYP exceeds 4 65V typ the MAX17019 bypasses the linear regulator through 1 59 bypass switch When the linear regulator is bypassed LDO5 supports loads up to 100mA In the single cell step up applications the 5V linear regulator is no longer necessary for the 5V bias supply Bypass SHDN to ground and leave LDO5 unconnected Connect BYP and INLDO to effectively disable the linear regulator 12 Linear Regulator Bypass Input When BYP exceeds 4 65V the controller shorts LDO5 to BYP through a 1 59 bypass switch and disables the linear regulator When BYP is low the linear regulator remains active The BYP input also serves as the VTTR buffer supply allowing VTTR to remain active even when the source sink linear regulator OUTD has been disabled under system standby suspend conditions In the single cell step up applications the 5V linear regulator is no longer necessary for the 5V bias supply Bypass 5 to ground with a 1yuF capacitor and leave this output unconnected Connect BYP and INLDO to the system s 5V supply to effectively disable the linear regulator MAXIM High Input Voltage Quad Output Controller Pin Description continued FUNCTION 5V Analog Bias Supply Vcc powers all the analog control blocks error amplifiers current sense amplifiers fault comparators etc and control logic Connect Vcc to the 5V system supply with a series 10Q re
16. or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V 1 8V VSHDN Vona VONB Vonc VoND 5V IREF li pos louTD no load FREQ GND UP DN Vcc TA 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS Input Voltage Range UP DN 1005 INLDO INA LDO5 UP DN LDOS INA Vcc rising edge hysteresis 160mV A Undervoltage Threshold VINA UVLO INBC Input Voltage Range SUPPLY CURRENTS ViNLDO Shutdown Supply Current liN SHDN LDO 5 5V to 38V SHDN GN 5 5V to 38V ON INLDO p ONB 25 SHDN SHDN D T SHDN ONB D D ViNLDO Suspend Supply Current lIN SUS Vcc Shutdown Supply Current Vpp Shutdown Supply Current GND TA 25 SHDN ONB GND UP DN ONA Vcc ONB O does not include switchi measured from Vcc INA Shutdown Current Vcc Supply Current Main Step Down Only NA ONB Vcc oes not include swi easured from Vcc Vcc Supply Curren Main Step Down and Regu 20 NA ONC Vcc oes not include swi easured from Vcc Vcc
17. output capacitance and ESR Based on these requirements the typical applica tion requires a low ESR polymer capacitor lower cost but higher output ripple voltage or bulk ceramic capacitors higher cost but low output ripple voltage SMPS Loop Compensation Voltage positioning dynamically lowers the output volt age in response to the load current reducing the loop gain This reduces the output capacitance requirement stability and transient and output power dissipation requirements as well The load line is generated by sens ing the inductor current through the high side MOSFET on resistance and is internally preset to 5mV A typ for regulator B and 7mV A typ for regulator C The load line ensures that the output voltage remains within the regulation window over the full load conditions The load line of the internal SMPS regulators also pro vides the AC ripple voltage required for stability To maintain stability the output capacitive ripple must be kept smaller than the internal AC ripple voltage and crossover must occur before the Nyquist pole 1 duty 2fsw occurs Based on these loop require ments a minimum output capacitance can be deter mined from the following AVLAZCLA 1 VREF f4 Vour 2fswRDROOP Vout VIN Cour 4 where Rproop is 2Rsense for regulator A 5mV A for regulator B or 7mV A for regulator C as defined in the Electrical Characteristics table and fsw is the switching f
18. trip To protect against this possibility overdesign the cir cuit to tolerate _ ge LOAD lLiMIT 2 where ILIMIT is the peak current allowed by the current limit circuit including threshold tolerance and sense resistance variation The MOSFETs must have a relatively large heatsink to handle the overload power dissipation Choose a Schottky diode Di with a forward voltage drop low enough to prevent the low side MOSFET s body diode from turning on during the dead time As a general rule select a diode with a DC current rating equal to 1 3 the load current This diode is optional and can be removed if efficiency is not critical VTT LDO Design Procedure IND Input Capacitor Selection CIND The value of the IND bypass capacitor is chosen to limit the amount of ripple and noise at IND and the amount of voltage sag during a load transient Typically IND con nects to the output of a step down switching regulator which already has a large bulk output capacitor Nevertheless a ceramic capacitor equivalent to half the VTT output capacitance should be added and placed as close as possible to IND The necessary capacitance value must be increased with larger load current or if the trace from IND to the power source is long and results in relatively high input impedance VTT LDO Output Voltage FBD The VTT output stage is powered from the IND input The VTT output voltage is set by the REFIND input
19. ulator and immediately pulls the output to ground through its low side MOSFET Turning on the low side MOSFET with 100 duty cycle rapidly discharges the output capacitors and clamps the output to ground Cycle Vcc below 1V or toggle OND to clear the fault latch and restart the linear regulator LDO Output UVP Each MAX17019 includes an output UVP circuit that begins to monitor the output once the startup blanking period has ended If the source sink LDO output voltage drops below 8896 typ of its nominal REFIND regulation voltage for 5ms the UVP sets the fault latch pulls the POKD output low forces the output into a high impedance state and shuts down the linear regulator Cycle Vcc below 1V or toggle OND to clear the fault latch and restart the regulator SMPS Design Procedure Step Down Regulators Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point ripple current ratio The primary design trade off lies in choosing a good switch ing frequency and inductor operating point and the fol lowing four factors dictate the rest of the design 20 Input voltage range The maximum value VIN MAX must accommodate the worst case high AC adapter voltage The minimum value VIN MIN must account for the lowest battery voltage after drops due to connectors fuses and battery selector switches If there is a choice at all lower input volt ages resu
20. 3V to 0 3V LDOS INA Vpp Vcc to GN Deiric 0 3V to 6V LXC IND eui 1 0V to ViNBC 0 3V 58 2 0 3V VBsTA 0 3V BST Vpp 0 3V to Vi xg 6V ONA ONB ONC OND to 0 3V to 6V BST Vpp 0 3V to Vi xc 6V POKB POKD to GND 0 3V to Vcc 0 3V BST Vpp 0 3V to Vi xA 6V REF REFIND FREQ UP DN REF Short Cirouit csset teste 1mA SYNC 16 GND 0 3V to Vcc 0 3 Continuous Power Dissipation Ta 70 C FBB FBC FBD GND 0 3V to Vcc 0 3V Multilayer PCB 48 Pin 6mm x 6mm TQFN BYP tO GND 0 3V to Vi pos 0 3V 74866 2 derated 37mW C above 70 2 9W CSPA CSNA to GND 0 3V to Vcc 0 3V Operating Temperature Range 40 C to 105 C DIA to erii 0 3V to Vpp 0 3V JUACTION 10119 12 110 5 siiras 150 INBC to 6V Storage Temperature Range 65 C to 150 C OUTD 0 3V Lead Temperature soldering 108 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these
21. HDN must be pulled high to enable the reference and ONB or ONC is pulled high the respective internal step down con troller regulator B or C becomes enabled and begins switching The internal voltage soft start gradually increments the feedback voltage by 10mV every 24 switching cycles for regulator B or every 12 switching cycles for regulator C Therefore OUTB reaches its nominal regulation voltage 1800 fswg after regulator B is enabled and OUTC reaches its nominal regulation voltage 900 fswc after regulator C is enabled see the REG B Startup Waveform Heavy Load and REG C Startup Waveform Heavy Load graphs in the Typical Operating Characteristics SMPS Power Good Outputs POK POKA POKB and POKC are the open drain outputs of window comparators that continuously monitor each output for undervoltage and overvoltage conditions POK_ is actively held low in shutdown SHDN GND standby ONA ONB ONC GND and soft start AVLAZCLA Once the soft start sequence terminates _ becomes high impedance as long as the output remains within 8 min of the nominal regulation voltage set by FB POK_ goes low once its corresponding output drops 1296 typ below its nominal regulation point an output overvoltage fault occurs or the output is shut down For a logic level POK_ output voltage connect external pullup resistor between _ and LDO5 A 100kQ pullup resistor works well in most applicatio
22. IC LEVELS SHDN Input Logic Threshold Hysteresis 20mV ON_ Input Logic Threshold Hysteresis 170mV UP DN Input Logic Threshold High Vcc FREQ Input Voltage Levels Unconnected RE Low GND SYNC Input Logic Threshold Note 1 Limits are 100 production tested at Ta 25 C Maximum and minimum limits are guaranteed by design and characterization Note 2 Regulation voltage tested with slope compensation Typical value is equivalent to 0 duty cycle In real applications the regulation voltage is higher due to the line regulation times the duty cycle 8 MAXIM High Input Voltage Quad Output Controller Ta 25 C Circuit of Figure 1 unless otherwise noted vs LOAD CURRENT SMPS REGULATOR A EFFICIENCY Typical Operating Characteristics SMPS REGULATOR A OUTPUT VOLTAGE vs LOAD CURRENT SMPS REGULATOR EFFICIENCY vs LOAD CURRENT
23. REFIND sets the LDO feedback regulation voltage VEBD VREFIND and the VTTR output voltage The VTT LDO FBD voltage and VTTR track the REFIND voltage over a 0 5V to 1 5V range This reference input feature makes the MAX17019 ideal for memory applica tions in which the termination supply must track the supply voltage 23 61041 17019 High Input Voltage Quad Output Controller VTT LDO Output Capacitor Selection CouTD A minimum value of 20UF or greater ceramic is needed to stabilize the VTT output OUTD This value of capac itance limits the switching regulator s unity gain band width frequency to approximately 1 2MHz typ to allow adequate phase margin for stability To keep the capacitor acting as a capacitor within the switching regulator s bandwidth it is important that ceramic capacitors with low ESR and ESL be used Since the gain bandwidth is also determined by the transconductance of the output MOSFETs which increases with load current the output capacitor might need to be greater than 20uF if the load current exceeds 1 5A but can be smaller than 20uF if the maxi mum load current is less than 1 5A As a guideline choose the minimum capacitance and maximum ESR for the output capacitor using the following 20yF OUT MIN Ur x 15A ILOAD R 5mQ x LOAD ESR _ 15 REsR value is measured at the unity gain bandwidth frequency given by approximat
24. Regulators DMAX 93 5 Minimum On Time All Switching Regulators tON MIN FREQ Vcc or GND 90 FREQ REF REGULATOR A Main Step Down Output Voltage Adjust Range Step down configuration UP DN BA Regulation Voltage ep down configuration UP DN Vcc CSPA VCSNA 0 to 20mV 90 duty cycle BA Regulation Voltage Overload ep down configuration UP DN Vcc BA Load Regulation BA Line Regulation Vcc ep down configuration UP D VCSNA to 20mV S V S VCSPA VCSNA to 20mV 90 duty cycle S V UP DN Vcc 0 Step down to 100 duty cycle UP DN Vcc BA Input Current Current Sense Input Common Mode Range VCSA UP DN GND or Vcc TA 25 C Current Sense Input Bias Current ICSA Ta 25 C Idle Mode Threshold VIDLEA Idle Mode is a trademark of Maxim Integrated Products Inc 61041 17019 High Input Voltage Quad Output Controller ELECTRICAL CHARACTERISTICS continued Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V VIND 1 8V VSHDN Vona VONB Vonc 5 IREF ILDO5 lourp load FR Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL Zero Crossing Threshold CONDITIONS EQ GND UP DN Vcc Ta 0 C to 85 C unless otherwise noted HA Gate D
25. Supply Curren Main Step Down and Regu 20 3 NA OND Vcc ONB oes not include switching easured from Vcc Vcc Supply Curren Main Step Down and Regu 20 3 3 INA Supply Current Vcc UP DN 2 AVLAXL VI High Input Voltage Quad Output Controller ELECTRICAL CHARACTERISTICS continued Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V 1 8V VSHDN Vona VONB Vonc VoND 5V IREF li pos lourp no load FREQ GND UP DN Vcc TA 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS 5V LINEAR REGULATOR 105 LDO5 Output Voltage VLDO5 VINLDO 5 5V to 38V li pos to 50mA BYP LDO5 Short Circuit Current Limit LDO5 BYP GND VINLDO 5 5V BYP Switchover Threshold LDO5 to BYP Switch Resistance 1 25V REFERENCE VBYP Rising edge V Reference Output Voltage No load 1 237 1 25 1 263 Reference Load Regulation Reference Undervoltage Lockout VREF UVLO REF 1A to 50 OSCILLATOR Oscillator Frequency fosc FREQ Vcc FREQ REF FREQ GND 1 0 SWA Regulator A 1 2 fosc Switching Frequency fswB fswc fosc 1 2 fosc Regulator B Regulator C Maximum Duty Cycle All Switching
26. Vcc ND Shutdown Current REFIND Input Range OND GND TA 25 C REFIND Input Bias Current VREFIND to 1 5V Ta 25 C OUTD Output Voltage Range MAXIM High Input Voltage Quad Output Controller ELECTRICAL CHARACTERISTICS continued Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V 1 8V VSHDN Vona VONB Vonc VoND 5V IREF li pos louTD no load FREQ GND UP DN Vcc Ta 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS with respect to VREFIND OUTD FBD loUTD 50 source load FBD Output Accuracy VFBD with respect to VREFIND OUTD FBD louTD 50pA sink load FBD Line Regulation VIND 1 0V to 2 8V louTD 200 FBD Input Current 1 1 5V Ta 25 C OUTD Linear Regulator Current Source load Limit Sink load Current Limit Soft Start Time With respect to internal OND signal High side on resistance Low side on resistance nternal MOSFET On Resistance lata 0 5mA Output Accuracy REFIND tovTTR UR 38mA TTR Maximum Current Rating FAULT PROTECTION Upper threshold rising edge hysteresis 50mV SMPS POK and Fault Thresholds Lower threshold falling edge hysteresis 50mV Upper threshold rising edge VTT LDO POKD and Faul
27. ctor value also determines the load current value at which PFM PWM switchover occurs Step Down Inductor Selection The switching frequency and inductor operating point determine the inductor value as follows L Vout Vin Your VinfgwlLoaD MAx L R Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions Most MAKLM High Input Voltage Quad Output Controller inductor manufacturers provide inductors in standard values such as 1 0UH 1 5uH 2 2UH 3 3uH etc Also look for nonstandard values which can provide a better compromise in LIR across the input voltage range If using a swinging inductor where the no load induc tance decreases linearly with increasing current evalu ate the LIR with properly scaled inductance values For the selected inductance value the actual peak to peak inductor ripple current AIINDUCTOR is defined by Vout Vin Your VinfswL AlINDUCTOR Ferrite cores are often the best choice although soft sat urating molded core inductors are inexpensive and can work well at 500kHz The core must be large enough not to saturate at the peak inductor current IPEAK AliNDUCTOR IPEAK LOAD MAX SMPS Output Capacitor Selection The output filter capacitor selection requires careful evaluation of several different design requirements stability transient response and output ripple volt age that place limits on the
28. e MOSFET The MAX17019 also includes output undervoltage output overvoltage and thermal fault protection The MAX17019 is available in a 48 pin 6mm x 6mm thin QFN package Applications Automotive Battery Powered Devices Embedded Control Systems Set Top Boxes MAKIM Features Fixed Frequency Current Mode Controllers 5 5V to 38V Input Range Step Down 1x Step Down Controller 1x Internal 5Ap p Step Down Regulator 1x Internal Step Down Regulator 1x 2A Source Sink Linear Regulator with Dynamic REFIN Internal BST Diodes Internal 5 50mA Linear Regulator Fault Protection Undervoltage Overvoltage Thermal Peak Current Limit Independent Enable Inputs and Power Good Outputs Voltage Controlled Soft Start High Impedance Shutdown 9 10 typ Shutdown Current 9 9 Ordering Information PART TEMP RANGE PIN PACKAGE MAX17019ATM 40 C to 125 C 48 TQFN EP Denotes a lead free ROHS compliant package EP Exposed pad Pin Configuration TOP VIEW MAXIM MAX17019 EXPOSED PAD PGND THIN QFN Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 610Z 17019 High Input Voltage Quad Output Controller ABSOLUTE MAXIMUM RATINGS INE DO SHDN to GN Dieron 0 3V to 43V V TREO ast bats haoc 0
29. e enable input to clear the fault latch and restart the regulator Thermal Fault Protection The MAX17019 features a thermal fault protection cir cuit When the junction temperature rises above 160 C a thermal sensor activates the fault latch pulls all POK outputs low and shuts down all regulators Toggle SHDN to clear the fault latch and restart the controllers after the junction temperature cools by 15 C 61041 17019 High Input Voltage Quad Output Controller VTT LDO Detailed Description VTT LDO Power Good Output POKD POKD is the open drain output of a window comparator that continuously monitors the VTT LDO output for undervoltage and overvoltage conditions POKD is actively held low when the LDO is disabled OND GND and in soft start Once the startup blanking time expires POKD becomes high impedance as long as the output remains within 6 min of the nominal regulation voltage set by REFIND POKD goes low once its corresponding output drops or rises 12 typ beyond its nominal regulation point or the output is shut down For a logic level POKD output voltage connect an external pullup resistor between POKD 005 A 100kQ pullup resistor works well in most applications VTT LDO Fault Protection LDO Output OVP If the output voltage rises above 11296 typ of its nomi nal regulation voltage the controller sets the fault latch pulls POKD low shuts down the source sink linear reg
30. ely and 36 lisi GBW T Cour V dA Once these conditions for stability are met additional capacitors including those of electrolytic and tantalum types can be connected in parallel to the ceramic capacitor if desired to further suppress noise or volt age ripple at the output VTTR Output Capacitor Selection The VTTR buffer is a scaled down version of the VTT regulator with much smaller output transconductance Therefore the compensation requirements also scale For typical applications requiring load currents up to x3mA a 0 22yF or greater ceramic capacitor is recommended REsR lt 0 39 24 VTT LDO Power Dissipation Power loss in the MAX17019 VTT LDO is significant and can become a limiting design factor in the overall MAX17019 design PDvrT 2A x 0 9V 1 8W The 1 8W total power dissipation is within the 40 pin TQFN multilayer board power dissipation specification of 2 9W The typical DDR termination application does not actually continuously source or sink high currents The actual VTT current typically remains around 100mA to 200mA under steady state conditions VTTR is down in the microampere range though the Intel specifica tion requires 3mA for DDR1 and 1mA for DDR2 True worst case power dissipation occurs on an output short circuit condition with worst case current limit The MAX17019 does not employ any foldback current limit ing and relies on the internal thermal shutdown fo
31. esistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input For the MAX17019 INBC input supply ceramic capacitors are preferred on input due to their low parasitic inductance which helps reduce the high frequency ringing on the INBC supply when the internal MOSFETs are turned off Choose an input capacitor that exhibits less than 10 temperature rise at the RMS input current for optimal circuit longevity BST Capacitors The boost capacitors CBsT must be selected large enough to handle the gate charging requirements of the high side MOSFETs For these low power applica tions 0 1uF ceramic capacitors work well Regulator A Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load current capability when using high voltage gt 20V AC adapters Low current applications usually require less attention The high side MOSFET NH must be able to dissipate the resistive losses plus the switching losses at both VIN MIN and VIN MAX Ideally the losses at VIN MIN should be roughly equal to the losses at VIN MAX with lower losses in between If the losses at VIN MIN are significantly higher consider increasing the size of NH Conversely if the losses at VIN MAX are significantly higher consider reducing the size of NH If VIN does not vary over a wide range maximum efficiency is achieved by selecting a high side MOSFET
32. g 18 comparator senses the inductor current during the off time For regulator A once VCSPA VCSNA drops below the 1mV zero crossing current sense threshold the com parator turns off the low side MOSFET DLA pulled low For regulators B and C once the current through the low side MOSFET drops below 100mA the zero crossing comparator turns off the low side MOSFET The minimum idle mode current requirement causes the threshold between pulse skipping PFM operation and constant PWM operation to coincide with the boundary between continuous and discontinuous inductor current operation also known as the critical conduction point The load current level at which PFM PWM crossover occurs ILOAD SKIP is equivalent to half the idle mode current threshold see the Electrical Characteristics table for the idle mode thresh olds of each regulator The switching waveforms can appear noisy and asynchronous when light loading causes pulse skipping operation but this is a normal operating condition that results in high light load effi ciency Trade offs in PFM noise vs light load efficiency are made by varying the inductor value Generally low inductor values produce a broader efficiency vs load curve while higher values result in higher full load effi ciency assuming that the coil resistance remains fixed and less output voltage ripple Penalties for using high er inductor values include larger physical size and degraded load t
33. ince it must allow for difficult to quantify factors that influence the turn on and turn off times These factors include the internal gate resistance gate charge threshold voltage source inductance and PCB layout characteristics The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation preferably including verification using a ther mocouple mounted on NH PD N Switching oapQa sw CossViN MAX 1 ku 2 wol GATE where Coss is the output capacitance of NH Qa sw is the charge needed to turn on the MOSFET and IGATE is the peak gate drive source sink current 1A typ Switching losses in the high side MOSFET can become a heat problem when maximum AC adapter voltages are applied due to the squared term in the switching loss equation C x VIN x fsw If the high side MOSFET chosen for adequate RDS ON at low battery voltages becomes extraordinarily hot when subjected to VIN MAX consider choosing another MOSFET with lower parasitic capacitance AVLAZCLA For the low side MOSFET NL the worst case power dissipation always occurs at maximum battery voltage 2 1 R v Loan Roson PD N Resistive The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD MAX but are not high enough to exceed the current limit and cause the fault latch to
34. k Input for the Main Switching Regulator FBA regulates to 1 0V Open Drain Power Good Output for the Main Switching Regulator POKA is low if FBA is more than 12 typ above or below the nominal 1 0V feedback regulation point POKA is held low during soft start and in shutdown POKA becomes high impedance when FBA is in regulation High Side Gate Driver Output for the Main Switching Regulator DHA swings from LXA to BSTA Inductor Connection of Converter A Connect LXA to the switched side of the inductor Boost Flying Capacitor Connection of Converter A The MAX17019 needs an external boost switch diode connected between Vpp and BSTA Connect to an external capacitor as shown in Figure 1 Low Side Gate Driver Output for the Main Switching Regulator DLA swings from GND to Vpp Inductor Connection for the Internal 3A Step Down Converter Connect LXB to the switched side of the inductor Boost Flying Capacitor Connection for the Internal 3A Step Down Converter The MAX17019 includes an internal boost switch diode connected between Vpp and BSTB Connect to an external capacitor as shown in Figure 1 Open Drain Power Good Output for the Internal Step Down Converter is low if FBB is more than 12 typ above or below the nominal 0 75V feedback regulation threshold POKB is held low during soft start and in shutdown POKB becomes high impedance when FBB is in regulation 13 61041
35. lt in better efficiency Maximum load current There are two values to con sider The peak load current ILOAD MAX determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selec tion inductor saturation rating and the design of the current limit circuit The continuous load current ILOAD determines the thermal stresses and thus drives the selection of input capacitors MOSFETs and other critical heat contributing components e Switching frequency This choice determines the basic trade off between size and efficiency The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and 2 Inductor operating point This choice provides trade offs between size vs efficiency and transient response vs output ripple Low inductor values pro vide better transient response and smaller physical Size but also result in lower efficiency higher output ripple and lower maximum load current due to increased ripple currents The minimum practical inductor value is one that causes the circuit to oper ate at the edge of critical conduction where the inductor current just touches zero with every cycle at maximum load Inductor values lower than this grant no further size reduction benefit The optimum operating point is usually found between 20 and 5096 ripple current When pulse skipping light loads the indu
36. ms of fractions of centimeters where a single mil liohm of excess trace resistance causes a measur able efficiency penalty Minimize current sensing errors by connecting CSPA and CSNA directly across the current sense resistor RSENSE e When trade offs in trace lengths must be made it is preferable to allow the inductor charging path to be made longer than the discharge path For example it is better to allow some extra distance between the input capacitors and the high side MOSFET than to allow distance between the inductor and the low side MOSFET or between the inductor and the out put filter capacitor e Route high speed switching nodes BST LX DHA and DLA away from sensitive analog areas REF REFIND FB CSPA Chip Information TRANSISTOR COUNT 22 577 PROCESS BiCMOS Package Information For the latest package outline information go to www maxim ic com packages PACKAGE TYPE PACKAGE CODE DOCUMENT NO 48 TQFN T4866 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 25 2008 Maxim Integrated Products MAXIM is a registered trademark of Maxim Integrated Products Inc 61041
37. nd Dropout needs additional output capacitance see the VTT LDO Output Capacitor Selection COUTD section FBD Source Sink Linear Regulator Input Bypass IND with a 10pF or greater ceramic capacitor to ground Feedback Input for the Internal Source Sink Linear Regulator FBD tracks and regulates to the REFIND voltage VTTR Ouput of Reference Buffer Bypass with 0 22uF for 3mA of output current REFIND Dynamic Reference Input Voltage for the Source Sink Linear Regulator and the Reference Buffer The linear regulator feedback threshold FBD tracks the REFIND voltage Shutdown Control Input The device enters its 5 supply current shutdown mode if VSHDN is less than the SHDN input falling edge trip level and does not restart until VSHDN is greater than the SHDN input rising edge trip level Connect SHDN to ViNi po for automatic startup of LDOS5 Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator Bypass to GND with a O 1uF or greater ceramic capacitor close to the controller In the single cell step up applications the 5V linear regulator is no longer necessary for the 5V bias supply Connect BYP and INLDO to the system s 5V supply to effectively disable the linear regulator 5V Internal Linear Regulator Output Bypass with 4 7 or greater ceramic capacitor The 5V linear regulator provides the bias power for the gate drivers Vpp and analog control circuitry Vcc The
38. ns SMPS Fault Protection Output Overvoltage Protection OVP If the output voltage rises above 11296 typ of its nomi nal regulation voltage the controller sets the fault latch pulls low shuts down the respective regulator and immediately pulls the output to ground through its low side MOSFET Turning on the low side MOSFET with 100 duty cycle rapidly discharges the output capacitors and clamps the output to ground However this commonly undamped response causes negative output voltages due to the energy stored in the output LC at the instant the OVP occurs If the load cannot tol erate a negative voltage place a power Schottky diode across the output to act as a reverse polarity clamp If the condition that caused the overvoltage persists such as a shorted high side MOSFET the input source also fails short circuit fault Cycle Vcc below 1V or toggle the respective enable input to clear the fault latch and restart the regulator Output Undervoltage Protection UVP Each MAX17019 includes an output UVP circuit that begins to monitor the output once the startup blanking period has ended If any output voltage drops below 88 typ of its nominal regulation voltage the UVP protection immediately sets the fault latch pulls the respective POK output low forces the high side and low side MOSFETs into high impedance states DH DL low and shuts down the respective regulator Cycle Vcc below 1V or toggle the respectiv
39. ntroller Internal SMPS Transient Response The load transient response depends on the overall output impedance over frequency and the overall amplitude and slew rate of the load step In applica tions with large fast load transients load step gt 80 of full load and slew rate gt 10A us the output capacitor s high frequency response ESL and ESR needs to be considered To prevent the output voltage from spiking too low under a load transient event the ESR is limited by the following equation ignoring the sag due to finite capacitance VSTEP R AILOAD MAX is RESR 1 where VsrEP is the allowed voltage drop AILOAD MAX 18 the maximum load step and RpcB is the parasitic board resistance between the load and output capacitor The capacitance value dominates the midfrequency output impedance and dominates the load transient response as long as the load transient s slew rate is less than two switching cycles Under these conditions the sag and soar voltages depend on the output capacitance inductance value and delays in the tran sient response Low inductor values allow the inductor current to slew faster replenishing charge removed from or added to the output filter capacitors by a sud den load step especially with low differential voltages across the inductor The sag voltage VsAG that occurs after applying the load current can be estimated by the following L AlLoapqmax
40. ove this maximum input voltage results in pulse skipping to avoid overcharging the output At the beginning of each cycle if the output voltage is still above the feedback threshold voltage the controller does not trigger an on time pulse effectively skipping a cycle This allows the controller to maintain regulation above the maximum input voltage but forces the con troller to effectively operate with a lower switching fre quency This results in an input threshold voltage at which the controller begins to skip pulses VIN SKIP VIN SKIP VoUT OSCTON MIN where fosc is the switching frequency selected by FREQ PCB Layout Guidelines Careful PCB layout is critical to achieving low switching losses and clean stable operation The switching power stage requires particular attention If possible mount all the power components on the top side of the board with their ground terminals flush against one another Follow the MAX17019 evaluation kit layout and use the following guidelines for good PCB layout e Keep the high current paths short especially at the ground terminals This practice is essential for sta ble jitter free operation e Keep the power traces and load connections short This practice is essential for high efficiency Using thick copper PCBs 202 vs 102 can enhance full load efficiency by 1 or more Correctly routing PCB traces is a difficult task that must be approached in ter
41. r pro tection Both the VTT and VTTR output voltages are referenced to the same REFIND input Applications Information Minimum Input Voltage The minimum input operating voltage dropout voltage is restricted by the maximum duty cycle specification see the Electrical Characteristics table For the best dropout performance use the slowest switching fre quency setting FREQ GND However keep in mind that the transient performance gets worse as the step down regulators approach the dropout voltage so bulk output capacitance must be added see the voltage sag and soar equations in the SMPS Design Procedure Step Down Regulators section The absolute point of dropout occurs when the inductor current ramps down during the off time AIDOWN as much as it ramps up during the on time Alup This results in a minimum operating voltage defined by the following equation 1i ViN MIN VOUT Vour Vois where VCHG Vpis are the parasitic voltage drops in the charge and discharge paths respectively A rea sonable minimum value for h is 1 5 while the absolute minimum input voltage is calculated with h 1 AVLAZCLA High Input Voltage Quad Output Controller Maximum Input Voltage The MAX17019 controller includes a minimum on time specification which determines the maximum input operating voltage that maintains the selected switching frequency see the Electrical Characteristics table Operation ab
42. ransient response especially at low input voltage levels MAKLM High Input Voltage Quad Output Controller SMPS POR UVLO and Soft Start Power on reset POR occurs when Vcc rises above approximately 1 9V resetting the undervoltage overvolt age and thermal shutdown fault latches The POR cir cuit also ensures that the low side drivers are pulled low until the SMPS controllers are activated The Vcc input undervoltage lockout UVLO circuitry prevents the switching regulators from operating if the 5V bias supply Vcc Vpp is below its 4 2 UVLO threshold Regulator A Startup Once the 5V bias supply rises above this input UVLO threshold and ONA is pulled high the main step down controller regulator A is enabled and begins switch ing The internal voltage soft start gradually increments the feedback voltage by 10mV every 12 switching cycles Therefore OUTA reaches its nominal regulation voltage 1200 fswa after regulator A is enabled see the REG A Startup Waveform Heavy Load graph in the Typical Operating Characteristics Regulator B and C Startup The internal step down controllers start switching and the output voltages ramp up using soft start If the bias supply voltage drops below the UVLO threshold the controller stops switching and disables the drivers LX_ becomes high impedance until the bias supply voltage recovers Once the 5V bias supply and INBC rise above their respective input UVLO thresholds S
43. requency selected by the FREQ setting see Table 1 Additionally an additional feedback pole capacitor from FB to analog ground Crg might be necessary to cancel the unwanted ESR zero of the output capacitor In general if the ESR zero occurs before the Nyquist pole then canceling the ESR zero is recommended If 14D ESR gt __ _ AntswCout Then CourESR CFB REB where RFB is the parallel impedance of the FB resistive divider SMPS Output Ripple Voltage With polymer capacitors the effective series resistance ESR dominates and determines the output ripple volt age The step down regulator s output ripple voltage VRIPPLE equals the total inductor ripple current AlINDUCTOR multiplied by the output capacitor s ESR Therefore the maximum ESR to meet the output ripple voltage requirement is VinfswL Vin Vour Vout Resp VRIPPLE where fsw is the switching frequency The actual capa citance value required relates to the physical case size needed to achieve the ESR requirement as well as to the capacitor chemistry Thus polymer capacitor selec tion is usually limited by ESR and voltage rating rather than by capacitance value Alternatively combining ceramics for the low ESR and polymers for the bulk capacitance helps balance the output capacitance vs output ripple voltage requirements 21 61041 17019 High Input Voltage Quad Output Co
44. river On Resistance DHA forced high and low LA Gate Driver On Resistance DLA forced high DLA forced low HA Gate Driver Source Sink urrent IDL SRC IDL SNK LA Gate Driver Source Sink urrent DHA forced to 2 5V DLA forced to 2 5V DLA forced to 2 5V 1 5 REGULATOR B Internal 3A Step Down Converter FBB Regulation Voltage FBB Regulation Voltage Overload 1 0 duty cycle Note 2 LXB 0 to 2 5A 0 duty cycle Note 2 0 747 0 755 0 762 FBB Load Regulation AVrBB AILXB LXB 0 to 2 5A FBB Line Regulation FBB Input Current nternal MOSFET On Resistance 0 to 100 duty cycle High side n channel Low side n channel LXB Peak Current Limit LXB Idle Mode Trip Level lIDLEB LXB Zero Crossing Trip Level 7 FBC Regulation Voltage REGULATOR C Internal 5A Step Down Converter ILxc 0 0 duty cycle Note 2 0 747 0 755 0 762 FBC Regulation Voltage Overload VFBC ILxc to 0 duty cycle Note 2 0 710 0 762 FBC Load Regulation ILxc to 4A FBC Line Regulation FBC Input Current 0 to 100 duty cycle TA 25 C 12 16 nternal MOSFET On Resistance LXC Peak Current Limit High side n channel Low side n channel LXC Idle Mode Trip Level LXC Zero Crossing Trip Level ND Input Voltage Range ND Supply Current OND
45. s the bias 14 supply required for the SMPS analog controller refer ence and logic blocks LDO5 supplies at least 50mA for external and internal loads including the MOSFET gate drive which typically varies from 5mA to 15mA per switching regulator depending on the switching frequency Bypass LDO5 with a 4 7uF or greater ceramic capacitor to guarantee stability under the full load conditions The MAX17019 switch mode step down switching reg ulators require a 5V bias supply in addition to the main power input supply This 5V bias supply is generated by the controllers internal 5V linear regulator 1005 This boot strappable LDO allows the controller to power up independently The gate driver Vpp input supply is typically connected to the fixed 5V linear reg ulator output 1005 Therefore the 5V LDO supply must provide LDO5 PWM controller and the gate drive power during power up MAXIM High Input Voltage Quad Output Controller C1 4 TuF 6V 0603 PWR 2 0402 5 0402 PS UTPUT R9 R12 4x 100kQ 5 0402 e R2 0Q 1 0402 AGND AGNDNZ C16 0 1uF 6V 0402 AGND C4 0 22uF 4V 0402 R13 15ko 6 196 0402 1 8V SMPS OUTPUT R14 15 0kQ 1 0402 AGND VZ ONA ONB ONC OND MAXIM MAX17019 INBC BSTB Figure 1 Standard Application Circuit 19 20 C21 2x 4 7uF 50V 1206 PWR PWR Nui L1
46. sistor and bypass to analog ground using a 1uF or greater ceramic capacitor Input to the Circuit in Reg A in Boost Mode Connect INA to LDO5 in step down mode UP DN Vcc Converter Configuration Selection Input for Regulator A When UP DN is pulled high UP DN Vcc regulator A operates as a step down converter Figure 1 When UP DN is pulled low UP DN GND regulator A operates as a low voltage step up converter Refer to the MAX17017 data sheet for step up configuration evel Oscillator Frequency Selection Input EQ Vcc RegA 250kHz RegB 500kHz RegC 250kHz EQ REF RegA 375kHz RegB 750kHz RegC 375kHz EQ GND RegA 500kHz RegB 1MHz RegC 500kHz 1 25V Reference Voltage Output Bypass REF to analog ground with a 0 1uF ceramic capacitor The reference sources up to 50pA for external loads Loading REF degrades output voltage accuracy according to the REF load regulation error The reference shuts down when the system pulls SHDN low in buck mode UP DN GND Negative Current Sense Input for the Main Switching Regulator Connect to the negative terminal of the current sense resistor Due to the CSNA bias current requirements limit the series impedance to less than 100 Positive Current Sense Input for the Main Switching Regulator Connect to the positive terminal of the current sense resistor Due to the CSPA bias current requirements limit the series impedance to less than 10Q Feedbac
47. t hysteresis 50mV Threshold Lower threshold falling edge hysteresis 50mV FB forced 50mV beyond POK trip threshold POK Propagation Delay FB forced 50mV above POK upper trip threshold Overvoltage Fault Latch Delay SMPS Undervoltage Fault FBA FBB or FBC forced 50mV below Latch Delay lower trip threshold VTT LDO Undervoltage Fault FBD forced 50mV below POKD lower Latch Delay trip threshold POK Output Low Voltage SINK 3mA VFBA 1 05V 0 8V Vrgp kage Currents VREFIND 50mV high impedance POK forced to 5V TA 25 Thermal Shutdown Threshold TSHDN Hysteresis 15 5 61041 17019 High Input Voltage Quad Output Controller ELECTRICAL CHARACTERISTICS continued Circuit of Figure 1 ViNLDO 12V VINA VINBC VDD Vcc VBYP VCSPA VCSNA 5V VIND 1 8V VSHDN Vona VONB Vonc VoND 5V IREF li pos louTD no load FREQ GND UP DN Vcc TA 0 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP GENERAL LOGIC LEVELS SHDN Input Logic Threshold Hysteresis 20mV SHDN 0 16V SHDN 17V 38V SHDN Input Bias Current 25 ON_ Input Logic Threshold Hysteresis 170mV ON_ Input Bias Current TA 25 C UP DN Input Logic Threshold UP DN Input Bias Current Ta 25 C High
48. tion Control The MAX17019 uses a light load pulse skipping operat ing mode for all switching regulators The switching regulators turn off the low side MOSFETs when the cur rent sense detects zero inductor current This keeps the inductor from discharging the output capacitors and forces the switching regulator to skip pulses under light load conditions to avoid overcharging the output Idle Mode Current Sense Threshold When pulse skipping mode is enabled the on time of the step down controller terminates when the output voltage exceeds the feedback threshold and when the current sense voltage exceeds the idle mode current sense threshold Under light load conditions the on time duration depends solely on the idle mode current sense threshold This forces the controller to source a minimum amount of power with each cycle To avoid overcharging the output another on time cannot begin until the output voltage drops below the feed back threshold Since the zero crossing comparator prevents the switching regulator from sinking current the MAX17019 switching regulators must skip pulses Therefore the controller regulates the valley of the out put ripple under light load conditions Automatic Pulse Skipping Crossover In skip mode an inherent automatic switchover to PFM takes place at light loads This switchover is affected by a comparator that truncates the low side switch on time at the inductor current s zero crossing The zero crossin
49. while simultaneously disabling the LDOS5 linear regulator This bootstraps the controller allowing power for the internal circuitry and external 5 loading to be generated by the output of a 5V switching regulator Bootstrapping reduces power dissipation due to driver and quiescent losses by providing power from a switch mode source rather than from a much less effi cient linear regulator The current capability increases from 50mA to 100mA when the LDOS5 output is switched over to BYP When BYP drops below the boot strap threshold the controller immediately disables the bootstrap switch and reenables the 5V LDO Reference REF The 1 25V reference is accurate to 196 over temperature and load making REF useful as a precision system refer ence Bypass REF to GND with a 0 1uF or greater ceram ic capacitor The reference sources up to 50uA and sinks 5pA to support external loads If highly accurate specifi cations are required for the main SMPS output voltages the reference should not be loaded Loading the refer ence slightly reduces the output voltage accuracy because of the reference load regulation error SMPS Detailed Description Fixed Frequency Current Mode PWM Controller The heart of each current mode PWM controller is a multi input open loop comparator that sums multiple signals the output voltage error signal with respect to the reference voltage the current sense signal and the slope compensation ramp Figure 3
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