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NATIONAL SEMICONDUCTOR ADC1173 Manual

1. 5 n 77 D 10089029 Differential Phase vs Temperature 0 6 0 5 0 4 25 o O 0 3 a CL Zz CQ 27 0 2 0 1 0 0 40 20 0 20 40 60 80 10089027 SFDR vs Temperature 80 60 40 20 0 40 20 0 20 40 TEMPERATURE 9C 60 80 10089035 Differential Gain vs Temperature 15 MHz fj 4 43 MHz TEMPERATURE C 10089026 SNR vs fin 0 2 4 6 8 INPUT FREQUENCY MHz 10089036 www national com ADC1173 Typical Performance Characteristics Continued THD vs fn SINAD vs f n 0 60 50 20 _ 40 a 40 30 lt a z bc o 20 60 10 80 0 0 2 4 6 8 0 2 4 6 8 INPUT FREQUENCY MHz INPUT FREQUENCY MHz 10089037 10089038 SFDR vs fn SNR vs SUPPLY VOLTAGE 80 80 60 60 m T N lt a 40 40 lt Z lt o E lt 20 20 0 0 0 2 4 6 8 2 70 2 85 3 00 3 15 3 30 INPUT FREQUENCY MHz SUPPLY VOLTAGE V 10089039 10089040 THD vs SUPPLY VOLTAGE SINAD vs SUPPLY VOLTAGE 0 20 g 7 40 lt I Z 2 60 80 2 70 2 85 3 00 3 15 3 30 2 70 2 85 3 00 3 15 3 30 SUPPLY VOLTAGE V SUPPLY VOLTAGE V 10089041 10089042 www national com 10 Typical Performance Characteristics Continued SFDR dB tgp ns SFDR vs SUPPLY VOLTAGE IDpp lApp vs TOTAL SUPPLY CURRENT mA 270 2 85 3 00 3 15 3 30 SUPPLY VOLTAGE V 10089043 Top
2. 0 2 DETAIL A TYP SCALE 20X 2 25 MAX TYP e EDEDEDEDIEDEDRIEDDDEL E Soh 0 05 0 1519 05 45 0 A 02 Ac SEE DETAIL A TYP LO 0 13 05 o 8 AQ W240 REV 24 Lead Package JM Ordering Number ADC1173CIJM NS Package Number M24D www national com 20 Physical DimensiOnsS inches millimeters unless otherwise noted Continued 1 8 0 1 24 13 4 7 72 A ee 4 40 1 JU UU UI U UU LU eese 41 1 m 3 0 65 PIN 1 IDENT LAND PATTERN RECOMENDATION 1 1 MAX 0 9 x DETAIL A 3 s 0 20 AAA Su 1 1 0 19 0 30 0 1 0 05 GAGE PLANE 0 25 22x SEATING PLANE DIMENSIONS ARE IN MILLIMETERS DETAIL A TYPICAL SCALE 20X MTC24 Rev D 24 Lead Package TC Ordering Number ADC1173CIMTC NS Package Number MTC24 LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant Support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used
3. DVpp DVss AVpp DVpp 3 Description Analog Input that is the high top side of the reference ladder of the ADC Nominal range is 1 0V to AVpp Voltage on and Vgg inputs define the Vin Conversion range Bypass well See Section 2 0 for more information Analog Input that is the low bottom side of the reference ladder of the ADC Nominal range is OV to 2 0V Voltage on and Vgg inputs define the Vin conversion range Bypass well See Section 2 0 for more information Reference Bottom Bias with internal pull down resistor Short to to self bias the reference ladder CMOS TTL compatible Digital input that when low enables the digital outputs of the ADC1173 When high the outputs are in a high impedance state CMOS TTL compatible digital clock Input Vi is sampled on the falling edge of CLK input Conversion data digital Output pins DO is the LSB D7 is the MSB Valid data is output just after the rising edge of the CLK input These pins are enabled by bringing the OE pin low Positive digital supply pin Connect to a clean quiet voltage source of 3V and DVpp should have a common source and be separately bypassed with a 10uF capacitor and a ceramic chip capacitor See Section 3 0 for more information www national com EZLLOGV ADC1173 Pin Descriptions and Equivalent Circuits Continued Pin No 2 24 14 15 18 20 21 www national com Symbol Equiva
4. March 2003 National Semiconductor 8 Bit 3 Volt 15 5 5 33mW A D Converter General Description Features The ADC1173 is a low power 15 MSPS analog to digital Internal Sample and Hold Function converter that digitizes signals to 8 bits while consuming just m Single 3V Operation 33 mW of power typ The ADC1173 uses a unique archi Internal Reference Bias Resistors tecture that achieves 7 6 Effective Bits Output formatting iS m Industry Standard Pinout straight binary coding m TRI STATE Outputs The excellent DC and AC characteristics of this device together with its low power consumption and 43V single Key Specifications supply operation make it ideally suited for many video imaging and communications applications including use in Resolution 5 Bils portable equipment Furthermore the ADC1173 is resistant 8 Maximum Sampling Frequency 15 MSPS min to latch up and the outputs are short circuit proof The top THD 54 dB typ and bottom of the ADC1173 s reference ladder is available DNL 0 85 LSB max for connections enabling a wide range of input possibilities ENOB at 3 58 MHz Input 7 6 Bits typ The ADC1173 is offered in SOIC EIAJ and TSSOP It is i Guaranteed No Missing Codes designed to operate over the commercial temperature range Differential Phase 0 5 Degree max of 40 C to 475 C m Differential Gain 1 596 typ m Power Consumption 33mW typ B excluding reference current Applications m Video Di
5. architecture to achieve 7 4 effective bits at and maintains superior dynamic perfor mance up to 1 2 the clock frequency The analog signal at Vi that is within the voltage range set by and Vgg are digitized to eight bits at up to 20 MSPS Input voltages below will cause the output word to consist of all zeroes Input voltages above Vg will cause the output word to consist of all ones Vpr has a range of 1 0 Volt to the analog supply voltage AVpp while has a range of 0 to 2 0 Volts should always be at least 1 0 Volt more positive than If and are connected together and Vag and are connected together the nominal values of and Vag 1 56V and 0 36V respectively If and are connected together and Vgg is grounded the nominal value of is 1 38V Data is acquired at the falling edge of the clock and the digital equivalent of the data is available at the digital outputs 2 5 clock cycles plus top later The ADC1173 will convert as long as the clock signal is present at pin 12 The Output Enable pin OE when low enables the output pins The digital outputs are in the high impedance state when the OE pin is high Applications Information 1 0 THE ANALOG INPUT The analog input of the ADC1173 is a switch followed by an integrator The input capacitance changes with the clock level appearing as 4 pF when the clock is low and 11 pF when the cloc
6. in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center Support Center Fax 49 0 180 530 85 86 Support Center Fax 81 3 5639 7507 Email new feedback nsc com Email europe support 9 nsc com Fax 465 6250 4466 Email jpn feedback 9 nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 Email ap support nsc com Tel 81 3 5639 7560 English Tel 44 0 870 24 0 2171 Tel 65 6254 4466 www national com Frangais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications 19149AUO2 MWEE 54511191 HOA 419 8 EZLLOGV
7. specifications apply for DVpp 3 0Vpc OE OV 2 0V Vag C 20 pF 15MHz at 50 duty cycle Boldface limits apply for T4 Tmn to Tmax all other limits T4 25 Notes 7 8 Typical Note 9 Symbol Parameter Conditions Limits Units 1 31 MHz SFDR Spurious Free Dynamic Range 3 58 MHz dB 7 5 MHz 1 31 MHz THD Total Harmonic Distortion 3 58 MHz dB fin 7 5 MHz Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2 All voltages are measured with respect to GND AVss DVss OV unless otherwise specified Note 3 When the input voltage at any pin exceeds the power supplies that is less than AVgs or DV gg or greater than AVpp or DVpp the current at that pin should be limited to 25 mA The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two Note 4 The absolute maximum junction temperatures T max for this device is 150 C The maximum allowable power dissipati
8. ENOB or EFFECTIVE BITS is another method of specifying Signal to Noise and Distortion Ratio or SINAD ENOB is defined as SINAD 1 76 6 02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits INTEGRAL NON LINEARITY INL is a measure of the deviation of each individual code from a line drawn from zero scale 12LSB below the first code transition through positive full scale Y2LSB above the last code transition The devia tion of any given code from this straight line is measured from the center of that code value The end point test method is used OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins www national com OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock PIPELINE DELAY LATENCY is the number of clock cycles between initiation of conversion and the availability of that conversion result at the output New data is available at every clock cycle but the data lags the conversion by the pipeline delay SAMPLING APERTURE DELAY is that time required after the fall of the clock input for the sampling switch to open The Sample Hold circuit effectively stops capturing the input sig nal and goes into the hold mode tps after the clock goes low SIGNAL TO NOISE RATIO SNR is the ratio of the rms value of the input signal to the rms value of the other spectr
9. VS Temperature N M ES TEMPERATURE 9C FREQUENCY Hz 10089025 10089032 10089028 www national com ADC1173 Specification Definitions ANALOG INPUT BANDWIDTH is a measure of the fre quency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input The test is performed with f n equal to 100 kHz plus integer multiples of The input frequency at which the output is 3 dB relative to the low frequency input signal is the full power bandwidth APERTURE JITTER is the time uncertainty of the sampling point tps or the range of variation in the sampling delay BOTTOM OFFSET is the difference between the input volt age that just causes the output code to transition to the first code and the negative reference voltage Bottom offset is defined as Egg Vag where Vz4 is the first code transition input voltage Note that this is different from the normal Zero Scale Error DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency recon structed sine wave at two different dc levels DIFFERENTIAL NON LINEARITY DNL is the measure of the maximum deviation from the ideal step size of 1 LSB DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave at two different dc levels EFFECTIVE NUMBER OF BITS
10. Vpp 3 0Vpc OV 2 0V Vag C 20 pF 15MHz at 50 duty cycle Boldface limits apply for Ty to Tmax all other limits 25 C Notes 7 8 Typical 28 T DC Accuracy 9 Video Accuracy DP Differential Phase Error 3 58 MHz sine wave 05 Degree DG Differential Gain Error 3 58 MHz sine wave 15 Analog Input and Reference V V min a 5 RT CLK LOW Cin Vin Input Capacitance Vin 1 5V 0 7Vrms NE GN NN pF Rin Input Resistance Rat Top Reference Resistor Q Q min Racer Reference Ladder Resistance to Vang O max Bottom Bottom Reference Resistor _ Hesistor Q mA Vat 7Vnrs lt 4 2 Reference Ladder Current V Reference Top Self Bias connected to Vara V min al Voltage connected to Vaga V max V Heference Bottom Self Bias connected to Vara Uus 0 32 V min RB Voltage connected to Vaga 0 40 www national com ADC1173 Converter Electrical Characteristics Continued The following specifications apply for DVpp 3 OE OV 2 0V Vag C 20 pF 15MHz at 50 duty cycle Boldface limits apply for T4 Tmn to Tmax all other limits T4 25 Notes 7 8 Typical Symbol Parameter Conditions Limits Note 9 connecte
11. al components below one half the sampling frequency not in cluding harmonics or dc SIGNAL TO NOISE PLUS DISTORTION S N D or SI NAD Is the ratio of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency including harmonics but excluding dc SPURIOUS FREE DYNAMIC RANGE SFDR is the differ ence expressed in dB between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input TOP OFFSET is the difference between the positive refer ence voltage and the input voltage that just causes the output code to transition to full scale and is defined as Where Vg is the full scale transition input volt age Note that this is different from the normal Full Scale Error TOTAL HARMONIC DISTORTION THD is the ratio of the rms total of the first six harmonic components to the rms value of the input signal Timing Diagram sample N 5 sample N 2 Sample N 4 Sample N 1 Sample N 5 CLK DBO 087 10089011 FIGURE 1 ADC1173 Timing Diagram Hi Z Hi Z To From Low To From High ADC1173 208 DO thru D7 OE 20 pF CLK Includes stray and distributed capacitance 10089012 FIGURE 2 ten tos Test Circuit 13 www national com EZLLOGV ADC1173 Functional Description The ADC1173 uses a new unique
12. and digital Even the generally accepted 90 degree crossing should be avoided as even a little coupling can cause problems at high frequen cies Best performance at high frequencies and at high resolution is obtained with a straight signal path Be especially careful with the layout of inductors Mutual inductance can change the characteristics of the circuit in which they are used Inductors should not be placed side by side not even with just a small part of their bodies being beside each other The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input Any external component e g a filter capacitor connected be tween the converter s input and ground should be connected to a very clean point in the analog ground return www national com ADC1173 Applications Information continued To Power Ground 10089016 FIGURE 6 Layout example showing separate analog and digital ground planes connected below the ADC1173 Figure 6 gives an example of a suitable layout All analog circuitry input amplifiers filters reference components etc should be placed on or over the analog ground plane All digital circuitry and I O lines should be placed over the digital ground plane 6 0 DYNAMIC PERFORMANCE The ADC1173 is ac tested and its dynamic performance is guaranteed To meet the published specifications the clock source driving the CLK input must be free of ji
13. d to 12 connected to Vass 7 VnBs Self Bias Voltage Delta connected to 138 connected to Vss 1 0 Power Supply Characteristics lApp Analog Supply Current DVpp 3 6V 68 mA 105 Digital Supply Current 3 6V 889 mA IAV IU Total Operating Current DVpp 3 6V CLK Low vs Note 10 Power Consumption DVpp 3 6V 41 CLK OE Digital Input Characteristics Logical High Input Voltage DVpp AVpp 3 6V 22 V min Vu Logical Low Input Voltage 3 6V 08 Vmax 5 Logic Input Capacitance 5 pF Digital Output Characteristics 2 7V lon 360pA 24 vmm DVpp 2 7V lop 1 1mA 21 19 Vmin DVpp 3 6V OE DVpp od TRI STATE Leakage Current VoL 20 UA Mes or AC Electrical Characteristics t Maximum Conversion Rate _ 29 38 Mm o 0 OupuDeay CLK high to low data vaid toot Output Dely CLK 24 Clock Meme fin 1 31 MHz 727 Effective Number of Bits fin 3 58 MHz 7 6 7 0 Bits min 1 31 MHz 49 SINAD Signal to Noise amp Distortion 3 58 MHz 47 7 dB min 1 31 MHz 49 SNR Signal to Noise Ratio 3 58 MHz 48 7 dB min www national com 6 Converter Electrical Characteristics Continued The following
14. driving the refer ence pins with a low impedance source By forcing a little current into or out of the top and bottom of the ladder as shown in Figure 4 the top and bottom refer ence voltages can be trimmed The resistive divider at the 15 amplifier inputs can be replaced with potentiometers The LMC662 amplifier shown was chosen for its low offset volt age and low cost Note that a negative power supply is needed for these amplifiers as their outputs may be required to go slightly negative to force the required reference voltages www national com ADC1173 Applications Information continued Ferrite Bead 000 t1 10 LM4040 2 5 ADC1173 NPP Fou IN 10089014 FIGURE 4 Better defining the ADC Reference Voltage Self bias is still used but the reference voltages are trimmed by providing a small trim current with the operational amplifiers Ferrite Bead 000 10 1000 to 95V LM4040 2 5 2N3904 0 01 ADC1173 IN 0 01 pF 1N4148 47 7 pem 2N3906 1 2 100 LMC662 3650 10089015 FIGURE 5 Driving the reference to force desired values requires driving with a low impedance source provided by the transistors Note that pins 16 and 22 are not connected www national com 16 Applications Information continued If reference voltages are desired that are mo
15. es this may increase the ladder current above the speci fied limit Toggling the clock twice at 1MHz or higher and returning it to the low state will eliminate the excess ladder current 17 An alternative power saving technique is to power up the ADC1173 with the clock active then halt the clock in the low state after two clock cycles Stopping the clock in the high state is not recommended as a power saving technique 5 0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals is essen tial to ensure accurate conversion Separate analog and digital ground planes that are connected beneath the ADC1173 are required to meet data sheet limits The analog and digital grounds may be in the same layer but should be separated from each other The analog and digital ground planes should never overlap each other Capacitive coupling between the typically noisy digital ground plane and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy The solution is to keep the analog circuity well separated from the digital circuitry and from the digital ground plane Digital circuits create substantial supply and ground tran sients The logic noise thus generated could have significant impact upon system noise performance The best logic fam ily to use in systems with A D converters is one which employs non saturating transistor designs or has low noise characteristics such as t
16. gitization m Digital Still Cameras Set Top Boxes Camcorders Personal Computer Video m Digital Television m CCD Imaging Electro Optics Pin Configuration OE 1 4 2 158 3 D1 4 02 5 05 6 18 ADC1173 04 7 18 05 8 D6 D7 MSB DVpp CLK 10089001 TRISTATE amp is a registered trademark of National Semiconductor Corporation 2003 National Semiconductor Corporation DS100890 www national com 19149AUO2 MWEE 54511191 HOA 419 8 EZLLOGV ADC1173 Ordering Information ADC1173CIJM SOIC EIAJ ADC1173CIJMX SOIC EIAJ tape amp reel ADC1173CIMTC TSSOP ADC1173CIMTCX TSSOP tape amp reel ADC1173EVAL Evaluation Board Block Diagram Disi AVpp DVpp pin 11 AVpp VRTS VRT ENCODER amp ERROR CORRECTION COARSE FINE COMPARATORS 17 8 OUTPUT DATA DRIVERS du OUT COARSE FINE ENCODER COMPARATORS E CORRECTION VRB VRBS CLOCK GEN AVss CLK Mec DVss pin 2 10089002 Pin T Description No 19 Analog signal input Conversion range is to Heference Top Bias with internal pull up resistor Short this to to self bias the reference ladder www national com 2 Pin Descriptions and Equivalent Circuits Continued Equivalent Circuit Pin No 17 23 22 12 3 thru O DEN lt 11 13 Symbol 1 CLK DO D7
17. he 74HC T and 74AC T Q families Worst noise generators are logic families that draw the larg est supply current transients during clock or signal edges like the 74F and the 74AC T families In general slower logic families such as 74LS and 74HC T will produce less high frequency noise than do high speed logic families such as the 74F and 74AC T families Since digital switching transients are composed largely of frequency components total ground plane copper weight will have little effect upon the logic generated noise This is because of the skin effect Total surface area is more important than is total ground plane volume An effective way to control ground noise is by connecting the analog and digital ground planes together beneath the ADC with a copper trace that is very narrow about 3 16 inch compared with the rest of the ground plane This narrowing beneath the converter provides a fairly high impedance to the high frequency components of the digital switching cur rents directing them away from the analog pins The rela tively lower frequency analog ground currents do not see a significant impedance across this narrow ground connection Generally analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the analog path In video high frequency systems however avoid crossing analog and digital lines altogether Clock lines should be isolated from ALL other lines analog
18. k is high Since a dynamic capacitance is more difficult to drive than a fixed capacitance choose an amplifier that can drive this type of load The LMH6702 LM6152 LM6154 LM6181 and LM6182 have been found to be ex cellent devices for driving the ADC1173 Do not drive the input beyond the supply rails www national com Figure 3 shows an example of an input circuit using the LM6181 This circuit has both gain and offset adjustments If you desire to eliminate these adjustments you should re duce the signal swing to avoid clipping at the ADC1173 output that can result from normal tolerances of all system components With no adjustments the nominal value for the amplifier feedback resistor is 5100 and the 5 1k resistor at the inverting input should be changed to 860Q and returned to 3V rather than to the Offset Adjust potentiometer Driving the analog input with input signals up to 2 8Vp p will result in normal behavior where voltages above Vpr will result in a code of FFh and input voltages below Vgg will result in an output code of zero Input signals above 2 8V p p may result in odd behavior where the output code is not FFh when the input exceeds 2 0 REFERENCE INPUTS The reference inputs Reference Top and Refer ence Bottom are the top and bottom of the reference ladder Input signals between these two voltages will be digitized to 8 bits External voltages applied to the reference input pins should be wi
19. lent Circuit DVss AVpp AVss Description The ground return for the digital supply AVsg and DVsgs should be connected together close to the ADC1173 Positive analog supply pin Connected to a clean quiet voltage source of 3 AVpp and DVpp should have a common source and be separately bypassed with a 10 capacitor and a 0 1 pF ceramic chip capacitor See Section 3 0 for more information The ground return for the analog supply AVss and DVss should be connected together close to the ADC1173 package Absolute Maximum Ratings note 1 Operating RatingsS otes 1 2 If Military Aerospace specified devices are required Temperature Range 40 C TA lt 75 please contact the National Semiconductor Sales Office Distributors for availability and specifications AVpp DVpp 2 7V to 3 6V IAVss DV gol OV to 100 mV AV pp DVpg 6 5V l 1 0V to Voltage on Any Pin 0 3V to 6 5V An AU ie to 2 0V pua ape HE 1 0V to 2 8V CLK OE Voltage 0 5 to AVpp 0 5V 22 Vin Voltage Range to Digital Output Voltage DVas to DVpp Input Current Note 3 25mA Package Input Current Note 3 50mA Package Dissipation at 25 C Note 4 ESD Susceptibility Note 5 Human Body Model 2000V Machine Model 200V Soldering Temp Infrared 10 sec Note 6 300 C Storage Temperature 65 C to 150 C Converter Electrical Characteristics The following specifications apply for D
20. n degrading dynamic performance Buffering the digital data outputs with 74ACQ541 for example may be necessary if the data bus to be driven is heavily loaded Dynamic performance can also be improved by adding 470 series resistors at each digital output reducing the energy coupled back into the converter output pins Using an inadequate amplifier to drive the analog input As explained in Section 1 0 the capacitance seen at the input alternates between 4 pF and 11 pF with the clock This dynamic capacitance is more difficult to drive than is a fixed capacitance and should be considered when choosing a driving device The LMH6702 LM6152 LM6154 LM6181 and LM6182 have been found to be excellent devices for driving the ADC1173 analog input Driving the pin or the pin with devices that can not source or sink the current required by the ladder As mentioned in section 2 0 care should be taken to see that any driving devices can source sufficient current into the Vay and sink sufficient current from the pin If these pins are not driven with devices than can handle the required current these reference pins will not be stable resulting in a reduction of dynamic performance Using a clock source with excessive jitter using an excessively long clock signal trace or having other signals coupled to the clock signal trace This will cause the sampling interval to vary causing excessive output noise and a red
21. nput goes above Vpp or below GND by more than 50 mV As an example if AVpp is 2 7Vpc the full scale input voltage must be lt 2 75Vpc to ensure accurate conversions TO INTERNAL CIRCUITRY 10089010 Note 8 To guarantee accuracy it is required that AVpp and DVpp be well bypassed Each supply pin must be decoupled with separate bypass capacitors Note 9 Typical figures are at Tj 25 C and represent most likely parametric norms Test limits are guaranteed to Nationals AOQL Average Outgoing Quality Level Note 10 At least two clock cycles must be presented to the ADC1173 after power up See Section 4 0 for details 7 www national com EZLLOGV ADC1173 Typical Performance Characteristics INL LSB SNR LSB THD dB INL vs Temperature TEMPERATURE C 10089020 SNR vs Temperature 60 50 O 40 20 0 20 40 60 80 TEMPERATURE C 10089022 THD vs Temperature 60 TEMPERATURE C 10089023 www national com DNL LSB SINAD dB DNL vs Temperature TEMPERATURE C 10089021 SNR vs fin fs 15 MSPS 10089033 SINAD vs Temperature IR e CA e e 0 40 20 0 20 40 60 80 TEMPERATURE 9C 10089034 Typical Performance Characteristics continued SINAD vs fin _ ft NS S 2 _____ __ e __ E x Z T T 10089031
22. on is dictated by T jmax the junction to ambient thermal resistance and the ambient temperature Ta and can be calculated using the formula T max TA 0j4 In the 24 pin TSSOP is 92 C W so PpMAX 1 358 mW at 25 C and 815 mW at the maximum operating ambient temperature of 75 C Typical thermal resistance of this part is 98 C W for the EIAJ SOIC Note that the power dissipation of this device under normal operation will typically be about 49 mW 33 mW quiescent power 13 mW reference ladder power 3 mW due to 1 TTL loan on each digital output The values for maximum power dissipation listed above will be reached only when the ADC 1173 is operated in a severe fault condition e g when input or output pins are driven beyond the power supply voltages or the power supply polarity is reversed Obviously such conditions should always be avoided Note 5 Human body model is 100 pF capacitor discharged through a 1 5kQ resistor Machine model is 220 pf discharged through ZERO Note 6 See 450 Surface Mounting Methods and Their Effect on Product Reliability or the section entitled Surface Mount found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices Note 7 The analog inputs are protected as shown below Input voltage magnitudes up to 6 5V or to 500 mV below GND will not damage this device However errors the A D conversion can occur if the i
23. pacitor close to the analog supply pin Avoid inductive components in the analog supply line The converter digital supply should not be the supply that is used for other digital circuitry on the board It should be the same supply used for the A D analog supply As is the case with all high speed converters the ADC1173 should be assumed to have little power supply rejection especially when self biasing is used by connecting and together No pin should ever have a voltage on it that is in excess of the supply voltages or below ground not even on a transient basis This can be a problem upon application of power to a circuit Be sure that the supplies to circuits driving the CLK OE analog input and reference pins do not come up any faster than does the voltage at the ADC1173 power pins 4 0 THE ADC1173 CLOCK Although the ADC1173 is tested and its performance is guaranteed with a 15MHz clock it typically will function with clock frequencies from 1MHz to 20MHz If continuous conversions are not required power consump tion can be reduced somewhat by stopping the clock at a logic low when the 1173 is not being used This reduces the current drain in the ADC1173 s digital circuitry from a typical value of 2 3mA to about 100 Note that powering up the ADC1173 with the clock stopped may not save power as it will result in an increased current flow by as much as 170 in the reference ladder In some cas
24. re than a few tens of millivolts from the self bias values the circuit of Figure 5 will allow forcing the reference voltages to whatever levels are desired This circuit provides the best performance because of the low source impedance of the transistors Note that the and Vggg pins are left floating can be anywhere between Vgg 1 0V and the analog supply voltage and can be anywhere between ground and 1 0V below Vpr To minimize noise effects and ensure accurate conversions the total reference voltage range Var should be a minimum of 1 0V and a maximum of about Best performance can be realized with 1 56 and 0 36 3 0 POWER SUPPLY CONSIDERATIONS Many A D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed A 1OpF tantalum or aluminum electrolytic capacitor should be placed within an of inch 2 5 centimeters of the A D power pins with a 0 1 pF ceramic chip capacitor placed as close as possible to the converter s power supply pins Lead less chip capacitors are preferred because they have low lead inductance While a single voltage source should be used for the analog and digital supplies of the ADC1173 these supply pins should be well isolated from each other to prevent any digital noise from being coupled to the analog power pins A 47 Ohm resistor is recommend between the analog and digital supply lines with a ceramic ca
25. thin the range specified in the Operating Ratings table 1 0V to AVpp for and to AVpp 1 0V for Vaz Any device used to drive the reference pins should be able to source sufficient current into the pin and sink sufficient current from the The reference ladder can be self biased by connecting to and connecting Vag to to provide top and bottom reference voltages of approximately 1 56V and 0 36V respectively with 3 0V This connection is shown in Figure 3 If Va and are tied together but Va is tied to analog ground a top reference voltage of approxi mately 1 38V is generated The top and bottom of the ladder should be bypassed with 10pF tantalum capacitors located close to the reference pins Applications Information continued 3V 5 12V un es Q Ferrite Bead 10 wFyyt 10 uF 0 1 uF 5VO Signal 240 Input 47 pF 100 47 I 12 1 567 1g nominal 10 uF 10V ADC1173 0 36V 93 nominal 10 uF 10V 10089013 FIGURE 3 Simple Low Component Count Self Bias Reference application Because of resistor tolerances the reference voltages can vary by as much as 6 Choose an amplifier that can drive a dynamic capacitance see text EZLLOGV The reference self bias circuit of Figure 3 is very simple and performance is adequate for many applications Superior performance can generally be achieved by
26. tter For best ac performance isolating the ADC clock from any digital circuitry should be done with adequate buffers as with a clock tree See Figure 7 to ADC CLK input CRYSTAL OSC to other circuit clock inputs 10089017 FIGURE 7 Isolating the ADC clock from Digital Circuitry It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals Other signals can introduce jitter into the clock signal www national com 7 0 COMMON APPLICATION PITFALLS Driving the inputs analog or digital beyond the power supply rails For proper operation all inputs should not go more than 50mV below the ground pins or 50mV above the supply pins Exceeding these limits on even a transient basis can cause faulty or erratic operation It is not uncommon for high speed digital circuits e g 74F and 74AC devices to exhibit undershoot that goes more than a volt below ground A resistor of 50Q in series with the offending digital input will usually eliminate the problem Care should be taken not to overdrive the inputs of the ADC1173 Such practice may lead to conversion inaccura cies and even to device damage Attempting to drive a high capacitance digital data bus The more capacitance the output drivers must charge for each conversion the more instantaneous digital current is required from and These large charging cur rent spikes can couple into the analog sectio
27. uction in SNR performance Simple gates with RC timing is generally inadequate as a clock source Input test signal contains harmonic distortion that inter feres with the measurement of dynamic signal to noise ratio Harmonic and other interfering signals can be re moved by inserting a filter at the signal input Suitable filters are shown in Figure 8 and Figure 9 The circuit of Figure 8 has cutoff of about 5 5 MHz and is suitable for input frequen cies of 1 MHz to 5 MHz The circuit of Figure 9 has a cutoff of about 11 MHz and is suitable for input frequencies of 5 MHz to 10 MHz These filters should be driven by a genera tor of 75 Ohm source impedance and terminated with a 75 ohm resistor Applications Information Continued 150 pF 150 pF 22 pF Input Output 750 220 pF 560 pF 560 pF 220 pF 10089018 FIGURE 8 5 5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input 15 pF 15 pF 4 7 pF Input Output 150 oF 270 oF 270 oF 150 pF 10089019 FIGURE 9 11 MHz Low Pass filter to eliminate harmonics at the signal input Use at input frequencies of 5 MHz to 10 MHz 19 www national com EZLLOGV ADC1173 Physical Dimensions inches millimeters unless otherwise noted denne a 9 27 TYP 24 15 0 713 1 27 LAND PATTERN RECOMMENDATION 154 gy 1425 GAGE js 0 8 B AY PIN 1 IDENT SEATING PLANE 0 25 0 5

NATIONAL SEMICONDUCTOR ADC1173 Manual

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