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NATIONAL SEMICONDUCTOR ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX Sample/Hold handbook

1. cus O chs cHe 1 A oINt 7 2 A DIN2 DGND AGND COPS microcontrollers HPC and MICROWIRE are trademarks of National Semicond Microsoft is a trademark of Microsoft Corporation 2001 National Semiconductor Corporation 0 011830 June 1999 Features m OV to 3 3V analog input range with single 3 3V power supply Serial MICROWIRE and SPI Compatible 2 4 or 8 channel differential or single ended multiplexer Analog input sample hold function Power down mode Variable resolution and conversion rate Programmable acquisition time Variable digital output word length and format No zero or full scale adjustment required Fully tested and guaranteed with a 2 5V reference No Missing Codes over temperature Key Specifications pjoH ejduies pue XAIN UHM s4elleAuoD Q v leas ubis snld A8 8 8801zH9QdV 801z1H9QV Z801z19QV 0801zH9QV m Resolution 12 bit plus sign m 12 bit plus sign conversion time 8 8 us min m 12 bit plus sign sampling rate 73 kHz max m ntegral linearity error 1 LSB max m Single supply 3 3V 10 m Power dissipation 15 mW max m Power down 40 uW typ Applications m Portable Medical instruments m Portable computing m Portable Test equipment DS011830 1 uctor Corporation www national com Ordering Information Industrial Temperature Range 40 C
2. ERR SKN TORRE DOR ix L 1 DS011830 27 17 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Timing Diagrams continued ADC12L038 Conversion with CS Continuously Low and 8 Bit Digital Output Format CCLK SCLK XG HHIH mx pt TT rr DOR EOC L DS011830 28 ADC12L038 Conversion with CS Continuously Low and 16 Bit Digital Output Format tc CCLK SCLK CONV DO DOR EOC DS011830 29 www national com 18 Timing Diagrams continued CCLK SCLK CONV DO Power Down ADC12L038 Software Power Up Down Using CS with 16 Bit Digital Output Format tspu or Power Up m AAA AV AU Ede fle Lu OEE AAA Lo Fi DB0 KKM DS011830 30 ADC12L038 Software Power Up Down with cs Continuously Low and 16 Bit Digital Output Format CCLK SCLK CONV DO XXX 118 HUH AAA 5009009000202222 Power Down tspU or Power Up KAKA DBO DS011830 31 19 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Timing Diagrams continued ADC12L038 Hardware Power Up Down Power Up Power Down tupu PD CCLK SCLK EOC DS011830 32 Note Hardware power up
3. 10 CCLK No Change Cycles Acquisition Time 18 CCLK No Change Cycles Acquisition Time 34 CCLK No Change Cycles Test Mode No Change CH1 CH7 become Active Outputs X Don t Care Note 22 The A D powers up with no Auto Cal no Auto Zero 10 CCLK acquisition time 12 bit sign conversion power up 12 or 13 bit MSB first and user mode See Tables TABLE 6 Conversion Read Data Only Mode Programming 23 www national com 8E0 Ic LOQV T 0 1c LOGV ZE0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Tables Continued TABLE 6 S Data Only Mode Programming Continued Read Only Previous DO Format No Conversion H X 1 we X Don t Care TABLE 7 Status Register ow DBO DB4 DB6 DB7 DB8 Location 8 or 9 16 or 17 Justification Test Mode Device Status DO Output Format Status High High High indicates indicates a Power an Auto Cal Sequence Sequence Sequence High indicates an 8 or 9 bit format High indicates a 12 or 13 bit format High indicates a 16 or 17 bit format High indicates that the sign bit is included When High When the conversion High result will be the output MSB device is first When in test indicates a Power Up Down is in is in is in progress progress progress Application Hints 1 0 DIGITAL INTERFACE 1 1 Interface Concepts The example in Figure 7 shows a typ
4. Note 11 Tested limits are guaranteed to National s AOQL Average Outgoing Quality Level Note 12 Positive integral linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and zero For negative integral linearity error the straight line passes through negative full scale and zero see Figure 2 and Figure 3 Note 13 Zero error is a measure of the deviation from the mid scale voltage a code of zero expressed in LSB It is the worst case value of the code transitions between 1 to 0 and 0 to 1 see Figure 4 Note 14 Total unadjusted error includes offset full scale linearity and multiplexer errors Note 15 The DC common mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together Note 16 Channel leakage current is measured after the channel selection Note 17 Timing specifications are tested at the TTL logic levels VIL 0 4V for a falling edge and VIH 2 4V for a rising edge TRI STATE output voltage is forced to 1 4V Note 18 The ADC12L030 family s self calibration technique ensures linearity and offset errors as specified but noise inherent in the self calibration process will result in a maximum repeatability uncertainty of 0 2 LSB Note 19 If SCLK and CCLK are driven from the same clock source then ta is 6 10 18 or 34 clock periods minimum and maximum Note 20
5. Where fc is the conversion clock CCLK frequency in MHz and Rg is the external source resistance in kO As an ex ample operating with a resolution of 12 Bits sign a 5 MHz clock frequency and maximum acquistion time of 34 conver sion clock periods the ADC s analog inputs can handle a source impedance as high as 6 The acquisition time may www national com 30 also be extended to compensate for the settling or response time of external circuitry connected between the MUXOUT and A DIN pins The acquisition time t4 is started by a falling edge of SCLK and ended by a rising edge of CCLK see Timing Diagrams If SCLK and CCLK are asynchronous one extra CCLK clock period may be inserted into the programmed acquisition time for synchronization Therefore with asnychronous SCLK and CCLK the acquisition time will change from conversion to conversion 7 0 INPUT BYPASS CAPACITANCE External capacitors 0 01 uF 0 1 pF can be connected between the analog input pins 7 and analog ground to filter any noise caused by inductive pickup asso ciated with long input leads These capacitors will not de grade the conversion accuracy 8 0 NOISE The leads to each of the analog multiplexer input pins should be kept as short as possible This will minimize input noise and clock frequency coupling that can cause conversion errors Input filtering can be used to reduce the effects of the noise sources 9 0 POWER SUPPLIES No
6. 69 9508 6208 Fax 65 2504466 Email support nsc com English Tel 44 0 870 24 0 2171 Email ap support nsc com www national com Fran ais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
7. 0 1100 1100 1101 2 500V 2 499V 2 500V 1 1111 1111 1111 2 500V 2 500V 1 0000 0000 0000 5 0 INPUT CURRENT At the start of the acquisition window t4 a charging current flows into or out of the analog input pins A DIN1 and A DIN2 depending on the input voltage polarity The analog input pins are CHO CH7 and COM when A DIN1 is tied to MUXOUT1 and A DIN2 is tied to MUXOUT2 The peak value of this input current will depend on the actual input voltage applied the source impedance and the internal multiplexer switch on resistance With MUXOUT1 tied to A DIN1 and MUXOUT2 tied to A DIN2 the internal multiplexer switch on resistance is typically 1 6 kQ The A DIN1 and A DIN2 mux on resistance is typically 750Q 6 0 INPUT SOURCE RESISTANCE For low impedance voltage sources lt 600Q the input charging current will decay before the end of the S H s acquisition time of 2 us 10 CCLK periods with fc 5 MHz to a value that will not introduce any conversion errors For high source impedances the S H s acquisition time can be increased to 18 or 34 CCLK periods For less ADC resolution and or slower CCLK frequencies the S H s acquisition time may be decreased to 6 CCLK periods To determine the number of clock periods N required for the acquisition time with a specific source impedance for the various resolutions the following equations can be used 12 Bit Sign Nc Rs 2 3 x fe x 0 824 8 Bit Sign Nc Rs 2 3 x fe x 0 57
8. 1c L OQV c 0 1c LOGV 0E0 Tc LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 AC Electrical Characteristics continued Thermal Part Number Resistance Note 5 The human body model is a 100 pF capacitor discharged through 1 5 kQ resistor into each pin Note 6 See AN450 Surface Mounting Methods and Their Effect on Product Reliability or the section titled Surface Mount found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices Note 7 Two on chip diodes are tied to each analog input through a series resistor as shown below Input voltage magnitude up to 5V above VA or 5V below GND will not damage this device However errors in the A D conversion can occur if these diodes are forward biased by more than 50 mV if the input voltage magnitude of selected or unselected analog input go above VA or below GND by more than 50 mV As an example if Va is 3 0 Vpc full scale input voltage must be lt 3 05 Vpc to ensure accurate conversions ANALOG TO INTERNAL INPUTS CIRCUITRY GND DS011830 6 Note 8 To guarantee accuracy it is required that the VA and Vp be connected together to the same power supply with separate bypass capacitors at each V pin Note 9 With the test condition for VREF VREF VREF given as 2 500V the 12 bit LSB is 610 uV and the 8 bit LSB is 9 8 mV Note 10 Typicals are at Ty TA 25 C and represent most likely parametric norm
9. 250 fully differential input with fixed 1 250V common mode voltage and 10 acquisition time unless otherwise specified Boldface limits apply for T4 Twin to Tmax all other limits T4 T 25 C Notes 7 8 9 Symbol Parameter Conditions Typical Limits Units Note 10 Note 11 Limits STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes Bis mim E H LSB maw LSB max ONL Differential Nor Linearity Tisma 2 LSB ma LSB max Offset Error After Auto Cal Notes 5 18 1 2 2 LSB O wawata LSB max TUE Total Unadjusted Error After Auto Cal 1 LSB CTS mwema L Resolution with No Missing Codes 851 5010 Bis min INL Positive Integral Linearity Error amp bit sign mode Note 12 LSB max INL Negative Integral Linearity Eror amp bit sign mode 612 LSB max DNL Differential Non Linearty Sbir sgnmoe m LSB mao Positive Ful Scale Eror 851 sign mode Note 12 LSB maw Negative Ful Scale Eror 851 sign mode Note 12 158 max Offset Error 8 bit sign mode after Auto Zero Note 13 1 2 LSB Vin VIN 1 250V www national com SEO Ic LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Converter Electrical Characteristics Continued The following specifications a
10. Respond to the program prompts It is recommended that the first instruction issued to the ADC12L038 be Auto Cal see Section 1 1 www national com 32 Application Hints continued variables DOL Data Out word length DI Data string for A D DI input DO A D result string SET CS HIGH OUT amp H3FC amp H2 OR INP amp HSFC OUT amp H3FC amp HFE AND INP amp H3FC OUT amp H3FC amp HFD AND INP amp HSFC OUT amp amp HEF AND INP amp HSFC 10 set RIS HIGH SET DTR LOW SET RTS LOW set B4 low LINE INPUT DI data for ADC12038 see Mode Table on data sheet DI INPUT ADC12038 output word length 8 9 12 15 16 or 17 DOL 20 SET CS HIGH OUT amp HSFC amp H2 OR INP amp HSFC OUT amp H3FC amp HFE AND INP amp HSFC OUT amp HSFC amp HFD AND INP amp HSFC SET CS LOW OUT amp H3FC amp H2 OR INP amp HSFC OUT amp H3FC amp 1 OR INP amp HSFC OUT amp amp HFD AND INP amp HSFC DO OUT amp H3FC amp 1 OR INP amp H3FC OUT amp H3FC amp HFD AND INP amp FOR N 1 TO 8 Temp MID DI N 1 IF Temp 0 THEN OUT amp amp 1 OR INP amp HSFC ELSE OUT amp HSFC amp HFE AND INP amp HSFC END IF out DI OUT amp amp 2 OR INP amp H3FC IF INP amp H3FE AND 16 16 THEN DO DO 0 ELSE DO DO 1 END IF OUT amp H3FC amp Hl OR INP amp H3FC OUT
11. The 12 Bit Conversion of Offset and 12 Bit Conversion of Full Scale modes are intended to test the functionality of the device Therefore the output data from these modes are not an indication of the accuracy of a conversion result www national com 10 AC Electrical Characteristics continued 0 1111 1111 1111 4095 0 1111 1111 1110 4094 POSITIVE 24 FULL SCALE TRANSITION P d I Pd r z P Vine gt ViN 0 0000 0000 0010 2 lt ZERO TRANSITION 0 0000 0000 0001 1 0 0000 0000 0000 0 VREF Vin gt Vine 1 1111 1111 1111 1 1 1111 1111 1110 2 VREF Veep YREF VREF T Vin Vine 7 GND lt Vy lt Vat GND lt lt Vat OUTPUT CODE TWO S COMPLEMENT 1 0000 0000 0001 4095 1 0000 0000 0000 4096 NEGATIVE FULL SCALE TRANSITION ANALOG INPUT VOLTAGE 0 011830 7 FIGURE 1 Transfer Characteristic 1215 POSITIVE INTEGRAL LINEARITY 815 ERROR de POSITIVE FULL SCALE ERROR E OFFSET ERROR 4096 4095 NEGATIVE E FULL SCALE ERROR NEGATIVE Ms INTEGRAL 8 LSB LINEARITY x ERROR 12LSB u OUTPUT CODE from 4096 to 4095 DS011830 8 FIGURE 2 Simplified Error Curve vs Output Code without Auto Calibration or Auto Zero Cycles 11 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 AC Electrical Characteristics c
12. amp H3FC amp HFD AND INP amp HSFC NEXT N IF DOL gt 8 THEN FOR N 9 TO DOL OUT amp amp 1 OR INP amp HSFC OUT amp H3FC amp HFD AND INP amp HSFC OUT amp H3FC amp H2 OR INP amp HSFC IF INP amp H3FE AND amp H16 H16 THEN DO DO 0 ELSE 1 END IF NEXT N END IF OUT amp H3FC amp HFA AND INP amp H3FC FOR N 1 TO 500 NEXT N PRINT DO set RTS HIGH SET DTR LOW SET RTS LOW set RTS HIGH SET DTR HIGH SET RTS LOW reset DO variable SET DTR HIGH SCLK low SCLK high Input DO SET DTR HIGH SCLK low SET DTR HIGH SCLK low SCLK high SCLK low and DI high INPUT Enter C to convert else RETURN to alter DI data s IF s z C OR s c THEN GOTO 20 ELSE GOTO 10 END IF END 33 0 011830 63 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Physical Dimensions inches millimeters unless otherwise noted 0 3977 0 4133 10 10 10 50 LEAD NO 1 IDENTIFICATION 7 4 7 6 0 3940 0 4190 10 00 10 65 0 050 0 0138 0 0200 0 010 0 010 0 029 0 0926 0 1043 SS 0 25 0 75 2 55 2 65 0 0040 0 0118 0 0091 0 0125 TYP ALL LEADS spp 0 1 B MAX TYP ALL LEAD TIPS ALL LEADS 0 0160 0 0500 TYP ALL LEADS 0 40 1 27 M16B REV F Order Number ADC12L030CIWM NS Package Number M16B 0 496 0 5
13. can be modified by the data shifted in on the DO pin Table 5 details the data required This is the data output ready pin This pin is an active push pull output It is low when the con version result is being shifted out and goes high to signal that all the data has been shifted out A logic low is required on this pin to program any mode or change the ADC s configuration as listed in the Mode Programming Table Table 5 such as 12 bit conversion 8 bit con version Auto Cal Auto Zero etc When this pin is high the ADC is placed in the read data only mode While in the read data only mode bring ing CS low and pulsing SCLK will only clock out on DO any data stored in the ADCs output shift register The data on DI will be neglected A new conversion will not be started and the ADC will remain in the mode and or configura tion previously programmed Read data only cannot be performed while a conversion Auto Cal or Auto Zero are in progress This is the power down pin When PD is high the A D is powered down when PD is low the A D is powered up The A D takes a maximum of 700 us to power up after the command is given These are the analog inputs of the MUX A channel input is selected by the address infor mation at the DI pin which is loaded on the rising edge of SCLK into the address register see Tables 2 3 4 The voltage applied to these inputs should not exceed V or go below GND Exceeding this range on an unsele
14. lt T lt 85 C NS Package Number ADC12L030 ADC12L032 ADC12L034 ADC12L038 Connection Diagrams uM 24 Pin Wide Body 16 Pin Wide Body SO Packages SO Packages 1 Vp CHO Vp CH1 2 DOR CH1 CCLK CH2 3 CCLK COM SCLK CH3 4 SCLK 5 DI DOR 1 DI ADC12L030 MUXOUT1 6 1 DO EOC 1 DO ADC12L034 E A DIN1 7 1 CS MUXOUT2 48 CONV VREF A DIN2 9 EOC DGND V VREF Ep DS011830 2 VREF AGND Top View DGND VA DS011830 4 20 Pin Wide Body Top View SO Packages 248 Pin Wide Body Vp SO Packages CH1 2 CCLK COM 53 SCLK CHO 41 Vp MUXOUT1 4 DI cH1 42 DOR A DIN1 5 1 DO CH2 3 CCLK ADC12L032 MUXOUT2 6 1 CS CH3 44 SCLK A DIN2 47 CONV CH4 4 5 DI CH5 6 DO VREF 8 EOC a CH6 7 2 CS Weert 1 9 DOR ADC12L038 10 Vat CH7 5 2 CONV 9 EOC MUXOUT1 PD Top View A DIN1 AGND MUXOUT2 VREF DGND Vat DS011830 5 Top View www national com 2 Pin Descriptions CCLK SCLK DI DO EOC The clock applied to this input controls the sucessive approximation conversion time in terval and the acquisition time The rise and fall times of the clock edges should not exceed 1 us This is the serial data clock input The clock applied to this input controls the rate at which the serial data exchange occurs The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register This a
15. necessary to do an auto zero cycle whenever the ambient temperature or the power supply voltage change significantly See the curves titled Zero Error Change vs Ambient Temperature and Zero Error Change vs Supply Voltage in the Typical Perfor mance Characteristics 14 0 DYNAMIC PERFORMANCE Many applications require the A D converter to digitize AC signals but the standard DC integral and differential nonlin earity specifications will not accurately predict the A D con verter s performance with AC input signals The important specifications for AC applications reflect the converter s abil ity to digitize AC signals without significant spectral errors and without adding noise to the digitized signal Dynamic characteristics such as signal to noise S N signal to noise distortion ratio S N D effective bits full power band width aperture time and aperture jitter are quantitative mea sures of the A D converter s capability 31 An A D converter s AC performance can be measured using Fast Fourier Transform FFT methods A sinusoidal wave form is applied to the A D converter s input and the trans form is then performed on the digitized waveform S N D and S N are calculated from the resulting FFT data and a spectral plot may also be obtained The A D converters noise and distortion levels will change with the frequency of the input signal with more distortion and noise occurring at higher signal frequencie
16. the negative input for the different versions of ADCs Number of DO Format SCLKs Expected 8 Bit MSB or LSB First SIGNOFF 8 senon o _ 12 Bit MSB or LSB First Where X can be a logic high H or low L 16 Bit MSB or LSB first 1 5 Power Up Down The ADC may be powered down at any time by taking the PD pin HIGH or by the instruction input on DI see Tables 5 If erroneous SCLK pulses desynchronize the communica 6 and the Power Up Down timing diagrams When the ADC tions the simplest way to recover is by cycling the power is powered down in this way the circuitry necessary for an supply to the device Not being able to easily resynchronize A D conversion is deactivated The circuitry necessary for the device is a shortcoming of leaving CS low continuously digital I O is kept active Hardware power up down is con The number of clock pulses required for an I O exchange trolled by the state of the PD pin Software power up down is may be different for the case when CS is left low continu controlled by the instruction issued to the ADC If a software ously vs the case when CS is cycled Take the I O sequence power up instruction is issued to the ADC while a hardware power down is in effect PD pin high the device will remain in the power down state If a software power down instruc 25 www national com SEO Ic LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Application Hints co
17. 0 015 Order Number ADC12L038CIWM NS Package Number M28B M28B REV A 35 www national com 8 0 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV Notes A D Converters with MUX and Sample Hold LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user ADC12L030 ADC12L032 ADC12L034 ADC12L038 3 3V Self Calibrating 12 Bit Plus Sign Serial I O National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 180 530 85 86 Response Group Tel 81 3 5639 7560 Tel 1 800 272 9959 Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Fax 1 800 737 7018 Deutsch Tel 49 0
18. 12 12 598 13 005 20 19 18 17 16 15 14 13 12 1 0 394 0 419 10 008 10 643 30 TYP LEAD NO 1 1 IDENT Y 1 2 3 4 5 6 7 8 9 10 0 010 MAX 0 254 0 291 0 299 7 391 7 585 0 010 0 029 20 093 0 104 0 254 0 737 9 2 362 2 642 0 004 0 012 ALL LEADS 0 102 0 305 Y SEATING ut n A PLANE 004 0 009 0 013 a 2060 050 0 050 0 014 0 020 0 229 0 330 ALL LEAD TIPS 0 406 1 270 1270 0 356 0 508 TYP ALL LEADS TYP ALL LEADS TYP U 008 TYP 0 203 M20B REV P Order Number ADC12L032CIWM NS Package Number M20B www national com 34 Physical Dimensions inches millimeters unless otherwise noted Continued LEAD NO 1 IDENTIFICATION 1 0 050 0 0200 0 0138 0 010 22 0 508 TYP 0 1043 aola 0 029 0 0926 iso 0 010 0 32 ALL LEADS 2 65 0 0118 0 75 0 23 2 35 0 0040 0 25 SEATING gt PLANE EE 8 MAX TYP 0 0500 ALL LEADS 0 014 ALL LEAD TIPS 0 35 0 0160 TYP ALL LEADS 0 40 M24B REV F Order Number ADC12L034CIWM NS Package Number M24B 0 300 7 60 0 291 7 40 0 420 10 65 0 393 10 00 0 030 0 75 0 009 0 25 0 713 18 10 0 696 17 70 0 013 0 32 0025 0 105 2 65 0 092 2 35 8 0 012 0 30 0 003 0 10 0 050 1 27 0 020 0 49 BSC 0 013 0 35 0 050 1 27 0 40
19. 4C335 has an internal DC DC converter that generates the necessary TIA EIA 232 E output levels from a 3 3V supply There are four 0 47 uF capacitors required for the DC DC converter that are not shown in the above schematic The assignment of the RS232 port is shown below Output Address arc x X X X A sample program written in Microsoft QuickBasic is shown on the next page The program prompts for data mode select instruction to be sent to the A D This can be found from the Mode Programming table shown earlier The data should be entered in 1 s and 0 s as shown in the table with DI0 first Next the program prompts for the number of SCLKs required for the programmed mode select instruction For instance to send all 0 lt to the A D selects CHO as the input CH1 as the input 12 bit conversion and 13 bit MSB first data output format if the sign bit was not turned off by a previous instruction This would require 13 SCLK periods since the output data format is 13 bits The part powers up with No Auto Cal No Auto Zero 10 CCLK Acquisition Time 12 bit conversion data out with sign 12 or 13 bit MSB First power up and user mode Auto Cal Auto Zero Power UP and Power Down instructions do not change these default settings The following power up sequence should be fol lowed 1 Run the program 2 Prior to responding to the prompt apply the power to the ADC12L038 3
20. 8 8 Single Ended Channels with COM as Zero Reference DS011830 39 FIGURE 9 CH0 CH2 CH4 and CH6 can be assigned to the MUX OUT1 pin in the differential configuration while CH1 CH3 CH5 CH7 can be assigned to the MUXOUT2 pin In the differential configuration the analog inputs are paired as follows CH0 with CH1 CH2 with CH3 CH4 with CH5 and CH6 with CH7 The A DIN1 and A DIN2 pins can be as signed positive or negative polarity With the single ended multiplexer configuration CH0 through CH7 can be assigned to the MUXOUT1 pin The COM pin is always assigned to the MUXOUT2 pin A DIN1 is assigned as the positive input A DIN2 is assigned as the negative input See Figure 10 The Multiplexer assignment tables for the ADC12L030 2 4 8 Tables 2 3 4 summarize the aforementioned functions for the different versions of A Ds Application Hints continued Differential Configuration CH4 MUX OUT1 CHS MUX OUT2 DS011830 40 A DIN1 and A DIN2 can be assigned as the or input Single Ended Configuration CHO CH1 CH2 CH3 CH4 MUX OUT 1 CH5 CH6 CH7 COM MUX OUT2 DS011830 41 A DIN1 is input A DIN2 is input FIGURE 10 ANALOG INPUT VOLTAGE RANGE ASSIGNED OV TO 2 5V INPUT Vpt 12 BITS UNSIGNED esinin ADC12L03Y INPUT COM Veer VREF DGND ANALOG INPUT VOLTAGE GROUND REFERENCE AGND LM4040AIM3 2 5 DS011830 46 FIGURE 11
21. E ISOLATION The ADC12L030 2 4 8 s performance is optimized by routing the analog input output and reference signal conductors as far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins Ground traces parallel to the clock signal traces can be used on printed circuit boards to reduce clock signal interference on the analog input output pins Application Hints continued DS011830 44 FIGURE 16 Ideal Ground Plane for the ADC12L038 12 0 THE CALIBRATION CYCLE A calibration cycle needs to be started after the power sup plies reference and clock have been given enough time to stabilize after initial turn on During the calibration cycle correction values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors These values are stored in internal RAM and used during an analog to digital conversion to bring the overall full scale offset and linearity errors down to the specified limits Full scale error typically changes 0 4 LSB over tempera ture and linearity error changes even less therefore it should be necessary to go through the calibration cycle only once after power up if the Power Supply Voltage and the ambient temperature do not change significantly see the curves in the Typical Performance Characteristics 13 0 THE AUTO ZERO CYCLE To correct for any change in the zero offset error of the A D the auto zero cycle can be used It may be
22. GE The difference in the voltages applied to the VREF and Veer defines the analog input span the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground over which 4095 positive and 4096 negative codes exist The voltage sources driving Vage OrVREF must have very low output impedance and noise The ADC12L030 2 4 8 can be used in either ratiometric or absolute reference applications In ratiometric systems the analog input voltage is proportional to the voltage used for the ADC s reference voltage When this voltage is the sys tem power supply the pin is connected to V4 and VREF s connected to ground This technique relaxes the system reference stability requirements because the analog input voltage and the ADC reference voltage move together This maintains the same output code for given input condi tions For absolute accuracy where the analog input voltage varies between very specific voltage limits a time and tem perature stable voltage source can be connected to the reference inputs Typically the reference voltage s magni tude will require an initial adjustment to null reference volt age induced full scale errors Below are recommended references along with some key specifications Output Temperature Part Number Voltage Coefficient Tolerance max LM4041CIM3 Adj 100ppm C LM4040AIM3 2 5 100ppm C The reference voltag
23. I STATE Falling and Rising Edge DO 1 2V TRI STATE DS011830 18 t FDO DS011830 19 DI Data Input Timing DI CONV DS011830 20 DO Data Output Timing Using CS 0 1 2 3 4 n SCLK tav gt Ktser up DO TRI STATE DOR DS011830 21 www national com 14 Timing Diagrams continued DO Data Output Timing with CS Continuously Low 0 1 2 3 4 SCLK tseT uP DO DOR EOC DS011830 22 ADC12L038 Auto Cal or Auto Zero CCLK SCLK CONV KKK DI DO DOR 0 011830 23 Note DO output data is not valid during this cycle 15 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Timing Diagrams continued ADC12L038 Read Data without Starting a Conversion Using cs La CONV E XX E sor el 7 EOC DS011830 24 ADC12L038 Read Data without Starting a Conversion with cs Continuously Low IMM NN _ pee Le KXXXXX T EOC DI DS011830 25 www national com 16 Timing Diagrams continued ADC12L038 Conversion Using CS with 8 Bit Digital Output Format CCLK SCLK CONV DOR EOC DS011830 26 ADC12L038 Conversion Using CS with 16 Bit Digital Output Format tA CCLK SCLK cory SUR cce
24. National Semiconductor ADC12L030 ADC12L032 ADC12L034 ADC12L038 3 3V Self Calibrating 12 Bit Plus Sign Serial I O A D Converters with MUX and Sample Hold General Description The ADC12L030 family is 12 bit plus sign successive ap proximation A D converters with serial and configurable input multiplexers These devices are fully tested with a single 3 3V power supply The ADC12L032 ADC12L034 and ADC12L038 have 2 4 and 8 channel multiplexers respec tively Differential multiplexer outputs and A D inputs are available on the MUXOUT1 MUXOUT2 A DIN1 and A DIN2 pins The ADC12L030 has a two channel multiplexer with the multiplexer outputs and A D inputs internally connected On request these A Ds go through a self calibration process that adjusts linearity zero and full scale errors to less than 14 LSB each The analog inputs can be configured to operate in various combinations of single ended differential or pseudo differential modes A fully differential unipolar analog input range OV to 3 3V can be accommodated with a single 3 3V supply In the differential modes valid outputs are obtained even when the negative inputs are greater than the positive because of the 12 bit plus sign two s compliment output data format The serial is configured to comply with NSC s MICROWIRE and Motorola s SPI standards For voltage references see the LM4040 or LM4041 data sheets ADC12L038 Simplified Block Diagram O
25. Single Ended Biasing 2 1 Biasing for Various Multiplexer Configurations Figure 11 is an example of biasing the device for single ended operation The sign bit is always low The digital output range is 0 0000 0000 0000 to 0 1111 1111 1111 One LSB is equal to 610 uV 2 5V 4096 LSBs For pseudo differential signed operation the biasing circuit shown in Figure 12 shows a signal AC coupled to the ADC This gives a digital output range of 4096 to 4095 With a 1 25V reference as shown 1 LSB is equal to 305 uV Al though the ADC is not production tested with a 1 25V refer ence linearity error typically will not change more than 0 3 LSB With the ADC set to an acquisition time of 10 clock periods the input biasing resistor needs to be 6000 or less Notice though that the input coupling capacitor needs to be 27 made fairly large to bring down the high pass corner In creasing the acquisition time to 34 clock periods with a 5 MHz CCLK frequency would allow the 6009 to increase to 6k which with a 1 uF coupling capacitor would set the high pass corner at 26 Hz The value of R1 will depend on the value of R2 An alternative method for biasing pseudo differential opera tion is to use the 1 25V from the LM4040 to bias any amplifier circuits driving the ADC as shown in Figure 13 The value of the resistor pull up biasing the LM4040 2 5 will depend upon the current required by the op amp biasing circuitry Fully differential operation i
26. The Configuration Application Hints Continued to the ADC to accomplish this configuration modification The next instruction shown in Figure 8 issued to the A D starts Modification timing diagram describes in detail the sequence conversion N 1 with 8 bits of resolution formatted MSB first of events necessary for a Data Out without Sign Data Out Again the data output during this cycle is the data from with Sign or 6 10 18 34 CCLK Acquisition time mode selec conversion N tion Table 5 describes the actual data necessary to be input 1 0 Sequence Conv N 12 Bit Sign 6 CCLK Data Out NTI Conv a dd E e e 8 Bit 12 Bit 12 Bit MSB First LSB First LSB First CHO DO Conv N 1 Conv N Conv N Conv N Conv N 1 Conv N 2 Data Data Data Data Data Data DS011830 37 FIGURE 8 Changing the ADC s Conversion Configuration The number of SCLKs applied to the A D during any conver detailed in Figure 7 Typical Power Supply Sequence as an sion I O sequence should vary in accord with the data out example The table below lists the number of SCLK pulses word format chosen during the previous conversion se required for each instruction quence The various formats and resolutions available are shown in Table 1 In Figure 8 since 8 bit without sign MSB first format was chosen during I O sequence 4 the number CS Strobed of 5 in e ad x Auto Cal 8 SCLKs Ing sequence the format
27. The following specifications apply for V VA Vp 3 3 Voc VREF 2 500 Voc VREF 0 12 bit sign conver sion mode t t 3 ns fox fsk 5 MHz Rs 250 source impedance for VREF and Vgge lt 259 fully differential input with fixed 1 250V common mode voltage and 10 tex acquisition time unless otherwise specified Boldface limits apply for TA Ty Tmn to Tmax all other limits Ta Ty 25 C Note 17 Symbol Parameter Conditions Typical Limits Note 10 Note 11 Conversion Clock Duty Cycle 60 tc Conversion Time 12 Bit Sign or 12 Bit 8 Bit Sign or 8 Bit 21 6 Cycles Programmed 6 6 T tck ta Acquisition Time Note 19 10 Cycles Programmed 18 Cycles Programmed 34 Cycles Programmed toa Self Calibration Time 4944 tox 4944 ta2 tsvNc Self Calibration or Auto Zero Synchronization Time 3 tck from DOR 0 40 0 60 tDOR DOR High Time when CS is Low 9 tsx 9 tsx Continuously for Read Data and Software Power Up Down tconv CONV Valid Data Time tipu Hardware Power Up Time Time from PD Falling Edge to EOC Rising Edge www national com 8 Units Limits MHz MHz MHz Hz us min max Us min us max min max us min us max min max us min us max max us max max us max min max Us min us max max us max max us max u
28. UT1 and MUXOUT2 VMuxouT 3 3V or VMuxouT 1 55V Ron Matching Channel to Channel Vin 1 65V and Vuuxour 1 55V Channel to Channel Crosstalk Vin Vpp fin 40 kHz MUX Bandwidth E DC and Logic Electrical Characteristics The following specifications apply for V VA Vp 3 3 Voc VREF 2 500 Voc VREF 0 12 bit sign conver sion mode fox fsk 5 MHz Rs 250 source impedance for VREF and VREF lt 250 fully differential input with fixed 1 250V common mode voltage and 10 tex acquisition time unless otherwise specified Boldface limits apply for T4 tO Tmax all other limits T4 T 25 C Notes 7 8 9 Symbol Parameter Conditions Typical Limits Units CCLK CS CONV DI PD AND SCLK INPUT CHARACTERISTICS Vina DO EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS Vourd Logical 1 Output Voltage V 3 0V lour 360 HA Vt 3 0V lout 10 HA Voutio Logical 0 Output Voltage V 3 0V lour 1 6 mA lout TRI STATE Output Current Vou OV Vout 3 3V 15 lsc POWER SUPPLY CHARACTERISTICS 15 Digital Supply Current CS HIGH Powered Down CCLK on CS HIGH Powered Down CCLK off la Positive Analog Supply Current Awake CS HIGH Powered Down CCLK on CS HIGH Powered Down CCLK off IREF 7 www national com SEO Ic LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 AC Electrical Characteristics
29. changes to l lt DIL wllnOut sine Read Status 8 SCLKs MSB first therefore the number of SCLKs required during Read Status ess Read Status 8 SCLKs 12 Bit Sign 1 8 SCLKs 1 3 CS Low Continuously Considerations 12 Bit Sign Conv 2 13 SCLKs 13 SCLKs When CS is continuously low it is important to transmit the exact number of SCLK pulses that the ADC expects Not 1 4 Analog Input Channel Selection doing so will desynchronize the serial communications to the ADC When the supply power is first applied to the ADC it will expect to see 13 pulses for each I O transmission The number of SCLK pulses that the ADC expects to see is the same as the digital output word length The digital output word length is controlled by the Data Out DO format The DO format maybe changed any time a conversion is started or when the sign bit is turned on or off The table below details out the number of clock periods required for different DO formats I O sequence 6 changes accordingly to 12 The data input on DI also selects the channel configuration for a particular A D conversion See Tables 2 3 4 5 In Figure 8 the only times when the channel configuration could be modified would be during I O sequences 1 4 5 and 6 Input channels are reselected before the start of each new conversion Shown below is the data bit stream required on DI during sequence number 4 in Figure 8 to set CH1 as the positive input and CHO as
30. cted channel will corrupt the reading of a selected channel This pin is another analog input pin It is used as a pseudo ground when the analog multi plexer is single ended These the pins These are the converter input pins MUXOUT1 is usually tied to A DIN1 MUXOUT2 is usually tied to A DIN2 If external circuitry is placed between MUXOUT1 and A DIN1 or MUX OUT2 and A DIN2 it may be necessary to pro tect these pins The voltage at these pins should not exceed V or go below AGND see Figure 5 This is the positive analog voltage reference input In order to maintain accuracy the voltage range of VREF Vreer Vner iS multiplexer output www national com 8E0 12 LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOGV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Pin Descriptions continued VREF Vat Vp DGND AGND www national com 1 Vpcto 3 3 Vpc and the voltage at VREF cannot exceed Va See Figure 6 for recom mended bypassing The negative voltage reference input In order to maintain accuracy the voltage at this pin must not go below GND or exceed VA See Figure 6 These are the analog and digital power supply pins Va and Vp are not connected together on the chip These pins should be tied to the same power supply and bypassed separately see Figure 6 The operating voltage range of Vat and Vp is 3 0 to 5 5 Voc This is the digital ground pin see Figure 6 This is the a
31. ddress controls which channel of the analog input multiplexer MUX is se lected and the mode of operation for the A D With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conver sion out on DO with the exception of the first bit of data When CS is low continuously the first bit of the data is clocked out on the rising edge of EOC end of conversion When CS is toggled the falling edge of CS always clocks out the first bit of data CS should be brought low when SCLK is low The rise and fall times of the clock edges should not exceed 1 us This is the serial data input pin The data ap plied to this pin is shifted by the rising edge of SCLK into the multiplexer address and mode select register Tables 2 3 4 5 show the as signment of the multiplexer address and the mode select data The data output pin This pin is an active push pull output when CS is Low When CS is High this output is in TRI STATE The A D conver sion result 00 012 and converter status data are clocked out by the falling edge of SCLK on this pin The word length and format of this result can vary see Table 1 The word length and format are controlled by the data shifted into the multiplexer address and mode select register see Table 5 This pin is an active push pull output and indi cates the status of the ADC12L030 2 4 8 When low it signals that the A D is busy with a conversion auto calibration auto zero or pow
32. down may occur at any time If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register ADC12L038 Configuration Modification Example of a Status Read Cycle N Cycle N 1 Program Read Status Start a Conversion DO Data from Cycle N DO Status Data 8 bit plus Sign Conversion tc 0 12 3 4 5 6 7 8 4 5 6 aide XX es E ea aie D DO L A A A A A EN N 1 Data Status Data DOR EOC t 05011830 33 Note In order for all 9 bits of status information to accessible the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign 12 bits 12 bits plus sign or greater Vat Vp From external To ADC pin circuitry DS011830 34 FIGURE 5 Protecting the MUXOUT1 MUXOUT2 A DIN1 and A DIN2 Analog Pins www national com 20 Timing Diagrams continued Analog Assigned INPUT Voltage 3 3V Analog Assi gned Input INPUT 2 500V Voltage Analog Input Voltage Ground Reference 0 011830 35 Tantalum Monolithic Ceramic or better FIGURE 6 Recommended Power Supply Bypassing and Grounding Tables Formats na Sign First E 21 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Tables Continued EMIL MM Sign First TABLE 1 Data Out Formats Conti
33. e inputs are not fully differential The ADC12L030 2 4 8 will not generate correct conversions or comparisons if is taken below VREF Correct conver sions result when Vage and Veer differ by 1V and remain at all times between ground and V The VREF common mode range Veer Veer 2 is restricted to 0 1 x Va to 0 6 x V4 Therefore with Va 3 3V the center of the reference ladder should not go below 0 33V or above 1 98V Figure 15 is a graphic representation of the voltage restric tions on and Veer 0 6 0 5V VREF V Vref V DS011830 43 FIGURE 15 Veer Operating Range 29 www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Application Hints continued 4 0 ANALOG INPUT VOLTAGE RANGE The ADC12L030 2 4 8 s fully differential ADC generate a two s complement output that is found by using the equa tions shown below for 12 bit resolution the Output Code Vint Vin 4096 VREF VREF for 8 bit resolution the Output Code Vint 256 VREF VREF 7 Round off to the nearest integer value between 4096 to 4095 for 12 bit resolution and between 256 to 255 for 8 bit resolution if the result of the above equation is not a whole number Examples are shown in the table below Output VREF VREF V V Code BE ME wv 2 500V Digital IN IN 2 500V 0V
34. er down cycle The rising edge of EOC signals the end of one of these cycles This is the chip select pin When a logic low is applied to this pin the rising edge of SCLK shifts the data on DI into the address register This low also brings DO out of TRI STATE With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conver sion out on DO with the exception of the first bit of data When CS is low continuously the first bit of the data is clocked out on the rising edge of EOC end of conversion When CS is toggled the falling edge of CS always clocks out the first bit of data CS should be brought low when SCLK is low The falling edge of CS resets a conversion in progress and starts the sequence for a new conversion When CS is brought back low during a conversion that conversion is prematurely ended The data in the output latches may be corrupted There fore when CS is brought back low during a CONV PD CH0 CH7 COM MUXOUTI1 MUXOUT2 A DIN1 A DIN2 VREF conversion in progress the data output at that time should be ignored CS may also be left continuously low In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchro nous After the ADC supply power is applied it expects to see 13 clock pulses for each sequence The number of clock pulses the ADC expects is the same as the digital output word length This word length
35. ical sequence of events after the power is applied to the ADC12L030 2 4 8 Auto 12 Bit Sign 12 Bit Sign DI Read Status Read Status Conv 1 Conv 2 Status Data Conv 1 DO Trash Trash Cal low Status Data Data DS011830 36 FIGURE 7 Typical Power Supply Power Up Sequence The first instruction input to the A D via DI initiates Auto Cal The data output on DO at that time is meaningless and is completely random To determine whether the Auto Cal has been completed a read status instruction is issued to the A D Again the data output at that time has no significance since the Auto Cal procedure modifies the data in the output shift register To retrieve the status information an additional read status instruction is issued to the A D At this time the status data is available on DO If the Cal signal in the status word is low Auto Cal has been completed Therefore the next instruction issued can start a conversion The data output at this time is again status information To keep noise from corrupting the A D conversion the status can not be read during a conversion If CS is strobed and is brought low during a conversion that conversion is prematurely ended EOC can be used to determine the end of a conversion or www national com 24 When Low the mode Low the result will be When sign bit is output LSB Low the not first device is included in user mode the A D controller can keep track in software of
36. ise spikes on the V4 and Vp supply lines can cause conversion errors the comparator will respond to the noise The ADC is especially sensitive to any power supply spikes that occur during the auto zero or linearity correction The minimum power supply bypassing capacitors recommended are low inductance tantalum capacitors of 10 uF or greater paralleled with 0 1 uF monolithic ceramic capacitors More or different bypassing may be necessary depending on the overall system requirements Separate bypass capacitors should be used for the V4 and Vp supplies and placed as close as possible to these pins 10 0 GROUNDING The ADC12L030 2 4 8 8 performance can be maximized through proper grounding techniques These include the use of separate analog and digital ground planes The digital ground plane is placed under all components that handle digital signals while the analog ground plane is placed under all components that handle analog signals The digital and analog ground planes are connected together at only one point either the power supply ground or at the pins of the ADC This greatly reduces the occurence of ground loops and noise Shown in Figure 16 is the ideal ground plane layout for the ADC12L038 along with ideal placement of the bypass ca pacitors The circuit board layout shown in Figure 16 uses three bypass capacitors 0 01 uF C1 and 0 1 uF C2 surface mount capacitors and 10 uF tantalum capacitor 11 0 CLOCK SIGNAL LIN
37. n Ratio fin 20 kHz Vin 2 5V dB fin 40 kHz Vin dB 3 dB Full Power Bandwidth Vin 2 5 where S N D kHz drops 3 dB REFERENCE INPUT ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS Cner Reference Input Capacitance FF CAD A DIN1 and A DIN2 Analog Input 15 pF oo _ A DIN1 and A DIN2 Analog Input Vin 3 3V or 0 1 1 0 HA max CH0 CH7 and COM Input Voltage GND 0 05 V min o Con CH0 CH7 and COM Input Capacitance Cuuuxcu MUX Output Capacitance Off Channel Leakage Note 16 On Channel 3 3V and 0 01 min CH0 CH7 and COM Pins Off Channel 0V BENI On Channel 0V and 0 01 Off Channel 3 3V E www national com 6 Converter Electrical Characteristics Continued The following specifications apply for Vt Va Vp 3 3 Voc VREF 2 500 Voc VREF 0 12 bit sign conver sion mode fox fsk 5 MHz Rg 250 source impedance for VREF and lt 250 fully differential input with fixed 1 250V common mode voltage and 10 tex acquisition time unless otherwise specified Boldface limits apply for T4 Twin tO Tmax all other limits T4 T 25 C Notes 7 8 9 Symbol Parameter Conditions Typical Limits Units Note 10 Note 11 Limits REFERENCE INPUT ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS On Channel Leakage Note 16 On Channel 3 3V and CH0 CH7 and COM Pins Off Channel OV On Channel OV and Off Channel 3 3V MUXO
38. n _ Capacitance of Logic Inputs Capacitance of Logic Inputs eal Inputs O pF 1 31 41 13 Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 When the input voltage at any pin exceeds the power supplies lt GND or gt VA or Vp the current at that pin should be limited to 20 mA The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four Note 4 The maximum power dissipation must be derated at elevated temperatures and is dictated by T 0j4 and the ambient temperature TA The maximum allowable power dissipation at any temperature is Pp Tymax TA4 0j4 or the number given in the Absolute Maximum Ratings whichever is lower For this device Ty max 150 C The typical thermal resistance of these parts when board mounted follow 9 www national com 8E0 Ic LOQV T 0
39. nalog ground pin see Figure 6 Absolute Maximum Ratings Notes 1 2 Operating Ratings Notes 1 2 If Military Aerospace specified devices are required Operating Temperature Range Tone Tes Tus please contact the National Semiconductor Sales Office ADC12L030CIWM Distributors for availability and specifications ADC 2 032CIWM Positive Supply Voltage ADC1 2L034CIWM Vat Vp 6 5V ADC12L038CIWM 40 C lt T lt 85 C Voltage at Inputs and Outputs Supply Voltage except CHO CH7 and COM 0 3V to V 0 3V V ce Vad 3 0V to 5 5V Voltage at Analog Inputs a lt 100 mV CH0 CH7 and COM GND 5V to V 5V Va OV to VA IVA 300 mV Ve OV to VREF Input Current at Any Pin Note 3 30 mA Vace Wari Ve 1V to Vat Package Input Current Note 3 120 mA Vage Common Mode Voltage Range Package Dissipation at _ T 25 C Note 4 500 mW T VBEE 3 ESD Susceptability Note 5 2 Body 1500V Soldering Information N Packages 10 seconds 260 C and MUXOUT2 Voltage Range OV to VA SO Package Note 6 A D IN Common Mode Voltage Range Vapor Phase 60 seconds 215 C Vint Infrared 15 seconds 220 C 2 Storage Temperature 65 C to 150 C Converter Electrical Characteristics The following specifications apply for Vt VA Vp 3 3 Voc VREF 2 500 Voc VREF 0 12 bit sign conver sion mode fox fsk 5 MHz Rs 250 source impedance for VREF and VREF lt
40. ntinued tion is issued to the ADC while hardware power up is in effect PD pin low the device will power down When the device is powered down by software it may be powered up by either issuing a software power up instruction or by taking PD pin high and then low If the power down command is issued during an A D conversion that conversion is dis rupted Therefore the data output after power up cannot be relied on 1 6 User Mode and Test Mode An instruction may be issued to the ADC to put it into test mode Test mode is used by the manufacturer to verify complete functionality of the device During test mode CH0 CH7 become active outputs If the device is inadvert ently put into the test mode with CS low continuously the serial communications may be desynchronized Synchroni zation may be regained by cycling the power supply voltage to the device Cycling the power supply voltage will also set the device into user mode If CS is used in the serial inter face the ADC may be queried to see what mode it is in This is done by issuing a read STATUS register instruction to the ADC When bit 9 of the status register is high the ADC is in test mode when bit 9 is low the ADC is in user mode As an alternative to cycling the power supply an instruction se quence may be used to return the device to user mode This instruction sequence must be issued to the ADC using CS The following table lists the instructions required to re
41. nued X High or Low state TABLE 2 ADC12L038 Multiplexer Addressing Analog Channel Addressed A D Input Multiplexer and Assignment Polarity Output Address with A DIN1 tied to MUXOUT1 Assignment Channel and A DIN2 tied to MUXOUT2 Assignment TABLE 3 ADC12L034 Multiplexer Addressing Analog Channel Addressed A D Input Multiplexer and Assignment Polarity Output Address with A DIN1 tied to MUXOUT1 Assignment Channel and A DIN2 tied to MUXOUT2 Assignment BHH EEE Ie E ma sa E x zzzzrrrrg DH po E p L H H L H H E L H H L H H www national com 22 Tables Continued TABLE 4 ADC12L032 and ADC12L030 Multiplexer Addressing Analog Channel Addressed Input Multiplexer MUX and Assignment Polarity Output Address with A DIN1 tied to MUXOUT1 Assignment Channel and A DIN2 tied to MUXOUT2 Assignment CHO CH1 Differential _ CH0 CH1 CH0 COM Single Ended CH1 COM TABLE 5 Mode Programming Mode Selected DO Format Current next Conversion Cycle Note 21 ADC12L030 does not have A DIN1 A DIN2 MUXOUT1 and MUXOUT2 pins ADC12L038 ADC12L034 ADC12L030 and ADC12L032 See Tables 2 3 4 See Tables 2 3 4 See Tables 2 3 4 L L See Tables p Cn 3 D o NIN Go ATA Data Out with Sign Acquisition Time 6 CCLK No Change Cycles Acquisition Time
42. ontinued 3 LSB 2 LSB 1LSB OFFSET ERROR POSITIVE POSITIVE INTEGRAL FULL SCALE ERROR LINEARITY ERROR e NEGATIVE NEGATIVE FULL SCALE L INTEGRAL ERROR LINEARITY ERROR gt 0 c ERROR LSB OUTPUT CODE from 4096 to 4095 4095 DS011830 9 FIGURE 3 Simplified Error Curve vs Output Code after Auto Calibration Cycle OUTPUT CODE FIGURE 4 Offset or Zero Error Voltage ANALOG INPUT VOLTAGE Vind OFFSET VOLTAGE DS011830 10 Typical Performance Characteristics The following curves apply for 12 bit sign mode after auto calibration unless otherwise specified The performance for 8 bit sign mode is equal to or better than shown Note 9 Linearity Error Change vs Temperature 0 15 Vat Vpt 3 3V 0 10 VREF 2 500V Vine B 2 0 N 1 250V LINEARITY ERROR CHANGE LSB e o e 60 40 20 0 20 40 60 80 100 TEMPERATURE DS011830 51 www national com Full Scale Error Change vs Temperature FULL SCALE ERROR CHANGE LSB 1 5 1 0 VREF 2 500V Vgpp Vine 7 VN s NEG FULL SCALE 0 5 1 5 60 40 20 0 20 40 60 80 100 TEMPERATURE DS011830 52 12 Full Scale Error Change vs Supply Voltage FULL SCALE ERROR CHANGE LSB 0 6 0 4 VREF 2200 VREF T 0 2 POS FULL SCALE di DN Pad 3 0 3 1 32 33 34 35 3 6 SUPPLY VOLTAGE DS011830 53 Typical Pe
43. pply for V Va Vp 3 3 Voc VREF 2 500 Voc VREF 0 12 bit sign conver sion mode fox fsk 5 MHz Rg 250 source impedance for VREF and VREF lt 250 fully differential input with fixed 1 250V common mode voltage and 10 tcrk acquisition time unless otherwise specified Boldface limits apply for T4 Ty Twin tO Tmax all other limits T4 T 25 C Notes 7 8 9 Symbol Parameter Conditions Typical Limits Units Note 10 Note 11 Limits STATIC CONVERTER CHARACTERISTICS TUE Total Unadjusted Error 8 bit sign mode after Auto Zero 3 4 LSB Notes 12 13 14 Multiplexer to Channel 0 05 LSB Matching Power Supply Sensitivity V 9 3V 10 Offset Error LSB Full Scale Error 1 5 LSB max Full Scale Error 1 5 LSB Integral Linearity Error LSB Integral Linearity Error LSB Output Data from Note 20 LSB 12 Bit Conversion of Offset LSB min see Table 5 Output Data from Note 20 LSB max 12 Bit Conversion of Full Scale LSB min see Table 5 UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS S N D Signal to Noise Plus fin 1 kHz 2 5 Vpp dB Distortion Ratio fin 20 kHz Vin 2 5 Vpp dB fin 40 kHz VIN 2 5 Vpp dB 3 dB Full Power Bandwidth Vin 2 5 Vpp where S N D 31 kHz drops 3 dB DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS S N D Signal to Noise Plus fin 1 kHz Vin 2 5V dB Distortio
44. rformance Characteristics The following curves apply for 12 bit sign mode after auto calibration unless otherwise specified The performance for 8 bit sign mode is equal to or better than shown Note 9 Continued Zero Error Change vs Temperature ta Lum 2 a 0 05 nn z lt lt n I 0 00 o 5 27 0 05 Verp 2 500V a Vat VD 3 3V 2 N 0 10 Vine 7 YN 0 15 60 40 20 0 20 40 60 80 100 TEMPERATURE C DS011830 54 Digital Supply Current vs Temperature DIGITAL SUPPLY CURRENT mA 60 40 20 0 20 40 60 80 100 TEMPERATURE C DS011830 57 Test Circuits DO TRI STATE tin TEST POINT ADC12L038 po 0 011830 15 Zero Error Change vs Supply Voltage Vine 7 2 3 0 3 1 3 2 SUPPLY VOLTAGE V 1 250V Analog Supply Current vs Temperature ANALOG SUPPLY CURRENT mA 3 3 3 4 35 3 6 60 40 20 0 TEMPERATURE C DS011830 55 DO except TRI STATE 3 3V TEST POINT MMD7000 or Equivalent 2 2k ADC12L038 pg MMD7000 or Equivalent DS011830 16 www national com 20 40 60 80 100 DS011830 56 SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Test Circuits continued Leakage Current ADC12L038 CHO ON CH1 0FF CH2 OFF Select T7 CH7 OFF DS011830 17 Timing Diagrams DO Falling and Rising Edge DO TR
45. s This can be seen in the S N D versus frequency curves These curves will also give an indication of the full power bandwidth the frequency at which the S N D or S N drops 3 dB Effective number of bits can also be useful in describing the A D s noise performance An ideal A D converter will have some amount of quantization noise determined by its reso lution which will yield an optimum S N ratio given by the following equation S N 6 02 x n 1 76 dB where n is the A D s resolution in bits The effective bits of a real A D converter therefore can be found by S N dB 1 76 6 02 As an example this device with a 2 5V 10 kHz sine wave input signal will typically have a S N of 78 dB which is equivalent to 12 6 effective bits n effective 15 0 AN RS232 SERIAL INTERFACE Shown below is a schematic for an RS232 interface to any IBM and compatible PCs The DTR RTS and CTS RS232 signal lines are buffered via level translators and connected to the ADC12L038 s DI SCLK and DO pins respectively The D flip flop drive the CS control line www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Application Hints continued RS232 Interface Connector DS011830 45 Note Va Vp and on the ADC12L038 each have 0 01 uF and 0 1 uF chip caps and 10 uF tantalum caps All logic devices are bypassed with 0 1 uF A gt VD caps The DS1
46. s max AC Electrical Characteristics continued The following specifications apply for Vt VA Vp 3 3 Voc VREF 2 500 Voc VREF 0 12 bit sign conver sion mode t t 3 ns fox fsk 5 MHz Rs 250 source impedance for VREF Vnagr lt 259 fully differential input with fixed 1 250V common mode voltage and 10 lt acquisition time unless otherwise specified Boldface limits apply for TA Ty Tmn tO Tmax all other limits Ta T 25 C Note 17 Symbol Parameter Conditions Typical Limits Units Note 10 Note 11 Limits tspu Software Power Up Time Time from Serial Data Clock Falling Edge to 500 700 us max EOC Rising Edge tacc Access Time Delay from 25 ns max sss tset_up Set Up Time of CS Falling Edge to ns min Pes DELAY Delay from SCLK Falling ns min _ ti toy Delay from CS Rising Edge to R 3k C 100 pF 70 ns max EN tuo DI Hold Time from Serial Data 5 ns min F sas tspi DI Set Up Time from Serial Data 5 ns min mme _ m tubo DO Hold Time from Serial Data R 3k 100 pF 35 ns topo Delay from Serial Data Clock 50 ns max mantap m m tapo DO Rise Time TRI STATE to High R 3k 100 pF 10 40 ns max ro DO Fall Time TRI STATE to Low R 3k 100 pF 15 40 ns max tag Delay from CS Falling Edge 50 ns max Emme FF m tsb Delay rom si Serial Data Clock Falling ns max em o n Ci
47. s shown in Figure 14 One LSB for this case is equal to 2 5V 4096 610 mV www national com SEO 1c LOQV T 0 1c L OQV c 0 1c LOGV 0E0 1c LOQV ADC12L030 ADC12L032 ADC12L034 ADC12L038 Application Hints continued ANALOG INPUT CHO VOLTAGE N CH1 3 3V RANGE CH2 OV TO 2 5V ASSIGNED to INPUT CH8 12 BITS SIGNED R2 R1 6000 DEPENDS ON ADC12L03Y k ACQUISITION INPUT TIME COM VREF 1 25V VREF LM4041AIM3 1 25 DGND ANALOG INPUT VOLTAGE GROUND REFERENCE DS011830 47 FIGURE 12 Pseudo Differential Biasing with the Signal Source AC Coupled Directly into the ADC ANALOG INPUT VOLTAGE RANGE OV TO 2 5V 12 BITS SIGNED 3 3V ASSIGNED N INPUT ANALOG INPUT VOLTAGE ADC 12L03Y ASSIGNED INPUT COM Veer 1 25 LM4041AIM3 1 2 ANALOG INPUT VOLTAGE GROUND REFERENCE DS011830 48 FIGURE 13 Alternative Pseudo Differential Biasing www national com 28 Application Hints continued ANALOG N CHO INPUT CH2 VOLTAGE CH4 RANGE ASSIGNED or 0 4v TO 2 9V INPUT cHe FULLY DIFFERENTIAL ADC12L03Y VAN CH1 VREF 12 BIT PLUS SIGN ANALOG INPUT CH3 VOLTAGE CH5 RANGE ASSIGNED or 0 4v To2 9vy INPUT cu7 VREF T DGND AGND ANALOG INPUT VOLTAGE GROUND REFERENCE L LM4040AIM3 2 5 DS011830 50 FIGURE 14 Fully Differential Biasing 3 0 REFERENCE VOLTA
48. turn the device to user mode DI Data x DiData Dio Dit DI2 bis DM Dis DIF TETMOE H x x X H H H H RESET TEST MODE DO with or without Sign Acquisition Time Start a Conversion X Don t Care After returning to user mode with the user mode instruction the power up data with or without sign and acquisition time instructions need to be resent to ensure that the ADC is in the required state before a conversion is started www national com 26 1 7 Reading the Data Without Starting a Conversion The data from a particular conversion may be accessed without starting a new conversion by ensuring that the CONV line is taken high during the I O sequence See the Read Data timing diagrams Table 6 describes the operation of the CONV pin 2 0 DESCRIPTION OF THE ANALOG MULTIPLEXER For the ADC12L038 the analog input multiplexer can be configured with 4 differential channels or 8 single ended channels with the COM input as the zero reference or any combination thereof see Figure 9 The difference between the voltages on the VREF and Veer pins determines the input voltage span The analog input voltage range is to V4 Negative digital output codes result when Vi gt Vin The actual voltage at or cannot go below AGND 4 Differential Channels CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 DS011830 3
49. when it would be appropriate to communicate to the A D again Once it has been determined that the A D has completed a conversion another instruction can be transmitted to the A D The data from this conversion can be accessed when the next instruc tion is issued to the A D Note when CS is low continuously it is important to transmit the exact number of SCLK cycles as shown in the timing diagrams Not doing so will desynchronize the serial com munication to the A D see Section 1 3 1 2 Changing Configuration The configuration of the ADC12L030 2 4 8 on power up defaults to 12 bit plus sign resolution 12 or 13 bit MSB First 10 CCLK acquisition time user mode no Auto Cal no Auto Zero and power up mode Changing the acquisition time and turning the sign bit on and off requires an 8 bit instruction to be issued to the ADC This instruction will not start a conversion The instructions that select a multiplexer address and format the output data do start a conversion Figure 8 describes an example of changing the configuration of the ADC 12L030 2 4 8 During I O sequence 1 the instruction on DI configures the ADC12L030 2 4 8 to do a conversion with 12 bit sign reso lution Notice that when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC sequences 2 and 3 a new conversion is not started The data output during these instructions is from conversion N which was started during I O sequence 1

NATIONAL SEMICONDUCTOR ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX Sample/Hold handbook

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