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ANALOG DEVICES SigmaDSP 28-/56-Bit Audio Processor with Two ADCs Four DACs ADAU1701 handbook

1. Table 37 015 014 D13 012 D11 D10 D9 08 07 06 05 04 D3 D2 D1 DO Default 0 0 0 0 11 10 AA09 08 07 06 05 04 02 01 00 0 0000 Table 38 Bit Name Description AA 11 0 Auxiliary ADC output data MSB first Rev 0 Page 34 of 52 ADAUT 701 2064 TO 2068 0x0810 TO 0x814 SAFELOAD DATA REGISTERS Many applications require real time microcontroller control of signal processing parameters such as filter coefficients mixer gains multichannel virtualizing parameters or dynamics processing curves When controlling a biquad filter for example all of the parameters must be updated at the same time Doing so prevents the filter from executing with a mix of old and new coefficients for one or two audio frames thus avoiding temporary instability and transients that may take a long time to decay To accomplish this the ADAU1701 uses safeload data registers to simultaneously load a set of five 28 bit values to the desired parameter RAM address Five registers are used because a biquad filter uses five coefficients and as previously mentioned it is desirable to do a complete update in one transaction The first step in performing a safeload operation is writing the parameter address to one of the safeload address registers 2069 to 2073 The 10 bit data word to be written is the address in initiate th
2. OBF 1 0 When the output port is being used as a clock master these bits set the frequency of the output bit clock OUTPUT BCLK Freq which is divided down from an internal 1024 x fs clock 49 152 MHz for a fs of 48 kHz Master Mode Only OBF 1 0 Setting 00 Internal clock 16 01 Internal clock 8 10 Internal clock 4 11 Internal clock 2 OLF 1 0 When the output port is used as a clock master these bits set the frequency of the output word clock on the OUTPUT LRCLK Freq OUTPUT LRCLK pins which is divided down from an internal 1024 x fs clock 49 152 MHz for a fs of 48 kHz Master Mode Only OLF 1 0 Setting 00 Internal clock 1024 01 Internal clock 512 10 Internal clock 256 11 Reserved FST This bit sets the type of signal on the OUTPUT LRCLK pins When this bit is set to 0 the signal is a word clock Frame Sync Type with a 5096 duty cycle when this bit is set to 1 the signal is a pulse with a duration of one bit clock at the beginning of the data frame TDM Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8 channel TDM output TDM Enable stream on the SDATA_OUTO pin MP6 MSB 2 0 These three bits set the position of the MSB of data with respect to the LRCLK edge The data output of the MSB Position ADAU1701 is always MSB first MSB 2 0 Setting 000 Delay by 1 001 Delay by 0 010 Delay by 8 011 Delay by 12 100 Delay by 16 101 Reserved 111 Reserved OWL 1 0 These bits set the
3. PWR 43 21 23 25 23 25 20 23 20 23 43 43 43 43 16 16 16 Multipurpose GPIO or Serial Output Port Data 1 SDATA_OUT1 Multipurpose GPIO Serial Output Port Data 0 or TDM Data Output SDATA OUTO Multipurpose GPIO or Serial Output Port LRCLK OUTPUT LRCLK Drive for 1 8 V Regulator The base of the voltage regulator external PNP transistor is driven from VDRIVE Supply for Input and Output Pins The voltage on this pin sets the highest input voltage that should be seen on the digital input pins This pin is also the supply for the digital output signals on the control port and MP pins IOVDD should always be set to 3 3 V The current draw of this pin is variable because it is dependent on the loads of the digital outputs Multipurpose GPIO or Serial Output Port BCLK OUTPUT ADDRt lC Address 1 In combination with ADDRO this sets the address of the IC so that four ADAU1701s can be used on the same bus CDATA SPI Data Input WB EEPROM Writeback Trigger A rising default or falling if set in the EEPROM messages edge on this pin triggers a writeback of the interface registers to the external EEPROM This function can be used to save parameter data on power down CLATCH SPI Latch Signal Must go low at the beginning of an SPI transaction and high at the end of a transaction Each SPI transaction can take a different number of CCLKs to complete depending on the addre
4. RSOO 0x0000 Table 45 Bit Name Description PC 9 0 10 bit program counter address RS 1 0 Select the register to be transferred to the data capture output RS 1 0 Register 00 Multiplier X input Mult X input 01 Multiplier Y input Mult Y input 10 Multiplier accumulator output MAC out 11 Accumulator feedback Accum fback Rev 0 Page 36 of 52 ADAUT 701 2076 0x081C DSP CORE CONTROL REGISTER Table 46 015 014 013 012 011 010 09 08 07 06 05 4 D3 D2 D1 DO Default RSVD RSVD GD1 GDO RSVD RSVD RSVD AACW GPCW IFCW IST ADM DAM CR SR1 SRO 0x0000 Table 47 DSP Core Control Register Bit Name Description GD 1 0 Sets debounce time of multipurpose pins that are set as GPIO inputs GPIO Debounce Control GD 1 0 Time ms 00 20 01 40 10 10 11 5 AACW Setting this bit allows data to be written directly to the auxiliary ADC data registers 2057 to 2060 from the Auxiliary ADC Data Registers Control Port control port When this bit is set the auxiliary ADC data registers ignores the settings on the multipurpose pins Write Mode GPCW When this bit is set the GPIO pin setting register 2056 can be written to directly from the control port and GPIO Pin Setting Register this register ignores the input settings on the multipurpose pins Control Port Write Mode IFCW When this bit is set
5. 5029 5028 5027 5026 5025 5024 523 5022 5021 5020 5019 5018 5017 5016 0 0000 Safeload Data 2 15 0 5015 5014 5013 5012 SD11 5010 5009 5008 5007 5006 5005 5004 503 5002 5001 5000 0 0000 0x0813 2067 5 Safeload Data 3 39 32 039 5038 5037 5036 5035 5034 5033 5032 0 00 Safeload Data 3 31 16 5031 5030 5029 5028 5027 5026 5025 5024 523 5022 5021 5020 5019 5018 5017 5016 0 0000 Safeload Data 3 15 0 5015 5014 5013 SD12 SD11 5010 5009 5008 5007 5006 5005 5004 503 5002 5001 5000 0 0000 0x0814 2068 5 Safeload Data 4 39 32 039 5038 5037 5036 5035 5034 5033 5032 0 00 Safeload Data 4 31 16 5031 5030 5029 5028 5027 5026 5025 5024 523 5022 5021 5020 5019 5018 5017 5016 0 0000 Safeload Data 4 15 0 5015 5014 5013 SD12 SD11 5010 5009 5008 5007 5006 5005 5004 503 5002 5001 5000 0 0000 0x0815 2069 2 Safeload Address 0 0 0 0 0 SA11 10 5 09 5 08 5 07 5 06 5 05 5 04 5 03 SAO2 5 01 saoo 0 0000 0 0816 2070 2 Safeload Address 1 0 0 0 0 SA11 10 5 09 5 08 5 07 5 06 5 05 5 04 5 03 SAO2 5 01 saoo 0 0000 0 0817 2071 2 Safeload Address 2 0 0 0 0 5 11 sA10 SAo9 5 08 5 07 5 06 5 05 5 04 5 03 5402 5 01 saoo 0 0000 0 0818 2072 2 Safeload Address 3 0 0 0 0 SA11 Sato 5409 5 08 5 07 5 06 5 05 5 04 5 03 5 02 5 01 saoo 0 0000 0x0819 2073 2 5 Add
6. condition and shift the next eight bits the 7 bit address plus the R W bit MSB first The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse This ninth bit is known as an acknowledge bit other devices withdraw from the bus at this point and return to the idle condition The R W bit determines the direction of the data A Logic 0 on the LSB of the first byte means the master will write information to the peripheral whereas a Logic 1 means the master will read information from the peripheral after writing the subaddress and repeating the start address A data transfer takes place until a stop condition is encountered stop condition occurs when SDA transitions from low to high while SCL is held high Figure 20 shows the timing of an write and Figure 21 shows an read Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations the ADAU1701 immediately jumps to the idle condition During a given SCL high period the user should only issue one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADAU1701 does not issue an acknowledge and returns to the idle condition If the user exceeds the highest subaddress while in auto increment mode one of two actions is t
7. data can be written directly to the interface registers 2048 to 2055 from the control port Interface Registers Control Port Write Mode In that state the interface registers are not written from the SigmaDSP program IST Initiate Safeload Transfer Setting this bit to 1 initiates a safeload transfer to the parameter RAM This bit is automatically cleared when the operation is complete There are five safeload register pairs address data only those registers that have been written since the last safeload event are transferred to the parameter RAM ADM This bit mutes the output of the ADCs The bit defaults to 0 and is active low therefore it must be set to 1 to Mute ADCs transmit audio signals from the ADCs DAM This bit mutes the output of the DACs The bit defaults to 0 and is active low therefore it must be set to 1 to Mute DACs transmit audio signals from the DACs CR This bit defaults to 0 and is active low It must be set to 1 for a signal to pass through the SigmaDSP core Clear Internal Registers to 0 SR 1 0 Sample Rate These bits set the number of DSP instructions for every sample and the sample rate at which the ADAU1701 operates At the default setting of 1x there are 1024 instructions per audio sample This setting should be used with sample rates such as 48 kHz and 44 1 kHz At the 2x setting the number of instructions per frame is halved to 512 and the ADCs and DACs nominally run at a 96 kHz s
8. 080 2062 5 Reserved 39 32 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0 00 Reserved 31 16 RSVD RsvD RsvD RSVD RSVD RsvD RSVD RSVD RSVD RsvD RsvD RSVD RSVD RSVD 0 0000 Reserved 15 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD IRSVD RsvD RsVD RSVD RSVD RSVD 0 0000 0 080 2063 5 Reserved 39 32 RSVD RsvD RSVD RSvD RSVD RsvD RsvD RSVD oxoo Reserved 31 16 RSVD RSVD RsvD RSVD RsvD RsvD RSVD RSVD RSVD RSVD RsvD RsvD RSVD RSVD RSVD 0 0000 Reserved 15 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RsvD RSVD RSVD RSVD RSVD 0 0000 0x0810 2064 5 Safeload Data 0 39 32 039 5038 5037 5036 5035 5034 sD33 5032 0 00 Safeload Data 0 31 16 5031 5030 5029 5028 5027 5026 5025 5024 5023 5022 5021 5020 5019 5018 5017 5016 0 0000 Safeload Data 0 15 0 5015 5014 5013 SD12 SD11 5010 5009 5008 5007 5006 5005 5004 sDo3 5002 5001 5000 0 0000 0 0811 2065 5 Safeload Data 1 39 32 039 5038 5037 5036 5035 5034 sD33 5032 0 00 Safeload Data 1 31 16 5031 5030 5029 5028 5027 5026 5025 5024 5023 5022 5021 5020 5019 5018 5017 5016 0 0000 Safeload Data 1 15 0 5015 5014 SD13 5012 SD11 5010 5009 5008 5007 5006 5005 5004 503 5002 5001 5000 0 0000 0x0812 2066 5 Safeload Data 2 39 32 039 5038 5037 5036 5035 5034 sD33 5032 0 00 Safeload Data 2 31 16 5031 5030
9. 1 Maximum specifications are measured across a temperature range 40 to 130 case and across DVDD range of 1 62 V to 1 98 V and AVDD range of 2 97 V to 3 63 V Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins TEMPERATURE RANGE Table 4 Parameter Min Typ Max Unit Functionality Guaranteed 0 70 C ambient PLL AND OSCILLATOR Table 5 Parameter Min Typ Max Unit PLL Operating Range MCLK Nom 2096 MCLK Nom 20 MHz PLL Lock Time 20 ms Crystal Oscillator gm Transconductance 78 mmho REGULATOR Table 6 Regulator Parameter Min Typ Max Unit DVDD Voltage 1 7 1 8 1 84 V 1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit Rev 0 Page 4 of 52 DIGITAL TIMING SPECIFICATIONS Table 7 Digital Timing ADAU1701 Limit Parameter Tmin Tmax Unit Description MASTER CLOCK 36 244 ns MCLK period 512 fs mode 48 366 ns MCLK period 384 fs mode tmp 73 488 ns MCLK period 256 fs mode tmp 291 1953 ns MCLK period 64 fs mode SERIAL PORT tei 40 ns INPUT BCLK low pulse width 40 ns INPUT BCLK high pulse width tus 10 ns INPUT_LRCLK setup Time to INPUT_BCLK rising tun 10 ns INPUT LRCLK hold Time from INPUT BCLK rising tsis 10 ns SDATA INx setup Time to BCLK IN rising 10 ns
10. 12 or 16 BCLKs with Clock Figure 34 Frame begins on falling edge Clock Data changes on falling edge Delayed from start of word clock by 1 BCLK TDM with Pulse Figure 35 Frame begins on rising edge Pulse Data changes on falling edge Delayed from start of word clock by 1 BCLK Rev 0 Page 44 of 52 ADAU1701 LEFT CHANNEL LRCLK SDATA C Fs 5 Figure 31 PS 16 Bits to 24 Bits per Channel LRCLK CU up m CHANNEL Een AE CHANNEL BCLK __4__ 5 _____ gt ae _LSB_ 7 06412 019 peg 1IFs Figure 32 Left Justified Mode 16 Bits to 24 Bits per Channel RIGHT CHANNEL LRCLK LEFT CHANNEL BCLK SDATA N LSB 1 5 5 Figure 33 Right Justified Mode 16 Bits to 24 Bits per Channel LRCLK 1418 256 BCLKs JUU nri L32 BCLKs i DATA LRCLK BCLK Figure 34 Mode LRCLK BCLK SDATA 06412 022 Figure 35 TDM Mode with Pulse Word Clock Rev 0 Page 45 of 52 ADAU1701 LAYOUT RECOMMENDATIONS PARTS PLACEMENT The ADC input voltage to current resistors and the ADC current set resistor should be placed as close as possible to the 2 3 and 4 input pins All 100 nF bypass capacitors which are recommended for every analog digital and PLL power ground pair should be placed as close as possible to the ADAU1701 The 3 3 V and 1 8 V signals on the board
11. 332 more bytes are included in the EEPROM but are not shown in Table 20 Writeback writeback occurs when the WB pin is triggered and data is written to the EEPROM from the ADAUI701 This function is typically used to save the volume setting and other parameter settings to the EEPROM just before power is removed from the system A rising edge on the WB pin triggers a writeback when the device is in self boot mode unless a message to set the WB to the falling edge sensitive 0x05 is contained in the self boot message sequence Only one writeback takes place unless a message to set multiple writebacks 0x04 is contained in the self boot message sequence The WP pin is pulled low when a writeback is triggered to allow writing to the EEPROM The ADAUI701 is only capable of writing back the contents of the interface registers to the EEPROM These registers are usually set by the DSP program but can also be written to directly after setting Bit 6 of the core control register The parameter settings that should be saved are configured SigmaStudio Rev 0 Page 25 of 52 ADAU1701 The writeback function writes data from ADAU1701 interface registers to the second page of the self boot EEPROM Address 32 to Address 63 Starting at EEPROM Address 26 so that the interface register data begins at Address 32 the EEPROM should be programmed with six bytes the message byte 0x01 two length bytes the chip address 0x00 and the 2
12. 8V REGULATOR CIRCUIT 100nF 100nF 10pF 10 PVDD AVDD DVDD VDRIVE AUDIO ADC VOUTO INPUT SIGNALS 1 DAC OUTPUT FILTERS ACTIVE OR PASSIVE 2 VOUT3 FILTD MULTIPURPOSE Q PIN INTERFACES ADAU1701 10 100nF 5 z 2 10 100nF L BS ADDRO ADDR1 CDATA WB EEPROM 3 3V CLATCH WP MICROCONTROLLER AND OR SELFBOOT LOGIC 4750 SDA COUT 3 3nF 56nF SCLICCLK PLL_LF PLE C PLL MODEO SELFBOOT SETTINGS PLL MODE1 MCLKI O RESET LOGIC LE 3 TO 25MHz 22pF RSVD 1000 AGND DGND PGND 22pF a E 06412 003 Figure 12 System Block Diagram Rev 0 Page 13 of 52 ADAU1701 OVERVIEW The core of the ADAUI701 is a 28 bit DSP 56 bit with double precision processing optimized for audio processing The program and parameter RAMs can be loaded with a custom audio processing signal flow built by using SigmaStudio graphical programming software from Analog Devices Inc The values stored in the parameter RAM control individual signal processing blocks such as equalization filters dynamics processors audio delays and mixer levels A safeload feature allows for transparent parameter updates and prevents clicks in the output signals The program RAM parameter RAM and register contents can be saved in an external EEPROM from which th
13. GPIO PIN SETTING REGISTER This register allows the user to set the GPIO pins through the control port High or low settings can be directly written to or read from this register after setting the GPIO pin setting register control port write mode GPCW in the core control register This register is updated once every LRCLK frame 1 5 ADAUT 701 Table 35 015 D14 013 012 011 010 09 08 07 06 05 04 03 02 01 00 Default 0 0 0 0 MP11 10 MPO9 MPO8 MPO7 5 04 MPO2 MPOO 0x0000 Table 36 Bit Name Description MP 11 0 Setting of multipurpose pin when controlled through SPI or IC Rev 0 Page 33 of 52 ADAU1701 2057 TO 2060 0x809 TO 0x80C AUXILIARY ADC DATA REGISTERS These registers hold the data generated by the 4 channel parameter word with the four MSBs and 12 LSBs set to 0 A auxiliary ADC The ADCs have eight bits of precision and can full scale code of 255 results in a value of 1 0 These registers be extended to 12 bits if filtering is selected in Bits FIL 1 0 of can be written to directly if the auxiliary ADC data registers the auxiliary ADC and power control register The SigmaDSP control port write mode AACW bit is set in the DSP core program reads this data as a 1 11 format data word with a range control register of 0 to 1 0 This data word is mapped to the 5 23 format
14. Input Output 4 4 Temperature 4 et eet Rd 4 eit rites 4 Digital Timing Specifications sse 5 Digital Timing Diagrams seen 6 Absolute Maximum Ratings sentent 8 Thermal Resistance eot RR EH Rae 8 ESD Caution eene eter rmt 8 Pin Configuration and Function 5 9 Typical Performance Characteristics ssss 12 System Block Diagram sentent 13 OVELVICW 14 Initialization xerit ted 15 Power Up Sequence sssini 15 Control Registers Setup 15 Recommended Program Parameter Loading Procedure 15 Power Reduction Modes see 15 Using the Oscillator 16 Setting Master Clock PLL Mode sse 16 Voltage Regulator 17 Audio AD CS cic RHET d 18 Audio DA CS eoe tre RE RE Re ERU 19 Control POLS E 20 Bes 21 SBI 24 ETE ERRORIS 25 Signal Process IDo tre 27 Numeric Formats retient ttt ttn tino tton 27 PHO SLATMIMING 27 REVISION HISTORY 10 06 Revision 0 Initial Version RAMs and Registers eee 28 Address M
15. Layout Recommendations seen 46 Parts Placement eese te eee eee dene 46 Grounding n veniet ihe t ne e PERSE 46 Typical Application Schematics ses 47 Boot Mode eene eee eee e nnne npe eue 47 FG Control tere 48 SPI COTO tee tette 49 Outlin Dimensions erit 50 Ordering Guide tme Re edle 50 Rev 0 Page 2 of 52 SPECIFICATIONS ADAUT 701 AVDD 3 3 V DVDD 1 8 V PVDD 3 3 V IOVDD 3 3 V ambient temperature 25 C master clock input 12 288 MHz unless otherwise noted ANALOG PERFORMANCE Table 1 Parameter Min Typ Max Unit Test Conditions Comments ADC INPUTS Number of Channels 2 Stereo input Resolution 24 Bits Full Scale Input 100 283 HArms UAp p 2 Vms input with 20 18 external 2 internal series resistor Signal to Noise Ratio A Weighted 100 dB Dynamic Range 60 dB with respect to full scale analog input A Weighted 95 100 dB Total Harmonic Distortion Noise 83 dB 3 dB with respect to full scale analog input Interchannel Gain Mismatch 25 250 mdB Crosstalk 82 Analog channel to channel crosstalk DC Bias 1 5 V Gain Error 11 11 DAC OUTPUTS Number of Channels 4 Two stereo output channels Resolution 24 Bits Full Scale Analog Output 0 9 2 5 Vp p Signal to Noise Ratio A Weighted 104 dB Dynamic Range 60 dB with respect to full scale analog output A Weighted 99 104 dB Total
16. Package Option ADAU1701JSTZ 0 C to 70 C 48 Lead LOFP ST 48 ADAUT1701JSTZ RL 0 to 70 48 Lead LOFP 13 Reel ST 48 EVAL ADAU1701EB Evaluation Board 12 Pb free part Rev 0 Page 50 of 52 ADAUT 701 NOTES Rev 0 Page 51 of 52 ADAUT 701 NOTES 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06412 0 10 06 0 DEVICES www analo g com Rev 0 Page 52 of 52
17. QUT RB gt DAC2 OUT k20 C gt DACS_OUT DVDD 100i cn 12 Sn3F 56nF c2 uF R6 475 FILTER_OUT FILTER_OUT 06412 023 ADAU1701 CONTROL ADC input Rs selected for full scale 2 Vrms input DVDD C15 100nF C16 100nF 10uF C20 100nF 100nF C18 C21 DVDD 100nF 1007 ZX5T953 E 5 0 00 c22 Z m RS 1k00 10uF C23 3 3 V gt 18 V Regulator ANO gt DVDD 18 0 R2 gt C gt DACO OUT 18k0 L gt DAC1 OUT MPx pins default settings inputs with internal pull ups DAC2 QUT These pins can be set to be GPl0s Aux ADC inputs or Serial Data 1 0 LD 74 2k20 ri R4 ut DVDD gt DAC3 OUT ADAU1701 NNN ADDRO 00 ADI CDATA WB 20 14 22pF CLATCH We 2 SDA COUT FE a a SF S04 2 x SCL CCLK 6 1561 12 288 MHz SELFBOOT RESET C RESET RSVD PLL MODEO 22pF R3 PLU MODE 18 0 FILTD E PLL_LF 100nF 7 ci C12 3n3F 56nF C2 10uF R6 475r DVDD SELFBOOT should be set HIGH for selfboot mode SELFBOOT should be set LOW for I2C control mode C49 R26 DAC 0UT 2 J AAA gt FILTER OUT 47uF 560r C50 16V Sn6F Recommended DAC Output filter Passive cB DAC_OUT W gn J NANN gt FILTER OUT 604r AD8608 R12 49k9 Recommended DAC Output filter Active 06412 024 Figure 37 PC Control Schematic Rev 0 Page 48 of 52
18. byte subaddress for the interface registers 0x08 0x00 There must be a message to the DSP core control register to enable writing to the interface registers prior to the interface register data in the EEPROM This should be stored in EEPROM Address 0 No op messages 0x03 can be used in between messages to ensure that these conditions are met Table 19 EEPROM Message Types The ADAUI701 writes to EEPROM Chip Address 0xA0 The LSBs of the addresses of some EEPROMs are pin configurable most cases these pins should be tied low to set the address to Ox AO The maximum number of bytes that is written back from the ADAUI701 is 35 eight 4 byte interface registers plus three bytes of EEPROM addressing overhead With SCL running at 384 kHz the writeback operation takes approximately 73 us to complete after being triggered Ensure that sufficient power is available to the system to allow enough time for a writeback to complete especially if the WB signal is triggered from a falling power supply voltage Message ID Message Type Following Bytes 0x00 End None 0x01 Write Two bytes indicating message length followed by appropriate number of data bytes 0x02 Delay Two bytes for delay 0x03 No operation executed None 0x04 Set multiple writeback None 0x05 Set WB to falling edge sensitive None 0x06 End and wait for writeback None Tabl
19. must be set to 1 8 V The chip includes an on board voltage regulator that allows the device to be used in systems without an available 1 8 V supply but with an available 3 3 V supply The only external components needed in such instances are a PNP transistor a resistor and a few bypass capacitors Only one pin VDRIVE is necessary to support the regulator The recommended design for the voltage regulator is shown in Figure 16 The 10 uF and 100 nF capacitors shown in this configuration are recommended for bypassing but are not necessary for operation Each DVDD pin should have its own 100 nF bypass capacitor but only one bulk capacitor 10 uF to 47 is needed for both DVDD pins With this configuration 3 3 V is the main system voltage 1 8 V is generated at the transistor s collector which is connected to the DVDD pins VDRIVE is connected to the base of the PNP transistor If the regulator is not used in the design VDRIVE can be tied to ground ADAUT 701 Two specifications must be considered when choosing a regulator transistor The transistor s current amplification factor hre or beta should be at least 100 and the transistor s collector must be able to dissipate the heat generated when regulating from 3 3 V to 1 8 V The maximum digital current drawn from the ADAUI701 is 60 mA The equation to determine the minimum power dissipation of the transistor is as follows 3 3 V 1 8 V x 60 mA 90 mW There are many trans
20. programmed to be used as serial data inputs serial data outputs digital control inputs outputs to and from the SigmaDSP core or inputs to the 4 channel auxiliary ADC These pins allow the ADAU1701 to be used with external ADCs and DACs They also use analog or digital inputs to control settings such as volume control or use output digital signals to drive LED indicators AUXILIARY ADC The ADAUI701 has a 4 channel auxiliary 8 bit ADC that can be used in conjunction with a potentiometer to control volume tone or other parameter settings in the DSP program Each of the four channels is sampled at the audio sampling frequency fs Full scale input on this ADC is 3 3 V so the step size is approxi mately 13 mV 3 3 V 256 steps The input resistance of the ADC is approximately 20 Table 63 indicates which four MP pins are mapped to the four channels of the auxiliary ADC The auxiliary ADC is enabled for those pins by writing 1111 to the appropriate portion of the multipurpose pin configuration registers The auxiliary ADC is turned on by setting the AAEN bit of the auxiliary ADC enable register see Table 58 Noise on the ADC input can cause the digital output to constantly change by a few LSBs If the auxiliary ADC is used to control volume this constant change causes small gain fluctuations To avoid this add a low pass filter or hysteresis to the auxiliary ADC signal path by enabling either function in the auxiliary ADC and po
21. rate signals by reducing the number of program steps per sample by a factor of 2 using the core control register the master clock frequencies must be 32 x fs 128 x fs 192 x fs or 256 x fs If the ADAU1701 is set to receive quad rate signals by reducing the number of program steps per sample by a factor of 4 using the core control register the master clock frequencies must be 16 x fs 64 x fs 96 x fs or 128 x fs On power up a clock signal must be present on so that the ADAU1701 can complete its initialization routine Table 12 PLL Modes MCLKI Input PLL MODEO PLL MODE1 64 x fs 0 0 256 x fs 0 1 384 x fs 1 0 512 x fs 1 1 The clock mode should not be changed without also resetting the ADAU1701 If the mode is changed during operation a click or pop can result in the output signals The state of the MODEXx pins should be changed while RESET is held low The PLL loop filter should be connected to the PLL pin This filter shown in Figure 15 includes three passive components two capacitors and a resistor The values of these components do not need to be exact the tolerance can be up to 1096 for the resistor and up to 2096 for the capacitors The 3 3 V signal shown in Figure 15 can be connected to the AVDD supply of the chip 3 3V 4750 3 3nF 56nF ADAU1701 PLL_LF Figure 15 PLL Loop Filter 06412 006 Rev 0 Page 16 of 52 VOLTAGE REGULATOR The digital voltage of the ADAU1701
22. up time lasts for 2 8 cycles of the clock on the MCLKI pin This time ranges from 10 7 ms for a 24 576 MHz 512 x fs input clock to 85 3 ms for a 3 072 MHz 64 x fs input clock This start up time is measured from the rising edge of RESET Following the PLL startup the duration of the ADAU1701 boot cycle is about 42 us for a fs of 48 kHz The user should avoid writing to or reading from the ADAU1701 during this start up time For an MCLK input of 12 288 MHz the full initialization sequence PLL startup plus boot cycle is approximately 21 ms As the device comes out of a reset the clock mode is immediately set by the PLL MODEO and MODEI pins The reset is synchronized to the falling edge of the internal clock Table 11 lists typical times to boot the ADAU1701 into an applications operational state assuming 400 kHz clock loading a full program parameter set and all registers about 8 5 kB In reality most applications will not fill the RAMs and therefore boot time Column 3 of Table 11 will be less CONTROL REGISTERS SETUP The following registers must be set as described in this section to initialize the ADAU1701 These settings are the basic minimum settings needed to operate the IC with an analog input output of 48 kHz More registers may need to be set depending on the application See the RAMs and Registers section for additional settings DSP Core Control Register Address 2076 Set Bits 4 2 ADM DAM and
23. voltage or pulled up down with a resistor 7 ADDRO D IN 21 and SPI Address 0 In combination with ADDRI this pin allows up to four ADAU1701s to be used on the same lC bus and up to two ICs to be used with a common SPI CLATCH signal 8 MP4 D IO 43 Multipurpose GPIO or Serial Input Port LRCLK INPUT LRCLK 9 MP5 D IO 43 Multipurpose GPIO or Serial Input Port BCLK INPUT BCLK 10 MP1 D IO 43 Multipurpose GPIO or Serial Input Port Data 1 SDATA INO 11 MPO D IO 43 Multipurpose GPIO or Serial Input Port Data 0 SDATA 1 12 25 DGND PWR Digital Ground Pin The AGND DGND and PGND pins can be tied directly together in a common ground plane DGND should be decoupled to a DVDD pin with a 100 nF capacitor 13 24 DVDD PWR 1 8V Digital Supply This can be supplied either externally or generated from a 3 3 V supply with the on board 1 8 V regulator DVDD should be decoupled to DGND with a 100 nF capacitor Rev 0 Page 9 of 52 ADAU1701 Pin No Mnemonic Description 14 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 36 48 MP7 MP6 MP10 VDRIVE IOVDD MP11 ADDR1 CDATA WB CLATCH WP SDA COUT SCL CCLK MP9 MP8 MP3 MP2 RSVD OSCO MCLKI PGND PVDD PLL LF AVDD D IO D IO D IO A OUT PWR D IO D IN D IO A IO D IO A IO D IO A IO D IO A IO X D OUT PWR PWR A OUT
24. 0 MP103 MP102 MP101 MP100 0x00 MP93 MP92 MP91 90 MP83 82 MP81 MP80 MP73 MP72 MP71 MP70 MP63 MP62 MP61 MP60 0x0000 Table 54 Bit Name Description MPx 3 0 Set the function of each multipurpose pin MPx 3 0 Setting 1111 Auxiliary ADC input see Table 63 1110 Reserved 1101 Reserved 1100 Serial data port inverted see Table 65 1011 Open collector output inverted 1010 GPIO output inverted 1001 GPIO input no debounce inverted 1000 GPIO input debounced inverted 0111 N A 0110 Reserved 0101 Reserved 0100 Serial data port see Table 65 0011 Open collector output 0010 GPIO output 0001 GPIO input no debounce 0000 GPIO input debounced Rev 0 Page 40 of 52 2082 0x0822 AUXILIARY ADC AND POWER CONTROL ADAUT 701 Table 55 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 04 03 02 01 00 Default RSVD RSVD RSVD RSVD RSVD RSVD FIL1 FILO AAPD VBPD VRPD RSVD DOPD D1PD D2PD D3PD 0 0000 Table 56 Bit Name Description FIL 1 0 Auxiliary ADC filtering FIL 1 0 Setting 00 4 bit hysteresis 12 bit level 01 5 bit hysteresis 12 bit level 10 Filter and hysteresis bypassed 11 Low pass filter bypassed AAPD ADC pow
25. 0 00 MP Pin Config 1 15 0 MP93 92 MP91 90 MP83 82 MP81 80 MP73 MP72 MP71 MP70 MP63 MP62 61 MP60 0 0000 0x0822 2082 2 Auxiliary ADC and RSVD RSVD RSVD RSVD RSVD RSVD FIL1 FILO AAPD VBPD VRPD RSVD DOPD D1PD D2PD D3PD 0 0000 Power Control 0x0823 2083 2 Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0 0000 0x0824 2084 2 Auxiliary ADC Enable AAEN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000 0x0825 2085 2 Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0 0000 0x0826 2086 2 jOscillator Power Down RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPD RSVD RSVD 0 0000 0x0827 2087 2 DACSetup RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 051 050 0 0000 Shading indicates that registers do not fill these locations so control bits do not exist in these locations Rev 0 Page 31 of 52 ADAU1701 CONTROL REGISTER DETAILS 2048 TO 2055 0X0800 TO 0X0807 INTERFACE REGISTERS The interface registers are used in self boot mode to save parameters that need to be written to the external EEPROM The ADAUI701 then recalls these parameters from the EEPROM after the next reset or power up Therefore
26. 01 ABSOLUTE MAXIMUM RATINGS Table 8 Parameter Rating DVDD to GND OVto2 2V AVDD to GND OV to 4 0 V IOVDD to GND OV to4 0V Digital Inputs 0 3 V IOVDD 0 3 V Maximum Junction Temperature 135 C Storage Temperature Range 65 C to 150 C Soldering 10 sec 300 C THERMAL RESISTANCE is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 9 Thermal Resistance Package Type Unit 48 Lead LOFP 72 19 5 C W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 8 of 52 Table 10 Pin Function Descriptions 5 VOUTO ADAUT 701 5 AGND 3 FILTD e 2 o
27. 15 114 1713 1712 IFO9 IFO8 iFo7 5 iFo4 iFos 2 0 0000 0x0807 205 4 Interface 0 31 16 0 0 0 0 IF27 iF26 iF25 iF24 23 22 iF21 iF20 IF19 IF18 17 16 0 0000 Interface 0 15 0 15 114 1713 1712 IFO9 iFo7 5 iFo4 iFos 2 1 0 0000 2056 2 GPIO setting 0 0 0 0 MP11 10 9 08 7 06 05 04 2 01 00 0 0000 0 0809 2057 2 Auxiliary ADC Data 0 0 0 0 0 AA11 10 09 AA08 AA07 06 05 04 02 01 faaoo 0 0000 Ox080A 2058 2 Auxiliary ADC Data 1 0 0 0 0 11 10 09 AA08 07 06 05 04 02 01 faaoo 0 0000 2059 2 Auxiliary ADC Data 2 0 0 0 0 11 10 09 AA08 AA07 06 05 04 02 01 00 0 0000 2060 2 Auxiliary ADC Data 3 0 0 0 0 11 09 AA08 AA07 06 05 04 02 01 00 0 0000 0 0800 2061 5 Reserved 39 32 RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0 00 Reserved 31 16 RSVD RSVD RsvD RsvD RsvD RsvD RsvD RSVD RSvD RSVD lRsvp Rsvp RsvD RSVD RSVD 0 0000 Reserved 15 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RsvD RsVD RSVD RSVD RSVD 0 0000 0
28. ADAUT 701 SPI CONTROL 0 00 615 100nF 6 100nF 10uF 17 C20 1007 WOnF cls C21 0 00 2 57953 U D R5 C23 3 3 gt 18 V Regulator 100nF ADC input Rs selected for full scole 2 Vrms input RI gt 18k0 2 R2 gt 4 gt paco_out 18k0 45 gt paci_out MPx pins default settings ore inputs with internal pul ups 44 These pins con be set be Geos Aux ADC input e oF Serial Dato 1 0 z gt DAC2 00T R4 B NM gt D C3 0uT ADDRO 100 ADI CDATA WB T 229F 100r Doy ap 4 1 9 SCL CCLK 227 12 288 MHz 1 CI RESET 22pF R3 180 cs 100nF 1007F TRAP H 3n3F 560F C2 10 cs 100nF R6 475 DVDD C6 47uF C48 R26 m DAC OUT DH FILTER OUT 47wF 560r c50 16V Recommended DAC Output filter Passive FILTER OUT Recommended DAC Output filter Active 06412 025 Figure 38 SPI Control Schematic Rev 0 Page 49 of 52 ADAUT 701 OUTLINE DIMENSIONS 0 75 0945 1 60 0 60 2 MAX 0 45 TOP VIEW 0 20 PINS DOWN 0 09 T i 3 55 0 0 08 PLAN COPLANARITY VIEW LEAD PITCH VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026 BBC Figure 39 48 Lead Low Profile Quad Flat Package LQFP ST 48 Dimensions shown in millimeters 051706 A ORDERING GUIDE Model Temperature Range Package Description
29. AMS AND REGISTERS Table 21 RAM Map and Read Write Modes Memory Size Address Range Read Write Write Modes Parameter RAM 1024 x 32 to 1023 0x0000 to 0x03FF Yes Yes Direct write safeload write Program RAM 1024 x 40 1024 to 2047 0x0400 to 0x07FF Yes Yes Direct write Internal registers should be cleared first to avoid clicks pops ADDRESS MAPS DATA RAM Table 21 shows the RAM map and Table 32 shows the ADAU1701 register map The address space encompasses a set of registers and two RAMs one holds signal processing parameters and one holds the program instructions The program RAM and parameter RAM are initialized on power up from on board boot ROMs see the Power Up Sequence section All RAMs and registers have a default value of all 0s except for the program RAM which is loaded with the default program see the Initialization section PARAMETER RAM The parameter RAM is 32 bits wide and occupies Address 0 to Address 1023 Each parameter is padded with four 05 before the MSB to extend the 28 bit word to a full 4 byte width The parameter RAM is initialized to all 0s on power up The data format of the parameter RAM is twos complement 5 23 This means that the coefficients can range from 16 0 minus 1 LSB to 16 0 with 1 0 represented by the binary word 0000 1000 0000 0000 0000 0000 0000 or by the hexadecimal word 0x00 0x80 0x00 0x00 The parameter RAM can be written using one of the two fol
30. ANALOG SigmaDSP 28 56 Bit Audio Processor DEVICES with Two ADCs and Four DACs ADAU1701 FEATURES 28 56 bit 50 MIPS digital audio processor Two ADCs SNR of 100 dB THD N of 83 dB Four DACs SNR of 104 dB THD of 90 dB Complete standalone operation Self boot from serial EEPROM Auxiliary ADC with 4 input mux for analog control GPIOs for digital controls and outputs Fully programmable with SigmaStudio graphical tool 28 bit x 28 bit multiplier with 56 bit accumulator for full double precision processing Clock oscillator for generating master clock from crystal PLL for generating master clock from 64 x fs 256 x fs 384 x fs or 512 x fs clocks Flexible serial data input output ports with I S compatible left justified right justified and TDM modes Sampling rates up to 192 kHz supported On chip voltage regulator for compatibility with 3 3 V systems 48 lead plastic LQFP APPLICATIONS Multimedia speaker systems MP3 player speaker docks Automotive head units Minicomponent stereos Digital televisions Studio monitors Speaker crossovers Musical instrument effects processors In seat sound systems aircraft motor coaches GENERAL DESCRIPTION The ADAUI701 is a complete single chip audio system with a 28 56 bit audio DSP ADCs DACs and microcontroller like control interfaces Signal processing includes equalization cross over bass enhancement multiband dynamics processing delay compensation speaker compens
31. C inputs for a 2 0 Vms input signal for a fs of 48 kHz The 47 uF capacitors are used to ac couple the signals so that the inputs are biased at 1 5 V Rev 0 Page 18 of 52 N Sud Ke Figure 17 Audio ADC Input Configuratio ADAU1701 18 18 ADCO ADC1 8 9 8 n ADAUT 701 AUDIO DACS ADAUI701 includes four Z A DACs The SNR ofthe DAC shows a triple pole active low pass filter that provides a steeper is 104 dB and the THD N is 90 dB A full scale output on the roll off and better stop band attenuation than the passive filter DACs is 0 9 Vims 2 5 Vp p In this configuration the V and pins of the AD8606 op The DACs are in an inverting configuration Ifa signal inversion amp are set to VDD and ground respectively from input to output is undesirable it can be reversed by using To properly initialize the DACs Bits DS 1 0 in the DAC setup either an inverting configuration for the output filter or by simply register Address 2087 should be set to 01 inverting the signal in the SigmaDSP program flow 4TWF geoQ The DAC outputs can be filtered with either an active or a 2 9 passive reconstruction filter A single pole passive low pass ili 5 filter with a 50 KHz corner frequency as shown in Figure 18 is 8 sufficient to filter the DAC out of band noise although an Figure 18 Passive DAC Output Filter active filter may provide better audio perf
32. CR each to 1 DAC Setup Register Address 2087 Set Bits 0 1 DS 1 0 to 01 RECOMMENDED PROGRAM PARAMETER LOADING PROCEDURE When writing large amounts of data to the program or parameter RAM in direct write mode the processor core should be disabled to prevent unpleasant noises from appearing at the audio output 1 SetBit3 and Bit 4 active low of the core control register to 1 to mute the ADCs and DACs This begins a volume ramp down 2 SetBit 2 active low of the core control register to 1 This zeroes the SigmaDSP accumulators the data output registers and the data input registers 3 Fillthe program RAM using burst mode writes 4 Fillthe parameter RAM using burst mode writes 5 Deassert Bit 2 to Bit 4 of the core control register SDATA INQ SDATA Figure 13 Default Program Signal Flow POWER REDUCTION MODES Sections of the ADAU1701 chip can be turned on and off as needed to reduce power consumption These include the ADCs DACs and voltage reference 06412 004 The individual analog sections can be turned off by writing to the auxiliary ADC and power control register By default the ADCs DACs and reference are enabled all bits set to 0 Each Rev 0 Page 15 of 52 ADAU1701 of these can be turned off by writing a 1 to the appropriate bits in this register The ADC power down mode powers down both ADCs and each DAC can be powered down individually The current savings is abo
33. Harmonic Distortion Noise 90 dB 1 dB with respect to full scale analog output Crosstalk 100 dB Analog channel to channel crosstalk Interchannel Gain Mismatch 25 250 mdB Gain Error 10 10 DC Bias 1 5 V VOLTAGE REFERENCE Absolute Voltage CM FILTA FILTD 1 5 V AUXILIARY ADC Full Scale Analog Input 3 0 V INL 0 5 DNL 1 0 Offset 15 mV Input Impedance 30 kQ Rev 0 Page 3 of 52 ADAU1701 DIGITAL INPUT OUTPUT Table 2 Parameter Min Typ Max Unit Comments Input Voltage High Vin 2 0 IOVDD V Input Voltage Low 0 8 V Input Leakage High liu 1 pA Excluding MCLKI Input Leakage Low lit 1 Excluding MCLKI and bidirectional pins Bidirectional Pin Pull Up Current Low 150 MCLKI Input Leakage High 3 MCLKI Input Leakage Low li 3 High Level Output Voltage lou 2 mA 2 0 V Low Level Output Voltage lo 2 mA 0 8 V Input Capacitance 5 pF GPIO Output Drive 2 mA POWER Table 3 Parameter Min Typ Max Unit SUPPLY VOLTAGE Analog Voltage 33 Digital Voltage 1 8 V PLL Voltage 33 IOVDD Voltage 3 3 V SUPPLY CURRENT Analog Current AVDD and PVDD 50 85 mA Digital Current DVDD 40 60 mA Analog Current Reset 35 55 mA Digital Current Reset 1 5 4 5 mA DISSIPATION Operation AVDD DVDD PVDD 286 5 mW Reset All Supplies 118 mW POWER SUPPLY REJECTION RATIO PSRR 1 kHz 200 mV Signal at AVDD 50 dB
34. I701 has a sophisticated control port that supports complete read write capability of all memory locations Control registers are provided to offer complete control of the chips configuration and serial modes The ADAU1701 can be configured for either SPI or C control or can self boot from an external EEPROM An on board oscillator can be connected to an external crystal to generate the master clock In addition a master clock phase locked loop PLL allows the ADAU1701 to be clocked from a variety of different clock speeds The PLL can accept inputs of 64 x fs 256 x fs 384 x fs or 512 x fs to generate the internal master clock of the core The SigmaStudio software is used to program and control the SigmaDSP through the control port Along with designing and tuning a signal flow the tools can be used to configure all of the DSP registers and burn a new program into the external EEPROM SigmaStudios graphical interface allows anyone with digital or analog audio processing knowledge to easily design a DSP signal flow and port it to a target application At the same time it provides enough flexibility and programmability for an experienced DSP programmer to have in depth control of the design In SigmaStudio the user can connect graphical blocks such as biquad filters dynamics processors mixers and delays compile the design and load the program and parameter files into the ADAU1701 memory through the control port Signal processing
35. NALOG gt DS P 4 CHANNEL INPUT 2e ANALOG PERFORMANCE AUDIO FILTA 28 56 BIT 50MIPS OUTPUT ADC_RES 2 AUDIO PROCESSOR CORE 40ms DELAY MEMORY FILTD CM A CONTROL RESET MODE INTERFACE AND SELECT se FBooT INPUT 8 CH DIGITAL INPUT OUTPUT MATRIX RESET SELF 5 BOOT AND DIGITAL IN RUX ADG DIGITAL OUT 5 WRITEBACK GPIO GPIO GPIO Figure 1 Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved ADAU1701 TABLE OF CONTENTS Features ei r o EE S EEEE EE 1 APPLICATIONS e ori RaT 1 General Description disni SRE Ss 1 Functional Block Diagram seen 1 Revision 2 Sp cifications ete opti rmt e 3 Analog Performance 3 Digital
36. S Subaddress AS 5 Chipaddress AS Data AM Data AM Data P 0 high low 1 Byte 1 Byte 2 Byte Figure 24 Single Word Read Format Chip address AS Subaddress AS Subaddress 5 5 Chip address AS Data AM Data R W 0 high low R Wz1 Word 1 Word 1 Byte 1 Byte 2 Figure 25 Burst Mode Read Format Rev 0 Page 23 of 52 ADAU1701 SPI PORT By default the ADAUI701 is in PC mode but can be put into SPI control mode by pulling CLATCH WP low three times The SPI port uses a 4 wire interface consisting of CLATCH CCLK CDATA and COUT signals and is always a slave port The CLATCH signal should go low at the beginning of a transaction and high at the end of a transaction The CCLK signal latches CDATA on a low to high transition COUT data is shifted out of the ADAU1701 on the falling edge of CCLK and should be clocked into a receiving device such as a microcontroller on the CCLK rising edge The CDATA signal carries the serial input data and the COUT signal is the serial output data The COUT signal remains three stated until a read operation is requested This allows other SPI compatible peripherals to share the same readback line All SPI transactions have the same basic format shown in Table 18 A timing diagram is shown in Figure 4 All data should be written MSB first The ADAU1701 cannot be taken out of SPI
37. SB position from the start of the word clock by one BCLK M 2 0 Setting 000 125 001 Left justified 010 TDM 011 Right justified 24 bits 100 Right justified 20 bits 101 Right justified 18 bits 110 Right justified 16 bits 111 Reserved Rev 0 Page 39 of 52 ADAU1701 2080 TO 2081 0x0820 TO 0x0821 MULTIPURPOSE PIN CONFIGURATION REGISTERS Each multipurpose pin can be set to different functions from these registers 2080 to 2081 The two 3 byte registers are broken up into 12 4 bit nibble sections that each control a different MP pin Table 54 lists the function of each nibble setting within the MP pin configuration registers The MSB of Table 52 Register 2080 each 4 bit configuration inverts the input to or output from the pin The internal pull up resistor approximately 10 of each MP pin is enabled when it is set as a digital input either a GPIO input or a serial data port input D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 04 03 02 01 00 Default MP53 MP52 MP51 MP50 MP43 MP42 MP41 MP40 0x00 MP33 MP32 MP31 MP30 MP23 MP22 MP21 MP20 MP13 MP12 MP11 MP10 MP03 MP02 1 0x0000 Table 53 Register 2081 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 04 03 02 01 DO Default MP113 112 MP111 MP11
38. SDATA hold Time from BCLK rising tios 10 ns OUTPUT LRCLK setup in slave mode 10 ns OUTPUT LRCLK hold in slave mode trs 5 ns OUTPUT BCLK falling to OUTPUT LRCLK timing skew tsops 40 ns SDATA_OUTx delay Time from OUTPUT BCLK falling in slave mode 40 ns SDATA_OUTx delay Time from OUTPUT BCLK falling in master mode SPI PORT fcak 6 25 MHz CCLK frequency teceL 80 ns CCLK pulse width low tcceH 80 ns CCLK pulse width high tas 0 ns CLATCH setup Time to CCLK rising 100 ns CLATCH hold Time from CCLK rising 80 ns CLATCH pulse width high tcps 0 ns CDATA setup Time to CCLK rising 80 ns CDATA hold Time from CCLK rising 101 ns COUT delay Time from CCLK falling PORT 400 kHz SCL frequency tsciH 0 6 Hs SCL high 1 3 Hs SCL low tscs 0 6 Hs Setup time relevant for repeated start condition 0 6 Hs Hold time After this period the first clock is generated tps 100 ns Data setup time tscr 300 ns SCL rise time tscr 300 ns SCL fall time 300 ns SDA rise time tspr 300 ns SDA fall time terr 0 6 Bus free time Time between stop and start MULTIPURPOSE PINS AND RESET 50 ns GPIO rise time tort 50 ns GPIO fall time ten 1 5 1 fs us GPIO input latency Time until high low value is read by core 20 ns RESET low pulse width 1 All timing specifications are given for the default 15 states of the serial input port and th
39. aken In read mode the ADAU1701 outputs the highest subaddress register contents until the master device issues a no acknowledge indicating the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL If the highest subaddress location is reached while in write mode the data for the invalid byte is not loaded into any subaddress register a no acknowledge is issued by the ADAUI701 and the part returns to the idle condition Rev 0 Page 21 of 52 ACK BY ADAU1701 EE FRAME 2 SUBADDRESS BYTE 1 ADAU1701 FRAME 1 CHIP ADDRESS BYTE SCK SDA START BY MASTER SCK CONTINUED ADAU1701 210 21 90 81021790 zx au 7 5 ez oR gt y n 5 ES T __ lt 55 xS e 2 gt lt 5 2 m ous 55 lt 3 i 52 S BD lt mE E exei pee pest gt ones tn a uo T z N 24 c gt aa m E ET ru UPS Er f lt E so a ul 5 1 B al E eg 5 We 35 u 5 a lt lt 2 N Jet a gt ci il Em 5 p ER aod edd 3 47 x gt 55 gt Y lt lt me lt r A a eee lt 2
40. ample rate At the 4x setting there are 256 instructions per cycle and the converters run at a 192 kHz sample rate SR 1 0 Setting 00 1x 1024 instructions 01 2x 512 instructions 10 4x 256 instructions 11 Reserved Rev 0 Page 37 of 52 ADAU1701 2078 0x081E SERIAL OUTPUT CONTROL REGISTER Table 48 D15 D14 D13 D12 011 D10 09 D8 D7 D6 D5 04 03 02 01 00 Default 0 0 OLRP OBP M S OBF1 OLF1 OLFO FST TDM MSB2 MSB1 MSBO OWL1 OWLO 0x0000 Table 49 Bit Name Description OLRP When this bit is set to 0 the left channel data is clocked when OUTPUT LRCLK is low and the right channel OUTPUT LRCLK Polarity data is clocked when OUTPUT LRCLK is high When this bit is set to 1 the right channel data is clocked when OUTPUT LRCLK is low and the left channel data is clocked when OUTPUT LRCLK is high OBP This bit controls on which edge of the bit clock the output data is clocked Data changes on the falling edge OUTPUT BCLK Polarity of OUTPUT BCLK when this bit is set to 0 and on the rising edge when this bit is set to 1 M S This bit sets whether the output port is a clock master or slave The default setting is slave on power up the Master Slave OUTPUT BCLK and OUTPUT LRCLK pins are set as inputs until this bit is set to 1 at which time they become clock outputs
41. aps nmi teile oer 28 Parameter ee sE 28 Data Lee e 28 Read Write Data Formats 0 28 Control Register A 30 Control Register Details ertet eet etes 32 2048 to 2055 0x0800 to 0x0807 Interface Registers 32 2056 0x808 GPIO Pin Setting 33 2057 to 2060 0x809 to 0x80C Auxiliary ADC Data Registers sse 34 2064 to 2068 0x0810 to 0x814 Safeload Data Registers 35 2069 to 2073 0x0815 to 0x819 Safeload Address Registers 35 2074 to 2075 0x081A to 0x081B Data Capture Registers 36 2076 0x081C DSP Core Control Register 37 2078 0x081E Serial Output Control Register 38 2079 0x081F Serial Input Control Register 39 2080 to 2081 0x0820 to 0x0821 Multipurpose Pin Configuration 40 2082 0x0822 Auxiliary ADC and Power Control 4l 2084 0x0824 Auxiliary ADC 41 2086 0x0826 Oscillator 41 2087 0x0827 DAC 20 42 Multipurpose Pism E E REA 43 Auxiliary ADD OAEI EE 43 General Purpose Input Output Pins ses 43 Serial Data Input Output Ports sse 43
42. ation and stereo image widening and can be used to compensate for real world limitations of speakers amplifiers and listening environments providing a dramatic improvements of perceived audio quality Its signal processing is comparable to that found in high end studio equipment Most processing is done in full 56 bit double precision mode resulting in very good low level signal performance The ADAU1701 isa fully programmable DSP The easy to use SigmaStudio software allows the user to graphically configure a custom signal processing flow using blocks such as biquad filters dynamics processors level controls and GPIO interface controls ADAUI701 programs can be loaded on power up either from a serial EEPROM through its own self boot mechanism or from an external microcontroller On power down the current state of the parameters can be written back to the EEPROM from the ADAUI701 to be recalled the next time the program is run Two X A ADCs and four Z A DACs provide a 98 5 dB analog input to analog output dynamic Each ADC has a THD of 83 dB and each DAC has a THD N of 90 dB Digital input and output ports allow a glueless connection to additional ADCs and DACs The ADAU1701 communicates through an bus or a 4 wire SPI port FUNCTIONAL BLOCK DIAGRAM PLL DIGITAL DIGITAL ANALOG ANALOG PLL LOOP 33V VDD GROUND VDD GROUND MODE FILTER CRYSTAL trrrr y 1 8V CLOCK REGULATOR OSCILLATOR ADAU1701 2 CHANNEL DSP A
43. blocks available in the provided libraries include e Single and double precision biquad filters e Processors with peak or rms detection for monochannel and multichannel dynamics and splitters Tone and noise generators e Fixed and variable gain e Loudness e Delay e Stereo enhancement e Dynamic bass boost e Noise and tone sources e FIR filters e Level detectors e GPIO control and conditioning Additional processing blocks are always being developed Analog Devices also provides proprietary and third party algorithms for applications such as matrix decoding bass enhancement and surround virtualizers Contact Analog Devices for information about licensing these algorithms The ADAU1701 operates from a 1 8 V digital power supply and a 3 3 V analog supply An on board voltage regulator can be used to operate the chip from a single 3 3 V supply It is fabricated on a single monolithic integrated circuit and is packaged in a 48 lead LQFP for operation over the 0 C to 70 C temperature range Rev 0 Page 14 of 52 ADAUT 701 INITIALIZATION This section details the procedure for properly setting up the ADAUI701 The following five step sequence provides overview of how to initialize the IC Apply power to ADAU1701 Wait for PLL to lock Load SigmaDSP program and parameters Set up registers including multipurpose pins and digital interfaces 5 Turn off the default muting of the conver
44. d can vary from four bytes for a control register write to eight bytes for a program RAM write Burst mode can be used to fill contiguous register or RAM locations A burst mode write begins by writing the address and data of the first RAM or register location to be written Rather than ending the control port transaction by issuing a stop command in mode or by bringing the CLATCH signal high in SPI mode after the data word as would be done in a single address write the next data word can be written immediately without specifying its address The ADAU1701 control port auto increments the address of each write even across the boundaries of the different RAMs and registers Table 23 and Table 25 show examples of burst mode writes Rev 0 Page 28 of 52 Table 22 Parameter RAM Read Write Format Single Address ADAUT 701 Byte 0 Byte 1 Byte 2 Byte 3 Bytes 4 6 chip adr 6 0 W R 000000 param adr 9 8 param adr 7 0 0000 param 27 24 param 23 0 Table 23 Parameter RAM Block Read Write Format Burst Mode Byte 0 Byte 1 Byte 2 Byte 3 Bytes 4 6 Bytes 7 10 Bytes 11 14 chip adr 6 0 W R 000000 param adr 7 0 0000 param 27 24 param 23 0 param adr 9 8 lt param_adr gt Table 24 Program RAM Read Write Format Single Address param adr 1 param_adr 2 Byte 0 Byte 1 Byte 2 Byte
45. e 20 EEPROM Data Example 1 0x01 0x00 0x05 0x00 0x08 Ox1C 0x00 0x40 Write Length Device addr Core control register address Core control register data 2 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 No op bytes 3 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 No op bytes 4 0x03 0x03 0x01 0x00 0x23 0x00 0x08 0x00 No op bytes Write Length Device addr Interface register address 5 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Interface register data 6 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Interface register data 7 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Interface register data 8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Interface register data 9 0x01 0x01 0x61 0x00 0x04 0x00 0x00 0x00 Write Length Device addr Program RAM address Program RAM data 10 0x00 0x00 0x01 0x00 0x00 0x00 OxE8 0x01 Program RAM data 11 0x00 0x00 0x00 0x00 0x01 0x00 0x08 0x00 Program RAM data continues for 332 more bytes Rev 0 Page 26 of 52 SIGNAL PROCESSING The ADAUI701 is designed to provide all audio signal processing functions commonly used in stereo or multichannel playback systems The signal processing flow is designed using the SigmaStudio software which allows graphical entry and real time control of all signal processing functions Many of the signal processing functions are coded using full 56 bit double precision arithmetic data The input and output word lengths of the DSP core are 24 bits Four extra headroom bits are used in the processor to allow int
46. e ADAU1701 can self boot on start up In this standalone mode parameters can be controlled through the on board multipurpose pins The ADAUI1701 can accept controls from switches potentiometers rotary encoders and IR receivers Parameters such as volume and tone settings can be saved to the EEPROM on power down and recalled again on power up The ADAUI701 can operate with digital or analog inputs and outputs or a mix of both The stereo ADC and four DACs each have an SNR of at least 100 dB and a THD N of at least 83 dB The 8 channel flexible serial data input output ports allow glueless interconnection to a variety of ADCs DACs general purpose DSPs S PDIF receivers and transmitters and sample rate converters The serial ports of the ADAU1701 can be configured in 155 left justified right justified or TDM serial port compatible modes Twelve multipurpose MP pins allow the ADAU1701 to input external control signals and output flags or controls to other devices in the system The MP pins can be configured as digital I Os inputs to the 4 channel auxiliary ADC or set up as the serial data I O ports As inputs they can be connected to buttons switches rotary encoders potentiometers IR receivers or other external circuitry to control the internal signal processing program When configured as outputs these pins can be used to drive LEDs control other ICs or connect to other external circuitry in an application The ADAU
47. e MET SDATA_INI truncated internally Proper operation of the right justified modes requires the LSB to align with the edge of the LRCLK SBT The default settings of all serial port control registers INPUT_LRCLK slave only correspond to 2 channel 125 mode All register settings apply to Mpa INPUT_BCLK slave only both master and slave modes unless otherwise noted MPS SDATA_OUTO TDM_OUT n 7 SDATA_OUT1 The function of each multipurpose pin in serial data port mode MP8 SDATA_OUT2 is shown in Table 65 Pin MPO to Pin MP5 support digital data MP9 SDATA_OUT3 input to the ADAU1701 and Pin MES to handle digital MP10 OUTPUT LRCLK master or slave data output from the DSP The configuration of the serial data MP11 OUTPUT BCLK master or slave input port is set in the serial input control register Table 51 and the configuration of the corresponding output port is controlled with the serial output control register Table 49 The clocks of Table 66 Data Format Configurations LRCLK Format LRCLK Polarity Type BCLK Polarity MSB Position 25 Figure 31 Frame begins on falling edge Clock Data changes on falling edge Delayed from LRCLK edge by 1 BCLK Left Justified Figure 32 Frame begins on rising edge Clock Data changes on falling edge Aligned with LRCLK edge Right Justified Figure 33 Frame begins on rising edge Clock Data changes on falling edge Delayed from LRCLK edge by 8
48. e loading into RAM Each of the five safeload registers takes one of the 1024 core instructions to load into the parameter RAM The total program lengths should therefore be limited to 1019 cycles 1024 minus 5 to ensure that the SigmaDSP core always has at least five cycles available The safeload is guaranteed to occur within one LRCLK period 21 for a fs of 48 kHz of the initiate safeload transfer bit being set The safeload logic automatically sends data to be loaded into RAM from only those safeload registers that have been written to since the last safeload operation For example if two parameters are to be updated in the RAM only two of the five safeload registers must be written When the initiate safeload transfer bit is asserted only data from those two registers are sent to the RAM the other three registers are not sent to the RAM and may hold old or invalid data Table 39 Safeload Address and Data Register Mapping parameter RAM to which the safeload is being performed After Safeload Safeload Safeload this address is written the 28 bit data word can be written to Register Address Register Data Register the corresponding safeload data register 2064 to 2068 2098 2066 1 2070 2065 The data formats for these writes are detailed in Table 30 and 2 2071 2066 Table 31 Table 39 shows how each of the five address registers 3 2072 2067 maps to
49. e serial output port see Table 66 Rev 0 Page 5 of 52 ADAU1701 DIGITAL TIMING DIAGRAMS gt ten tun ja SDATA INX LEFT JUSTIFIED MSB 1 MODE SDATA INX 1 tsis SDATA_INX RIGHT JUSTIFIED LSB MODE T 8 BIT CLOCKS 24 BIT DATA e 12 BIT CLOCKS 20 BIT DATA 14 BIT CLOCKS 18 BIT DATA 16 BIT CLOCKS 16 BIT DATA m MMC Figure 2 Serial Input Port Timing yt ge og tei I tLos a T 1 4 LRCLK OUTX A lt tsops tsopm 7 SDATA_OUTX MODE SDATA_OUTX SDATA_OUTX RIGHT JUSTIFIED LSB MODE P 8 BIT CLOCKS 24 BIT DATA 8 12 BIT CLOCKS 20 BIT DATA 14 BIT CLOCKS 18 BIT DATA n 16 BIT CLOCKS 16 BIT DATA Figure 3 Serial Output Port Timing Rev 0 Page 6 of 52 06412 026 06412 027 ADAU1701 L tccpL CLATCH 3 1 gt 1 fy N SEE ESNA NS NS NA A ee e 06412 028 SDA SCLK 06412 029 4 tsc gt tscs Figure 5 Port Timing 4 typ ipu d RESET 06412 030 Figure 6 Master Clock and RESET Timing Rev 0 Page 7 of 52 ADAU17
50. e subaddresses are automati cally incremented at word boundaries can be used for writing large amounts of data to contiguous memory locations This increment happens automatically after a single word write unless a stop condition is encountered The registers and RAMs in the ADAUI701 range in width from to five bytes so the auto increment feature knows the mapping between subaddresses and the word length of the destination register or memory location A data transfer is always terminated by a stop condition Both SDA and SCL should have 2 2 pull up resistors on the lines connected to them The voltage on these signal lines should not be more than IOVDD 3 3 V Table 15 ADAUI701 Address Byte Format Bit2 Bit4 Bit5 Bit 6 Bit 7 0 1 1 0 1 ADDR1 ADDRO R W Table 16 ADAU1701 Addresses ADDR1 ADDRO Read Write Slave Address 0 0 0 0x68 0 0 1 0x69 0 1 0 0 1 1 0 6 1 0 0 Ox6C 1 0 1 0 6 1 1 0 Ox6E 1 1 1 Ox6F ADAUT 701 Addressing Initially each device on the bus is in an idle state and monitoring the SDA and SCL lines for a start condition and the proper address The master initiates a data transfer by establishing a start condition defined by a high to low transition on SDA while SCL remains high This indicates that an address data stream follows devices on the bus respond to the start
51. edge of INPUT BCLK when this bit is set 0 and on the rising edge when this bit is set at 1 M 2 0 These two bits control the data format that the input port expects to receive Bit 3 and Bit 4 of this control Serial Input Mode register override the settings of Bits 2 0 therefore all four bits must be changed together for proper operation in some modes The clock diagrams for these modes are shown in Figure 31 Figure 32 and Figure 33 Note that for left justified and right justified modes the LRCLK polarity is high and then low which is opposite from the default setting of ILP When these bits are set to accept a TDM input the ADAU1701 data starts after the edge defined by ILP The ADAU1701 TDM data stream should be input on Pin SDATA INO Figure 34 shows TDM stream with high to low triggered LRCLK and data changing on the falling edge of the BCLK ADAU1701 expects the MSB of each data slot to be delayed one BCLK from the beginning of the slot as it would in stereo 125 format In mode Channel 0 to Channel 3 are in the first half of the frame and Channel 4 to Channel 7 are in the second half Figure 35 shows an example of a TDM stream running with a pulse word clock which is used to interface to ADI codecs in auxiliary mode To work in this mode with either the input or output serial ports set the ADAU1701 to begin the frame on the rising edge of LRCLK to change data on the falling edge of BCLK and to delay the M
52. er down both ADCs VBPD Voltage reference buffer power down VRPD Voltage reference power down DOPD DACO power down D1PD DAC1 power down D2PD DAC2 power down D3PD DAC3 power down 2084 0x0824 AUXILIARY ADC ENABLE Table 57 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Default AAEN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x0000 Table 58 Bit Name Description AAEN Enable the auxiliary ADC 2086 0x0826 OSCILLATOR POWER DOWN Table 59 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 DA D3 D2 D1 DO Default RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPD RSVD RSVD 0x0000 Table 60 Bit Name Description OPD Power down the oscillator Rev 0 Page 41 of 52 ADAUT 701 2087 0x0827 DAC SETUP To properly initialize the DACs Bits DS 1 0 in this register should be set to 01 Table 61 015 014 013 012 011 010 08 07 06 05 04 03 02 01 DO Default RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 051 DSO 0x0000 Table 62 Bit Name Description DS 1 0 DAC setup DS 1 0 Setting 00 Reserved 01 Initialize DACs 10 Reserved 11 Reserved Rev 0 Page 42 of 52 ADAUT 701 MULTIPURPOSE PINS The ADAUI701 has 12 multipurpose MP pins that can be individually
53. eration is shown in Figure 27 The COUT pin goes from three state to being driven at the beginning of Byte 3 In this example Byte 0 to Byte 2 contain the addresses and R W bit and subsequent bytes carry the data Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 chip adr 6 0 R W 0000 subadr 11 8 subadr 7 0 data data Continues to end of data mU ar CDATA BYTE 0 06412 014 BYTE 1 BYTE 2 BYTE3 Figure 26 SPI Write to ADAU1701 Clocking Single Write Mode NR ever COUT DATA DATA DATA Hiz 06412 015 Figure 27 SPI Read from ADAU1701 Clocking Single Read Mode Rev 0 Page 24 of 52 SELF BOOT On power up the ADAU1701 can load a program and a set of parameters that have been saved in an external EEPROM Combined with the auxiliary ADC and the multipurpose pins this eliminates the need for a microcontroller in the system The self booting is accomplished by the ADAU1701 acting as a master on the bus on start up which occurs when the pin is set high The ADAU1701 cannot self boot in SPI mode The maximum necessary EEPROM size for program and parameters is 9248 bytes or just over 8 5 kB This does not include register settings or overhead bytes but such factors do not add a significant number of bytes This much memory is only needed if the program RAM 1024 x five bytes parame
54. ernal gains of up to 24 dB without clipping Additional gains can be achieved by initially scaling down the input signal in the DSP signal flow NUMERIC FORMATS DSP systems commonly use a standard numeric format Fractional number systems are specified by an A B format where A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point The ADAUI701 uses the same numeric format for both the parameter and data values The format is as follows Numerical Format 5 23 Linear range 16 0 to 16 0 1 LSB Examples 1000 0000 0000 0000 0000 0000 0000 16 0 1110 0000 0000 0000 0000 0000 0000 4 0 1111 1000 0000 0000 0000 0000 0000 1 0 1111 11100000 0000 0000 0000 0000 0 25 11111111 0011 0011 0011 0011 0011 0 1 1111 1111 1111 1111 1111 1111 1111 1 LSB below 0 0 0000 0000 0000 0000 0000 0000 0000 0 0 0000 0000 1100 1100 1100 1100 1101 0 1 0000 0010 0000 0000 0000 0000 0000 0 25 0000 1000 0000 0000 0000 0000 0000 1 0 0010 0000 0000 0000 0000 0000 0000 4 0 0111 1111 1111 1111 1111 1111 1111 16 0 1 LSB The serial port accepts up to 24 bits on the input and is sign extended to the full 28 bits of the DSP core This allows internal gains of up to 24 dB without internal clipping A digital clipper circuit is used between the output of the DSP core and the DACs or serial port outputs see Figure 28 This clips the top four bits of the si
55. f of the frame TDM mode allows fewer multipurpose pins to be used freeing more pins for other functions The serial modes are set in the serial output and serial input control registers The serial data clocks need to be synchronous with the ADAU1701 master clock input Rev 0 Page 43 of 52 ADAUT 701 The input control register allows control of clock polarity and data input modes The valid data formats are 15 left justified right justified 24 20 18 16 bit and 8 channel TDM In all modes except for the right justified modes the serial port accepts an arbitrary number of bits up to a limit of 24 Extra bits do not cause an error but they are truncated internally Proper operation of the right justified modes requires that there be exactly 64 BCLKs per audio frame The TDM data is input on SDATA INO The LRCLK in TDM mode can be input to the ADAU1701 either as a 50 50 duty cycle clock or as a bit wide pulse In TDM mode ADAU1701 can be a master for 48 kHz and 96 kHz data but not for 192 kHz data Table 64 lists the modes in which the serial output port can function Table 64 Serial Output Port Master Slave Mode Capabilities 2 Channel Modes PS Left Justified fs Right Justified 8 Channel TDM 48 kHz Master and slave Master and slave 96 kHz Master and slave Master and slave 192 kHz Master and slave Slave only The output control registers allow the user to control clock polarities clock freq
56. face 0 31 16 0 0 0 0 IF27 IF26 IF25 24 23 22 21 IF20 IF19 718 17 16 0 0000 Interface 0 15 0 F15 fiF14 1 1712 9 08 iFo7 5 104 iFos 02 1 00 0 0000 0x0802 2050 4 Interface 0 31 16 0 0 0 0 IF27 IF26 IF25 24 23 22 21 IF20 IF19 718 17 16 0 0000 Interface 0 15 0 15 114 1713 1712 9 iFo7 5 104 iFos 2 1 0 0 0000 0x0803 2051 4 Interface 0 31 16 0 0 0 0 IF27 IF26 IF25 124 23 22 21 IF20 IF19 718 17 16 0 0000 Interface 0 15 0 1 15 114 iF13 1712 11 9 08 iFo7 liFos fiFo4 iFo2 0 0 0000 4 2052 4 Interface 0 31 16 0 0 0 0 IF27 IF26 IF25 124 23 22 21 IF20 IF19 IF18 717 16 0 0000 Interface 0 15 0 15 114 iF13 1712 11 9 iFo7 liFos fiFo4 iFos iFo2 1 0 0 0000 0 0805 2053 4 Interface 0 31 16 0 0 0 0 IF27 IF26 IF25 124 23 22 21 IF20 IF19 718 17 16 0 0000 Interface 0 15 0 1715 114 1713 1712 9 IFO8 iFo7 5 iFo4 iFos 2 0 0 0000 0 0806 2054 4 Interface 0 31 16 0 0 0 0 IF27 iF26 iF25 iF24 23 22 21 20 IF19 IF18 17 16 0 0000 Interface 0 15 0
57. g flow to be sent to one of two readable registers This feature is useful for monitoring and displaying information about internal signal levels or compressor limiter activity For each of the data capture registers a capture count and a register select must be set The capture count is a number between 0 and 1023 that corresponds to the program step number where the capture is to occur The register select field programs one of four registers in the DSP core that transfers this information to the data capture register when the program counter reaches this step The captured data is in 5 19 twos complement data format which comes from the internal 5 23 data word with the four LSBs truncated The data that must be written to set up the data capture is a concatenation of the 10 bit program count index with the 2 bit register select field The capture count and register select values that correspond to the desired point to be monitored in the signal processing flow can be found in a file output from the program compiler The capture registers can be accessed by reading from Location 2074 and Location 2075 The format for reading and writing to the data capture registers is shown in Table 28 and Table 29 Table 44 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 05 04 03 02 01 00 Default 0 0 0 0 PCO9 PCO8 PCO7 6 5 4 PCO3 PCO2 PCO1 PCOO RSO1
58. gnal to produce a 24 bit output ADAU1701 with a range of 1 0 minus 1 LSB to 1 0 Figure 28 shows the maximum signal levels at each point in the data flow in both binary and decibel levels 4 BIT SIGN EXTENSION i SIGNAL SERIAL DIGITAL DATA IN PROCESSING DIGITAL 1 23 FORT 1 23 Q 5 23 FORMAT CLIPPER 0dB 0dB 5 23 5 23 1 23 24dB 24dB 0dB 06412 016 Figure 28 Numeric Precision and Clipping Structure PROGRAMMING On power up the ADAU1701 default program passes the unprocessed input signals to the outputs shown in Figure 13 but the outputs are muted by default see the Power Up Sequence section There are 1024 instruction cycles per audio sample resulting in about 50 MIPS available The SigmaDSP runs ina stream oriented manner meaning that all 1024 instructions are executed each sample period The ADAU1701 can also set up to accept double or quad speed inputs by reducing the number of instructions per sample that are set in the core control register The part can be programmed easily using SigmaStudio Figure 29 a graphical tool provided by Analog Devices No knowledge of writing line level DSP code is required More information about SigmaStudio be found at www analog com 99 n 4 tm 06412 035 Figure 29 SigmaStudio Screen Shot Rev 0 Page 27 of 52 ADAU1701 R
59. gt 43 ADAU1701 TOP VIEW Not to Scale IOVDD MP11 2 ADDR1 CDATA WB 5 SDA COUT SCL CCLK X DVDD gt CLATCH WP 06412 002 Figure 7 48 Lead LQFP Pin Configuration Pin No Mnemonic Page Description 1 37 42 AGND PWR Analog Ground Pin The AGND DGND and PGND pins can be tied directly together in a common ground plane AGND should be decoupled to an AVDD pin with a 100 nF capacitor 2 ADC1 A_IN 18 Analog Audio Input 1 Full scale 100 Arms input Current input allows input voltage level to be scaled with an external resistor An 18 kO resistor gives a 2 Vims full scale input 3 ADC RES A IN 18 ADC Reference Current The full scale current of the ADCs can be set with an external 18 kO resistor connected between this pin and ground 4 ADCO A IN 18 Analog Audio Input 0 Full scale 100 Arms input Current input allows input voltage level to be scaled with an external resistor An 18 kO resistor gives a 2 Vms full scale input 5 RESET D IN Active Low Reset Input Reset is triggered on a high to low edge and the ADAU1701 exits reset on a low to high edge For more information about initialization see the Power Up Sequence section 6 SELFBOOT D IN 25 Enable Disable Self Boot SELFBOOT selects control port low or self boot high Setting this pin high initiates a self boot operation when the ADAU1701 is brought out of reset This pin can be tied directly to the control
60. in accordance with the specification The ADAUI701 reads from EEPROM Chip Address 0xA1 The LSBs of the addresses of some EEPROMs pin configurable in most cases these pins should be tied low to set this address ADAU1701 EEPROM Format The EEPROM data contains a sequence of messages Each discrete message is one of the seven types defined in Table 19 Each message consists of a sequence of one or more bytes The first byte identifies the message type Bytes are written MSB first Most messages are block write 0x01 types which are used for writing to the ADAU1701 program RAM parameter RAM and control registers The body of the message following the message type should start with a 0x00 byte this is the chip address As with all other control port transactions following the chip address is a 2 byte register memory address field Table 20 shows an example of what should be stored in the EEPROM starting with EEPROM Address 0 In this example the interface registers are first set to control port write mode Line 1 which is followed by 18 no operation no op bytes Line 2 to Line 4 so that the interface register data appears on Page 2 of the EEPROM Next follows the write header Line 4 and then 32 bytes of interface register data Line 5 to Line 8 Finally the program RAM data starting at ADAU1701 Address 0x04 0x00 is written Line 9 to Line 11 In this example the program length is 70 words or 350 bytes so
61. in an input using the full range of the ADC The matching of these resistors to the ADC RES resistor is important to the operation of the ADCs For these three resistors a 196 tolerance is recommended Either the ADCO and or ADCI input pins can be left unconnected if that channel of the ADC is unused These calculations of resistor values assume a 48 kHz sample rate The recommended input and current setting resistors scale linearly with the sample rate because the ADCs have a switched capacitor input The total value 2 internal plus external resistor of the RES resistor with sample rate fs new can be calculated as follows 48 000 R 220 kOx total S NEW The values of the resistors internal plus external in series with the ADCO and ADCI pins can be calculated as follows 48 000 R RMS Input Voltage x10 Input Total 8 NEW Table 13 lists the external and total resistor values for common signal input levels at a 48 KHz sampling rate A full scale rms input voltage of 0 9 V is shown in the table because a full scale signal at this input level is equal to a full scale output on the DACs Table 13 ADC Input Resistor Values Total ADCO ADC1 Full Scale Input Resistance RMS Input ADC RES Resistor External Voltage V Value Internal kO 0 9 18 7 9 1 0 18 8 10 2 0 18 18 20 Figure 17 shows a typical configuration of the AD
62. ions within the ADAU1701 are directly addressable and their sizes exceed the range of single byte addressing All subsequent bytes starting with Byte 3 contain the data such as control port data program data or parameter data The number of bytes per word depends on the type of data that is being written The exact formats for specific types of writes are shown in Table 22 to Table 31 The ADAUI701 has several mechanisms for updating signal processing parameters in real time without causing pops or clicks If large blocks of data need to be downloaded the output of the DSP core can be halted using the CR bit in the DSP core control register Address 2076 new data can be loaded and then the device can be restarted This is typically done during the booting sequence at start up or when loading a new program into RAM In cases where only a few parameters need to be changed they can be loaded without halting the program To avoid unwanted side effects while loading parameters on the fly the SigmaDSP provides the safeload registers The safeload registers can be used to buffer a full set of parameters for example the five coefficients of a biquad and then transfer these parameters into the active program within one audio frame The safeload mode uses internal logic to prevent contention between the DSP core and the control port The control port pins are multifunctional depending on the mode in which the part is operating Table 14 de
63. istors such as the FZT953 from Zetex Semiconductors with these specifications available in small SOT 23 or SOT 223 packages 3 3V 1kQ ADAU1701 DVDD VDRIVE 06412 007 Figure 16 Voltage Regulator Configuration Rev 0 Page 17 of 52 ADAU1701 AUDIO ADCS ADAUI701 has two X A ADCs The signal to noise ratio SNR of the ADCs is 100 dB and the THD N is 83 dB The stereo audio ADCs are current input therefore a voltage to current resistor is required on the inputs This means that the voltage level of the input signals to the system can be set to any level only the input resistors need to be scaled to provide the proper full scale current input The ADCO and ADCI input pins as well as ADC_RES have an internal 2 resistor for ESD protection The voltage seen directly on the ADC input pins is the 1 5 V common mode The external resistor connected to ADC_RES sets the full scale current input of the ADCs The full range of the ADC inputs is 100 with an external 18 resistor on ADC_RES 20 total because it is in series with the internal 2 The only reason to change the ADC_RES resistor is if a sampling rate other than 48 kHz is used The voltage to current resistors connected to ADCO ADCI set the full scale voltage input of the ADCs With a full scale current input of 100 Arms 2 0 signal with an external 18 resistor in series with the 2 internal resistor results
64. its corresponding data register 4 2073 2068 After the address and data registers are loaded the initiate safeload transfer bit in the core control register should be set to Table 40 D39 D37 036 035 033 032 031 030 029 028 027 026 025 024 023 022 021 020 019 018 017 016 015 D14 013 012 011 010 D9 08 07 05 04 D3 01 00 Default 039 5038 037 036 035 5034 033 032 0 00 031 030 029 028 027 026 025 024 023 5022 021 020 5019 5018 5017 5016 0 0000 5015 014 5013 012 011 5010 009 008 007 006 005 004 003 002 001 000 0 0000 Table 41 Description SD 39 0 Data program parameters register contents to be loaded into the RAMs or registers Safeload Data 2069 TO 2073 0x0815 TO 0x819 SAFELOAD ADDRESS REGISTERS Table 42 015 014 013 012 011 010 09 08 07 06 05 04 D3 D2 D1 DO Default 0 0 0 0 SA11 5 10 5 09 SA08 5 07 5 06 5 05 5 04 5 5 02 5 01 SAOO 0 0000 Table 43 Bit Name Description SA 11 0 Address of data that is to be loaded into the RAMs or registers Safeload Address Rev 0 Page 35 of 52 ADAU1701 2074 TO 2075 0X081A TO 0X081B DATA CAPTURE REGISTERS The ADAUI701 data capture feature allows the data at any node in the signal processin
65. lowing methods a direct read write or a safeload write Direct Read Write This method allows direct access to the program RAM and parameter RAM This mode of operation is typically used during a complete new loading of the RAM using burst mode addressing The clear registers bit in the core control register should be set to 0 using this mode to avoid any clicks or pops in the outputs Note that this mode can be used during live program execution but because there is no handshaking between the core and the control port the parameter RAM is unavailable to the DSP core during control writes resulting in clicks and pops in the audio stream Safeload Write Up to five safeload registers can be loaded with the parameter RAM address data The data is then transferred to the requested address when the RAM is not busy This method can be used for dynamic updates while live program material is playing through the ADAUI701 For example a complete update of one biquad section can occur in one audio frame while the RAM is not busy This method is not available for writing to the program RAM or control registers The ADAUI701 data RAM is used to store audio data words for processing For the most part this process is transparent to the user The user cannot directly address this RAM space which has a size of 2k words from the control port Data RAM utilization should be considered when implementing blocks that require large amounts of data RAM s
66. mode without a full reset Chip Address R W The first byte of an SPI transaction includes the 7 bit chip address and a R W bit The chip address is set by the ADDRO pin This allows two ADAU1701s to share a CLATCH signal yet still operate independently When ADDRO is low the chip address is 0000000 when it is high the address is 0000001 see Table 17 The LSB of this first byte determines whether the SPI transaction is a read Logic Level 1 or a write Logic Level 0 Table 18 Generic Control Word Format Table 17 ADAU1701 SPI Address Byte Format BitO Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 0 0 0 0 0 0 ADDRO R W Subaddress The 12 bit subaddress word is decoded into a location in one of the memories or registers This subaddress is the location of the appropriate RAM location or register The MSBs of the subaddress are zero padded to bring the word to a full 2 byte length Data Bytes The number of data bytes varies according to the register or memory being accessed During a burst mode write an initial subaddress is written followed by a continuous sequence of data for consecutive memory register locations The detailed data format for continuous mode operation is shown in Table 23 and Table 25 in the Read Write Data Formats section A sample timing diagram for a single write SPI operation to the parameter RAM is shown in Figure 26 A sample timing diagram of a single read SPI op
67. ormance Figure 19 6040 FILTER OUT 3 3nF 49 9kO 06412 011 Figure 19 Active DAC Output Filter Rev 0 Page 19 of 52 ADAU1701 CONTROL PORTS The ADAUI701 can operate in one of three control modes e control control e Self boot no external controller The ADAUI701 has both a 4 wire SPI control port and a 2 wire bus control port Each be used to set the RAMs and registers When the SELFBOOT pin is low at power up the part defaults to mode but can be put into SPI control mode by pulling the CLATCH WP pin low three times When the SELFBOOT pin is set high at power up the ADAU1701 loads its program parameters and register settings from an external EEPROM on startup The control port is capable of full read write operation for all addressable memory and registers Most signal processing parameters are controlled by writing new values to the param eter RAM using the control port Other functions such as mute and input output mode control are programmed by writing to the registers addresses may be accessed in both a single address mode or a burst mode The first byte Byte 0 ofa control port write contains the 7 bit chip address plus the R W bit The next two bytes Byte 1 and Byte 2 together form the subaddress of the memory or register location within the ADAU1701 This subaddress must be two bytes because the memory locations Table 14 Control Port Pins and SELFBOOT Pin Funct
68. other IC If the crystal oscillator is not used this pin can be left disconnected Master Clock Input MCLKI can either be connected to a 3 3 V clock signal or can be the input from the crystal oscillator circuit PLL Ground Pin The AGND DGND and PGND pins can be tied directly together in a common ground plane PGND should be decoupled to PVDD with a 100 nF capacitor 3 3 V Power Supply for the and the Auxiliary ADC Analog Section This should be decoupled to PGND with a 100 nF capacitor PLL Loop Filter Connection Two capacitors and a resistor need to be connected to this pin as shown in the Setting Master Clock PLL Mode section 3 3V Analog Supply This should be decoupled to AGND with a 100 nF capacitor Rev 0 Page 10 of 52 ADAU1701 Pin No Mnemonic Page Description 38 PLL MODEO D IN 16 PLL Mode Setting PLL MODEO and PLL MODE set the output frequency 39 PLL D IN 16 of the master clock PLL See the Setting Master Clock PLL Mode section for more details 40 CM A OUT 1 5 V Common Mode Reference 47 uF decoupling capacitor should be connected between this pin and ground to reduce crosstalk between the ADCs and DACs The material of the capacitors is not critical This can be used to bias external analog circuits as long as they are not drawing current from CM for example the noninverting input of an op amp 41 FILTD A OUT DAC Filter Decoupling Pin Should be connected
69. pace such as delays The SigmaDSP core processes delay times in one sample increments therefore the total pool of delay available to the user equals 2048 multiplied by the sample period For a fs of 48 kHz the pool of available delay is a maximum of about 43 ms In practice this much data memory is not available to the user because every block in a design uses a few data memory locations for its processing In most DSP programs this does not signifi cantly impact the total delay time The SigmaStudio compiler manages the data RAM and indicates if the number of addresses needed in the design exceeds the maximum available READ WRITE DATA FORMATS The read write formats of the control port are designed to be byte oriented This allows easy programming of common microcontroller chips To fit into a byte oriented format 0s are appended to the data fields before the MSB to extend the data word to eight bits For example 28 bit words written to the parameter RAM are appended with four leading 0s to equal 32 bits 4 bytes 40 bit words written to the program RAM are not appended with 0 because they are already a full five bytes These zero padded data fields are appended to a 3 byte field consisting of a 7 bit chip address a read write bit and an 11 bit RAM register address The control port knows how many data bytes to expect based on the address given in the first three bytes The total number of bytes for a single location write comman
70. r 7 0 data 23 0 Table 30 Safeload Address Register Write Format Byte 0 Byte 1 Byte 2 Byte 3 Byte4 chip adr 6 0 W R 0000 safeload adr 11 8 safeload adr 7 0 000000 param adr 9 8 param adr 7 0 Table 31 Safeload Data Register Write Format Byte 0 Byte 1 Byte 2 Byte 3 Byte4 Bytes 5 7 chip adr 6 0 W R 0000 safeload adr 11 8 safeload adr 7 0 00000000 0000 data 27 24 data 23 0 Rev 0 Page 29 of 52 ADAUT 701 CONTROL REGISTER MAP Table 32 Register Map MSB LSB D39 038 037 036 035 D33 032 Reg Reg bof D31 030 029 028 027 026 025 D24 023 022 021 020 019 018 017 016 Hex Bytes Name D15 014 013 012 011 010 D9 08 07 06 05 04 D3 D2 01 DO Default 0 0800 2048 4 Interface 0 31 16 0 0 0 0 IF27 iF26 IF25 iF24 23 22 iF21 iF20 IF19 IF18 717 16 0 0000 Interface 0 15 0 1715 1713 1712 IFO9 08 IFO7 5 104 iFos 2 1 0 0000 2049 4 Inter
71. ress 4 0 0 0 0 SA11 sA10 5409 5 08 5 07 5 06 5 05 5 04 5 03 5 02 5 01 saoo 0 0000 Rev 0 Page 30 of 52 ADAU1701 MSB LSB No 039 038 037 036 035 034 033 D32 Reg Reg bf D31 030 029 028 027 026 025 024 023 022 021 020 019 018 017 016 Hex Dec Bytes Name 015 014 013 012 011 010 09 08 07 06 105 3 102 DO Default 0x081A 2074 2 Capture 0 0 0 0 0 PCO9 PCO8 PCO7 5 4 PCO3 PCO2 PCO1 PCOO RSO1 18500 0 0000 0 081 2075 2 Data Capture 1 0 0 0 0 PCO9 PCO8 PCO7 5 4 PCO3 PCO2 PCOO RSO1 18500 0 0000 0 081 2076 2 DSP core control RSVD RSVD GD1 GDO RSVD RSVD RSVD AACW GPCW 157 DAM CR SR1 580 0 0000 0x081D 2077 1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0 00 0x081E 2078 2 Serial output control 0 0 OLRP M S OLF1 OLFO FST 5 2 5 1 MSBO OWLO 0 0000 Ox081F 2079 1 Serial input control 0 0 0 ILP IBP M2 1 MO 0x00 0x0820 2080 3 Config 0 23 16 MP53 MP52 MP51 MP50 MP43 MP42 MP41 MP40 0x00 MP Pin Config 0 15 0 MP33 2 MP31 MP30 MP23 22 MP21 20 MP13 MP12 MP11 MP10 MPO2 01 00 0 0000 0x0821 2081 3 MP Pin Config 1 23 16 MP113 112 MP111 MP110 MP103 MP102 101 MP100
72. s 3 7 chip_adr 6 0 W R 00000 prog_adr 10 8 prog_adr 7 0 prog 39 0 Table 25 Program RAM Block Read Write Format Burst Mode Byte 0 Byte 1 Byte 2 Bytes 3 7 Bytes 8 12 Bytes 13 17 chip_adr 6 0 W R 00000 prog adr 10 8 prog adr 7 0 prog 39 0 prog adr prog adr 1 prog adr 2 Table 26 Control Register Read Write Format Core Serial Out 0 Serial Out 1 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 chip adr 6 0 W R 0000 reg adr 11 8 reg adr 7 0 data 15 8 data 7 0 Table 27 Control Register Read Write Format RAM Configuration Serial Input Byte 0 Byte 1 Byte 2 Byte 3 chip adr 6 0 W R 0000 reg adr 11 8 reg adr 7 0 data 7 0 Table 28 Data Capture Register Write Format Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 chip adr 6 0 W R 0000 data capture adr 11 8 data capture adr 7 0 000 progCount 10 6 progCount 5 0 regSel 1 0 ProgCount 10 0 is the value of the program counter where the data capture occurs the table of values is generated by the SigmaStudio compiler 2 RegSel 1 0 selects one of four registers see the 2074 to 2075 0x081A to 0x081B Data Capture Registers section Table 29 Data Capture Control Port Readback Register Read Format Byte 0 Byte 1 Byte 2 Bytes 3 5 chip adr 6 0 W R 0000 data capture adr 11 8 data capture ad
73. set as inputs these pins can be used with push button switches or rotary encoders to control DSP program settings Digital outputs can be used to drive LEDs or external logic to indicate the status of internal signals and control other devices Examples of this use include indicating signal overload signal present and button press confirmation When set as an output each pin can typically drive 2 mA This is enough current to directly drive some high efficiency LEDs Standard LEDs require about 20 mA of current and can be driven from a GPIO output with an external transistor or buffer Because of issues that could arise from simultaneously driving or sinking a large current on many pins care should be taken in the application design to avoid connecting high efficiency LEDs directly to many or all of the MPx pins If many LEDs are required use an external driver When the GPIO pins are set as open collector outputs they should be pulled up to a maximum voltage of 3 3 V the voltage on IOVDD SERIAL DATA INPUT OUTPUT PORTS The flexible serial data input and output ports of the ADAU1701 can be set to accept or transmit data in 2 channel format or in an 8 channel TDM stream Data is processed in twos complement MSB first format The left channel data field always precedes the right channel data field in the 2 channel streams In TDM mode Slot 0 to Slot 3 are in the first half of the audio frame and Slot 4 to Slot 7 are in the second hal
74. set to 1 read This causes the ADAU1701 SDA to reverse and begin driving ADAUT 701 data back to the master The master then responds every ninth pulse with an acknowledge pulse to the ADAU1701 Figure 25 shows the timing of a burst mode read sequence This figure shows an example where the target read registers are two bytes The ADAU1701 increments its subaddress every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes Other address ranges may have a variety of word lengths ranging from one to five bytes The ADAU1701 always decodes the subaddress and sets the auto increment circuit so that the address increments after the appropriate number of bytes Figure 22 to Figure 25 use the following abbreviations S start bit P stop bit AM acknowledge by master AS acknowledge by slave Chip address AS Subaddress high AS Subaddresslow AS Data Byte1 AS Data Byte 2 AS DataByteN P R W 0 Figure 22 Single Word Write Format Chip address AS Subaddress AS Subaddress AS Data AS Data AS Data AS Data AS P R W 0 high low Word 1 Word 1 Word 2 Word 2 Byte 1 Byte 2 Byte 1 Byte 2 Figure 23 Burst Mode Write Format Chip address AS Subaddress A
75. should also each be bypassed with a single bulk capacitor 10 uF to 47 All traces in the crystal oscillator circuit Figure 14 should be kept as short as possible to minimize stray capacitance In addition avoid long board traces connected to any of these components because such traces may affect crystal start up and operation GROUNDING A single ground plane should be used in the application layout Components in an analog signal path should be placed away from digital signals Rev 0 Page 46 of 52 TYPICAL APPLICATION SCHEMATICS SELF BOOT MODE DVUD C5 1007 C16 c19 10017 10uF C20 100nF 10087 621 10uF 100rF DVDD C22 c23 100 input Rs selected for full scale 2 Vrms input E RI gt 18 0 R2 1 MPx pins default settings ore inputs with internal 0 MPO These pins can be set to be Grids Aux ADC inpuls Seriol Dota I O M2 2215 m MP3 j ut R4 ups ADAUI701 gt HB SEN 12 288 cu SELF gt 22pF R3 180 100nF c4 104 c5 100nF cB 47 49 R26 DAC OUT 47uF 560 C50 16V 5n5F Recommended DAC Output filter Active Figure 36 Self Boot Mode Schematic Rev 0 Page 47 of 52 ADAUT 701 2 51953 5 100 3 3 gt 18 V Regulator 0 00 gt DACO_OUT M gt DAC
76. ss and read write bit that are sent at the beginning of the SPI transaction WP Self Boot EEPROM Write Protect This pin is an open collector output when in self boot mode The ADAU1701 pulls this low to prohibit writes to an external EEPROM This pin should be pulled high to 3 3 V SDA Data This pin is a bidirectional open collector The line connected to this pin should have a 2 2 pull up resistor COUT This SPI data output is used for reading back registers and memory locations It is three stated when an SPI read is not active SCL PC Clock This pin is always an open collector input when in PC control mode In self boot mode this pin is an open collector output PC master The line connected to this pin should have 2 2 pull up resistor CCLK SPI Clock This pin can either run continuously or be gated off in between SPI transactions Multipurpose GPIO Serial Output Port Data 3 SDATA OUT3 or Auxiliary ADC Input 0 Multipurpose GPIO Serial Output Port Data 2 SDATA_OUT2 or Auxiliary ADC Input 3 Multipurpose GPIO Serial Input Port Data 3 SDATA IN3 or Auxiliary ADC Input 2 Multipurpose GPIO Serial Input Port Data 2 SDATA IN2 or Auxiliary ADC Input 1 Reserved Tie to ground either directly or through a pull down resistor Crystal Oscillator Circuit Output A 100 O damping resistor should be connected between this pin and the crystal This output should not be used to directly drive a clock to an
77. system parameters such as volume and EQ settings can be saved during power down and recalled the next time the system is turned on There are eight 32 bit interface registers which allow eight 28 bit plus zero padding parameters to be saved The parameters to be saved in these registers are selected in the graphical programming tools These registers are updated with their corresponding parameter RAM data once per sample period An edge which can be set to be either rising or falling triggers the ADAUI701 to write the current contents of the interface registers to the EEPROM See the Self Boot section for details The user can write directly to the interface registers after the interface registers control port write mode IFCW in the DSP core control register has been set In this mode the data in the registers is written from the control port not from the DSP core Table 33 D31 030 029 028 027 026 025 D24 D23 022 021 D20 D19 D18 D17 D16 015 014 D13 012 011 010 09 08 07 06 05 04 03 02 D1 DO Default 0 0 0 0 IF27 IF26 IF25 IF24 IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16 0x0000 IF15 IF14 IF13 IF12 IF11 IF10 IFO9 IFO8 IFO7 IFO6 IFO5 IFO4 IFO3 IFO2 IFO1 IFOO 0x0000 Table 34 Bit Name Description IF 27 0 Interface register 28 bit parameter Rev 0 Page 32 of 52 2056 0x808
78. tails these multiple functions Pin Mode SPI Mode Self Boot SCL CCLK SCL input CCLK input SCL output SDA COUT SDA open collector output COUT output SDA open collector output ADDR1 CDATA WB ADDR1 input CDATA input WB writeback trigger CLATCH WP Unused input tie to ground or VDD CLATCH input WP EEPROM write protect open collector output ADDRO ADDRO input ADDRO input Unused input tie to ground or VDD Rev 0 Page 20 of 52 PORT ADAUI701 supports a 2 wire serial I C compatible microprocessor bus driving multiple peripherals Two pins serial data SDA and serial clock SCL carry information between the ADAU1701 and the system master controller In C mode the ADAU1701 is always a slave on the bus meaning it cannot initiate a data transfer Each slave device is recognized by a unique address The address byte format is shown in Table 15 The ADAU1701 slave addresses are set with the ADDRO and ADDRI pins The address resides in the first seven bits of the write The LSB of this byte sets either a read or write operation Logic Level 1 corresponds to a read operation and Logic Level 0 corresponds to a write operation Bit 5 and Bit 6 of the address are set by tying the ADDRx pins of the ADAUI701 to Logic Level 0 or Logic Level 1 The full byte addresses including the pin settings and read write bit are shown in Table 16 Burst mode addressing where th
79. ter RAM 1024 x four bytes and interface registers 8 x four bytes are completely full Most applications will not use the full program and parameter RAMs so an 8 kB EEPROM will be sufficient A self boot operation is triggered on the rising edge of RESET when the SELFBOOT and WP pins are set high The ADAU1701 reads the program parameters and register settings from the EEPROM After the ADAUI701 finishes self booting additional messages be sent to the ADAUI701 on the bus although this typically is not necessary in a self booting application The device address is 0x68 for a write and 0x69 for a read in this mode The ADDRx pins have different functions when the chip is in this mode so the settings on them are ignored The ADAUI701 does not self boot if WP is set low Holding this pin low allows the EEPROM to be programmed in circuit The WP pin is pulled low it typically has a resistor pull up to enable writes to the EEPROM but this in turn disables the self boot function until the WP pin is returned high The ADAUI701 is a master on the bus during self boot and writeback Although it is uncommon for an application using self boot to also have a microcontroller connected to the control lines care should be taken that no other device tries to write to the bus during self boot or writeback The ADAU1701 generates SCL at 8 x fs therefore for a fs of 48 kHz SCL runs at 384 kHz SCL has a duty cycle of 3 8
80. ters clear the data registers and initialize the DAC setup register see the Control Registers Setup section for specific settings pop To only test analog audio pass through ADCs to DACs Steps 3 and 4 can be skipped and the default internal program can be used POWER UP SEQUENCE The ADAUI701 has a built in power up sequence that initializes the contents of all internal RAMs on power up or when the device is brought out of a reset On the positive edge of RESET the contents of the internal program boot ROM are copied to the internal program RAM memory the parameter RAM is filled with values all 0s from its associated boot ROM and all registers are initialized to 05 The default boot ROM program copies audio from the inputs to outputs without processing it see Figure 13 In this program serial digital Input 0 and Input 1 are output on and and serial digital Output 0 and Output 1 ADCO and ADCI are output on DAC2 and DAC3 The data memories are also zeroed at power up New values should not be written to the control port until the initialization is complete Table 11 Power Up Time Max Program Init Parameter Register MCLKI Input Time Boot Time Total 3 072 MHz 64 x fs 85 ms 175 ms 260 ms 11 289 MHz 256 x fs 23 ms 175 ms 198 ms 12 288 MHz 256 x fs 21 ms 175 ms 196 ms 18 432 MHz 384 fs 16 ms 175 ms 191 ms 24 576 MHz 512 x 6 11 ms 175 ms 186 ms The PLL start
81. to a 10 uF capacitor to ground The capacitor material is not critical The voltage on the FILTD is 1 5 V 43 VOUT3 A OUT 19 VOUTO to VOUT3 are the DAC Outputs Full scale output voltage is 0 9 Vims These 44 VOUT2 OUT 19 outputs can be used with either active or passive output reconstruction filters 45 VOUT1 A_OUT 19 46 VOUTO A_OUT 19 47 FILTA A_OUT ADC Filter Decoupling Pin Should be connected to a 10 pF capacitor to ground The capacitor material is not critical The voltage on the FILTA pin is 1 5 V 1 PWR power ground A IN analog input D IN digital input A OUT analog output D IO digital input output D IO A IO digital input output or analog input output Rev 0 Page 11 of 52 ADAUT 701 TYPICAL PERFORMANCE CHARACTERISTICS dB dB fs 48kHz 06412 031 0 02 04 06 08 10 12 14 16 18 20 22 FREQUENCY kHz Figure 8 ADC Pass Band Filter Response fs 48 kHz FREQUENCY kHz Figure 9 ADC Stop Band Filter Response fs 48 kHz Rev 0 Page 12 of 52 dB dB 06412 033 0 0 5 1 0 1 5 2 0 FREQUENCY kHz Figure 10 DAC Pass Band Filter Response fs 48 kHz 06412 034 FREQUENCY kHz Figure 11 DAC Stop Band Filter Response fs 48 kHz ADAUT 701 SYSTEM BLOCK DIAGRAM 3 3V 100nF 100nF 3 3V TO 1
82. to drive a digital input There are two options for using the ADAU1701 to provide a master clock to other ICs in the system The first and less recommended method is to use a high impedance input digital buffer on the OSCO signal If this is done minimize the trace length to the buffer input The second method is to use a clock from the serial output port Pin MP11 can be set as an output master clock divided down from the internal core clock If this pin is set to serial output port OUTPUT BCLK mode in the multipurpose pin configuration register 2081 and the port is set to master in the serial output control register 2078 the desired output frequency can also be set in the serial output control register with Bits OBF 1 0 see Table 49 If the oscillator is not utilized in the design it can be powered down to save power This can be done ifa system master clock is already available in the system By default the oscillator is powered on The oscillator powers down when a 1 is written to the OPD bit of the oscillator power down register see Table 60 SETTING MASTER CLOCK PLL MODE The MCLK input of the ADAU1701 feeds PLL which generates the 50 MIPS SigmaDSP core clock In normal operation the input to MCLK must be one ofthe following 64 x fs 256 x fs 384 x or 512 x fs where fs is the input sampling rate The mode is set on PLL MODEO and as described in Table 12 If the ADAU1701 is set to receive double
83. uencies clock types and data format In all the input port function only as slaves whereas the output port clocks can be set to function as either masters or slaves The INPUT LRCLK MP4 and INPUT BCLK 5 pins are used to clock the SDATA INx MP0 to MP3 signals and the OUTPUT LRCLK 10 and OUTPUT BCLK 11 pins are used to clock the SDATA_OUTx MP6 to 9 signals If an external ADC is connected as a slave to the ADAU1701 use both the input and output port clocks The OUTPUT LRCLK MP10 and OUTPUT BCLK MP11 pins must be set into master mode and connected externally to the INPUT LRCLK MP4 and INPUT BCLK MP5 pins as well as to the external ADC clock input pins The data is output from the external ADC into the SigmaDSP on one of the four INx pins MPO to MP3 Connections to an external DAC are handled exclusively with the output port pins The OUTPUT LRCLK and OUTPUT BCLK pins can be set to function as either masters or slaves and the SDATA_OUT x pins are used to output data from the SigmaDSP to the external DAC Table 66 describes the proper configurations for standard audio data formats Table 65 Multipurpose Pin Serial Data Port Functions modes except for the right justified modes MSB delayed by 8 Multipurpose Pin Function 12 or 16 bits the serial port accepts an arbitrary number of MPO SDATA_INO TDM_IN bits up to a limit of 24 Extra bits do not cause an error but ar
84. ut 15 mA when the ADCs are powered down and about 4 mA for each DAC that is powered down The voltage reference which is supplied to both the ADCs and DACs should only be powered down if all ADCs and DACs are powered down The reference is powered down by setting both Bit 6 and Bit 7 of the control register USING THE OSCILLATOR The ADAU1701 can use an on board oscillator to generate its master clock The oscillator is designed to work with a 256 x fs master clock which is 12 288 MHz for a fs of 48 kHz and 11 2896 MHz for a fs of 44 1 KHz The crystal in the oscillator circuit should be an AT cut parallel resonator operating at its fundamental frequency Figure 14 shows the external circuit recommended for proper operation ADAU1701 c1 1000 OSCO 2 MCLKI 06412 005 Figure 14 Crystal Oscillator Circuit The 100 damping resistor on OSCO gives the oscillator a voltage swing of approximately 2 2 V The crystal shunt capaci tance should be 7 pF Its load capacitance should be about 18 although the circuit supports values of up to 25 pF The necessary values of the C1 and C2 load capacitors can be calculated from the crystal load capacitance as follows CIxC2 3 stray C1 C2 where C is the stray capacitance in the circuit and is usually assumed to be approximately 2 pF to 5 pF L OSCO should not be used to directly drive the crystal signal to another IC This signal is an analog sine wave and is not appropriate
85. wer control register 2082 as described in Table 56 The filter is enabled by default when the auxiliary ADC is enabled When data is read from the auxiliary ADC registers two bytes 12 bits of data plus zero padded LSBs are available because of this filtering AUX ADC 20kQ INPUT PIN 9 1 52 1 8 51 10kQ 06412 017 Figure 30 Auxiliary ADC Input Circuit Figure 30 shows the input circuit for the auxiliary ADC Switch S1 enables the auxiliary ADC and is set by Bit 15 of the auxiliary ADC enable register The sampling switch S2 operates at the audio sampling frequency The auxiliary ADC data registers can be written to directly after AACW in the DSP core control register has been set In this mode the voltages on the analog inputs are not written into the registers but rather the data in the registers is written from the control port PVDD supplies the 3 3 V power for the auxiliary ADC analog input The digital core of the auxiliary ADC is powered with the 1 8 V DVDD signal Table 63 Multipurpose Pin Auxiliary ADC Mapping Multipurpose Pin Function MPO N A MP1 N A MP2 ADC1 MP3 ADC2 MP4 N A MP5 N A MP6 N A MP7 N A MP8 ADC3 MP9 ADCO MP10 N A MP11 N A GENERAL PURPOSE INPUT OUTPUT PINS The general purpose input output GPIO pins can be used as either inputs or outputs These pins are readable and can be set either through the control interface or directly by the SigmaDSP core When
86. word length of the output data word All bits following the LSB are set to 0 Output Word Length OWL 1 0 Setting 00 24 bits 01 20 bits 10 16 bits 11 Reserved Rev 0 Page 38 of 52 ADAUT 701 2079 0x081F SERIAL INPUT CONTROL REGISTER Table 50 D7 D6 D5 04 03 02 01 DO Default 0 0 0 ILP IBP M2 M1 MO 0x00 Table 51 Bit Name Description ILP When this bit is set to 0 the left channel data on the SDATA_INx pins is clocked when INPUT_LRCLK is low and INPUT_LRCLK Polarity the right channel data is clocked when INPUT_LRCLK is high When this bit is set to 1 the clocking of these channels is reversed In TDM mode when this bit is set to 0 data is clocked in starting with the next appropriate BCLK edge set in Bit 3 of this register after falling edge on the INPUT LRCLK pin When this bit is set to 1 and the device is running in TDM mode the input data is valid on the BCLK edge after a rising edge on the word clock INPUT LRCLK INPUT LRCLK can also operate with a pulse input rather than a clock In this case the first edge of the pulse is used by the ADAU1701 to start the data frame When this polarity bit is set to 0 a low pulse should be used when the bit it set to 1 a high pulse should be used IBP This bit controls on which edge of the bit clock the input data changes and on which edge it is clocked Data INPUT BCLK Polarity changes on the falling
87. x9 92 lt 4 oa v 5 9 ss 2 2 N icc 5 eae eer week ET 7 T ul mE zo Ww gt c SES 0 SESS gt uo uo s zu Pass zu mE lt c ul m sss ed E E E M 5 p d eas 5 bass 2 E SDA CONTINUED 46 Ya n gt x Ou ou ou z ow 2 z z x o 2 E E o lt gt 2 Q 9 LA 5 2 Q Figure 21 Read from ADAU1701 Clocking Rev 0 Page 22 of 52 PC Read and Write Operations Figure 22 shows the timing of a single word write operation Every ninth clock the ADAU1701 issues an acknowledge by pulling SDA low Figure 23 shows the timing of a burst mode write sequence This figure shows an example where the target destination registers are two bytes The ADAU1701 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2 byte word length The timing of a single word read operation is shown in Figure 24 Note that the first R W bit is 0 indicating a write operation This is because the subaddress still needs to be written to set up the internal address After the ADAU1701 acknowledges the receipt of the subaddress the master must issue a repeated start command followed by the chip address byte with the R W

ANALOG DEVICES SigmaDSP 28-/56-Bit Audio Processor with Two ADCs Four DACs ADAU1701 handbook

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