MAXIM INTEGRATED PRODUCTS MAX1144/MAX1145 Manual
Contents
1. 100 30 0 2 40 TEMPERATURE C 6 MAX1144 45 toc05 100 A e e TOTAL SUPPLY CURRENT mA 0 01 MAX1144 MAX1145 AVpp DVpp 3 3V fscLk 3 6MHz external clock 5096 duty cycle 24 clocks conversion 150ksps EF TA 25 C unless otherwise noted TOTAL SUPPLY CURRENT vs CONVERSION RATE USING SHUTDOWN 0 1 10 100 1000 CONVERSION RATE ksps MAX1144 45 toc08 MAX1144 45 toc10 SINAD PLOT 100 saMPLE 150kHz 80 sx f0 8 L2 60 e E s a zm 40 lt 30 20 10 04 1 0 100 FREQUENCY kHz THD PLOT 10 20 30 SS 40 won B 60 70 80 90 100 110 1 10 100 FREQUENCY kHz AVLAZCLAVI 14 Bit ADCs 150ksps 3 3V Single Supply Pin Description FUNCTION ADC Reference Input Connect a 2 048V voltage source to REF Bypass REF to AGND with A Zut capacitor og Supply Connect to pin 4 og Ground This is the primary analog ground star ground og Supply 3 3V 45 Bypass AVpp to AGND pin 3 with a 0 1uF capacitor al Ground down Control Input Drive SHDN low to put the ADC in shutdown mode ser Programmable Output 2 ser Programmable Output 1 4 2 3 4 5 6 7 8 9 E2. DOUT SCLK DIN and CS Bringing SHDN low places the MAX1144 MAX1145 in its 1 2uA shutdown mode A logic low on RST halts the MAX1144 MAX1145 opera tion and returns the part to its power on reset state In external clock mode SSTRB is low and pulses high for one clock cycle at the start of conversion In internal clock mode SSTRB goes low at the start of the conver sion and goes high to indicate that the conversion is finished The DIN input accepts control byte data which is clocked in on each rising edge of SCLK After CS goes MAXIM DESCRIPTION User programmable outputs follow the state of the control byte s three LSBs and are updated simultaneously when a new control byte is written Outputs are push pull In hardware and software shutdown these outputs are unchanged and remain low impedance low or after a conversion or calibration completes the first logic 1 clocked into DIN is interpreted as the START bit the MSB of the 8 bit control byte The SCLK input is the serial data transfer clock which clocks data in and out of the MAX1144 MAX1145 SCLK also drives the ADC conversion steps in external clock mode see the nternal and External Clock Modes section DOUT is the serial output of the conversion result DOUT is updated on the falling edge of SCLK DOUT is high impedance when CS is high CS must be low for the MAX1144 MAX1145 to accept a ontrol byte The serial interface is disabled when CS i
3. the first arriving logic 1 is defined as the start bit of the control byte Until this first start bit arrives any num ber of logic O bits can be clocked into DIN with no effect If at any time during acquisition or conversion CS is brought high and then low again the part is placed into a state where it can recognize a new start bit If a new start bit occurs before the current conver sion is complete the conversion is aborted and a new acquisition is initiated 10 Internal and External Clock Modes The MAX1144 MAX1145 use either the external serial clock or the internal clock to perform the successive approximation conversion In both clock modes the external clock shifts data in and out of the MAX1144 MAX1145 Bit 5 INT EXT of the control byte programs the clock mode External Clock In external clock mode the external clock not only shifts data in and out but also drives the ADC conver sion steps In short acquisition mode SSTRB pulses high for one clock period after the seventh falling edge of SCLK fol lowing the start bit The MSB of the conversion is avail able at DOUT on the eighth falling edge of SCLK Figure 2 MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply Ee TLL ELL LY Let PULU Lel LI Li UJ TIN BIP M1 MO P2 P1 PO I4 icoNv FILLED WITH ZEROS d ra SSTRB PO CLOCKED IN Figure 6 Internal
4. 1uF TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Hysteresis VHYST 0 2 V Input Capacitance CIN 10 pF DIGITAL OUTPUTS Output High Voltage IsoURCE 0 5mA ISINK SMA Output Low Voltage ISINK 16mA Three State Leakage Current CS DVpp Three State Output Capacitance POWER SUPPLIES Analog Supply 3 135 3 3 3 465 Digital Supply 3 135 3 3 3 465 Unipolar mode 3 9 8 Analog Supply Current L Bipolar mode 7 11 Unipolar or bipolar mode Digital Supply Current 2 id nd SHDN 0 or software power down mode Power Supply Rejection Ratio Note 8 AVpp DVpp 3 135V to 3 465V TIMING CHARACTERISTICS Figures 5 and 6 AVpp DVpp 3 3V 5 TA Tmin to Tmax unless otherwise noted PARAMETER SYMBOL CONDITIONS DIN to SCLK Setup DIN to SCLK Hold SCLK to DOUT Valid CS Fall to DOUT Enable CLOAD 50pF CS Rise to DOUT Disable CLOAD 50pF CS to SCLK Rise Setup D Io joa jono joao CS to SCLK Rise Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Fall to SSTRB CLOAD 50pF CS Fall to SSTRB Enable tsDv CLOAD 50pF external clock mode CS Rise to SSTRB Disable tSTR CLOAD 50pF external clock mode SSTRB Rise to SCLK Rise tscK Internal clock mode RST Pulse Width tRS 0 Ja ja joao jo 0 Jon jo 4 MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply
5. calibration starts internal calibration Software power down mode 32 external clocks per conversion long acquisition mode These three bits are stored in a port register and output to pins P2 P1 PO for use in addressing a mux or PGA These three bits are updated in the port register simultaneously when a new control byte is MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply F taca SCLK PU UCU OU Le U U LeU LO LL Le LT LP staat Be EU wi mo P2 pt Po DIN BIP SSTRB B13 DOUT 4 MSB 812 B11 B10 m WITH k Bo ee 87 ele 8 x x ND IDLE ACQUISITION CONVERSION IDLE STATE Figure 2 Short Acquisition Mode 24 Clock Cycles External Clock Table 2 User Programmable Outputs PROGRAMMED THROUGH CONTROL BYTE POWER ON OR SCHEER RST DEFAULT range is O to 2 048V unipolar or 2 048V bipolar Unipolar and bipolar mode selection is configured with bit 6 of the serial control byte Table 1 Figure 1 shows the equivalent input circuit of the MAX1144 MAX1145 The resistor network on the analog input provides 16 5V fault protection This circuit limits the current going into or out of the pin to less than 2mA The overvoltage protection is active even if the device is in a power down mode or if AVpp O Digital Interface The digital interface pins consist of SHDN RST SSTRB
6. later In external clock mode SSTRB goes high at the beginning of calibration and goes low to signal the end of calibration Calibration should be performed in the same clock mode that is used for conversions Reference The MAX1144 MAX1145 require an external reference The external reference must be bypassed with a A Zut capacitor The input impedance at REF is a minimum of 16kQ for DC currents During conversion an external reference at REF must deliver up to 150uA DC load current and have an output impedance of 10Q or less Analog Input The MAX1144 MAX1145 use a capacitive DAC that provides an inherent track hold function Drive AIN with a source impedance less than 10Q Any signal condi tioning circuitry must settle with 14 bit accuracy in less than 500ns Limit the input bandwidth to less than half the sampling frequency to eliminate aliasing The MAX1144 MAX1145 have a complex input impedance that varies from unipolar to bipolar mode Figure 1 Input Range The analog input range in unipolar mode is O to 6V for the MAX1144 and O to 2 048V for the MAX1145 In bipolar mode the analog input can be 6V to 6V for the MAX1144 or 2 048V to 2 048V for the MAX1145 Unipolar or bipolar mode is programmed with the UNI BIP bit of the control byte When using a reference other than the suggested 2 048V the full scale input range varies accordingly The full scale input range depends on the voltage at REF and the sampling mode sele
7. nonlinearity INL is the deviation of the values on an actual transfer function from a straight line This straight line can be either a best straight line fit or a line drawn between the end points of the transfer function once offset and gain errors have been nullified INL for the MAX1144 MAX1145 is measured using the end point method Differential Nonlinearity Differential nonlinearity DNL is the difference between an actual step width and the ideal value of 1LSB A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function Aperture Jitter Aperture jitter tau is the sample to sample variation in the time between the samples OUTPUT CODE FS 2 048V FS 2 048V _4 096V A 16384 0 4FS 1LSB INPUT VOLTAGE LSBs Figure 9 MAX1145 Bipolar Transfer Function 4 096V Full Scale Aperture Delay Aperture delay tap is the time between the rising edge of the sampling clock and the instant when an actual sample is taken Signal to Noise Ratio For a waveform perfectly reconstructed from digital samples signal to noise ratio SNR is the ratio of full scale analog input RMS value to the RMS quantization error residual error The ideal theoretical minimum analog to digital noise is caused by quantization error only and results directly from the ADC s resolution N bits SNR 6 02 x N 1 76 dB In reality there are other noise sources bes
8. the order of AVpp and DVpp sequencing Either supply can be present in the absence of the other Do not apply an external reference voltage until after both AVpp and DVpp are present Be sure that digital return currents do not pass through the analog ground All return current paths must be low impedance A 5mA current flowing through a PC board ground trace impedance of only 0 05Q creates an error voltage of about 250uV or about 0 5LSBs error with a 4V full scale system The board layout should ensure that digital and analog signal lines are kept separate Do not run analog and digital lines parallel to one another If you must cross one with the other do so at right angles The ADC is sensitive to high frequency noise on the AVpp power supply Bypass this supply to the analog ground plane with 0 1uF If the main supply is not ade quately bypassed add an additional 1uF or 10uF low ESR capacitor in parallel with the primary bypass capacitor MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply OUTPUT CODE A FULL SCALE mm TRANSITIO 10 FS 2 048V sde ISB ven INPUT VOLTAGE LSBs FS 3 2LSB Figure 8 MAX1145 Unipolar Transfer Function 2 048V Full Scale Transfer Function Figures 8 and 9 show the MAX1145 s transfer functions In unipolar mode the output data is in binary format and in bipolar mode it is in two s complement format Definitions Integral Nonlinearity Integral
9. to self heating Also to reduce linearity errors due to finite amplifier gain use an amplifier circuit with sufficient loop gain at the fre quencies of interest DC Accuracy If DC accuracy is important choose a buffer with an offset much less than the MAX1144 MAX1145 s maxi mum offset 6mV or whose offset can be trimmed while maintaining good stability over the required tem perature range Operating Modes and Serial Interfaces The MAX1144 MAX1145 are fully compatible with MICROWIRE and SPI QSPI devices MICROWIRE and SPI QSPI both transmit a byte and receive a byte at the same time The simplest software interface requires only three 8 bit transfers to perform a conversion one 8 bit transfer to configure the ADC and two more 8 bit transfers to clock out the 14 bit conversion result Short Acquisition Mode 24 SCLK Configure short acquisition by setting M1 0 and MO 0 In short acquisition mode the acquisition time is 5 clock cycles The total period is 24 clock cycles per conversion Long Acquisition Mode 32 SCLK Configure long acquisition by setting M1 1 and MO 1 In long acquisition mode the acquisition time is 13 clock cycles The total period is 32 clock cycles per conversion Calibration Mode A calibration is initiated through the serial interface by setting M1 O and MO 1 Calibration can be done in either internal or external clock mode though it is desir able that the part be calibrated in the sam
10. 19 2465 Rev 0 4 02 dh d al dh 14 Bit ADCs 150ksps 3 3V Single Supply General Description The MAX1144 MAX1145 are 150ksps 14 bit ADCs These serially interfaced ADCs connect directly to SPI QSPI and MICROWIRE devices without external logic They combine an input scaling network internal track hold clock and three general purpose digital output pins for external multiplexer or PGA con trol in a 20 pin SSOP package The excellent dynamic performance THD 90dB high speed 150ksps in bipolar mode and low power 8 0mA of these ADCs make them ideal for applications such as industrial process control instrumentation and medical applica tions The MAX1144 accepts input signals of O to 6V unipo lar or 6V bipolar while the MAX1145 accepts input signals of O to 2 048V unipolar or 2 048V bipolar Operating from a single 3 135V to 3 465V analog digital supply powerdown modes reduce current consump tion to 0 15mA at 10ksps and further reduce supply current to less than 20pA slower data rates A serial strobe output SSTRB allows direct connection to the TMS320 family digital signal processors The MAX1144 MAX1145 user can select either the internal clock or an external serial interface clock for the ADC to perform analog to digital conversions The MAX1144 MAX1145 feature internal calibration cir cuitry to correct linearity and offset errors On demand calibration allows the user to optimize perfor
11. 44 MAX1145 Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply ABSOLUTE MAXIMUM RATINGS AVpp to AGND DVpp to DND 0 3V to 6V AGND to DGND rre bitten 0 3V to 0 3V AINCO AGIND tette reet ent bede een ael Pe ies 16 5V CREF REF to AGND 0 3V to AVpp 0 3V Digital Inputs to DOND ren 0 3V to 6V Digital Outputs to DGND Continuous Power Dissipation TA 70 C 20 Pin SSOP derate 8 00mW C above 70 C 640mW 0 3V to DVpp 0 3V Operating Temperature Ranges MAX114 CAP inertes 0 C to 70 C MAXIA EAP iactat E e pde 40 C to 85 C Storage Temperature Range 60 C to 150 C Junction Temperature 150 C Lead Temperature soldering 10s 300 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS AVpp DVpp 3 3V 5 fscLk 3 6MHz external clock 50 duty cycle 24 cloc
12. Clock Mode SSTRB Detailed Timing In long acquisition mode SSTRB pulses high for one clock period after the 15th falling edge of SCLK follow ing the start bit The MSB of the conversion is available at DOUT on the 16th falling edge of SCLK Figure 3 In external clock mode SSTRB is high impedance when CS is high Figure 4 In external clock mode CS is normally held low during the entire conversion If CS goes high during the conversion SCLK is ignored until CS goes low This allows external clock mode to be used with 8 bit bytes Internal Clock In internal clock mode the MAX1144 MAX1145 generate their own conversion clock This frees the microprocessor from the burden of running the SAR conversion clock MAXIM NOTE FOR BEST NOISE PERFORMANCE KEEP SCLK LOW DURING CONVERSION and allows the conversion results to be read back at the processor s convenience at any clock rate up to 4MHz SSTRB goes low at the start of the conversion and goes high when the conversion is complete SSTRB will be low for a maximum of Zus during which time SCLK should remain low for best noise performance An inter nal register stores data when the conversion is in progress SCLK clocks the data out of the internal stor age register at any time after the conversion is complete The MSB of the conversion is available at DOUT when SSTRB goes high The subsequent 13 falling edges on SCLK shift the remaining bits out of the internal storage regist
13. GITAL OUTPUT CODE vs DIGITAL OUTPUT CODE vs TEMPERATURE 1 0 1 0 a T 3 A AVpp DVpp 3 135V 8 un am 0 8 B AVpp DVpp 3 3V E a E n E C AVpp DVpp 3 465V E 8 0 6 E 0 6 Z B DD V VDD E 04 04 E a ce Ss 02 02 e 2 a E 0 2 0 z 02 z 02 5 z E 3 5 04 E 0 4 z Z Ap A 2 0 8 0 8 1 0 1 0 j 3413 6825 10237 13649 1 3413 6825 10237 13649 40 20 0 20 40 60 80 1707 5119 8531 11943 15355 1707 5119 8531 11943 15355 TEMPERATURE C DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE MAXIM 5 SVLELXVIN DULELXVIN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply bipolar input REF 2 048V 4 7uF on R OFFSET ERROR mV i o on us E RU n2 o n2 on A AVpp DVpp 3 135V B AVpp DVpp 3 3V C AVpp DVpp 3 465V OFFSET VOLTAGE vs TEMPERATURE MAX1144 45 toc04 RROR FULL SCALE Typical Operating Characteristics continued EF 1uF on CR GAIN ERROR vs TEMPERATURE GAIN AMPLITUDE dB 110 100 0 20 4 EMPERATURE C 60 80 FFT PLOT PLE 150kHz 5kHz A AVpp DVpp 3 135V B AVpp DVpp 3 3V C AVpp DVpp 3 465V MAX1144 45 toc07 fSAMPLE 150kHz MAX1144 45 toc09 AMPLITUDE dB 0 1 1 FREQUENCY kH N
14. N A erial Strobe Output In internal clock mode SSTRB goes low when the ADC begins a conversion and goes igh when the conversion is finished In external clock mode SSTRB pulses high for one clock period before the MSB decision It is high impedance when CS is high in external clock mode U U User Programmable Output 0 S h Serial Data Output MSB first straight binary format for unipolar input two s complement for bipolar input Each bit is clocked out of DOUT at the falling edge of SCLK E no EN wo Reset Input Drive RST low to put the device in the power on default mode See the Power On Reset section Serial Data Clock Input Serial data on DIN is loaded on the rising edge of SCLK and serial data is updated on DOUT on the falling edge of SCLK In external clock mode SCLK sets the conversion speed JA Digital Ground Connect to pin 5 o Digital Supply 3 3V 5 Bypass DVpp to DGND pin 14 with a 0 1uF capacitor EN Oo N Serial Data Input Serial data on DIN is latched on the rising edge of SCLK Chip Select Input Drive CS low to enable the serial interface When CS is high DOUT is high impedance In external clock mode SSTRB is high impedance when CS is high a a o Reference Buffer Bypass Bypass CREF to AGND pin 3 with 1yF Analog Ground Connect to pin 3 n2 e MAXIM Analog Input SVLELXVIN DVLELXVIN MAX1144 MAX1145 14 Bit ADCs 150ks
15. TIMING CHARACTERISTICS Figures 5 and 6 continued AVpp DVpp 3 3V 596 TA Tmin to Tmax unless otherwise noted Note 1 Tested at AVpp DVpp 3 3V bipolar input mode Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nullified Note 3 Offset nullified Note 4 Conversion time is defined as the number of clock cycles multiplied by the clock period clock has 5096 duty cycle Includes the acquisition time Note 5 Acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode Note 6 Performance is limited by the converter s noise floor typically 300pVp p Note 7 When an external reference has a different voltage than the specified typical value the full scale of the ADC scales propor tionally Note 8 Defined as the change in positive full scale caused by a 5 variation in the nominal supply voltage Typical Operating Characteristics MAX1144 MAX1145 AVpp DVpp 3 3V fscLk 3 6MHz external clock 50 duty cycle 24 clocks conversion 150ksps bipolar input REF 2 048V 4 7yF on REF 1uF on CREF TA 25 C unless otherwise noted INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY TOTAL SUPPLY CURRENT vs DI
16. YMBOL CONDITIONS MIN TYP Unipolar 7 5 10 5 Bipolar 5 9 8 4 Unipolar 100 1000 Bipolar 3 4 5 3 Input Capacitance 32 CONVERSION RATE Internal Clock Frequency MAX1144 Input Impedance MAX1145 Aperture Delay tAD Aperture Jitter tad MODE 1 24 EXTERNAL CLOCK CYCLES PER CONVERSION Unipolar External Clock Frequency fSCLK Bipolar fg Sample Rate S fscLk 24 Bipolar Unipolar tCONV ACQ 24 fSCLK Bipolar Conversion Time Note 4 MODE 2 INTERNAL CLOCK External Clock Frequency Data Transfer Only Conversion Time SSTRB low pulse width Unipolar Acquisition Time Note 5 EDS ipolar MODE 3 32 EXTERNAL CLOCK CYCLES PER CONVERSION External Clock Frequency fSCLK Unipolar or bipolar fg Unipolar or bipolar fscLk 32 P E Sample Rate tCONV ACQ Unipolar or bipolar 32 SCLK 2 P Conversion Time Note 4 EXTERNAL REFERENCE Input Range Notes 6 7 VREF 2 048V fscLK 3 6MHz Input Current VREF 2 048V fscLk 0 In power down fscLk 0 DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Vin 0 or DVpp MAXIM 3 SbPLLXVM bPbLLXVMN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply ELECTRICAL CHARACTERISTICS continued AVpp DVpp 3 3V 5 fscLk 3 6MHz external clock 50 duty cycle 24 clocks conversion 150ksps bipolar input VREF 2 048V CREF 4 7UF CcREF
17. aTion N MILLIMETERS e PACKAGE OUTLINE SSOP 5 3x 65mm APPROVAL DOCUMENT CONTROL NO 21 0056 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 18 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2002 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
18. cted Tables 3 and 4 MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply Figure 7 AIN Buffer for AC DC Use Input Acquisition and Settling Clocking in a control byte starts input acquisition The main capacitor array starts acquiring the input as soon as a start bit is recognized using the same input range as the previous conversion If the opposite input range is selected by the second DIN bit the part immediately switches to the new sampling mode Acquisition time is one and a half clock cycles shorter when switching from unipolar to bipolar or bipolar to unipolar modes than when continuously converting in the same mode Acquisition can be extended by eight clock cycles by setting M1 1 and MO 1 long acquisition mode The sampling instant in short acquisition completes on the falling edge of the sixth clock cycle after the start bit Figure 2 Acquisition is 5 clock cycles in short acquisi tion mode and 13 clock cycles in long acquisition mode Short acquisition mode is 24 clock cycles per conversion Using the external clock to run the conver sion process limits unipolar conversion speed to 125ksps instead of 150ksps as in bipolar mode The input resistance in unipolar mode is larger than that of bipolar mode Figure 1 The RC time constant in unipo lar mode is larger than that of bipolar mode reducing the maximum conversion rate in 24 external clock mode Long acquisition mode with external clock allows b
19. e mode in which it will be used to do conversions The part remains in calibration mode for approximately 80 000 14 clock cycles unless the calibration is aborted Calibr ation is halted if RST or SHDN goes low or if a valid start condition occurs Software Shutdown A software power down is initiated by setting M1 1 and MO O After the conversion completes the part shuts down It reawakens upon receiving a new start bit Conversions initiated with M1 1 and MO 0 shut down use the acquisition mode selected for the previ OUS conversion Shutdown Mode The MAX1144 MAX1145 may be shut down by pulling SHDN low or by asserting software shutdown In addi tion to lowering power dissipation to 4uW considerable power can be saved by shutting down the conv erter for short periods between conversions There is no need to perform a calibration after the converter has been shut down unless the time in shutdown is long enough that the supply voltage or ambient temperature may have changed Supplies Layout Grounding and Bypassing For best system performance use separate analog and digital ground planes The two ground planes should be tied together at the MAX1144 MAX1145 Use pin 3 and pin 14 as the primary AGND and DGND respec tively If the analog and digital supplies come from the same source isolate the digital supply from the analog with a low value resistor 10 The MAX1144 MAX1145 are not sensitive to
20. e the MAX1144 MAX1145 with the same clock mode used for performing conversions Offsets resulting from synchronous noise such as the conversion clock are canceled by the MAX1144 MAX1145 s calibration circuitry However because the magnitude of the offset produced by a synchronous signal depends on the signal s shape recalibration may be appropriate if the shape or relative timing of the Clock or other digital signals change as may occur if more than one clock signal or frequency is used Input Scaler The MAX1144 MAX1145 have an input scaler which allows conversion of true bipolar input voltages while operating from a single 3 3V supply The input scaler attenuates and shifts the input as necessary to map the external input range to the input range of the internal ADC The MAX1144 analog input range is O to 6V unipolar or 6V bipolar The MAX1145 analog input DESCRIPTION 7 MSB START The first logic 1 bit after CS goes low defines the beginning of the control byte 1 unipolar O bipolar Selects unipolar or bipolar conversion mode In unipolar mode analog input signals from O to 6V MAX1144 or O to VREF MAX1145 can be converted In bipolar mode analog input signals from 6V to 6V MAX1144 or VREF to VREF MAX1145 can be converted Selects the internal or external conversion clock 1 internal O external MO Mode 24 external clocks per conversion short acquisition mode Start
21. er Figure 5 CS does not need to be held low once a conversion is started 11 SbPLLXVM bPbLLXVMN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply Table 3 Unipolar Full Scale and Zero Scale PART ZERO SCALE FULL SCALE 6 VREF 2 048 VREF MAX1144 0 MAX1145 0 When internal clock mode is selected SSTRB does not go into a high impedance state when CS goes high Figure 6 shows the SSTRB timing in internal clock mode In internal clock mode data can be shifted into the MAX1144 MAX1145 at clock rates up to 4MHz pro vided the minimum acquisition time taca is kept above 1 39us in bipolar mode and 1 67us in unipolar mode Data can be clocked out at 4MHz Output Data The output data format is straight binary for unipolar conversions and two s complement in bipolar mode The MSB is shifted out of the MAX1144 MAX1145 first in both modes MN Data Framing The falling edge of CS does not start a conversion on the MAX1144 MAX1145 The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte A conversion starts on the falling edge of SCLK after the seventh bit of the control byte the P1 bit is clocked into DIN The start bit is defined as e The first high bit clocked into DIN with CS low any time the converter is idle e g after AVpp is applied e The first high bit clocked into DIN after CS is pulsed high then low If a falling edge on CS force
22. ides quanti zation noise including thermal noise reference noise clock jitter etc Therefore SNR is calculated by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamen tal the first five harmonics and the DC offset 15 MAXIM SbPLLXVM bPbLLXVMN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply Signal to Noise Plus Distortion Signal to noise plus distortion SINAD is the ratio of the fundamental input frequency s RMS amplitude to the RMS equivalent of all other ADC output signals SINAD dB 20 x log SignalgMs NoiseRMS Total Harmonic Distortion Total harmonic distortion THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself This is expressed as v 4 Va v4 ei Vi THD 20 x log where V1 is the fundamental amplitude and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics Spurious Free Dynamic Range Spurious free dynamic range SFDR is the ratio of RMS amplitude of the fundamental maximum signal compo nent to the RMS value of the next largest distortion component Functional Diagram MAXIM MAX1144 MAX1145 INPUT SCALING ETWORK COMPARATOR ALOG TIMING CONTROL wewory CONTROL 16 CALIBRATION ENGINE MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply Typical Applicat
23. ion Circuit Ordering Information continued PIN INL PACKAGE LSB MAX1145ACAP 0 C to 70 C 20 SSOP MAX1145BCAP 0 C to 70 C 20 SSOP MAX1145AEAP 40 C to 85 C 20 SSOP MAX1145BEAP 40 C to 85 C 20 SSOP AN MAXIN MAX1144 Chip Information TRANSISTOR COUNT 21 807 PROCESS BiCMOS MAXIM 17 SbPLLXVM bPbLLXVMN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply Package Information The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages INCHES MILLIMETERS MIN MAX MIN MAX 068 0 078 1 73 1 99 002 0 008 0 05 0 21 010 0 015 025 10 38 004 0 008 0 09 0 20 SEE VARIATIONS 205 0 209 5 20 5 38 0256 BSC 0 65 BSC 301 0 311 7 65 7 90 025 0 037 0 63 0 95 0 8 0 8 SSOP EPS MILLIMETERS MIN MAX 6 07 6 33 6 07 6 33 7 07 7 33 8 07 8 33 10 07 10 33 To mjic o u Q C hx J 4 INCLUDE MOLD FLASH SSVI AXIAVI RUSIONS N E CE 15mm 6 006 proprietary inrorw
24. ks conversion 150ksps bipolar input VREF 2 048V CREF 4 7ypF CcREF 1uF TA Tmin to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS DC ACCURACY Note 1 Resolution Relative Accuracy Bipolar mode Note 2 MAX114 B No Missing Codes 14 Differential Nonlinearity DNL Bipolar mode MAX114 A 1 MAX114 B 1 00 Transition Noise Offset Error Unipolar Gain Error Note 3 Bipolar Offset Drift Bipolar and Unipolar Excluding reference drift Gain Drift Bipolar and Unipolar Excluding reference drift DYNAMIC SPECIFICATIONS 5kHz SINE WAVE INPUT 150ksps 3 6MHZ CLOCK BIPOLAR INPUT MODE MAX1144 12Vp p MAX1145 4 096Vp p Signal to Noise Plus Distortion SINAD 5k 82 75 dB Signal to Noise Ratio SNR Total Harmonic Distortion THD 5k 75 Spurious Free Dynamic Range SFDR ANALOG INPUT Input Range MAX1144 Unipolar Bipolar MAX1145 Unipolar Bipolar MAXIM 14 Bit ADCs 150ksps 3 3V Single Supply ELECTRICAL CHARACTERISTICS continued AVpp DVpp 3 3V 5 fscLk 3 6MHz external clock 50 duty cycle 24 clocks conversion 150ksps bipolar input VREF 2 048V CREF 4 7ypF CcREF 1uF TA TMiN to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER S
25. mance Three user programmable logic outputs are provided for the control of an 8 channel mux or PGA The MAX1144 MAX1145 are available in a 20 pin SSOP package and are fully specified over the 40 C to 85 C temperature range Applications Industrial Process Control Industrial UO Modules Data Acquisition Systems Medical Instruments Portable and Battery Powered Equipment Functional Diagram and Typical Application Circuit appear at end of data sheet SPI and QSPI are trademarks of Motorola Inc MICROWIRE is a trademark of National Semiconductor Corp MAXIM Features 150ksps Bipolar and 125ksps Unipolar Sampling ADC 14 Bits No Missing Codes 1LSB INL Guaranteed 100dB THD 3 3V Single Supply Operation Low Power Operation 5mA typ Unipolar Mode 1 20A Shutdown Mode Software Configurable Unipolar and Bipolar Input Ranges 0 to 6V and 6V MAX1144 0 to 2 048V and 2 048V MAX1145 Internal or External Clock SPI QSPI MICROWIRE TMS320 Compatible Serial Interface Three User Programmable Logic Outputs Small 20 Pin SSOP Package ete 9 9 SbPLLXVM bPbLLXVMN Ordering Information TEMP PIN INL RANGE PACKAGE LSB MAX1144ACAP 0 C to 70 C 20 SSOP MAX1144BCAP 0 C to 70 C 20 SSOP MAX1144AEAP 40 C to 85 C 20 SSOP t MAX1144BEAP 40 C to 85 C 20 SSOP 2 PART Ordering Information continued at end of data sheet Pin Configuration TOP VIEW MAXIM MAX11
26. o the sampling interval an effective input offset is pro duced Asynchronous signals produce random noise on the input whose high frequency components may be aliased into the frequency band of interest Minimize noise by presenting a low impedance at the frequen cies contained in the noise signal at the inputs This requires bypassing AIN to AGND or buffering the input with an amplifier that has a small signal bandwidth of several MHz or preferably both AIN has a bandwidth of about 4MHz Offsets resulting from synchronous noise such as the conversion clock are canceled by the MAX1144 MAX1145 s calibration scheme However because the 13 SbPLLXVM PbLLXVMN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply magnitude of the offset produced by a synchronous signal depends on the signal s shape recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change which can occur if more than one clock signal or frequency is used Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX1144 MAX1145 s THD 90dB at frequencies of interest If the chosen amplifier has insufficient com mon mode rejection which results in degraded THD performance use the inverting configuration to elimi nate errors from common mode voltage Low tempera ture coefficient resistors reduce linearity errors caused by resistance changes due
27. oth unipolar and bipolar sampling of 112ksps as 3 6MHz 32 clock cycles by adding eight extra clock cycles to the conversion Most applications require an input buffer amplifier If the input signal is multiplexed the input channel should be switched immediately after acquisition rather than near the end of or after a conversion This allows more time for the input buffer amplifier to respond to a large step change in input signal The input amplifier must MAXIM 0 0033uF have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time At the beginning of acquisition the capacitive DAC is connected to the amplifier output causing some output disturbance Ensure that the sampled voltage has set tled to within the required limits before the end of the acquisition time If the frequency of interest is low AIN can be bypassed with a large enough capacitor to charge the capacitive DAC with very little change in voltage However for AC use AIN must be driven by a wideband buffer at least 10MHz which must be sta ble with the DAC s capacitive load in parallel with any AIN bypass capacitor used and also must settle quickly Figure 7 Digital Noise Digital noise can couple to AIN and REF The conver sion clock SCLK and other digital signals that are active during input acquisition contribute noise to the conversion result If the noise signal is synchronous t
28. ps 3 3V Single Supply Detailed Description The MAX1144 MAX1145 ADCs use a successive approximation technique and input track hold T H cir cuitry to convert an analog signal to a 14 bit digital output The MAX1144 MAX1145 easily interface to microprocessors uPs The data bits can be read either during the conversion in external clock mode or after the conversion in internal clock mode BIPOLAR o VOLTAGE REFERENCE q C TRACK AF S2 A UNIPOLAR T H OUT HOLD S3 t HOLD TRACK S1 BIPOLAR UNIPOLAR S2 S3 T H SWITCH R2 7 6kQ MAX1144 OR 2 5KQ MAX1145 R3 3 9KQ MAX1144 OR INFINITY MAX1145 Figure 1 Equivalent Input Circuit Table 1 Control Byte Format BIT NAME In addition to a 14 bit ADC the MAX1144 MAX1145 include an input scaler an internal digital microcontroller calibration circuitry and an internal clock generator The input scaler for the MAX1144 enables conversion of input signals ranging from O to 6V unipolar input or 6V bipolar input The MAX1145 accepts O to 2 048V unipolar input or 2 048V bipolar input Input range is software selectable Calibration To minimize linearity offset and gain errors the MAX1144 MAX1145 have on demand software calibra tion Initiate calibration by writing a control byte with bit M1 O and bit MO 1 Table 1 Select internal or exter nal clock for calibration by setting the INT EXT bit in the control byte Calibrat
29. s igh g 2 0 User Programmable Outputs The MAX1144 MAX1145 have three user programma ble outputs PO P1 and P2 The power on default state for the programmable outputs is zero These are push ull CMOS outputs suitable for driving a multiplexer a PGA or other signal preconditioning circuitry Bits O 1 and 2 of the control byte control the user programma ble outputs Tables 1 2 xe SPLLXVM bPbLLXVMN MAX1144 MAX1145 14 Bit ADCs 150ksps 3 3V Single Supply TT I taca sx LE O UU O U Au Jet W NY wr mo P2 pi Po SSTRB 31 c Liu erh LL Le DOUT 4 B13 8 FILLED WITH Msg 812 B11 B2 B1 X X mp CONVERSION A D IDLE ACQUISITION STATE Figure 3 Long Acquisition Mode 32 Clock Cycles External Clock an IDLE Jemp mm eem L4 X oe In CLOCKED IN Figure 4 External Clock Mode SSTRB Detailed Timing The user programmable outputs are set to zero during power on reset or when RST goes low During hardware or software shutdown PO P1 and P2 are unchanged and remain low impedance Starting a Conversion Start a conversion by clocking a control byte into the device s internal shift register With CS low each rising edge on SCLK clocks a bit from DIN into the MAX1144 MAX1145 s internal shift register After CS goes low or after a conversion or calibration completes
30. s a start bit before the con version or calibration is complete then the current operation terminates and a new one starts Applications Information Power On Reset When power is first applied to the MAX1144 MAX1 145 or if RST is pulsed low the internal calibration registers are set to their default values The user programmable registers PO P1 and P2 are low and the device is configured for bipolar mode with internal clocking Calibration Periodically calibrate the MAX1144 MAX1145 to com pensate for temperature drift and other variations After any change in ambient temperature more than 10 C the device should be recalibrated A 100mV change in supply voltage or any change in the reference voltage should be followed by a calibration Calibration cor 12 Table 4 Bipolar Full Scale Zero Scale and Negative Scale NEGATIVE FULL ZERO SCALE SCALE PURE Sarr MAX1144 6 VREF 2 048 6 VREF 2 048 rects for errors in gain offset integral nonlinearity and differential nonlinearity The MAX1144 MAX1145 should be calibrated after power up or after the assertion of reset Make sure the power supplies and the reference voltage have fully settled prior to initiating the calibration sequence Initiate calibration by setting M1 O and MO 1 in the control byte In internal clock mode SSTRB goes low at the beginning of calibration and goes high to signal the end of calibration approximately 80 000 clock cycles
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MAXIM INTEGRATED PRODUCTS MAX1144/MAX1145 Manual