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IDT IDT72421 IDT72201 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 Manual

1. CMOS SyncFIFO IDT72421 1DT72201 64 x 9 256 x 9 512 x 9 IDT72211 1DT72221 1 024 x 9 2 048 x 9 IDT72231 IDT72241 e 4 096 9 8 192 9 IDT72251 FEATURES DESCRIPTION e 64x 9 bit organization IDT72421 The IDT72421 72201 72211 72221 72231 72241 72251 SyncFIFO e 256 x 9 bit organization IDT72201 are very high speed low power First In First Out FIFO memories with e 512 x 9 bit organization IDT72211 clocked read and write controls These devices have a 64 256 512 1 024 e 1 024 x 9 bit organization IDT72221 2 048 4 096 and8 192 x 9 bitmemory array respectively These FIFOs are e 2 048 x 9 bit organization IDT72231 applicable fora wide variety of data buffering needs such as graphics local area 4 096 x 9 bit organization IDT72241 networks and interprocessor communication 8 192 x 9 bit organization IDT72251 These FIFOs have 9 bitinput and output ports The input portis controlled e 10ns read write cycle time by a free running clock WCLK and two write enable pins WEN1 WEN2 e Read and Write Clocks can be independent Data is written into the Synchronous FIFO on every rising clock edge when the Dual Ported zero fall through time architecture write enable pins are asserted The output portis controlled by another clock e Empty and Full Flags signal FIFO status pin RCLK and two read enable pins REN1 REN2 The Read Clock can e Programmable Almost Empty and Almost Full flags can be set be tied to t
2. AL o 8 V 0 8 7 0 SX _ fut set 88 Re Default Value 007H _ Defauit value 0 8 1 0 8 1 0 00 00502 06 06274 1 o IDT72231 2 048 x 9 BIT IDT72241 4 096 x 9 BIT IDT72251 8 192 x 9 BIT 8 7 0 7 0 8 7 0 E Empty Offset LSB Reg VESTITI N Default Value 0074 LN Default Value 007H NN Default Value 007H 8 2 0 8 3 0 8 4 0 lt 1 v 8 amp 8 7 0 8 amp 8 7 0 8 7 0 ST eem ST meum N DefautValue007H Z N Default Value 007H Default Value 007H 8 8 3 0 8 4 0 9 2655 drw 05 Figure 3 Offset Register Location and Default Values 10 72421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 OUTPUTS FULL FLAG FF The Full Flag FF will go LOW inhibiting further write operation when the device is full If no reads are performed after Reset RS the Full Flag FF will go LOW after 64 writes for the IDT72421 256 writesforthe IDT72201 512 writes for the IDT72211 1 024 writes for the 10772221 2 048 writes for the IDT72231 4 096 writes forthe IDT72241 and8 192 writes forthe IDT72251 The Full Flag FF is synchronized with respect to the LOW to HIGH transition of the Write Clock EMPTY FLAG EF The Empty Flag EF
3. DEPTH EXPANSION The IDT72421 72201 72211 72221 72231 72241 72251 can be adaptedto applications when the requirements are for greater than 64 256 512 1 024 2 048 4 096 8 192 words The existence of two enable pins on the read and write port allow depth expansion The Write Enable 2 Load pin is used as a second write enable in a depth expansion configuration thus the Programmable flags are setto the defaultvalues Depth expansion is possible by using one enable input for system control while the other enable inputis controlled by expansion logic to direct the flow of data A typical application would have the expansion logic alternate data access from one device to the next in asequential manner These devices operate in the Depth Expansion configuration when the following conditions are met 1 The WEN2 LD pinis held HIGH during Reset so that this pin operates a second Write Enable 2 External logic is used to control the flow of data Please see the Application Note DEPTH EXPANSION OF IDT S SYN CHRONOUS FIFOs USING THE RING COUNTER APPROACH for details ofthis configuration RESET RS READ CLOCK RCLK READ ENABLE 1 REN1 OUTPUT ENABLE OE DATA OUT Qo Qs EMPTY FLAG EF PROGRAMMABLE ALMOST EMPTY PAE READ ENABLE 2 REN2 2655 drw 16 Figure 14 Block Diagram of Single 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 8 192 x 9 Synchronous FIFO DATA OUT Q READ ENABLE 2 REN2 2655 drw 17 Figure 15 Bloc
4. tSKEW1 The Latency Timings apply only at the Empty Boundary EF LOW Figure 9 Empty Flag Timing E ru IDT72421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES tCLKH tCLKL 4 WCLK tENS tENS N 77 tENH If diplicalle P WA PAF Full m 1 words in FIFO Full m words in FIFO 3 tekewo tPAF tPAF 2655 drw 12 NOTES 1 m PAF offset 2 64 m words in FIFO for IDT72421 256 m words for IDT72201 512 m words for IDT72211 1 024 m words for IDT72221 2 048 m words for 10172231 4 096 m words for IDT72241 and 8 192 m words for IDT72251 3 tskEW is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle If the time between the rising edge of RCLK and the rising edge of WCLK is less than tskew2 then PAF may not change state until the next WCLK rising edge 4 f a write is performed on this rising edge of the Write Clock there will be Full m 1 words in the FIFO when PAF goes LOW Figure 10 Programmable Full Flag Timing TCLKH tCLKL WCLK 7 tENH WENT tENS N 7 tENH WEN2 z TS If Applicable 227 NN PAE n words in FIFO n 1 words in FIFO 2 tskEw2 RCLK ENS 777 tENH RENI We cu 2655 drw 13 NOTES 1 n PAE
5. the FIFO ifthe FF is LOW WEN2 Write Enable 2 The FIFO is configured at reset to have either two write enables or programmable flags If WEN2 LD is HIGH at reset this pin operates as a second write enable If WEN2 LD is LOW at reset this pin operates as a control to load andread the programmable flag offsets Ifthe FIFO is configured to have two write enables WENT must be LOW and WEN2 must be HIGH to write data into the FIFO Data will not be written into the FIFO if the FF is LOW Ifthe FIFO is configured to have programmable flags WEN2 LD is held LOW to write or read the programmable flag offsets Data outputs for a 9 bit bus Data is read from the FIFO on a LOW to HIGH transition of RCLK when REN1 and REN2 are asserted When and REN2 are LOW data is read from the FIFO on every LOW to HIGH transition of RCLK Data will not be read from the FIFO ifthe EF is LOW When and REN2 are LOW data is read from the FIFO on every LOW to HIGH transition of RCLK Read Enable 2 Data will not be read from the FIFO ifthe EF is LOW 0 When is LOW the data output bus is active If OE is HIGH the output data bus will be in a high impedance li E E Output Enable state EF Empty Flag When EF is LOW the FIFO is empty and further data reads from the output are inhibited When EF is HIGH the FIFO is not empty EF is synchronized to RCLK PA c K Read Clock Read Enable 1 2 d 050 1 m 2 N
6. Clock WCLK Datais stored inthe RAM array sequentially and independently of any ongoing read operation Inthis configuration when Write Enable 1 WEN1 isHIGH the input register holds the previous data and no newdatais allowed to be loadedinto the register Ifthe FIFO is configured to have two write enables which allows for depth expansion there are two enable control pins See Write Enable 2 paragraph below for operation in this configuration Toprevent data overflow the Full Flag FF will go LOW inhibiting further write operations Upon the completion of a valid read cycle the Full Flag FF will go HIGH after twFF allowing a valid write to begin Write Enable 1 WEN is ignored when the FIFO is full READ CLOCK RCLK Data can be readon the outputs on the LOW to HIGH transition ofthe Read Clock RCLK The Empty Flag EF and Programmable Almost Empty flag PAE are synchronized with respectto the LOW to HIGH transition of RCLK The Write and Read Clocks can be asynchronous or coincident READ ENABLES RENT REN2 When both Read Enables REN1 2 are LOW data is read from the RAM array to the output register on the LOW to HIGH transition ofthe Read Clock RCLK When either Read Enable REN1 REN2 is HIGH the output register holds the previous data and no new data is allowed to be loaded into the register When all the data has been read from the FIFO the Empty Flag EF will go LOW inhibiting further read oper
7. and tri state if OE 1 3 clocks RCLK WCLK can be free running during reset Figure 4 Reset Timing tCLKH 3 WCLK tDH 6 020 420100010101010 620000107 DATA IN VALID WENT NO OPERATION tENS TENH If d SANS NO OPERATION O RCLK 2655 drw 07 REN2 NOTE 1 tskew1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle If the time between the rising edge of RCLK and the rising edge of WCLK is less than tskew1 then FF may not change state until the next WCLK edge Figure 5 Write Cycle Timing T IDT72421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURERANGES tCLK tCLKH tCLKL RCLK tENS RENT ENE 1021 NOOPERATION tA Qo Qa VALID DATA 2 cn E tekewi WCLK WEN2 S 2655 drw 08 NOTE 1 tskew1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle If the time between the rising edge of RCLK and the rising edge of WCLK is less than tskew1 then EF not change state until the next edge Figure 6 Read Cycle Timing WCLK DS XOOQOOK hh X o X e OX om D TENS Do First V
8. less When these FIFOs are ina Single Device Configuration the Read Enable 2 REN2 control input can be grounded see Figure 14 In this configuration the Write Enable 2 Load WEN2 LD pinis set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting the corresponding input controls signals of multiple devices Acomposite flag shouldbe created for each of the endpointstatus flags EF and FF The partial status flags AE and AF can be detected from any one device Figure 15 demonstrates a 18 bit word width by using two IDT72421 72201 7221 1 72221 72231 72241 72251s Any word width can be attained by adding additional IDT72421 72201 72211 72221 72231 72241 72251s When these FIFOs are in a Width Expansion Configuration the Read Enable 2 2 control input can be grounded see Figure 15 In this WRITE CLOCK WCLK WRITE ENABLE 1 WENT WRITE ENABLE 2 LOAD WEN2 LD DATA IN Do Ds FULL FLAG FF PROGRAMMABLE ALMOST FULL PAF RESET RS DATA IN D WRITE CLOCK WCLK WRITE 1 WEN1 WRITE ENABLE2 LOAD WEN2 LD FULL FLAG FF 1 FULL FLAG FF 2 PROGRAMMABLE PAF READ ENABLE 2 REN2 TEMPERATURE RANGES configuration the Write Enable 2 Load WEN2 LD pin is LOW at Reset so thatthe pin operates as acontroltoloadand read the programmable flag offsets
9. 1 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 AC ELECTRICAL CHARACTERISTICS Commercial Vcc 5V 10 TA 0 C to 70 C Industrial Voc 5V 10 40 to e amp Ind l 10772421125 10772201125 10772211125 10772221125 10772231125 10772241125 10772251125 10772421110 10772421115 10772201110 10772201115 10772211110 10772211115 10772221110 10772221115 10772231110 10772231115 10772241110 10772241115 10772251110 10772251115 Parameter i tsKewe Skew time between Read Clock amp Write Clock for 18 Almost Empty Flag amp Programmable Almost Full Flag NOTES 1 Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product 2 Pulse widths less than minimum values are not allowed 3 Values guaranteed by design not currently tested 5V AC TEST CONDITIONS In Pulse Levels Input Rise Fall Times 1 1K Input Timing Reference Levels Output Reference Levels D U T Output Load See Figure 1 6800 Supp CAPACITANCE ta 25 C f 1 0MHz Symbol Parameter Conditions Unit input Capacitance pF a Court OutputCapacitance Vout 0V pF NOTES qu d Figure 1 Output Load includes jig and scope capacitances 1 With output deselected OE gt 2 Characterized values not currently tested IDT7
10. 2421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 SIGNAL DESCRIPTIONS INPUTS DATA IN 00 D8 Data inputs for 9 bit wide data CONTROLS RESET RS Reset is accomplished whenever the Reset RS inputis taken to a LOW state During reset both internal read and write pointers are set to the first location Aresetis required after power up before a write operation can take place The Full Flag FF and Programmable Almost Fullflag PAF willbe reset to HIGHaftertRsF The Empty Flag EF and Programmable Almost Empty flag PAE willbe resetto LOW after tRSF During reset the output register is initialized to allzeros andthe offset registers are initialized to their default values WRITE CLOCK WCLK Awrite cycleis initiated on the LOW to HIGH transition of the Write Clock WCLK Data setup andhold times must be metin respectto the LOW to HIGH transition of WCLK The Full Flag and Programmable Almost Full flag PAF are synchronizedwith respectto the LOW to HIGH transition of WCLK The Write and Read Clocks can be asynchronous or coincident WRITE ENABLE 1 Ifthe FIFO is configured for programmable flags Write Enable 1 WENT isthe only enablecontrolpin In this configuration when Write Enable 1 WENT isLOW data canbe loadedinto the input registerand RAM array on the LOW to HIGH transition ofevery Write
11. E will go HIGH after 1 for the IDT72421 72201 72211 72221 72231 72241 72251 Ifthereis no Empty offset specified the Programmable Almost Empty flag PAE will go LOW at Empty 7 words The Programmable Almost Empty flag PAE is synchronized with respect to the LOW to HIGH transition of the Read Clock RCLK DATA OUTPUTS Qo Q8 Data outputs for a 9 bit wide data H H H H H o SemPes oa oL pon os o NUMBER OF WORDS IN FIFO n 1 to 1 024 m 1 n 1 to 2 048 1 n 1 to 4 096 m 1 n 1 to 8 192 m 1 1 024 m t01 023 2 048 202 047 4 096 2 104 095 8 192 2 108 191 1024 8192 NOTES 1 n Empty Offset 7 default value 2 m Full Offset m 7 default value IDT72421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES tRS RS I tRSS OQO 7 tRSF tRSF E 1 Qo Qs E ES DU 0 2655 drw 06 NOTES E 1 Holding WEN2 LD HIGH during reset will make the pin act as a second write enable pin Holding WEN2 LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers EN eu 2 After reset the outputs will be LOW if OE 0
12. Programmable When PAE is LOW the FIFO is almost empty based onthe offsetprogrammed into the FIFO The default Almost Empty Flag offset at reset is Empty 7 PAE is synchronized to RCLK AF Programmable When PAF is LOW the FIFOis almost full based on the offset programmed into the FIFO The default offset Almost Full Flag at reset is Full 7 PAF is synchronized to WCLK Full Flag When FF is LOW the FIFO is full and further data writes into the input are inhibited When FF is HIGH the FIFO isnot full FF is synchronized to WCLK One 5 volt power supply pin One 0 volt ground pin N Voc 0 10772421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING Symbol Rating Unit CONDITIONS Vrerm Terminal Voltage with 0 5to 47 0 V Symbol Parameter Min Typ Max Unit Respectto GND Voc Supply Voltage 45 50 55 V Commercial Industrial Supply Voltage Input High Voltage 0 Commercial Industrial Storage Temperature b510 125 DC Output Current 50 to 50 NOTE 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause InputLow Voltage permanent damage to the device This is stress rating only and functional operation Commercial Industrial of the device at these or any other c
13. alid Write WENT SX tENS If K T RCLK Qo Qe gt 1012 2655 drw 09 1 When tskew1 gt minimum specification traL tcLk tskew1 13 lt minimum specification 2tcLk tskew1 or tskew1 The Latency Timings apply only at the Empty Boundary EF LOW Figure 7 First Data Word Latency Timing 10772421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES NO WRITE NO WRITE NO WRITE 1 XXXXKXXXXXK OX KKK WENT Po etre ROO RCLK 7 tENH 5 tENS RENT REN2 OE LOW ii 1 IN OUTPUT REGISTER NEXT DATA READ 2655 drw 10 NOTE 1 Only one of the two write enable inputs WEN1 or WEN2 needs to go inactive to inhibit writes to the FIFO Figure 8 Full Flag Timing WCLK tDS NA NA S NV NS S NENE K DATAWRITE2 gt NEN NIN YY Do D8 LXK pata warre 1 aTa were tENS N ENH NW 1 teENS WEN2 4 If Applicable ter r tre tSKEW1 tSKEW1 RCLK REN1 REN2 OE LOW tA E Qo DATA IN OUTPUT REGISTER DATA READ 2655 drw 11 NOTE 1 When tskew1 gt minimum specification maximum tSKEW1 tskew1 lt minimum specification tFRL maximum 2tcLk tSKEW1 or tcLK
14. ations Once a valid write operation has been accomplished the Empty Flag EF will go HIGH after tREF and a valid readcanbegin The Read Enables REN1 REN2 areignored when the FIFO isempty TEMPERATURE RANGES OUTPUT ENABLE OE When Output Enable OE is enabled LOW the parallel output buffers receive data from the output register When Output Enable OE is disabled HIGH the Q output data bus is in a high impedance state WRITE ENABLE 2 LOAD WEN2 LD This is a dual purpose pin The FIFO is configured at Reset to have programmableflags or to have twowrite enables which allows depth expansion If Write Enable 2 Load WEN2 LD is set HIGH at Reset RS LOW this pin operates as a second write enable pin If the FIFO is configured to have two write enables when Write Enable WENT is LOW and Write Enable 2 Load WEN2 LD is HIGH data can be loaded into the input register and RAM array onthe LOW to HIGH transition of every Write Clock WCLK Data is storedin the RAM array sequentially and independently of any ongoing read operation In this configuration when Write Enable WENT is HIGH and or Write Enable 2 Load WEN2 LD is LOW the input register holds the previous data and no new data is allowed to be loaded into the register Toprevent data overflow the Full Flag FF will go LOW inhibiting further write operations Upon the completion of a valid read cycle the Full Flag FF will go HIGH after twFF allowing a valid
15. he Write Clock for single clock operation or the two clocks can run to any depth asynchronous of one another for dual clock operation An output enable pin e Programmable Almost Empty and Almost Full flags default to OE is provided on the read port for three state control ofthe output Empty 7 and Full 7 respectively The Synchronous FIFOs have two fixed flags Empty EF and Full FF e Output enable puts output data bus in high impedance state Two programmable flags Almost Empty PAE and Almost Full PAF are e Advanced submicron CMOS technology provided for improved system control The programmable flags default to e Available in the 32 pin plastic leaded chip carrier PLCC and Empty 7 and Full 7 for PAE and PAF respectively The programmable flag 32 pin Thin Quad Flat Pack TQFP offset loadingis controlled by a simple state machine andis initiated by asserting e For through hole product please see the IDT72420 72200 72210 the load pin LD 72220 72230 72240 data sheet These FIFOs are fabricated using IDT s high speed submicron CMOS e Industrial temperature range 40 C to 85 C is available technology FUNCTIONAL BLOCK DIAGRAM WCLK Do De LD n 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 8 192 9 XE RS AE 2655 drw01 55 Qo Qs IDT andthe IDT logo are registered trademarks of Integrated Device Technology Inc The SyncFIFO is a registered trademark of Integrated Device Technolog
16. k Diagram of 64 x 18 256 x 18 512 x 18 1 024 x 18 2 048 x 18 4 096 x 18 8 192 x 18 Synchronous FIFO Used in a Width Expansion Configuration ORDERING INFORMATION IDT _ XXXXX X XX X X Device Type Power Speed Package Process Temperature Range BLANK Commercial 0 C to 70 10 Industrial 40 to 85 Plastic Leaded Chip Carrier PLCC J32 1 Thin Quad Flat Pack TQFP PR32 1 Commercial Only Clock Cycle Time Commercial amp Industrial Commercial amp Industrial SPeed in Nanoseconds Low Power 72421 64x 9 SyncFIFO 72201 256 x 9 SyncFIFO 72211 512 x 9 SyncFIFO 1 024 x 9 SyncFIFO 72231 2 048 x 9 SyncFIFO 72241 4 096 x 9 SyncFIFO 72251 8 192 x 9 SyncFIFO 2655 drw18 NOTES 1 Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product DATASHEET DOCUMENT HISTORY 10 03 2000 pgs 2 3 4 and 14 05 01 2001 pgs 1 2 3 4 and 14 CORPORATE HEADQUARTERS for SALES for Tech Support 2975 Stender Way 800 345 7015 or 408 727 6116 408 330 1753 Santa Clara 95054 fax 408 492 8674 FIFOhelp idt com WWW idt com
17. offset 2 tskewe is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle If the time between the rising edge of WCLK and the rising edge of RCLK is less than tskew2 then PAE may not change state until the next RCLK rising edge 3 read is performed on this rising edge of the Read Clock there will be Empty n 1 words in the FIFO when PAE goes LOW Figure 11 Programmable Empty Flag Timing 10772421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES tCLKH tCLKL WCLK tENS tENH 5 lt tENS TN WENT ASE tos tbH oo KK XK KK KKK lt lt iar ae E ii EM Figure 12 Write Offset Registers Timing tCLKH RCLK tENS tENH D SL NN tENS Qo Qz DATAIN OUTPUT REGISTER FULL OFFSET LSB FULL OFFSET MSB 2655 drw15 EMPTY OFFSET EMPTY OFFSET LSB MSB Figure 13 Read Offset Registers Timing 10772421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION Asingle IDT72421 72201 72211 72221 72231 72241 72251 may be used when the application requirements are for 64 256 512 1 024 2 048 4 096 8 192 words or
18. onditions above those indicated in the operational TA Operating Temperature 70 C sections of the specification is not implied Exposure to absolute maximum rating Commercial conditions for extended periods may affect reliability d y Operating Temperature 40 85 C Industrial DC ELECTRICAL CHARACTERISTICS Commercial Vcc 5V 10 Ta 0 C to 70 C Industrial Voc 5V 10 40 to 85 C IDT72421 IDT72201 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 and Ind i and Ind i 10 15 25 ns 10 15 25 ns ame Parameter En i InputbeakageCurent Anyimpu a Pod Po S OR Output 1 Voltage lon 2 2 4 eee 2 4 NOTES Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product Measurements with 0 4 lt Vin lt Vcc OE gt 0 4 lt Vout lt Vcc Tested with outputs open lout 0 RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz Typical Icc1 1 7 0 7 fs 0 02 CL fs in mA These equations are valid under the following conditions Vcc 5V 25 C fs WCLK frequency RCLK frequency in MHz using TTL levels data switching at fs 2 CL capacitive load in pF 7 All Inputs Vcc 0 2V GND 0 2V except RCLK WCLK which toggle at 20 MHz SOV om 10772421 72201 72211 72221 72231 72241 7225
19. set register in sequence is written HE a Empty Offset LSB Empty Offset MSB Full Offset LSB Full Offset 58 p 4 EEEE Write Into FIFO 4 No Operation NOTE 1 For the purposes of this table WEN2 Vin 2 The same selection sequence applies to reading from the registers REN1 and REN2 are enabled and read is performed on the LOW to HIGH transition of RCLK Figure 2 Write Offset Register 10772421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES Thecontents of the offset registers can be readon the output lines when the A read and write should not be performed simultaneously to the offset Write Enable 2 Load WEN2 LD pin is set LOW and both ReadEnables REN1 registers 2 are set LOW Data can be read on the LOW to HIGH transition ofthe Read Clock RCLK IDT72421 64 x 9 BIT IDT72201 256 x 9 BIT 8 65 0 8 7 0 Z NZ N Default Value 007H YN Default Value 007H_ 8 0 8 0 8 65 0 8 7 0 ESARETTELTT Offset LSB Reg X Offset LSB Reg N Default Value 007H Defautvaueoo7H 8 0 8 0 IDT72211 512 x 9 BIT IDT72221 1 024 x 9 BIT 8 7 0 8 7 54 Empty Offset LSB X Empty Offset LSB Reg ZN Default Value 007H Defautt Value 007H_ 8 1 0 8 1 0 LAYS lt A NE o f Xf
20. will go LOW inhibitingfurther read operations when the read pointer is equal to the write pointer indicating the device is empty The Empty Flag EF is synchronized with respect to the LOW to HIGH transition ofthe Read Clock RCLK PROGRAMMABLE ALMOST FULL FLAG PAF The Programmable Almost Full flag PAF will go LOW when the FIFO reaches the almost full condition If no reads are performed after Reset RS the Programmable Almost Fullflag PAF will go LOW after 64 m writes forthe IDT72421 256 m writes forthe IDT72201 512 m writes forthe IDT7221 1 TABLE 1 STATUS FLAGS NUMBER OF WORDS IN FIFO IDT72421 IDT72201 n 1 to Fi 1 n 1 to 1 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 024 m writes forthe IDT 72221 2 048 m writes forthe IDT72231 4 096 m writes forthe IDT 72241 and 8 192 m writes for the IDT72251 The offset is definedin the Full offset registers Ifthereis Fulloffset specified the Programmable Almost Full flag PAF will go LOW at Full 7 words The Programmable Almost Full flag PAF is synchronized with respectto the LOW to HIGH transition of the Write Clock PROGRAMMABLE ALMOST EMPTY FLAG PAE The Programmable Almost Empty flag PAE will go LOW when the read pointer is n 1 locations less than the write pointer The offset n is defined in the Empty Offset registers If no reads are performed after Reset the Programmable Almost Empty flag PA
21. write to begin Write Enable 1 WEN and Write Enable 2 Load WEN2 LD are ignored when the FIFO is full The FIFO isconfiguredtohave programmable flags when the Write Enable 2 Load WEN2 LD is set LOW at Reset RS LOW The IDT72421 72201 72211 72221 72231 72241 72251 devices contain four 8 bit offset registers which can be loaded with data on the inputs or read onthe outputs See Figure 3for details of the size ofthe registers and the default values Ifthe FIFOisconfiguredto have programmable flags when the Write Enable 1 WENT and Write Enable 2 Load WEN2 LD are set LOW data onthe inputs Dis written into the Empty Least Significant Bit Offset register on the first LOW to HIGH transition ofthe Write Clock WCLK Datais written intothe Empty Most Significant Bit Offset register on the secondLOW to HIGH transition ofthe Write Clock WCLK into the Full Least Significant Bit Offset register on the third transition and into the Full Most Significant Bit Offset register on the fourth transition Thefifth transition ofthe Write Clock WCLK again writestothe Empty Least Significant Bit Offset register However writing all offsetregisters does not haveto One ortwo offset registers can be written and then by bringing the Write Enable 2 Load WEN2 LD pin HIGH the FIFO is returned to normal read write operation When the Write Enable 2 Load WEN2 LD pin is set LOW the Write Enable 1 WENT is LOW the next off
22. y Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SEPTEMBER 2002 2002 Integrated Device Technology Inc All rights reserved Product specifications subject to change without notice DSC 2655 2 10772421 72201 72211 72221 72231 72241 72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9 256 x 9 512 x 9 1 024 x 9 2 048 x 9 4 096 x 9 and 8 192 x 9 TEMPERATURE RANGES PIN CONFIGURATION sp ono 0 INDES AEA EAA INDEX OO pwp a 1 9 10 11 12 13 14 15 16 14 15 16 17 18 19 20 m 8 8 8 6 2655 dw 02 8 8 8 2655 drw02a TQFP PR32 1 order code PF PLCC J32 1 order code J TOP VIEW TOP VIEW PIN DESCRIPTIONS symbol Name 0000 00004 Datainputs Datainputstora9 bitbus 000000000 O RS Reset When RS is set LOW internal read and write pointers are set to the first location of the RAM array FF and PAF go HIGH and PAE and EF go LOW A reset is required before an initial WRITE after power up WOLK WriteClook 1 Datais written into the FIFO ona LOW to HIGH transition of WCLK when the Write Enable s are asserted WENT Write Enable 1 Ifthe FIFO is configured to have programmable flags WENT is the only write enable pin When WENTis LOW data is written into the FIFO on every LOW to HIGH transition WCLK If the FIFO is configured to have two write enables WENT must be LOW and WEN2 mustbe HIGH to write data into the FIFO Data will not be written into

IDT IDT72421 IDT72201 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 Manual

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