LXT901 DATA SHEET
Contents
1. APRIL 1996 LXT901 Universal Ethernet Interface Adapter Internal MA U O The LXT901 Universal Ethernet Interface Adapter is de Functional Feat signed for IEEE 802 3 physical layer applications It pro PUR DE CANNES vides all the active circuitry to interface most standard 8023 Integrated Filters Simplifies FCC Compliance controllers to either the 10BASE T media or Attachment Unit Interface AUI In addition to standard 10 Mbps Ethernet the LXT901 also supports full duplex operationat 10BASE T compliant Transceiver 20 Mbps AUI Transceiver LXT901 functions include Manchester encoding decoding receiver squelch and transmit pulse shaping jabber link testing and reversed polarity detection correction The Convenience Features LXT901 can be used to drive either AUI drop cable or the 10BASE T twisted pair cable with only a simple isolation transformer Integrated filters simplify the design work Automatic Polarity Correction required for FCC compliant EMI performance Selectable Programmable Impedance Driver termination impedance allows the LXT901 to be used with either shielded or unshielded twisted pair cable Power Down Mode and four loopback modes Integrated Manchester Encoder Decoder Supports Standard and Full Duplex Ethernet Automatic Manual AUI RJAS Selection The LXT901 is fabricated with an advanced CMOS process Available in 64 pin TQFP and 44 PLCC package2. Electronics TD01 0756K LEDC FDE and TGO1 0756W LEDR A Bias resistor RBIAS should LEDT PDN 1245 KO go located LEDL RBIAS close to the pin VCC1 and isolated from other GND1 GND2 signals LINE STATUS e Green Red Red a lt eel 0001311 322 7 LXT901 Universal Ethernet Interface Adapter FULL DUPLEX SUPPORT FIGURE 15 380C24 or other full duplex capable controller the LXT901 supports full duplex Ethernet effectively doubling the avail able bandwidth of the network In this application the LXT901 AUI port is not used Figure 15 shows the LXT901 with a Texas Instruments 380C24 CommProcessor The 380C24 is compatible with Mode 4 and 1 both High When used with the Figure 15 Full Duplex Application TMS380C24 Full Duplex Ethemet Comprocessor TEN 1 16 EH RCLK TPIP RXD TPONB COL TPONA Wd mon LEDC FDE 10 BASE T TWISTED PAIR NETWORK AUTOSEL NTH PROGRAMMING MDO OPTIONS UTP STP LI RJAB RLD RCMPT JAB PLR TEST PAUI LEDR LEDT PDN LEDL VCC1 RBIAS VCC2 GND1 GND2 Half Full Duplex Selection controlled by TMS380C24 pins TESTO and OUTSELO REMOTE STATUS LINE STATUS Suitable TP transformers include the Fil Mag 23Z128 and 23Z128SM Valor PT4069 and ST7011 Belfuse S553 0716 and A553 071
3. Enable QE TEST I Start_SQE_Test_Timer Cl SQE SQE_Test_Timer_Done L ES LXT901 Universal Ethernet Interface Adapter POLARITY REVERSE FUNCTION The LXT901 polarity reverse function uses both link pulses and end of frame data to determine polarity of the received signal A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity Reversed polarity is also detected if four frames are received with a reversed start of idle Whenever a correct polarity frame or a correct link pulse is received these two counters are reset to zero If the LXT901 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms the polarity is reset to the default non flipped condition If Link Integrity Testing is disabled polarity detection is based only on received data Polarity correction is always enabled COLLISION DETECTION FUNCTION The collision detection function operates on the twisted pair side of the interface For standard half duplex 10BASE T Operation a collision is defined as the simultaneous pres ence of valid signals on both the TPI circuit and the TPO circuit The LXT901 reports collisions to the back end via the COL pin If the TPI circuit becomes active while there is activity on the TPO circuit the TPI data is passed to the back end over the RXD ci
4. a esop eq pinous svIgH sa sisal seig DHM9002 2PD 1 PWE DYOOZ ZFOU SHUP OTVH pue 9170 ESSV 91 0 55 1110 15 690b Ld 11582172 pue 8ZIZEZ ei eqeuns SNLYLS INN SNLYLS yun SNOLLdO SNINAYHOOUd 33Sso1nv 109 av WSTIOULNOO 19 WIL NIL gan EN 5469236 0001310 49b m 11 16 LXT901 Universal Ethernet Interface Adapter OA kn M N AUI ENCODER DECODER ONLY portisnotused With MD1 and MDO both Low the LXT901 FIGURE 14 logic and framing are set to Mode 1 compatible with AMD AM7990 controllers The LI pin is tied Low disabling the link test function The LBK input controls loopback A 20 MHz system clock is supplied at CLKI with CLKO left open In this application the DTE is connected to a coaxial network through AUTOSEL is tied Low and PAUL is tied High manually selecting the AUI port The twisted pair Figure 14 AUI Encoder Decoder Only Application SYSTEM CLOCK AM7990 JOUK BACK END RCLK CONTROLLER RXD INTERFACE CD COL LOOPBACK D LBK CONTROL AUTOSEL PROGRAMMING OPTIONS D CONNECTOR to AUI DROP CABLE mn c 6 STATUS Suitable AUI transformers include the Chassis 12V Fil Mag 23290 and Gnd 232905 Valor LT6030 and SM6030 and HALO
5. Table 2 Controller Compatibility Mode Options Controller Mode Setting MD1 MDO Mode 1 For Advanced Micro Devices AM 7990 or compatible controllers Mode 2 For Intel 82596 or compatible controllers Lo Lo High Mode 3 For Fujitsu MB86950 MB86960 or compatible controllers Seeq 8005 High Low Mode 4 For National Semiconductor 8390 or compatible controllers TI TMS380C26 w Low W a High High 1 SEEQ controllers require inverters on CLKI LBK RCLK and COL LEVEL ONE 5469236 0001299 TTS Mi LXT901 Universal Ethernet Interface Adapter JABBER CONTROL FUNCTION Figure 3 is a state diagram of the LXT901 Jabber control function The LXT901 on chip watchdog timer prevents the DTE from locking into a continuous transmit mode When a transmission exceeds the time limit the watchdog timer disables the transmit and loopback functions and activates the JAB pin Once the LXT901 is in the jabber state the TXD circuit must remain idle for a period of 0 25 to 0 75 seconds before it will exit the jabber state SQE FUNCTION the integrated PLS MAU mode the LXT901 supports the signal quality error SQE function as shown in Figure 4 After every successful transmission on the 10BASE T net work the 901 transmits the SQE signal for 10BT 5BTover the internal circuit which is indicated on the COL pin of the device When using the 10BASE 2 port of the 901 the SQE function is d
6. center left The PAUI pin is tied Low and all other option pins are tied High This set up selects the following options Automatic Port Selection PAUI Low and AUTOSEL High Normal Receive Threshold NTH High Mode 4 compatible with National NS8390 controllers MDO High MDI High 100 Q termination for unshielded TP cable UTP STP High Link Testing Enabled LI High Status outputs are grouped at lower left Local status outputs drive LED indicators and remote status indicators are avail able as required Power and ground pins are shown at the bottom of the diagram A single power supply is used for both VCC1 and VCC2 with a decoupling capacitor installed between the power and ground busses The TP and AUI interfaces are shown at upper and lower right respectively Impedance matching resistors are in stalled in each I O pair but no external filters are required Suitable transformers are listed in notes 2 and 3 DUAL NETWORK SUPPORT 10BASE T AND TOKEN RING FIGURE 9 Figure 9 shows the LXT901 with a Texas Instruments 380C26 CommProcessor The 380C26 is compatible with Mode 4 and MDI both High When used with the 380C26 both the LXT901 and a TMS38054 Token Ring transceiver can be tied to a single RJ45 allowing dual network supportfrom asingle connector The LXT901 AUI port is not used I 11 10 EN 5469236 0001304 152 EN MANUAL PORT SELECT WITH LINK TEST FUNCTION FIGURES 10 AND 11 With MD
7. is High the normal TP squelch threshold is in effect Threshold When NTH is Low the normal TP squelch threshold is reduced by 4 5 dB d E 5 ode Select 0 Mode select pins determine controller compatibility mode in accordance with ode Select 1 Table 2 Down down condition A 10 MHz clock output This clock signal should be directly connected to the transmit clock input of the controller ransmit Data Input signal containing NRZ data to be transmitted on the network TXD is connected directly to the transmit data output of the controller Transmit Enable Enables data transmission and starts the watchdog timer Synchronous to TCLK see Test Specifications for details t ajou Q 2 Crystal A 20 MHz crystal must be connected across these pins Oscillator or a 20 MHz clock applied at CLKI with CLKO left open ollision Detect Output which drives the collision detect input of the controller 17 Automatic When High automatic port selection is enabled the 901 defaults to L Port Select the AUI port only if TP link integrity Fail When Low manual port selection is enabled the PAUI pin determines the active port Receive LED drain driver for the receive indicator LED Output is pulled Low during receive Transmit LED Open drain driver for the transmit indicator Output is pulled Low during Power Down transmit If externally tied Low the LXT901 goes to
8. jw 330 Yi Y Yi Ya Red Green Red Red D CONNECTOR to AUI DROP CABLE T o o Chassis 12 Gnd p VCC2 GND1 GND2 Suitable crystals include the MTRON MP 1 and MP 2 Suitable TP transformers include the Fil Mag 232128 and 2321285 Valor PT4069 and ST7011 Belluse 5553 0716 and A553 0716 and Halo Electronics TD42 2006Q and TG42 2006WH1 Suitable AUI transformers include the Fil Mag 23290 and 23Z90SM Valor LT6030 and ST7030 and Halo Electronics TD01 0756K and TG01 0756W Bias resistor RBIAS should be located close to the pin and isolated from other Signals ESE EH 5469236 0001307 971 NN LXT901 Universal Ethernet Interface Adapter Figure 11 Manual Port Select with Seeq 8005 Controller External 20 2 Source To 10 BASE T TWISTED PAIR NETWORK Port Selection PROGRAMMING OPTIONS D 330 M Amber Amber m REMOTE 8 LINE STATUS D CONNECTOR to AUI DROP CABLE 330 330 Z x Y han Red P d rbd LEDC FDE LEDR LEDT PDN m c a o Chassis 12 V Gnd e GND1 GND2 Suitable TP transformers include the Fil Mag 232128 and 2321285 Valor PT4069 and ST7011 Belfuse 553 0716 and A553 0716 and HALO Electronics TD42 2006Q and TG42 2006WH1 Suitable AUI transformers include the Fil Mag 23290 and 23Z90SM Valor LT6030 and ST7030 and HALO Electronics TD01 756K and TGO1 0756W Bias resistor RBIAS should be located close to the pin and isola
9. 6 and HALO Electronics TD42 2006Q and TG42 2006WH1 Bias resistor RBIAS should be located close to the pin and isolated from other signals Suitable crystals include the MTRON MP 1 and MP 2 ms n 469236 0001332 269 ESE LXT901 Universal Ethernet Interface Adapter TEST SPECIFICATIONS NOTE Minimum and maximum values in Tables 3 through 12 and Figures 16 through 39 represent the performance specifications of the LXT901 and are guaranteed by test except as noted by design Table 3 Absolute Maximum Ratings Parameter Sym Min Units DC supply referenced to GND Vcc 03 Ambient operating temperature o 5 150 Storage temperature 65 CAUTION Operations at or beyond these limits may result in permanent damage to the device Normal operation not guaranteed at these extremes Table 4 Recommended Operating Conditions Parameter Symbol Min Typ Max Units Test Conditions Recommended supply voltage Vcc 4 75 5 0 525 fan YN Recommended operating temperature 0 70 C 1 Voltage with respect to ground unless otherwise specified Table 5 I O Electrical Characteristics Over Recommended Range __Parameter_____ Symbol Max Unite TeatGonditons Input Low voltage Vit Input High voltage Vin t Output Low voltage VoL Output Low voltag
10. Interface Adapter Figure 9 LXT901 380C26 Interface for Dual Network Support of 10BASE T and Token Ring To TI TMS38054 From TI Token Ring TMS38054 Transceiver Token Ring Transceiver 380C26 TXD TXE TXC RXD CRS COL LBK To 10 BASE T TWISTED PAIR NETWORK 37 5 Q 196 375019 7 Yo AUTOSEL PROGRAMMING OPTIONS qe e eo gt lt l REMOTE STATUS LINE STATUS 330 330 330 330 s SZ s LEDC FDE LEDR LEDT PDN LEDL VCC1 RBIAS E VCC2 GND1 GND2 A Suitable crystals include the MTRON MP 1 and MP 2 Green Red Red Red Suitable TP transformers include the Fil Mag 232128 and 2321285 Valor PT4069 and ST7011 Belfuse 5553 0716 and A553 0716 and HALO Electronics TD42 2006Q and TG42 2006WH1 VEN Bias resistor RBIAS should be located close to the pin and isolated from other signals Additional magnetics and switching logic not shown is required to implement the dual network solution ER 545523 LEVEL 11 12 b 0001306 Tb5 ESE LXT901 Universal Ethernet Interface Adapter Figure 10 LAN Adapter Board Manual Port Select with Link Test Function A 20pF 20 MHz MB86950 or MB86960 BACK END CONTROLLER INTERFACE To 10 BASE T TWISTED PAIR NETWORK Port Selection PROGRAMMING OPTIONS 330 330 330 T 1 Ma Si EE Amber Amber Amber m I L L eH REMOTE amp LINE Ll STATUS 330 2330
11. Interface Adapter Figures 16 through 21 Timing Diagrams for Mode 1 MD1 0 MDO 0 Figure 16 Mode 1 RCLK Start of Frame Timing ilo Bolo 1 1 o TPIP TPI or DIP DIN tcp 1 11 1 NOTE 1 changes 25 ns after the rising edge of RCLK Figure 17 Mode 1 RCLK End of Frame alo 1 1 1 o TPIP TPIN or DIP DIN CD I3 ido Filo f1 fo fo NOTE 1 RXD changes 25 ns after the rising edge of RCLK e LEVEL E EN 5469236 0001316 SOU NN ERE LXT901 Universal Ethernet Interface Adapter M Figure 18 Mode 1 Transmit Timing Figure 19 Mode 1 Collision Detect Timing CI f tcouD tCOLOFF COL Figure 20 Mode 1 COL CI Output Timing Figure 21 Mode 1 Loopback Timing LEVEL EE 5469236 0001317 ayo EN 11 23 LXT901 Universal Ethernet Interface Adapter Figures 22 through 27 Timing Diagrams for Mode 2 MD1 0 MDO 1 Figure 22 Mode 2 RCLK Start of Frame Timing lalo slo 1 1 1 1 or DIP DIN 11 NOTE 1 RXD changes at the rising edge of RCLK The controller is sampled at the falling edge Figure 23 Mode 2 RC
12. LK End of Frame Timing AN TPIP TPIN or DIP DIN tcDOFF 1 o NOTE 1 RXD changes at the rising edge of RCLK The controller is sampled at the falling edge 11 24 0001318 787 m ESE LXT901 Universal Ethernet Interface Adapter Figure 24 Mode 2 Transmit Timing Figure 25 Mode 2 Collision Detect Timing Figure 26 Mode 2 COL CI Output Timing The CD output is disabled for a maximum of 55 bit times after TEN turns off Figure 27 Mode 2 Loopback Timing EHNE ONE 5469236 0001319 513 EN 11 25 LXT901 Universal Ethernet Interface Adapter Figures 28 through 33 Timing Diagrams for Mode 3 MD1 1 MDO 0 Figure 28 Mode 3 RCLK Start of Frame Timing filo alo 1 o lo or DIP DIN tcp lafo 1 o 1 1 1 RXD changes at the rising edge of RCLK The controller is sampled at the falling edge Figure 29 Mode 3 RCLK End of Frame Timing Dido TPIP TPIN or DIP DI tCDOFF lo olo o NOTE 1 RXD changes at the rising edge of RCLK The controller is sampled at the falling edge T BH 5469236 0001320 335 NI LXT901 Universal Ethernet Interface Adapter Figure 30 Mode 3 Transmit Timing Figure 31 Mode 3 Collision Detect Timing Figure 32 Mod
13. O Low and MDI tied High the LXT901 logic and framing are set to Mode 3 compatible with Fujitsu MB86950 and MB86960 and SEEQ 8005 controllers Figure 10 shows the setup for Fujitsu controllers Figure 11 shows the four inverters required to interface with the SEEQ 8005 controller As in Figure 8 both these Mode 3 applications show the LI pin tied High enabling Link Testing and the UTP STP and NTH pins are both tied High selecting the standard receiver threshold and 100 2 termination for unshielded TP cable However in these applications AUTOSEL is tied Low allowing external port selection through the PAUI pin The remote status outputs are inverted to drive LED indicators 150 Q SHIELDED TWISTED PAIR ONLY FIGURE 12 Figure 12 shows the LXT901 in a typical twisted pair only application The DTE is connected to a 10BASE T network through the twisted pair RJ45 connector The AUI port is notused With tied High and MD1 Low the LX T901 logic and framing are set to Mode 2 compatible with Intel 82596 controllers 20 MHz system clock input at CLK is used in place of the crystal oscillator CLKO is leftopen The LI pin externally controls the link test function The UTP STP and NTH pins are both tied Low selecting the reduced receiver threshold and 150 Q termination for shielded TP cable The switch at LEDT PDN manually controls the power down mode THREE MEDIA APPLICATION FIGURE 13 Like Figure 12 Figure 13 shows
14. arameter is guaranteed by design not subject to production testing 3 IEEE 802 3 specifies maximum jitter additions at 1 5 ns for the AUI cable 0 5 ns from the encoder and 3 5 ns from the MAU Parameter Jabber Timing Maximum transmit time Unjab time Link integrity Timing Time link loss receive Link Min receive Link Max receive Link Transmit period ER LEVEL 1436 5469236 0001314 031 ERE LXT901 Universal Ethernet Interface Adapter Table 9 RCLK Start of Frame Timing Over Recommended Parameter Symbol Typical Maximum IDATA wawas e aes ee UM lt OE Receive data setup Mode INC from RCLK Modes2 3and4 wos 3 f s Receive data hold A MESRINE UR ERN sow qom oue nos RCLK after CD off NE s s fa om ss e RC NOR i u 2 CD Turnoff delay measured from middle of last bit so timing specification is unaffected by the value of the last bit TEN setup fromTCLK setup from TCLK Decoder acquisition time Parameter COL turn on delay Symbol Typical Maximum tCOLD us ns ns 1 Typical values are at 25 and are for design aid only not guaranteed and not subject to production testing ESE ONE 5469236 0001315 775 11 21 LXT901 Universal Ethernet
15. e Output Low voltage Open drain LED Driver Output High voltage Output High voltage VOL Output rise time cmos _ T Output fall time cmos moun MCN man de TCLK amp RCLK TTL gt t EM Co on puer Bap e oo CLKI rise time externally driven CLKI duty cycle externally driven Supply Current Normal mode 99 no ma TammitisgorT m se ma Tansitingor AUT 1 Typical values are at 25 C and are for design aid only not guaranteed and not subject to production testing Power Down Mode 2 Limited functional tests are performed at these input levels The majority of functional tests are performed at levels of OV and 3V ESE ONE EN 5469236 0001313 175 11 19 LXT901 Universal Ethernet Interface Adapter Table 6 AUI Electrical Characteristics Over Recommended Range Parameter Parameter Transmit output impedance Transmit timing jitter addition Transmit timing jitter added by 5 5 After line model specified by the MAU and PLS sections 802 3 for 10BASE T internal MAU Receive input impedance ZIN kQ Between TPIP TPIN CIP CIN amp DIP DIN Differential squelch threshold DS 585 mV 5 MHz square wave input Normal threshold NTH 1 1 Typical values are at 25 C and are for design aid only not guaranteed and not subject to production testing 2 P
16. e 3 COL CI Output Timing Figure 33 Mode 3 Loopback Timing ESE ONE 5469236 0001321 271 Mi 11 27 LXT901 Universal Ethernet Interface Adapter Figures 34 through 39 Timing Diagrams for Mode 4 MD1 1 MDO 1 Figure 34 Mode 4 RCLK Start of Frame Timing 1 1 1 1 TPIP TPI or DIP DIN alo 1 ls NOTE 1 RXD changes the falling edge of RCLK The controller is sampled at the rising edge Figure 35 Mode 4 RCLK End of Frame Timing a a TPIP TPIN or DIP DIN tCDOFF 5 pope a 1 changes the falling edge of RCLK The controller is sampled the rising edge 11 28 EN 5469236 0001322 108 ERE LXT901 Universal Ethernet Interface Adapter Figure 36 Mode 4 Transmit Timing Figure 38 Mode 4 COL CI Output Timing Figure 39 Mode 4 Loopback Timing ESE EE 5469236 0001323 044 11 29
17. ected When UTP is High 100 2 termination for unshielded TP is selected Twisted Pair A differential input pair from the twisted pair cable Receive filter is integrated on chip In Manual Port Select mode AUTOSEL Low PAUI selects the active 38 61 TPIP 39162 TPIN Receive port When PAUI is High port is selected When PAUI is Low the TP port is selected In Auto Port Select mode PAUI must be tied to 4013 Port AUI Select ground DIP Receive Differential input pair from the AUI transceiver DI circuit 42 5 DIN 1 Pair The input is Manchester encoded 43 7 DOP AUI Transmit A differential output driver pair for the AUI transceiver cable The 4418 DON Pair output is Manchester encoded LEVEL 11 4 EH 546923b 0001298 069 NE ESE LXT901 Universal Ethernet Interface Adapter lt FUNCTIONAL DESCRIPTION NOTE This information is for design aid only The LXT901 Universal Ethernet Interface Transceiver per forms the physicallayer signaling PLS and Media Attach ment Unit MAU functions as defined by the IEEE 802 3 specification It functions as a PLS Only device for use with IOBASE 2 10 5 coaxial cable networks or as an Integrated PLS MAU for use with 10BASE T twisted pair networks In addition to standard 10 Mbps operation the LXT901 also supports full duplex 20 Mbps operation The LXT901 interfaces a back end controller to eit
18. es these alternate pulse intervals when received from aremote unit Remote status conditions are reported to the controller over the RLD RJAB and RCMPT output pins Figure 7 Remote Signaling Link Integrity Pulse Timing 10ms 15ms 10ms 15ms RLD Note 1 LI 15ms 10ms 15ms 10ms RJAB Note 2 LI 19 ms 20 ms 10 ms 20 ms 10 ms 20ms 10 20 10 Note 3 For Remote Link Down RLD signaling the interval between LI pulses increments from 10 ms to 15 ms to 20 ms and then cycle starts over For Remote Jabber RJAB signaling the interval between LI pulses decrements from 20 ms to 15 ms to 10 ms and then the cycle starts over For Remote Compatibility RCMPT signaling the interval between LI pulses continually switches between 10 ms and 20 ms ESSE EN 5469236 0001303 25b MN LXT901 Universal Ethernet Interface Adapter APPLICATION INFORMATION NOTE This information is for design aid only Figures 8 through 15 show typical LXT901 applications AUTO PORT SELECT WITH EXTERNAL LOOPBACK CONTROL FIGURE 8 Figure 8 is a typical LXT901 application The diagram is arranged to group similar pins together it does notrepresent the actual LXT901 pinout The controller interface pins transmit data clock and enable receive data and clock and the collision detect carrier detectand loopback control pins are shown at the top left Programmable option pins are grouped
19. etermined by the external MAU attached Figure 3 Jabber Control Function Power On NO OUTPUT DO Activee XMIT_Max_Timer_Done XMIT Disable LPBK Disable CI SQE UNJAB WAI Start Unjab Timer XMIT Disable LPBK Disable SQE DO Active Unjab_Timer_Not_Done Unjab Timer Done EB 5469236 0001300 547 RECEIVE FUNCTION The LXT901 receive function acquires timing and data from the twisted pair network the TPI circuit or from the AUI the DI circuit Valid received signals are passed through the on chip filters and Manchester decoder then output as decoded NRZ data and receive timing on the RXD and RCLK pins respectively An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams The receive function is activated only by valid data streams above the squelch level and with proper timing If the differential signal at the TPI or the DI circuit inputs falls below 75 of the threshold level unsquelched for 8 bit times typical the LXT901 receive function enters the idle state If the polarity of the TPI circuit is reversed LXT901 detects the polarity reverse and reports it via the PLR output The LXT901 automatically corrects reversed polarity Figure 4 SQE Function Power On OUTPUT IDLE DO Active OUTPUT DETECTED DO Idle SQE WAIT TEST Start SQE Test Wait Timer SQE Test Wait Timer Done 9 XMIT Disable XMIT
20. her an AUI drop cable or a twisted pair TP cable The controller interface includes transmit and receive clock and NRZ data channels as well as mode control logic and signaling The AUI interface comprises three circuits Data Output DO Data Input DI and Collision CI The twisted pair inter face comprises two circuits Twisted Pair Input TPI and Twisted Pair Output TPO In addition to the three basic interfaces the LXT901 contains an internal crystal oscillator and four LED drivers for visual status reporting Functions are defined from the back end controller side of the interface The LXT901 Transmit function refers to data transmitted by the back end to the AUI cable PLS Only mode or to the twisted pair network Integrated PLS MAU mode The LXT901 Receive function refers to data re ceived by the back end from the AUI cable PLS Only or from the twisted pair network Integrated PLS MAU mode In the integrated PLS MAU mode the LXT901 performs all required MAU functions defined by the IEEE 802 3 10BASE T specification such as collision detection link integrity testing signal quality error messaging jabber control and loopback In the PLS Only mode the LXT901 receives incoming signals from the AUI DI circuit with 18 ns of jitter and drives the AUI DO circuit CONTROLLER COMPATIBILITY MODES The LXT901 is compatible with most industry standard controllers including devices produced by Advanced Micro Devices AMD In
21. hip enters a link fail state and disables the transmit and normal loopback functions The LXT901 ignores any link integrity pulse with interval less than 2 7 ms The LXT901 will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses LINK TEST FAIL WAIT XMIT Disable RCVR Disable LPBK Disable Link_Count Link_Count 1 Link_Test_Revd Idle Idle LINK TEST FAIL Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT Disable RCVR Disable LPBK Disable Link_Count LC_Max LINK TEST FAIL EXTEND XMIT Disable RCVR Disable LPBK Disable TPI Idle DO Idle ink_Test_Min_Timer_Done Link_Test_Revd True TPI idle Link Test Max Timer Done Link Test Min Timer Not Done Link Test Rcvd True B LEVEL EH 5969236 0001302 317 Boe LXT901 Universal Ethernet Interface Adapter s 59 a CMM fi NN REMOTE SIGNALING The LXT901 transmits standard link pulses which meet the 10BASE T specification However the LXT901 encodes additional status information into the link pulse by varying the link pulse timing This is referred to as remote signaling Using alternate pulse intervals the LXT901 can signal three local conditions link down jabber and remote signaling compatibility Figure 7 shows the interval variations used to signal local status to the other end of the line The LXT901 also recogniz
22. power down state Link LED Open drain driver for link integrity indicator Output is pulled Low during link test pass If externally tied Low intemal circuitry is forced to Link Pass state and 901 will continue to transmit link test pulses 21 LEDC Collision LED Open drain driver for the collision indicator pulls Low during collision 14 15 20 If externally tied Low the LXT901 disables the internal TP loopback and collision detect circuits for full duplex operation or external TP loopback _ EN 5469236 0001297 122 113 LXT901 Universal Ethernet Interface Adapter Table 1 Pin Descriptions continued To en g 23 39 GNDI 33 55 GND2 40 GNDA 24 RBIAS z am N Ground Returns 1 2 and TQFP only Compatibility with the LXT901 remote signaling features An output to notify the controller of activity on the network recovered 10 MHz clock which is synchronous to the received data and connected to the controller receive clock input Twisted Pair Transmit Pairs A amp B Two differential driver pair outputs A and B to the twisted pair cable The outputs are pre equalized no external filters are required Two pairs are used to provide compatibility with both 100 Q load cable and 150 Q load cable F A B B UTP STP Select When UTP is Low 150 Q termination for shielded TP is sel
23. rcuit disabling normal loopback Figure 5 is a state diagram of the LX T901 collision detection Figure 5 Collision Detection Function DO Active 9 Idle XMIT Enabled DO Active e TPI Active XMIT Enabled DO Idle XMIT Disabled DO Active TP Idle LEVEL EE COLLISION DO DI CI SQE function Refer to Test Specifications for collision detection and COL CI output timing NOTE For full duplex opera tion the collision detection circuitry must be disabled LOOPBACK FUNCTION The LXT901 provides the normal loopback function speci fied by the 1OBASE T standard for the twisted pair port The loopback function operates in conjunction with the transmit function Data transmitted by the back end is internally looped back within the LXT901 from the TXD pin through the Manchester encoder decoder to the RXD pin and returned to the back end This normal loopback function is disabled when a data collision occurs clearing the RXD circuit for the TPI data Normal loopback is also disabled during link fail and jabber states The LXT901 also provides three additional loopback func tions An external loopback mode useful for system level testing is controlled by pin 21 LEDC FDE When LEDC FDE is tied Low the LXT901 disables the collision detec tion and internal loopback circuits to allow external loopback Forced TP loopback is controlled by pin 22 LBK When the TP por
24. s and requires only a single 5 volt power supply Diagnostic Features ONS n Four LED Drivers Laptop Palmtop portables PCMCIA compatibles AUI RJA5 Loopback gears AUTOSEL MODE SELECT LOGIC PAUI Controller Compatibility LBK Port Select Loopback Link Test TWISTED PAIR INTERFACE PULSE NA SHAPER gt amp e i Gg FILTER 8 COLLISION pa POLARITY CORRECT MANCHESTER ENCODER REMOTE SIGNALING ISQUELCH LINK DETECT MANCHESTER S Jb Ze P COLLISION COLLISION Loaic YE l 1 RECEIVER Le LEDT PDN NTH JAB PLR DROP CABLE TE j RXD RCLK COL EDC FDE ERE ONE EN 5 0001295 35T Remote Signaling of Link Down and Jabber conditions LXT901 Universal Ethernet Interface Adapter Figure 1 LXT901 Pin Assignments RLD LI JAB TEST TCLK TXD LXT901PC TEN CLKO CLKI COL AUTOSEL LEDT PDN LXT901TC 1 2 3 4 5 6 7 8 9 LEDT PDN LEDR 11 2 S4L923b 00012955 296 Mi EX LXT901 Universal Ethernet Interface Adapter Table 1 LXT901 Pin Descriptions Description 1110 Power Inputs 5 volt power supply inputs 34 56 VCC 2 1 2 and A TQFP only Collision Differential input pair connected to the AUI transceiver circuit The input is collision signaling or SQE Normal When NTH
25. t is selected and LBK is High TP loopback is forced overriding collisions on the TP circuit When LBK is Low normal loopback is in effect Active DI DO Activee Activee XMIT Enabled DO Idle 5469236 0001301 443 EN 11 7 LXT901 Universal Ethernet Interface Adapter AUI loopback is also controlled by the LBK pin When the AUI portis selected and LBK is High data transmitted by the back end is internally looped back from the TXD pin through the Manchester encoder decoder to the RXD pin When LBK is Low no AUI loopback occurs LINK INTEGRITY TEST Figure 6 is a state diagram of the LXT901 Link Integrity test function The link integrity test is used to determine the Figure 6 Link Integrity Test Function Power On IDLE TEST Start Link Loss Timer Start Link Test Min Timer TPI Active Link Test Rcvd True Link Test Min Timer Done Link Loss Timer Done TP Idle Link Test Rcvd False LINK TEST FAIL RESET Link Count 0 XMIT Disable RCVR Disable LPBK Disable TPI Active Link_Test_Revd False TPI Active status of the receive side twisted pair cable Link integrity testing is enabled when pin 8 11 is tied High When enabled the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic If no serial data stream or link integrity pulses are detected within 50 150 ms the c
26. ted from other signals EH 0001308 638 m 11 14 ERE LXT901 Universal Ethernet Interface Adapter Figure 12 150 Q Shielded Twisted Pair Only Application 20 MHz SYSTEM CLKO CLOCK CLKI TXD TEN 82596 TCLK BACK END RCLK CONTROLLER INTERFACE DA RXD CD COL 37 5 Q 196 37 50 196 LBK To 10 BASE T TWISTED PAIR NETWORK AUTOSEL PAUI PROGRAMMING Ga ads OPTIONS MDO MD1 Link Test UTP STP 759 1 Enable LI Suitable TP transformers include the Fil Mag 232128 and 2321285 REMOTE RJAB Valor PT4069 and ST7011 Belfuse STATUS RLD 5553 0716 and A553 0716 and HALO RCMPT Electronics TD42 2006Q and LINE STATUS JAB TG42 2006WH1 PLR 10K iw TEST LEDC FDE A Bias resistor RBIAS should be located LEDR close to the pin and isolated from LEDL 12 4 other signals LEDT PDN RBIAS 45V VCC1 VCC2 GND1 GND2 E EN 5469236 0001309 774 EB ONE 11 15 LXT901 Universal Ethernet Interface Adapter xeo2 doua INY a YOLOANNOD ix Fe XH E tA ET QNO XH tr09Wd MHOMLIN XVOO 6 2 S 2 a Sao a q G Three Medi igure 13 F MYOMLIN HIVd G31SIAL 1 3SV8 01 OL 7950 1091 PUB 9920 10 01 OTVH PUB 060 18 pue O09 L1 08A WSO6ZEZ 06262 et NY elqeuns speufiis jugo uid
27. tel Fujitsu National Semiconductor Seeq and Texas Instruments Four different contro signal timing and polarity schemes Modes 1 through 4 are re quired to achieve this compatibility Mode select pins MDO and MD1 determine Controller compatibility modes as listed in Table 2 Refer to Test Specifications for a complete set of timing diagrams for each mode TRANSMIT FUNCTION The LXT901 receives NRZ data from the controller at the TXD input as shown in the first diagram and passes it through a Manchester encoder The encoded data is then transferred to either the AUI cable the DO circuit or the twisted pair network the TPO circuit The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP shown in Figure 2 The TPO output is pre distorted and prefiltered to meet the 10BASE T jitter template An internal continuous resis tor capacitor filter is used to remove any high frequency clocking noise from the pulse shaping circuitry Inte grated filters simplify the design work required for FCC compliant EMI performance During idle periods the LXT901 transmits link integrity test pulses on the TPO circuit if LI is enabled and integrated PLS MAU mode is selected The UTP pin controls LXT901 termination im pedance When UTP STP is Low the LXT901 15 set for shielded TP 150 Q When UTP STP is High the LXT901 is set for unshielded TP 100 Q Figure 2 LXT901 TPO Output Waveform ww
28. the LXT901 in Mode 2 compatible with Intel 82596 controllers with the same options and twisted pair interface However Figure 13 adds a pair of connections to the AUI port which was not used in Figure 12 Twotransformers are used to couple the AUI port to either a D connector or a BNC connector A DP8392 coax transceiver with PM6044 power supply are required to drive the thin coax network through the BNC LA LXT901 Universal Ethernet Interface Adapter Figure 8 LAN Adapter Board Auto Port Select with External LPBK Control NS8390 BACK END CONTROLLER INTERFACE To 10 BASE T TWISTED PAIR NETWORK LOOPBACK ENABLE PAUI AUTOSEL PROGRAMMING OPTIONS REMOTE STATUS LINE STATUS D CONNECTOR to AUI DROP CABLE iw 330 330 330 Yu Xa Green Red Red Y Red LEDC FDE LEDR LEDT PDN LEDL VCC1 RBIAS Chassis 12V VCC2 GND1 GND2 ang T o Suitable crystals include the MTRON 1 and 2 Suitable TP transformers include the Fil Mag 23Z128 and 2321285 Valor PT4069 and ST7011 Belfuse 5553 0716 and A553 0716 and Halo Electronics TD42 2006Q and TG42 2006WH1 Suitable AUI transformers include the Fil Mag 23Z90 and 23290SM Valor LT6030 and ST7030 and Halo Electronics TD01 0756K and TG01 0756W Bias resistor RBIAS should be located close to the pin and isolated from other signals LEVEL 54592365 ERE 0001305 029 Ei LXT901 Universal Ethernet
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LXT901 DATA SHEET