ON Semiconductor MC74AC74 MC74ACT74 handbook
Contents
1. 18 16 19 56 0 240 0 260 6 10 6 60 0 145 0 185 3 69 4 69 0 015 0 021 0 38 0 53 0 040 0 070 1 02 1 78 2 54 BSC 0 052 0 095 1 32 2 41 ak g z 0 008 0 015 0 20 0 38 T 0 115 0 135 2 92 3 43 0 290 0 310 7 37 7 87 Eater 10 10 0 015 0 039 0 38 1 01 SEATING PLANE C gt W D 14 PL M 0 13 0 005 9 http onsemi com 9 MC74AC74 74 74 SOIC 14 CASE 751A 03 ISSUE H NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION MAXIMUM MOLD PROTRUSION 0 15 0 006 PER SIDE DIMENSION DOES INCLUDE DAMBAR PROTRUSION ALLOWABLE 0 25 0 010 BA DAMBAR PROTRUSION SHALL BE 0 127 Is e 0 005 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION gt MILLIMETERS INCHES 45 DIM MIN MAX MIN MAX c 855 8 75 0 337 0 344 380 4 00 0 150 0 157 D 035 0 49 0 014 0 019 1 LS Z Lj 0 40 1 25 0 016 0 049 SEATING lie D 14 PL K M 1272. DETAIL E 6 TERMINAL NUMBERS ARE SHOWN FOR REFE RENCE ONLY 7 DIMENSION A AND B ARE TO BE RMINED AT DATUM PLANE W MILLIMETERS INCHES MIN MAX MIN MAX 4 90 5 10 0 193 0 200 4 30 4 50 0 169 0 177 1 20 0 047 0 05 0 15 0 002 0 006 0 50 0 75 0 020 10 030 0 65 BSC 0 026 BSC 0 50 0 60 0 020 10 024 0 09 0 20 0 004 0 008 0 09 0 16 0 004 0 006 0 19 0 30 0 007 0 012 0 19 0 25 0 007 0 010 6 40 BSC 0 252 BSC 0 8 0 8 K K1 SECTION N N H Ki L il H DETAIL lt SOLDERING FOOTPRINT p 7 06 9 1 C C C C 0 65 dez om PM C m DIMENSIONS MILLIMETERS For additional information on our Pb Free strategy and soldering details please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual SOLDERRM D http onsemi com 11 0 13 0 005 C 0 10 0 004 VIEW P MC74AC74 74 74 SOEIAJ 14 CASE 965 01 ISSUE A LE M m DETAIL NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE MOLD FLASH OR PROTRUSIONS SHAL
3. ON Semiconductor P O Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Email orderlit onsemi com N American Technical Support 800 282 9855 Toll Free USA Canada Europe Middle East and Africa Technical Support Phone 421 33 790 2910 Japan Customer Focus Center Phone 81 3 5773 3850 ON Semiconductor Website www onsemi com Order Literature http www onsemi com orderlit For additional information please contact your local Sales Representative MC74AC74 D
4. V VoH Minimum High Level 4 5 lout 50 uA Output Voltage Vin Vit or Vin 24 mA 24 mA Maximum Low Level Output Voltage Maximum Input Leakage Current Additional Max Icc Input Vin Vit or Vin 24 mA 5 5 45 5 5 45 5 5 45 5 5 24 mA 1 65 V Max 3 85 Min VIN Voc or GND TMinimum Dynamic Output Current Maximum Quiescent Supply Current All outputs loaded thresholds on input associated with output under test TMaximum test duration 2 0 ms one output loaded at a time AC CHARACTERISTICS For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book DL138 D Vec 25 C Parameter v e E pe pF to 85 C 50 pF Maximum Clock 5 0 Frequency e ss eo roo o ne Voltage Range 5 0 V is 5 0 V 0 5 V http onsemi com 5 74 74 MC74ACT74 AC OPERATING REQUIREMENTS ys un hc deeem up Time HIGH or LOW mE to Hold Time HIGH or LOW 50 to i Cpn or Cpn or Spn T Pulse Width i Recovery Time or Spn to CP Voltage Range 5 0 V is 5 0 V 0 5 V CAPACITANCE TM NE ES 0m X alii ER Power Dissipation Capacitance MM M BE Vcc 5 0 V http onsemi com 6 74 74 MC74ACT74 ORDERING INFORMATION MC74AC74N PDIP 14 MC74AC74NG PDIP 14 Pb Free 25 Units Rail MC74ACT74N PDIP 14 MC74ACT74NG PDIP 14 Pb
5. BSC 0 050BSC PLANE J 0 19 0 25 0 008 0 009 6 25 101005 T B 0 25 0 004 0 009 m o 7 09 7 580 620 0228 0 244 025 0 50 0 010 0 019 SOLDERING FOOTPRINT 7X 7 04 HU UU DIMENSIONS MILLIMETERS For additional information on our Pb Free strategy and soldering details please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual SOLDERRM D http onsemi com 10 MC74AC74 74 74 PACKAGE DIMENSIONS 14x REF TSSOP 14 CASE 948G 01 ISSUE B NOTES T UG ANSI u 0 10 0 004 49 0 15 0 006 0 15 0 006 0 10 0 004 SEATING DIMENSIONING AND TOLERANCING Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER DIMENSION A DOES NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS MOLD FLASH OR GATE BURRS SHALL NOT 0 25 0 01 0 EXCEED 0 15 0 006 PER SIDE 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION M INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0 25 0 010 PER SIDE 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR CESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION PROTRUSION SHALL BE 0 08 0 003 TOTAL F IN EX
6. EE Input Rise and Fall Time Note 5 10 ACT Devices except Schmitt Inputs lVcessv Operating Ambient Temperature Range Output Current High Output Current Low 1 Vin from 30 to 70 Vcc see individual Data Sheets for devices that differ from the typical input rise and fall times 2 from 0 8 V to 2 0 V see individual Data Sheets for devices that differ from the typical input rise and fall times DC CHARACTERISTICS 25 Conditions Guaranteed Limits Minimum High Level 1 5 2 1 2 1 Vout 0 1 V Input Voltage 2 25 3 15 3 15 Vcc 0 1 2 75 3 85 3 85 Maximum Low Level 1 5 0 9 0 9 Vout 0 1 V Input Voltage 2 25 1 35 1 35 Vcc 0 1 2 75 1 65 1 65 Minimum High Level 5 2 99 2 9 lout 50 uA Output Voltage E 4 49 4 4 5 49 5 4 Vin Vit or Vin 2 56 i 12 mA 3 86 24 mA 4 86 24 mA Maximum Low Level 0 002 0 1 lout 50 uA Output Voltage 0 001 0 1 0 001 0 1 Vin Vit or Vin 0 36 12 mA 0 36 loL 24 mA 0 36 24 mA 5 5 Maximum Input Output t Maximum Quiescent Supply Current eee Ns E idi All outputs loaded thresholds on input associated with output under test TMaximum test duration 2 0 ms one output loaded at a time NOTE liy and Icc 3 0 V are guaranteed to be less than or equal to the respec
7. Free MC74AC74DG SOIC 14 55 Units Rail Pb Free MC74AC74DR2G SOIC 14 2500 Tape amp Reel Pb Free MC74ACT74DG SOIC 14 55 Units Rail Pb Free MC74ACT74DR2G SOIC 14 2500 Tape amp Reel Pb Free MC74AC74DT TSSOP 14 96 Units Rail MC74AC74DTR2 TSSOP 14 2500 Tape amp Reel MC74AC74DTR2G TSSOP 14 MC74ACT74DT TSSOP 14 96 Units Rail MC74ACT74DTR2 TSSOP 14 2500 Tape amp Reel MC74ACT74DTR2G TSSOP 14 MC74AC74MEL SOEIAJ 14 MC74AC74MELG SOEIAJ 14 Pb Free 2000 Tape amp Reel MC74ACT74MEL SOEIAJ 14 MC74ACT74MELG SOEIAJ 14 Pb Free TFor information on tape and reel specifications including part orientation and tape sizes please refer to our Tape and Reel Packaging Specifications Brochure BRD8011 D This package is inherently Pb Free http onsemi com 7 MC74AC74 74 74 MARKING DIAGRAMS PDIP 14 SOIC 14 TSSOP 14 SOEIAJ 14 74 74 74 74 Assembly Location WL L Wafer Lot Year WW W Work Week Pb Free Package Note Microdot may be in either location http onsemi com 8 MC74AC74 74 74 PACKAGE DIMENSIONS PDIP 14 CASE 646 06 ISSUE P pac DIMENSIONING AND TOLERANCING PER ANSI 14 5 1982 CONTROLLING DIMENSION INCH DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL DIMENSION B DOES NOT INCLUDE MOLD FLASH ROUNDED CORNERS OPTIONAL INCHES MILLIMETERS A MIN MAX MIN MAX 0 715 0 770
8. L NOT EXCEED 0 15 0 006 PER SIDE 4 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY 5 THE LEAD WIDTH DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 0 003 TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0 46 0 018 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 2 05 0 081 005 0 20 0 002 0 008 b 0 35 0 50 0 014 0 020 0 10 0 20 0 004 0 008 D 9 90 10 50 0 390 0 413 E 510 545 0201 0 215 e 1 27 BSC 0 050 BSC HE 740 820 0291 0 323 0 50 0 50 0 85 0 020 0 033 LE 1 10 1 50 0 043 0 059 M 09 109 09 10 Q 070 0 90 0 028 0 035 Z 142 0 056 ON Semiconductor and W are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters
9. MC74AC74 MC74ACT74 Dual D Type Positive Edge Triggered Flip Flop The MC74AC74 74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary Q Q outputs Information at the input is transferred to the outputs on the positive edge of the clock pulse Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse After the Clock Pulse input threshold voltage has been passed the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input Asynchronous Inputs LOW input to Sp Set sets Q to HIGH level LOW input to Cp Clear sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on Cp and Sp makes both Q and Q HIGH Features Outputs Source Sink 24 mA ACT74 Has TTL Compatible Inputs Pb Free Packages are Available 02 5 Q 0 D CP Sp 0 GND Figure 1 Pinout 14 Lead Packages Conductors Top View PIN ASSIGNMENT PIN FUNCTION Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Q1 Q1 Qo Outputs Q2 Semiconductor Components Industries LLC 2006 1 October 2006 Rev 7 ON Semiconductor http onsemi com eee SUFFIX 646 14 3 SOIC 14 lt xi D SUFFIX 14 NS CASE 751A CASE 948G de TSSOP 14 14 SR D
10. T SUFFIX 965 SOEIAJ 14 Ke M SUFFIX ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet Publication Order Number MC74AC74 D MC74AC74 MC74ACT74 TRUTH TABLE Each Half NOTE HIGH Voltage Level L LOW Voltage Level X Immaterial LOW to HIGH Clock Transition Qo Qo Previous Q Q before LOW to HIGH Transition of Clock NOTE This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays Figure 3 Logic Diagram MAXIMUM RATINGS DC Supply Voltage Referenced to GND 0 5 to 47 0 DC Input Voltage Referenced to GND 0 5 to Voc 0 5 DC Output Voltage Referenced to GND 0 5 to 0 5 oa Stresses exceeding Maximum Ratings may damage the device Maximum Ratings are stress ratings only Functional operation above the Recommended Operating Conditions is not implied Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability http onsemi com 2 74 74 74 KR OPERATING CONDITIONS Symbol Parameter _________ 8e o pe ape a RTT tT Input Rise and Fall Time Note 457 Devices except Schmitt Inputs Voc 4 5 V
11. tive limit 5 5 V Vcc http onsemi com 3 MC74AC74 MC74ACT74 AC CHARACTERISTICS For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book DL138 D Parameter ERE eG hec Propagation Delay or Spn to or Qn Propagation Delay Spn to Qn or Qn Propagation Delay to Qn or Qn Propagation Delay to Qn or Qn Voltage Range 3 3 V is 3 3 V 0 3 V Voltage Range 5 0 V is 5 0 V 0 5 V AC OPERATING REQUIREMENTS A or or Spn Pulse Width Recovery Time or Spn to Voltage Range 3 3 V is 3 3 V 0 3 V Voltage Range 5 0 V is 5 0 V 0 5 V Min 100 140 5 0 3 5 4 0 3 0 4 5 3 5 3 5 2 5 http onsemi com 4 74 25 C 50 pF TA 25 C 50 pF Cus woe 125 95 125 40 13 0 m 90 100 5 E 105 120 35 13 5 oe 95 25 105 S 8 0 135 40 160 60 100 10 5 S 140 35 145 T 6 0 100 25 105 S 40 to 85 C C 50 pF 74 74 MC74ACT74 DC CHARACTERISTICS 74ACT 74AC V Symbol Parameter Ta 25 40 10 Conditions 85 C Guaranteed Limits Minimum High Level 4 5 1 5 2 0 2 0 V Vout 0 1 V Input Voltage 5 5 1 5 2 0 2 0 or Vcc 0 1 Vit Maximum Low Level 45 Vout 0 1 V Input Voltage 5 5 or Vcc 0 1
12. which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT Literature Distribution Center for
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