TEXAS INSTRUMENTS CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 datasheet
Contents
1. __________ wa 10 10 Input Capacitance ESS a me ec 58 Power Dissipation Cpp 5 34 pF Capacitance Notes 4 5 NOTES 4 Cpp is used to determine the dynamic power consumption per package 5 Vec fi Vec fo where f Input Frequency fo Input Frequency Output Load Capacitance Vcc Supply Voltage CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Prerequisite For Switching Specifications 40 C TO 85 C 55 C 125 C HC TYPES Maximum Clock Frequency MHz MHz N mN MHz MR Pulse Width 25 2 o Clock Pulse Width 2 o n 2 o 2 o Set up Time Data to Clock and E to Clock Hold Time Data to Clock 2 o 2 o 2 o Hold Time E to Clock 2 o 2 o 2 o Removal Time MR to Clock 2 o 2 2 2 2 2 2 2 o o o o o o o HCT TYPES wx 9 ___ exem ___ a Bewerten w e 8 12 fw ECCE Pme fw peamees 8 ECCE ECCE ECCE I N Po Co 2 2 2 2 o o o o o 2 CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Test Circuits and Waveforms tC twL twH di 50 10 NOTE Outputs should be switching from 10 Voc to 90 Vcc in accordance with device truth table For fyyax input duty cycle 50 FIGURE 1 HC CLOCK PULSE RI2. 14 PINS SHOWN MECHANICAL DATA 0 25M Seating Plane 2 00 MAX PLASTIC SMALL OUTLINE PACKAGE 0 15 NOM t Gage Plane c3 0 10 A NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion not to exceed 0 15 4040062 C 03 03 45 TEXAS INSTRUMENTS www ti com MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PINS SHOWN 0 15 NOM i casera a E Seating Plane ea 20 MAX 0 15 1j Z 0 0 0 05 PINS DIM A MAX A MIN 4040064 F 01 97 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 Dou 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Inst
3. as those for three state shown on the left The test circuit is Output R 1kQ to CL 50pF FIGURE 9 HC AND HCT THREE STATE PROPAGATION DELAY TEST CIRCUIT K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 28 Feb 2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp 3 Type Drawing Qty 5962 8682501EA ACTIVE CDIP J 16 1 None Call TI Level NC NC NC 5962 8875901EA ACTIVE CDIP J 16 1 None Call TI Level NC NC NC CD54HC173F ACTIVE CDIP J 16 1 None Call TI Level NC NC NC CD54HC173F3A ACTIVE CDIP J 16 1 None Call TI Level NC NC NC CD54HCT173F3A ACTIVE CDIP J 16 1 None Call TI Level NC NC NC CD74HC173E ACTIVE PDIP N 16 25 Pb Free CU NIPDAU Level NC NC NC RoHS CD74HC173M ACTIVE SOIC D 16 40 Pb Free NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM CD74HC173M96 ACTIVE SOIC D 16 2500 Pb Free CU NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM CD74HC173MT ACTIVE SOIC D 16 250 Pb Free NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM CD74HC173NSR ACTIVE SO NS 16 2000 Pb Free CU NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM CD74HC173PW ACTIVE TSSOP PW 16 90 Pb Free CU NIPDAU Level 1 250C UNLIM RoHS CD74HC173PWR ACTIVE TSSOP PW 16 2000 Pb Free CU NIPDAU Level 1 250C UNLIM RoHS CD74HC173PWT ACTIVE TSSOP PW 16 250 Pb Free CU NIPDAU Level 1 250C UNLIM RoHS CD74HCT173E ACTIVE PD
4. www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated
5. 3 amp 18 5962 8682501EA E RV FS 45 INSTRUMENTS Data sheet acquired from Harris Semiconductor SCHS158E February 1998 Revised October 2003 Features Three State Buffered Outputs Gated Input and Output Enables Fanout Over Temperature Range Standard Outputs 10 LSTTL Loads Bus Driver Outputs 15 LSTTL Loads Wide Operating Temperature Range 55 C to 125 C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types 2V to 6V Operation High Noise Immunity 30 30 of Vcc at Vcc 5V HCT Types 4 5V to 5 5V Operation Direct LSTTL Input Logic Compatibility 0 8V Max 2V Min CMOS Input Compatibility lj lt 14A at Pinout CD54HC173 CD54HCT173 CERDIP CD74HC173 PDIP SOIC SOP TSSOP CD74HCT173 PDIP SOIC TOP VIEW CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 High Speed CMOS Logic Quad D Type Flip Flop Three State Description The HC173 and HCT173 high speed three state quad D type flip flops are fabricated with silicon gate CMOS technol ogy They possess the low power consumption of standard CMOS Integrated circuits and can operate at speeds com parable to the equivalent low power Schottky devices The buffered outputs can drive 15 LSTTL loads The large output drive capability and three state feature make these parts ide ally suited for interfacing with bus lines in
6. 5 08 Cau x ge Plane l Seating Plane 125 3 18 MIN gt 4 0 010 0 25 NOM d 0 430 10 92 MAX D MAX 7 0 51 0 2 t 0 38 0 010 0 25 49 14 18 Pin Only 20 Pin vendor option A 4040049 E 12 2002 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Falls within JEDEC 5 001 except 18 and 20 pin minimum body length Dim The 20 pin end lead shoulder width is a vendor option either half or full width bp o gt 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA D R PDSO G16 PLASTIC SMALL OUTLINE PACKAGE 0 394 10 00 0 386 9 80 SS 8 Pin 1 Index Area 0 050 1 27 0 020 0 51 0 012 0 31 4 0 010 0 25 49 L 0 069 1 75 Max 7 0 004 0 10 Gauge Plane x Seating Plane 0 010 0 25 4040047 4 F 07 2004 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MS 012 variation AC 35 TEXAS INSTRUMENTS www ti com NS R PDSO G
7. CKAG B nnmnmnmnmnn ed 0 065 1 65 0 045 1 14 lt 0 005 0 13 MIN 0 026 0 66 0 014 0 36 0 100 2 54 PINS B 14 16 18 20 gt 0 300 0 300 0 300 0 300 A 7 62 7 62 7 62 7 62 BSC BSC BSC BSC ET 0 785 840 0 960 1 060 1 19 94 21 34 24 38 26 92 C B MIN Ep 0 300 0 300 0 310 0 300 7 62 7 62 7 87 7 62 EAN 0 245 0 245 0 220 0 245 6 22 6 22 5 59 6 22 0 060 1 52 0 015 0 38 0 200 5 08 MAX n Y Seating Plane t 0 130 3 30 MIN x U U 0 15 0 014 0 36 4040083 F 03 03 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice This package is hermetically sealed with a ceramic lid using glass frit Index point is provided on cap for terminal identification only on press ceramic glass frit seal only Falls within MIL STD 1835 GDIP1 114 GDIP1 T16 GDIP1 T18 and GDIP1 T20 MECHANICAL DATA N R PDIP T PLASTIC DUAL IN LINE PACKAGE 16 PINS SHOWN PINS DIM A MAX A MIN MS 001 VARIATION 0 020 MIN 0 015 0 38 00
8. HCT173 Functional Diagram TRUTH TABLE INPUTS H High Voltage Level L Low Voltage Level X Irrelevant T Transition from Low to High Level Qo Level Before the Indicated Steady State Input Conditions Were Established NOTE 1 When either OE1 or OE2 or both is are high the output is dis abled to the high impedance state however sequential opera tion of the flip flops is not affected CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Logic Diagram 3 CIRCUITS IDENTICAL ABOVE CIRCUIT IN DASHED ENCLOSURE CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Absolute Maximum Ratings DC Supply Voltage Vcc DC Input Diode Current For Vj lt 0 5V or Vi gt Veg 0 5 20mA DC Output Diode Current loy For Vo lt 0 5V or Vo gt 0 5 20 DC Output Source or Sink Current per Output Pin Io For Vo gt 0 5V or lt Voc 0 5 25mA DC Voc or Ground Current IGG 70mA 0 5V to 7V Operating Conditions Temperature Range Ta Supply Voltage Range Vcc HC Types 2V to 6V TYPOS ise eee eter ect d 4 5V to 5 5V DC Input or Output Voltage Vi Vo Input Rise and Fall Time 550C to 125 C 1000ns Max 500ns Max 400ns Max Thermal Information Package Thermal Impedance see Note 2 E PDIP Package M SOIC Package NS SOP Package PW TSSOP Package Maximum Jun
9. IP N 16 25 Pb Free CU NIPDAU Level NC NC NC RoHS CD74HCT173M ACTIVE SOIC D 16 40 Pb Free NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM CD74HCT173M96 ACTIVE SOIC D 16 2500 Pb Free CU NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM CD74HCT173MT ACTIVE SOIC D 16 250 Pb Free NIPDAU Level 2 260C 1 YEAR RoHS Level 1 235C UNLIM The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan May not be currently available please check http www ti com productcontent for the latest availability information and additional product content details None Not yet available Lead Pb Free Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Gre
10. SE AND FALL TIMES AND PULSE WIDTH INVERTING OUTPUT FIGURE 3 HC AND HCU TRANSITION TIMES AND PROPAGA TION DELAY TIMES COMBINATION LOGIC OUTPUT Vcc SET RESET OR PRESET FIGURE 5 HC SETUP TIMES HOLD TIMES REMOVAL TIME AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS t t WL WH TCL tC 6ns NOTE Outputs should be switching from 10 Vcc to 90 Vec accordance with device truth table For fyyax input duty cycle 50 FIGURE 2 HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INVERTING OUTPUT FIGURE 4 HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES COMBINATION LOGIC OUTPUT SET RESET OR PRESET FIGURE 6 HCT SETUP TIMES HOLD TIMES REMOVAL TIME AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Test Circuits and Waveforms continued OUTPUT OUTPUT DISABLE Y DISABLE OUTPUT LOW OUTPUT LOW TO OFF TO OFF OUTPUT HIGH OUTPUT HIGH TO OFF 1 3V OUTPUTS OUTPUTS s lt OUTPUTS ENABLED DISABLED ENABLED OUTPUTS OUTPUTS DISABLED ENABLED FIGURE 7 HC THREE STATE PROPAGATION DELAY FIGURE 8 HCT THREE STATE PROPAGATION DELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH TIED HIGH THREE FOR tpz AND 1 2 OR LOW STATE GND FOR AND tpzy TPUT OUTPUT QUTRU DISABLE NOTE Open drain waveforms tp 7 and tpz are the same
11. blished by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military
12. bus oriented sys tems The four D type flip flops operate synchronously from a com mon clock The outputs are in the three state mode when either of the two output disable pins are at the logic 1 level The input ENABLES allow the flip flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic 1 level the Q outputs are fed back to the inputs forcing the flip flops to remain in the same state Reset is enabled by taking the MASTER RESET MR input to a logic 1 level The data outputs change state on the positive going edge of the clock The HCT173 logic family is functionally as well as pin com patible with the standard LS logic family Ordering Information TEMP RANGE PART NUMBER c PACKAGE CD54HCT173F3A 5510125 116 Ld CERDIP CD74HC173M 55 to 125 NOTE When ordering use the entire part number The suffixes 96 and R denote tape and reel The suffix T denotes a small quantity reel of 250 CD74HC173MT 55 to 125 CD74HC173M96 55 to 125 CD74HC173NSR 55 to 125 CD74HC173PW 55 to 125 CD74HC173PWR 55 to 125 CD74HC173PWT 55 to 125 CD74HCT173E 55 to 125 CD74HCT173M 55 to 125 CD74HCT173MT 55 to 125 CD74HCT173M96 55 to 125 CAUTION These devices are sensitive to electrostatic discharge Users should follow proper IC Handling Procedures Copyright 2003 Texas Instruments Incorporated CD54HC173 CD74HC173 CD54HCT173 CD74
13. ction Temperature Maximum Storage Temperature Range Maximum Lead Temperature Soldering 10s SOIC Lead Tips Only CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 2 The package thermal impedance is calculated in accordance with JESD 51 7 DC Electrical Specifications TEST CONDITIONS 40 C TO 859C 55 C TO 125 C PARAMETER SYMBOL Vcc V UNITS HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Quiescent Device Current ale MAE lt lt AB elf P lt CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 DC Electrical Specifications Continued TEST CONDITIONS 40 C TO 859C 55 C TO 125 C PARAMETER SYMBOL Vcc V Fu ave wx wn wax m wax jos Three State Leakage loz Vip or 10 5 10 5 10 uA Current VIH HCT TYPES High Level Input 4 5 2 2 2 V Voltage 5 5 Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Out
14. en RoHS amp no Sb Br TI defines Green to mean Pb Free and in addition uses package materials that do not contain halogens including bromine Br or antimony Sb above 0 1 of total product weight 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the Addendum Page 1 K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 28 Feb 2005 accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 2 J R G DIP Tx 14 LEADS SHOWN CERAMIC DUAL IN LINE PA
15. put Voltage TTL Loads Quiescent Device Current Additional Quiescent Device Current Per Input Pin 1 Unit Load Three State Leakage loz or 5 5 10 5 5 0 10 uA Current VIH NOTE 3 For dual supply systems theoretical worst case V 2 4V Vcc 5 5V specification is 1 8mA HCT Input Loading Table NOTE Unit Load is Alcc limit specified in DC Electrical Specifications table e g 360uA max at 25 C CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Switching Specifications Input ty t 6ns EN 40 C TO 85 C 559C TO 125 C HC TYPES eme s 3 9 Propagation Delay MR to tPHL C 50pF 2 173 Output rco WE E sme pp s Pme Dem oua wm ume 2 _ zs ee fk eee O e fF Output Transition Times trip CL 50pF o 99 Jn 5 9 5 ep e qe 3s p a ae 6 IEEE REND 3 Input Input Capacitance Three State Output lt Capacitance Power Dissipation Capacitance Notes 4 5 HCT TYPES Propagation Delay Clock to PLH PHL ee MEME d Propagation Delay MR to PHL 8 E TEC T Propagation Delay Output seer DEOR 39 as _ E ew faf s f e L oer 8 9 2 Es wx 8
16. ruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information pu
Download Pdf Manuals
Related Search
TEXAS INSTRUMENTS CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 datasheet