TERIDIAN 73S8023C handbook
Contents
1. Revision Date Description 1 0 6 13 2005 First publication 1 1 7 15 2005 Converted to Teridian format 1 2 12 5 2007 Add EMV and ISO logo remove leaded package option change 32QFN punched to SAWN package 1 3 1 17 2008 Changed dimension of bottom exposed pad on 32QFN mechanical package figure 1 4 1 8 2009 Added NDS logo to page 1 and assigned document number 1 5 4 3 2009 Removed all references to VPC as VPC must be tied to VDD 2009 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Simplifying System Integration is a trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http Awww teridian com or by checking with your sales representative Teridian Semico2. 22 Interrupt signal to the processor Active Low Multi function indicating fault conditions and card presence Open drain output configuration it includes an internal 20 KQ pull up to Vpp RSTIN Reset Input This signal controls the RST signal to the card I OUC System controller data I O to from the card Includes internal pull up resistor to Vpp AUX1UC System controller auxiliary data I O to from the card Includes internal pull up resistor to V pp AUX2UC System controller auxiliary data I O to from the card Includes internal pull up resistor to V pp CS When CS 1 the control and signal pins are configured normally When CS is set low signals CMDVCC RSTIN PWRDN 5V V CLKDIV1 CLKDIV2 CLKSEL are latched I OUC AUX1UC and AUX2UC are set to high impedance pull up mode and won t pass data to or from the smart card OFF output is tri stated CLKSEL 16 Selects CLK and RST operational mode When CLKSEL is low default the circuit is configured for asynchronous card operation and the sequencer manages the control of CLK and RST When CLKSEL is high the signal CLK is a buffered copy of STROBE and the signal RST is directly controlled by RSTIN STROBE 25 When CLKSEL 1 the signal CLK is controlled directly by STROBE CLKOUT 32 CLKOUT is the buffered version of the signal on pin XTALIN Rev 1 5 DS_8023C_019 73S8023C Data Sheet 2 Syste
3. 73S8023C Smart Card Interface Simplifying System Integration DATASHEET ISO IEC VNDS 7816 3 EMVCo DESCRIPTION The Teridian 73S8023C is a low power high efficiency single smart card interface IC suitable for 3V and 5V cards It provides full electrical compliance with ISO 7816 3 and EMV 4 0 EMV2000 specifications Hardware support for any type of synchronous cards memory cards is provided Interfacing with the system controller is done through the control bus composed o digital inputs to control the interface and one interrupt output to inform the system controller of the card presence and faults Data exchange with the card is managed from the system controller using the I O line and eventually the auxiliary I O lines A chip select input allows multiple 73S8023C ICs to share the same control bus When chip select is set low the host microcontroller inputs are latched and outputs are taken to a high impedance state The card clock signal can be generated by an on chip oscillator using an external crystal or by connecting an external clock signal The 73S8023C device incorporates an ISO 7816 3 activation deactivation sequencer that controls the card signals Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry The 73S8023C requires only a single 2 7 V to 3 6 V power supply and features a high efficiency embedded DC DC converter
4. Active mode lcc lt 65 MA 3 V Active mode single pulse of 100 mA for 2 us 5 V Card supply voltage fixed load 25 mA including ripple and noise Active mode single pulse of 100 mA for 2 us 3 V fixed load 25 mA Active mode current pulses of 40 nAs with peak Icc lt 200 mA t lt 400 ns 5 V Active mode current pulses of 40 nAs with peak Icc lt 200 mA t lt 400 ns 3 V Vecr VCC Ripple 350 mV Maximum supply current Static load current ccmax tothe card Vcc gt 4 6 or 2 7 V as 100 mA selected L 10 uH locr lcc fault current 100 125 180 mA Vsr Se See EE Cr on Vec 1 uF 005 045 025 Vins Vec slew rate Fall rate Ce Mat on deactivate Cre on Vec 1uF 0 1 0 3 0 5 V us External filter capacitor C Von to GND p 047 33 4 7 uF L Inductor LIN to Vpp 10 uH 2 SE Vcc 5V Icc 65 mA Limax Imax in inductor Voo 2 7 V 400 mA P Vec 5 V lec 65 mA 0 n Efficiency Voo 3 3 V 87 Yo Rev 1 5 19 73S8023C Data Sheet DS_8023C_019 Converter Efficiency Vcc 5 V 100 95 90 85 80 75 70 Efficiency 65 60 55 50 Icc mA Figure 12 DC DC Converter efficiency Vcc 5 V Output current on Vcc at 5 V Input voltage on Vpp at 2 7 3 0 3 3 and 3 6 volts Converter Efficiency Vcc 3 V 100 95 90 8
5. 11 8 3 Activation Sequence Asynchronous Mode 12 8 4 Deactivation Sequence Asynchronous Mode 14 9 OFF nd Fault Detection u SIR etna EEN 14 10 HO Circuitry and TIMING TE 15 11 Typical Application Schematic tenet anan U u uu uuu u T 17 12 Electrical Specificatii uuu u asana aaa nawan naa gana naa ake NEESS 18 12 1 Absolute Maximum RattingS A 18 12 2 Recommended Operating Conditions n nrnna 18 12 3 Package Thermal Parameters a a n anna 18 12 4 Card Interface Characteristics ioin A u DEN E NA KAG NAN TE E KG ANG AAK KE pa depa A 19 12 5 Digital le LEE 22 12 6 DE Characteristics asi saa ka u S Saa mu wa DAKA NG AG TA DA EA Ka as GB ie E Ag aaa UN aa a 23 12 7 Voltage Temperature Fault Detection Circus 23 13 Mechanical Drawing 32 QFN I I uu uu u 24 14 Package Pin Designation 32 QFN U u uu uuu 25 15 Ordering lee d EE 26 16 Related Documentation J J J J J Q J J Q Q J Q J Q J J J J 26 17 Contact Information ccciccccceticececsiseentsecsessansisacnnesecesnansvseentsvececonsteedeoceterccontsveconssverscaeaavvadecatineaaaanies 26 REVISION Hueste M a EEGENEN 27 Rev 1 5 3 73S8023C Data Sheet DS_8023C_019 Figures Figure 1 Figure 2 Figure 3 Figure 4 Fi
6. AUX1 11 AUX1 Auxiliary data signal to from card Includes a pull up resistor to Vcc AUX2 10 AUX2 Auxiliary data signal to from card Includes a pull up resistor to Vec RST 14 Card reset Provides reset RST signal to card CLK 13 Card clock Provides clock CLK signal to card The rate of this clock is determined by crystal oscillator frequency and CLKDIV selections PRES 7 Card Presence switch Active high indicates card is present Includes a pull down current source PRES 6 Card Presence switch Active low indicates card is present Includes a pull up current source VCC 15 Card power supply Logically controlled by sequencer output of DC DC converter Requires an external filter capacitor to the card GND GND 12 Card ground 1 2 Miscellaneous Inputs and Outputs Name Pin Description XTALIN 23 Crystal oscillator input can either be connected to crystal or driven as a source for the card clock XTALOUT 24 Crystal oscillator output connected to crystal Left open if XTALIN is being used as external clock input VDDF_ADJ 17 Vbp fault threshold adjustment input this pin can be used to adjust V ppF value that controls deactivation of the card Must be left open if unused NC 4 Non connected pin Must be left open 1 3 Power Supply and Ground wane Pin oso O VDD 3 20 System controller interface supply voltage Supply voltage for internal power supply and DC DC converter power supp
7. This architecture plus a Power Down digital input that allow placing the IC in a very low power mode making the 73S8023C particularly suitable for low power applications cell phones PDAs payphones hand held POS terminals ADVANTAGES e Supports both synchronous and asynchronous smart cards e Replacement for TDA8002 with up to 600 mW in power savings EMV ICCmax condition 7 e The inductor based DC DC converter provides higher current and efficiency gt Ideal for battery powered applications gt Suitable for high current cards and SAMs 100 mA max gt Single 2 7 V to 3 6 V power supply allows removal j of 5 V from the system e Power down mode 2 uA typical 7 e Package Small Format 5x5mm 32 QFN April 2009 FEATURES Card Interface Complies with ISO 7816 3 EMV 4 0 A DC DC Converter provides 3V 5V to the card from an external power supply input High efficiency converter gt 80 Vpp 3 3 V Vec 5 V and Icc 65 MA Up to 100 mA supplied to the card SO 7816 3 Activation Deactivation sequencer with emergency automated deactivation Protection includes 2 voltage supervisors which detect voltage drops on card Vcc and on Vpp power supply The Vpop voltage supervisor threshold value can be externally adjusted True over current detection 150 mA max 2 card detection inputs 1 for either possible switch configuration Full support of synchronous cards System Cont
8. ee E Sipweon 73S8023C pp 2 TT d 6 PRES RSTIN 2 cg EE NOTE 1 CRYSTAL 22pF PWRDN_from_uC Z PRES CMDVCC H L cs VDDF_ADJ 9 See NOTE 5 a ae 100nF See NOTE 4 Na Oo Q 05 524585 be St OU zO estom ue L gt agay 32QFN L4 CLKSEL_from_uC A gt OFF_interrupt_to_uC K NOTES RSTIN_from_uC l SO7816 1uF NDS EMV 3 3uF lt _ _ CMDVCC_from_uc 1 VDD supply must be 2 7V to 3 6V DC 27pF 27pF S 27pF 2 Keep L1 close to pin 2 VDD ER c7 cg ci LOW ESR lt 100mohms C1 3 Required if external clock from uP is used R2 cb should be placed near the SC S 5 P K k connecter contact 4 Required if crystal is used EN de A w 7 Y1 C2 and C3 must be removed if external clock is used Z DIN ORO DA bad ka AAN 5 Pin can not float Must be driven or connected to GND if ROXAtYE GB Card detection 0 Sama H CLK track should be routed power down function is not used switch is aa e OES eee i C ar II HU 6 Internal pull up allows it to be left open if unused SE c8 7 Rext1 and Rext2 are external resistors to ground and VDD to modify the VDD fault voltage Can be left open Smart Card Connector 8 Capacitors C7 and C8 are optional C6 is mandatory for NDS Figure 11 73S8023C Typical Application Schematic Rev 1 5 17 73S8023C Data Sheet DS_8023C_019 12 Electrical Specification 12 1 Absolute Maximum Ratings ES Operation outside these rating limi
9. Voo FAULT y FAULT Dene Ka CONVERTER I GND PWRDN 15 vcc cs ICC RESET cmpvec 18 I DIGITAL BUFFER 14 Ror 19 I CIRCUITRY RSTIN amp 311 FAULT LOGIC AN ICC CLOCK ug o 2I BUFFER CLK OFF 29 25 CLKDIV1 STROBE 30 L16 CLKDIV2 ISO 7816 3 SE 23 7 XTALIN PRES 24 XTALOUT GENERATION PRES OVER CLKOUT TEME TEMP FAULT aq 9 IIO IOUC 11 ICC I O BUFFERS A AUX1UC 10 AUX2UC AUX2 Figure 1 73S8023C Block Diagram 2 Rev 1 5 DS_8023C_019 73S8023C Data Sheet Table of Contents 1 Pin Description 5 ES De gell En le 5 1 2 Miscellaneous Inputs and Output 5 1 3 Power Supply and Ground NEEN 5 LA Microcontroller Interace ak kakao ka kaka A AAN KA ens ANA BAN ba Ka Kn NGANAN KAN ANA KAKA KN EA y AN A SEN BA a A AN 6 2 System Controller Interface i u u iu A dan akan ga aana agung anda aana ege 7 3 e UE EE 8 4 DC DC Converter Card Power Supply U u u 8 5 Voltage SUPCIviSlON E 9 Gs POW r DOWN Qu u aana T aa DAGAN dev NGA a NGAEN anaa aan ba GD Nha GENK ah aaa A DENG Na a dinan 10 Z Over T emperature Motor uuu sanagi ENEE nies Nang aa NEES Deene neng una 10 8 Activation and Deactivation U U U u u u u uuu uu u 11 8 1 Activation Sequence Synchronous Mode 11 8 2 Deactivation Sequence Synchronous Mode l nsn nu
10. digital circuitry is powered by the power supply applied on the VDD pin Von also defines the voltage range for the interface with the system controller The Vpp Voltage supervisor is also used to initialize the ISO 7816 3 sequencer at power on and also to deactivate the card at power off or upon a fault The voltage threshold of the Vpp voltage supervisor is internally set by default to 2 3 V nominal However it may be desirable in some applications to modify this threshold value The pin VDDF_ADJ pin 17 is used to connect an external resistor Rex to ground to raise the Vpp fault voltage to another value Vppe The resistor value is defined as follows Rext 180 kO JUN oe 2 33 An alternative more accurate method of adjusting the Vpp fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground see Figure 11 73S8023C Typical Application Schematic In order to set the new threshold voltage the equivalent resistance must be determined This resistance value will be designated Kx Kx is defined as R1 R1 R3 Kx is calculated as Kx 2 649 Van 0 6042 where Vo is the desired new threshold voltage To determine the values of R1 and R3 use the following formulas R3 72000 Kx R1 R3 Kx 1 Kx Taking the example above where a V pp fault threshold voltage of 2 7 V is desired solving for Kx gives gt Kx 2 649 2 7 0 6042 0 377 Solving for R3 gives R3 72000
11. the session and are indicated to the system controller by the fall of OFF The following steps list the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or a fault condition sets OFF low 1 RST goes low at time t 2 CLK stops low at time to 3 I O goes low at time tz Out of reception mode 4 Vcc is shut down at time t After a delay ts discharge of the Vcc capacitor Vcc is low Rev 1 5 11 73S8023C Data Sheet DS_8023C_019 CMDVCC OR OFF VCC IO RSTIN RST STROBE CLK to DG t3 t4 t5 to Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault t1 RST falls approx 0 5us after deactivation begins t2 CLK falls approx 7 5us after RST falls t3 IO falls approx 2us after CLK falls t4 VCC is shut down ts VCC goes to 0 after discharge of VCC capacitor approx 100us after deactivation begins Note Host should set STROBE low when CMDVCC is set high otherwise CLK may be truncated CLK truncation may occur if an OFF event is triggered Figure 4 Synchronous Deactivation Operation CKSEL High 8 3 Activation Sequence Asynchronous Mode The 73S8023C smart card interface IC has an internal 10 ms delay at power on reset or upon application Of Voo gt Vopr Or upon exit of Powe
12. 0 377 191 kO Solving for R1 gives gt R1 191000 0 377 1 0 377 115 6 kO Using standard 1 resistor values gives R3 191 kQ and R1 115 kQ These values give an equivalent resistance of Kx 0 376 a 0 3 error Using 1 external resistors and a parallel resistance of 72 k ohms will result in a 6 tolerance in the value of VDD Fault The sources of variation due to integrated circuit process variations and mismatches include the internal reference voltage less than 1 the internal comparator hysteresis and offset less than 1 7 for part to part processing and environment the internal resistor value mismatch and value variations less than 1 8 and the external resistor values 1 If the 2 3 V default threshold is acceptable this pin must be left unconnected Rev 1 5 9 73S8023C Data Sheet DS_8023C_019 6 Power Down A power down function is provided via the PWRDN pin active high When activated the Power Down PD mode disables all the internal analog functions including the card analog interface the oscillators and the DC DC converter to put the 73S8023C in its lowest power consumption mode PD mode is only allowed in the deactivated condition out of a card session when the CMDVCC signal is driven high from the host controller The host controller invokes the power down state when it is desirable to save power The signals PRES and PRES remain functional in PD mode such that a car
13. 1 AUX2 high Se WA lbp Supply Current on Vpp Step up mode ICC 0 A7 m UO AUX1 AUX2 high i PWRDN 1 Supply Current on Vpp in Start stop bit 0 Ee 0 11 2 5 vat Power Down mode All digital inputs driven H with a true logical 0 or 1 12 7 Voltage Temperature Fault Detection Circuits Symbol Parameter Condition Min Typ Max Unit Vop fault Vpp Voltage No external resistor on Voor supervisor threshold VDDF_ADJ ane Se y Vcc fault Vcc Voltage Vcc 5V 4 20 4 6 V Vccr supervisor threshold Vec 3V 25 2 7 V Tr Die over temperature fault 115 145 C E Card over current fault 100 150 mA 23 Rev 1 5 73S8023C Data Sheet DS_8023C_019 13 Mechanical Drawing 32 QFN 0 85 NOM 0 9MAX lt gt La 5 P gt 4 0 00 0 005 raf 2 5 i i lt 0 20 REF 1 O 2 N ou 3 Ya Y S lt SEATING TOP VIEW PLANE SIDE VIEW o a Se __ _ _ 3 0 3 75 Ss CHAMFERED A k nen Le 1 5 1 875 Sch MW UU UU Uu KE Ns UJ Ra seo a HE jan A 2 D C 3 Dies CH Or D qta ps pe sika ou L O E 54 1 3 L J N SIE gna iW Z Ne ON Y 03510 45 LD 0 5 Gel 25 BOTTOM VIEW Figure 14 32 QFN Mechanical Drawing 24 Rev 1 5 DS_8023C_019 73S8023C Data Sheet 14 Package Pin Designation 32 QFN lt Use handling procedures nece
14. 1 XTAL 1 0 1 4 XTAL 1 1 Yo XTAL card clock depends on the duty cycle and waveform of the signal applied on the pin XTALIN When other division rates are used the 73S8023C circuitry guarantees a duty cycle in the range 45 to 55 conforming to ISO 7816 3 and EMV 4 1 specifications e Interrupt output to the host As long as the card is not activated the OFF pin informs the host about the card presence only low no card in the reader When CMDVCC is set low Card activation sequence requested from the host a low level on OFF means a fault has been detected e g card removed during a card session or voltage fault or thermal over current fault that automatically initiates a deactivation sequence e Power Down The PWRDN pin is a digital input that allows the host controller to put the 73S8023C in its Power Down state This pin can only be activated outside of a card session e The CLKOUT signal is a buffered output of the signal applied to the XTALIN pin whether it is an external clock source or it is configured as a crystal oscillator CLKOUT can be used when using multiple 73S8023C devices to share a single clock signal e The STROBE input directly drives the smart card CLK signal when operating in synchronous mode STROBE is ignored in asynchronous mode When the division rate is equal to 1 CLKDIV2 0 and CLKDIV1 1 the duty cycle of the Rev 1 5 7 73S8023C Data Sheet DS_8023C_019 3 Oscillator The 73
15. 5 80 75 e2 7V 70 Efficiency A 3 0V 65 A 3 3V Linear lt 3 6V Linear 60 55 50 Icc mA Figure 13 DC DC Converter Efficiency Vcc 3 V Output current on Vcc at 3 V Input voltage on Vpp at 2 7 3 0 3 3 and 3 6 volts 20 Rev 1 5 DS_8023C_019 73S8023C Data Sheet Symbol Parameter Condition Min Typ Max Unit Interface Requirements Data Signals I O AUX1 AUX2 and host interfaces I OUC AUX1UC AUX2UC Top IsHorTH and Vinact requirements do not pertain to I OUC AUX1UC and AUX2UC Output level high I O AUX1 lon 0 0 9 Vcc Vect 0 1 V Von AUX2 lon 40 pA 0 75 Vcc Vcc 0 1 V Vv Output level high I OUC lon 0 0 9 Von Vpp 0 1 V Sit AUX1UC AUX2UC low 40 pA 0 75 Vpp Vo 011 V VoL Output level low lo zl MA 0 3 V Input level high I O AUX1 Vin AUX2 1 8 Vcc 0 30 V Input level high I OUC Vu AUX1UC AUX2UC tg yoy 1020 x Vi Input level low 0 3 0 8 V Vv Output voltage when outside lo 0 0 1 V NACT of session lo 1 mA 0 3 V Jean Input leakage Vin Mee 10 uA Input current low I OUC Vii 90 CS 1 0 65 mA be AUX1UC AUX2UC Vi 0 CS 0 5 uA Input current low I O AUX1 _ AUX2 Vi 0 2 mA For output low IsHortL Short circuit output current shorted t
16. S8023C device has an on chip oscillator that can generate the smart card clock using an external crystal connected between the pins XTALIN and XTALOUT to set the oscillator frequency When the card clock signal is available from another source it can be connected to the pin XTALIN and the pin XTALOUT should be left unconnected Signal CLKOUT is the buffered version of the signal on XTALIN 4 DC DC Converter Card Power Supply An internal DC DC converter provides the card power supply This converter is able to provide either 3 V or 5 V card voltage from the power supply applied on the Vpp pin The digital ISO 7816 3 sequencer controls the converter Card voltage selection is carried out by the digital input 5V 3V The circuit is an inductive step up converter regulator The external components required are 2 filter capacitors on the power supply input Von next to the LIN pin 100 nF 10 uF an inductor and an output filter capacitor on the card power supply Vcc The circuit performs regulation by activating the step up operation when Vcc is below a set point of 5 0 or 3 0 volts minus a comparator hysteresis voltage and the input supply V pp is less than the set point for Vcc When V pp is greater than the set point for Vcc Voo 3 6 V Vcc 3 V the circuit operates as a linear regulator Depending on the inductor values the voltage converter can provide current on Vcc as high as 100 mA The circuit provides over current protection and limi
17. d insertion sets OFF high The micro controller must then set PWRDN low and wait for the internal stabilization time prior to starting any card session prior to turning CMDVCC low Resumption of the normal mode occurs approximately 10 ms stabilization of the internal oscillators and reset of the circuitry after PWRDN is set low No card activation should be invoked during this 10 ms time period If a card is present OFF can be used as an indication that the circuit has completed its recovery from power down state OFF will go high at the end of the stabilization period Should CMDVCC go low during PWRDN 1 or within the 10 ms internal stabilization reset time it will not be taken into account and the card interface will remain inactive Since CMDVCC is taken into account on its edges it should be toggled high and low again after the 10 ms to activate a card Figure 2 illustrates the sequencing of the PD and Normal modes PWRDN must be connected to GND if the power down function is not used PRES OFF gt OFF follows PRES regardless of PWRDN l PWRDN during a card mo PWRDN h ffect wh PWRDN session has no effect x L the cardi SE Internal RC OSC lt 10ms gt C After setting PWRDN 0 CMDVCC the controller must wait at EUIS assay least 10ms before setting j q fiat EE ion CMDVCC 0 _ Figure 2 Power Down Mo
18. de Operation CS high 7 Over temperature Monitor A built in detector monitors die temperature When an over temperature condition occurs a card deactivation sequence is initiated and an error or fault condition is reported to the system controller 10 Rev 1 5 DS_8023C_019 73S8023C Data Sheet 8 Activation and Deactivation 8 1 Activation Sequence Synchronous Mode The 73S8023C smart card interface IC has an internal 10 ms delay at power on reset or on application Of Voo gt Vopr No activation is allowed at this time CMDVCC edge triggered must then be set low to activate the card The following steps list the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low 1 CMDVCC is set low 2 Turn on Vec and I O AUX1 AUX2 to reception mode at the end of tact 3 RST is a copy of RSTIN and CLK is a copy of STROBE after t CMDVCC VCC STROBE CLK tact lt gt ap tact 500us t gt 0 5us after tact RST RSTIN CLK STROBE Figure 3 Activation Sequence Synchronous Mode 8 2 Deactivation Sequence Synchronous Mode Deactivation is initiated either by the system controller by setting the CMDVCC high or automatically in the event of hardware faults Hardware faults are over current overheating Vpp fault and card extraction during
19. gure 5 Figure 6 Figure 7 Figure 8 13958023C BOCK DIA ET 2 Power Down Mode Operation CS bb 10 Activation Sequence Synchronous Mode sae ea area nn 11 Synchronous Deactivation Operation CKSEL High I n nra 12 Asynchronous Activation Sequence RSTIN Low When CMDVCC Goes Low 13 Asynchronous Activation Sequence Timing Diagram A7 13 Asynchronous Deactivation Sequence ssse SE 14 Timing Diagram Management of the Interrupt Line OPE 15 Figure 9 I O and I OUC State Diagram U l nan 16 Figure 10 I O I OUC Delays Timing Diagram akase sesa senar eaaa anane aaa aana aaa anana anaa anana nean anana 16 Figure 11 73S8023C Typical Application Schematic a n 17 Figure 12 DC DC Converter efficiency Vcc 5 V I aaa aaa anana aaa nn 20 Figure 13 DC DC Converter Efficiency Vcc 2MI aa aa anana aaa nana aane nana 20 Figure 14 32 QFN Mechanical Drawing n aaa anana anana nana naar 24 Figure 15 32 QFN 73S8023C Pin Out 25 Table Table 1 Choice of VCC PIN CapacHor saa sata ws u aus Kala eee AA KENAA A ANA a NA A Kabe A anaa a Waaa 8 4 Rev 1 5 DS_8023C_019 73S8023C Data Sheet 1 Pin Description 1 1 Card Interface Name Pin Description MO 9 Card I O Data signal to from card Includes a pull up resistor to Vcc
20. i Yes oe lt amp gt not uote e BCE na No Bee eg Kc vouc Yo Mo amp S lt gt SA SC not UO Y Ps ie N oor r Yes Y ga Come Kusen 122 ee A 7 e Figure 9 I O and IIOUC State Diagram IOUC Delay from I O to I OUC Delay from I OUC to I O gt ton lt Geng gt Gah ui pu to m 100ns tio ty 25ns tvouc_HL 100ns tyouc_tH 25ns lt gt lt IOUC_LH Figure 10 IIO IIOUC Delays Timing Diagram Rev 1 5 16 73S8023C Data Sheet DS_8023C_019 11 Typical Application Schematic AUX2UC_to from_uC AUX1UC_to from_uC See NOTE 6 OUC_to from_uC STROBE_from_uC CLKDIV1_from_uC CLKDIV2_from_uC See NOTE 3 5V 3V_select_from_uC See note 7 CLKOUT_to_uc lt vob m lt External_clock_from uC oH o ol o o o 7 AAA A NPN NIN OR VDD EPANSOOOW 202235320 R3 Z Os gt aqq0gg00 Rext2 EES C4 C5 255 5 C2 ae ls L1 10uH D O goz lt o 24 Gg 7 z GND XTALOUT a 10uF 100nF See NOTE 1 r 3 UN AVALINT 99 220 A VDD OFF Y1 4 Inc GND 21 yop
21. ignals when the system controller pulls the CMDVCC low while the RSTIN is high 1 CMDVCC is set low 2 Next the internal Vcc control circuit checks the presence of Vcc at D In normal operation the voltage Vcc to the card becomes valid during this time If not OFF goes low to report a fault to the system controller and the power Vcc to the card is turned off 3 Due to the fall of RSTIN at tz turn I O AUX1 AUX2 to reception mode CLK is applied to the card at the end of ts after I O is in reception mode 5 RST is to be a copy of RSTIN after tz RSTIN may be set high before t4 however the sequencer won t set RST high until 42000 clock cycles after the start of CLK CMDVCC ta 0 510 ms timing by 1 5MHz internal Oscillator t2 1 5us I O goes to reception state ts gt 0 5us CLK active ta gt 42000 card clock cycles Time for RST to become the copy of RSTIN Figure 6 Asynchronous Activation Sequence Timing Diagram 2 Rev 1 5 13 73S8023C Data Sheet DS_8023C_019 8 4 Deactivation Sequence Asynchronous Mode Deactivation is initiated either by the system controller by setting CMDVCC high or automatically in the event of hardware faults Hardware faults are over current overheating Vpp fault Vcc fault and card extraction during the session The following steps list the deactivation sequence and the timing of the card control signals when the system con
22. is minimal 20 ns else rise fall times are a factor C 35 pF Duty cycle for CLK 48 lt By lt 52 45 55 Yo 12 5 Digital Signals Symbol Parameter Condition Min Typ Max Unit Digital I O Except for OSC I O Vit Input Low Voltage 0 3 0 8 V Vin Input High Voltage 1 8 Vpp 0 3 V VoL Output Low Voltage lo 2 MA 0 45 V Von Output High Voltage lon 1 MA Vpop 0 45 V Rour Pull up resistor OFF 20 kO ta Time from CS going high to 50 ns interface active Time from CS going low to toz interface inactive Hi Z SE gt Set up time control signals tis to CS rising edge P Se Hold time control signals ts from CS rising edge 30 Set up time control signals tio to CS fall a aS Hold time control signals tor from CS fall ns ul Input Leakage Current GND lt Vin lt Vpop 5 5 HA 22 Rev 1 5 DS_8023C_019 73S8023C Data Sheet Symbol Parameter Condition Min Typ Max Unit Oscillator XTALIN I O Parameters VILXTAL Input Low Voltage XTALIN 0 3 0 3 Vpp V V IHXTAL Input High Voltage XTALIN 0 7 Vpp Vpp 0 3 V ILXTAL Input Current XTALIN GND lt Vin lt Mon 30 30 HA fmax Max freq Osc or external clock 27 MHz trie lt 10 fin i j imi k 0 Sin External input duty cycle limit 45 lt Sex lt 55 48 52 Yo 12 6 DC Characteristics Symbol Parameter Condition Min Typ Max Unit Linear mode ICC 0 I O AUX
23. ly source GND DC DC converter ground GND Digital ground LIN 2 External inductor Connect external inductor from pin 2 to Vpp Keep the inductor close to pin 2 Rev 1 5 5 73S8023C Data Sheet DS _8023C_019 1 4 Microcontroller Interface Name Pin Description CMDVCC 18 Command Vcc negative assertion Logic low on this pin causes the DC DC converter to ramp the Vcc supply to the card and initiates a card activation sequence 5V 3V 31 5 volt 3 volt card selection Logic one selects 5 volts for Vcc and card interface logic low selects 3 volt operation When the part is to be used with a single card voltage this pin should be tied to either GND or Vpp However it includes a high impedance pull up resistor to default this pin high selection of 5V card when unconnected PWRDN Power Down control input Active High When Power Down PD mode is activated all internal analog functions are disabled to place the 73S8023C in its lowest power consumption mode The PD mode is allowed only out of a card session PWRDN high is ignored when CMDVCC 0 Must be tied to ground when power down function is not used CLKDIV1 CLKDIV2 29 30 Sets the divide ratio from the XTALIN oscillator or external clock input to the card clock These pins include pull down resistors CLKDIV1 CLKDIV2 Clock Rate 0 0 XTALIN 8 0 1 XTALIN 4 1 1 XTALIN 2 1 0 XTALIN OFF
24. m Controller Interface e The CS chip select input allows multiple devices to operate in parallel When CS is high the system interface signals operate as described When CS is taken low the system interface signals are latched internally The pins OUC AUX1UC and AUX2UC are weakly pulled up and the OFF signal is put into a high impedance state e The CLKSEL signal selects between synchronous and asynchronous operation When CLKSEL is low asynchronous operation is selected When CLKSEL is high synchronous operation is selected e Digital inputs allow direct control of the card interface from the host as follows Pin CMDVCC When set low starts an activation sequence if a card is present Pin 5V 3V Defines the card voltage e The card I O and Reset signals have their corresponding controller I Os to be connected directly to the host Pin RSTIN controls the card RST signal When enabled by the sequencer RST is equal to RSTIN for both synchronous and asynchronous modes Pin I OUC data transfer to card I O contact Pins AUX1UC and AUX2UC auxiliary I O lines associated to the auxiliary I Os which are connected to the C4 and C8 card connector contacts e Two digital inputs control the card clock frequency division rate CLKDIV1 and CLKDIV2 define the card clock frequency from the input clock frequency crystal or external clock The division rate is defined as follows CLKDIV2 CLKDIV1 CLK 0 0 Ve XTAL 0
25. nd outside the card session 14 Rev 1 5 DS_8023C_019 73S8023C Data Sheet OFF is low by OFF is low by card extracted any fault PRES OFF CMDVCC VCC outside card session within card session within card session Figure 8 Timing Diagram Management of the Interrupt Line OFF 10 I O Circuitry and Timing The I O AUX1 and AUX2 pins are in the low state after power on reset and they are in the high state when the activation sequencer turns on the I O reception state See Section 8 Activation and Deactivation for more details on when the I O reception is on The state of the I OUC AUX1UC and AUX2UC pins is high after power on reset Within a card session and when the I O reception state is on the first I O line on which a falling edge is detected becomes the input I O line and the other becomes the output I O line When the input I O line rising edge is detected both I O lines return to their neutral state Figure 9 shows the state diagram of how the I O and I OUC lines are managed to become input or output The delay between the I O signals is shown in Figure 10 In order to be compliant to the NDS specifications a 27 pF capacitor must be added between pins I O C7 and GND C5 at the smart card connector Rev 1 5 15 73S8023C Data Sheet DS_8023C_019 Ne lt y J No VO KE ia a
26. nductor Corp 6440 Oak Canyon Rd Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www Teridian com Rev 1 5 27
27. o Vcc 15 mA through 33 Q For output high IsHortH Short circuit output current shorted to ground 15 mA through 33 Q C 80 pF 10 to fis 2 90 For I OUC tr te Output rise time fall times AUX1UC AUX2UC 100 ns C 50 pF tir tic Input rise fall times 1 us Output stable for Rpu Internal pull up resistor gt 200 ns 8 11 14 kQ For pins IOUC Ipuhiz Pull up current Hi Z state AUX1UC AUX2UC 5 HA when CS 0 FDwax Maximum data rate 1 MHz Delay I O to I OUC I OUC to I O 100 Started falling edge to falling edge Trpio ns Delay I O to I OUC I OUC to I O 10 rising edge to rising edge Cin Input capacitance 10 pF NDS applications require a 27 pF capacitor on I O placed at the smart card connector Rev 1 5 21 73S8023C Data Sheet DS_8023C_019 Symbol Parameter Condition Min Typ Max Unit Reset and Clock for card interface RST CLK Vou Output level high lon 200 pA 0 9 Vcc Vcc V Vo Output level low loL 200 uA 0 0 2 V Output voltage when outside lo 0 0 1 V Vinact of a session loo 1 mA 0 3 V lrst um Output current limit RST 30 mA lekum Output current limit CLK 70 mA C 35 pF for d f CLK 10 to 90 8 Ze tr te Output rise time fall time C 200 pF for 100 o RST 10 to 90 CLKSEL 1 Cap load on CLK and Delay time STROBE to CLK keno Td RSTIN to RST RST
28. r Down mode The card interface may only be activated when OFF is high which indicates a card is present No activation is allowed at this time CMDVCC edge triggered must then be set low to activate the card The following steps list the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low 1 CMDVCC is set low 2 Next the internal Vcc control circuit checks the presence of Vcc at the end of t4 In normal operation the voltage Vcc to the card becomes valid during t1 If Vcc does not become valid then OFF goes low to report a fault to the system controller and the power Vcc to the card is turned off 3 Turn I O AUX1 AUX2 to reception mode at the end of tz CLK is applied to the card at the end of ts 5 RST is a copy of RSTIN after tz RSTIN may be set high before t4 however the sequencer won t set RST high until 42000 clock cycles after the start of CLK P 12 Rev 1 5 DS_8023C_019 73S8023C Data Sheet CMDVCC ti t2 tg 4 gt lt b a gt t 0 510 ms timing by 1 5 MHz internal Oscillator t2 1 5 us I O goes to reception state t32 0 5 us CLK starts ta 2 42000 card clock cycles Time for RST to become the copy of RSTIN Figure 5 Asynchronous Activation Sequence RSTIN Low When CMDVCC Goes Low The following steps list the activation sequence and the timing of the card control s
29. roller Interface 3 Digital inputs control the card activation deactivation card reset and card voltage 3 Digital inputs control the card clock division rate and card clock source selection 1 Digital output interrupt to the system controller allows the system controller to monitor the card presence and faults 1 Power down digital input places the 73S8023C in a very low power mode card deactivated 1 Chip select digital input for parallel operation of several 73S8023C ICs 1 External clock input STROBE used for synchronous operation 1 Digital output clock buffered version of signal on XTALIN Crystal oscillator or host clock XTALIN up to 27 MHz Power Supply Vpp 2 7 V to 3 6 V 6 kV ESD Protection on the card interface APPLICATIONS Point of Sales and Transaction Terminals Payphones Set Top Boxes DVD HDD Recorders Payment card interfaces in portable devices PDAs mobile phones Rev 1 5 2009 Teridian Semiconductor Corporation 1 73S8023C Data Sheet DS_8023C_019 FUNCTIONAL DIAGRAM VDD VDDF_ADJ LIN VDD 20 17 2 3 4 NC zl 1 SND VDD VOLTAGE SUPERVISOR Icc FAULT SND VOLTAGE REFERENCE
30. ssary for a static sensitive component CLKOUT CLKDIV2 cLKDIV1 sTRoBE gt Ei gt LO a o 28 AUX2UC 27 AUX1UC 26 OUC 24 XTALOUT 23 XTALIN vVDD 22 OFF nc TERIDIAN 21 GND PRDWN 73S8023C 20 vpp PRES 6 19 RSTIN PRES 7 18 CMDVCC CSI 8 17 VDDF_ADJ N mM st w ei ei ei ei ei ei L Ld L J L el N g Q x O 5 z lt 0 x a Top View Figure 15 32 QFN 73S8023C Pin Out Rev 1 5 25 73S8023C Data Sheet DS_8023C_019 15 Ordering Information Part Description Order Number Packaging Mark 73S8023C QFN 32 pin Lead Free QFN 73S8023C IM F 73S8023C 73S8023C QFN 32 pin Lead Free QFN Tape Reel 73S8023C IMR F 73S8023C 16 Related Documentation The following 73S8023C documents are available from Teridian Semiconductor Corporation 73S8023C Data Sheet this document 73S8023C QFN Demo Board User s Guide 17 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8023C contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email scr support teridian com For a complete list of worldwide sales offices go to http Avww teridian com 26 Rev 1 5 DS_8023C_019 73S8023C Data Sheet Revision History
31. troller sets the CMDVCC high or OFF goes low due to a fault or card removal RST goes low at the end of time t CLK stops low at the end of time to I O goes low at the end of time ts Out of reception mode Vec is shut down at the end of time t After a delay ts discharge of the Vcc capacitor Vcc is low A GQ S CMDVCC OR OFF RST CLK l l wo y VCC t t MA t ts t gt 0 5 us timing by 1 5 MHZ internal Oscillator to 27 5 us ts 20 5 us Le 0 5 us ts depends on Vcc filter capacitor ti t2 t3 t4 t5 100 us Figure 7 Asynchronous Deactivation Sequence 9 OFF and Fault Detection There are two cases for which the system controller can monitor the OFF signal to query regarding the card presence outside card sessions or for fault detection during card sessions Monitoring Outside a Card Session In this condition CMDVCC is always high OFF is low if the card is not present and high if the card is present Because it is outside a card session any fault detection will not act upon the OFF signal No deactivation is required during this time Monitoring During a Card Session CMDVCC is always low and OFF falls low if the card is extracted or if any fault is detected At the same time that OFF is set low the sequencer starts the deactivation process Figure 8 shows the timing diagram for the signals CMDVCC PRES and OFF during a card session a
32. ts Icc to 150 mA When an over current condition is sensed the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output OFF Choice of the inductor The nominal inductor value is 10 uH rated for 400 mA The inductor is connected between LIN pin 2 and the Vpp supply voltage The inductor value can be optimized to meet a particular configuration lcc_max The inductor should be located on the PCB as close as possible to the LIN pin of the IC Choice of the Vcc capacitor Depending on the applications the requirements in terms of both the Vcc minimum voltage and the transient currents that the interface must provide to the card are different Table 1 shows the recommended capacitors for each Vcc power supply configuration and applicable specification Table 1 Choice of VCC Pin Capacitor Specification Requirement Application Min Vcc Voltage A z e E e Max Transient Capacitor Capacitor Specification Allowed During Current Charge Type Value Transient Current EMV 4 1 4 6 V 30 nAs SES 3 3 uF w ISO 7816 3 4 5 V 20 nAs ESR lt 100 mO 1 uF NDS 4 65 V 40 nAs 3 3 WF 8 Rev 1 5 DS_8023C_019 73S8023C Data Sheet 5 Voltage Supervision Two voltage supervisors constantly check the presence of the voltages Vpp and Vcc A card deactivation sequence is triggered upon a fault detected by these voltage supervisors The
33. ts may cause permanent damage to the device Parameter Rating Supply Voltage Vpp 0 5 to 4 0 VDC Input Voltage for Digital Inputs 0 3 to Vpop 0 5 VDC Storage Temperature 60 C to 150 C Pin Voltage except LIN and card interface 0 3 to Voo 0 5 VDC Pin Voltage LIN 0 3 to 6 0 VDC Pin Voltage card interface 0 3 to Vcc 0 5 VDC ESD Tolerance Card interface pins 6 kV ESD Tolerance Other pins 2 kV ESD testing on Card pins uses the HBM condition 3 pulses each polarity referenced to ground The smart card pins are protected against shorting between any combination of smart card pins 12 2 Recommended Operating Conditions Parameter Rating Supply Voltage Vpp 2 7 to 3 6 VDC Ambient Operating Temperature 40 C to 85 C Input Voltage for Digital Inputs O V to Voo 0 3 V 12 3 Package Thermal Parameters Package Rating 32QFN 47 C W with bottom pad soldered 32QFN 78 C W without bottom pad soldered 18 Rev 1 5 DS_8023C_019 73S8023C Data Sheet 12 4 Card Interface Characteristics Symbol Parameter Condition Min Typ Max Unit Card Power Supply Vcc DC DC Converter General conditions 40 C lt T lt 85 C 2 7 V lt Vpp lt 3 6 V Inactive mode Inactive mode lec 1 mA Active mode lcc lt 65 mA 5 V
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