TERIDIAN 73S8009C Manual
Contents
1. VDD See NOTE 7 T 10uH e VDD ly to uC auch o uC lt See NOTE3 C3 C6 See NOTE 8 VBAT e om 10uF O 1uF OFF interrupt to uC WWWNININININ ua Nfp o 0 0 DU See NOTE 1 l OUC to from uC C 79 34 o VBUS Pushbutton Switch AUXI1UC_tolfrom uC lt gt i i ipis AUX2UC_to from_uC 2 23 SW1 gt 3 22 Nu ui 4 21 CMDVCC5_from_uC 5 20 CMDVCC3_from_uC 6 19 Om 7 18 PA RSTIN from ul gt 8 x 27pF See CLKIN from uC gt C5 NOTE 6 RDY status to uC See NU 73880009C AS AA SIS as 32 QFN NOTES OFF_ACK_from_uC 0 k OFF REQ to uC lt 27pF EE See CS from uc VDD c4 NOTES See NOTE 4 ne n vV r 20K NOTES se _ 0 47uF Low ESR 100 M 1 VBUS 4 5V to 5 5V DC SEL Card detection ZIA should be placed near the di 2 VPC 2 7V to 6 5V DC should only be used when Vaar and e elo died e Pi SC connecter gontact VBus are unused o NU 3 VBAT 4 0V to 6 5V DC WM SC ll hi d i i Qd 4 Internal pull up allows it to be left open if unused j 35 8 AAA KA WA AA 5 Resistor footpring is included in case some filtering is needed on CLK DO 70 Of gt farfromRST I O CA and C8 6 Capacitors C4 and C5 are provisional and their footprints should be added for added noise rejection if necessary 7 Inductor must be rated for 400 mA maximum peak current 8 Voo 3 3V 0 3V 40mA max Requires min two 0 1uF caps to gnd2. Smart Card Connector Figure 3 Typical 73S8009C Application Schematic Rev 1 5 17 73S8009C Data Sheet DS_8009C_025 3 2 Power Supply and Converter The power supply and converter circuit takes power from any one of three sources Vpc Vsus and Vgar Vpc is specified to range from 2 7 to 6 5 volts and would typically be supplied by a single cell battery with a voltage range of 2 7 to approximately 3 1 volts Vpc is also appropriate for system supplies of 3 3 or 5 volts Mous is typically supplied by a connected USB cable and ranges in value from 4 5 to 5 5 volts 6 5 V maximum Vear is expected to be supplied from a battery of two series connected cells with a voltage value of 4 0 V to 6 5 V Vgar and Mous are connected to Vpc by two FET switches configured as an SPDT switch break before make They are not enabled at the same time Vous is automatically selected in lieu of Vgar when Veus is present If Vpc is provided and Vgar Or Maus are also used the source of Vpc must be diode isolated from the Vpc pin to prevent current flow from Vgar or Vgus into the Vpc source The power supplied to the Vpc is up converted to the voltage Vp utilizing an inductive step up converter A series power inductor nominal value 10 uH is connected from Vpc to LIN and a 10 uF filter capacitor plus a 0 1 uF capacitor must be connected to Vpc Vp requires a 4 7 uF filter capacitor and will have a nominal value of 5 5 V during normal operat
3. 20 Rev 1 5 DS_8009C_025 73S8009C Data Sheet 3 6 Activation and De activation Sequence The host controller is fully responsible for the activation sequencing of the smart card signals CLK RST UO AUX1 and AUX2 All these signals are held low by the 73S8009C when the card is in the de activated state Upon card activation the fall of CMDVCC 3 5 all the signals are held low by the 73S8009C until RDY goes high The host should set the signals RSTIN I OUC CLKIN AUX1UC and AUX2UC low prior to activating the card and allow RDY to go high before transitioning any of these signals In order to initiate activation the card must be present and OFF must be high At t1 50 amp s if RDY O or overcurrent circuit will de activate safety feature CMDVCC5 or CMDVCC3 t1 Ne gle ss VCC valid IHOUC Ignored J UO J IO OUC if RDY 1 RDY RSTIN Ignored RST RST RSTIN if RDY 1 CLKIN Ignored CLK CLK CLKIN if RDY 1 IO AUX1 AUX2 CLK RST are held LOW until RDY 1 and CMDVCCx 0 Figure 5 Activation Sequence Deactivation is initiated either by the system controller by setting both CMDVCC 3 5 high or automatically in the event of hardware faults or assertion of the OFF_ACK signal Hardware faults are over current under voltage and card extraction during the session The host can manage the I O signals CLKIN RSTIN and CMDVCC 3 5 to create other de activat
4. X200 mA t 400 ns 3 V Active mode current pulses of 1 62 1 92 V 20nAs with peak lcc 100 mA t 400 ns 1 8 V Vecrip Vec ripple frippLe 20 kHz 200 MHz 350 mV lccmax Card supply output Static load current Vcc 1 65 B 40 mA current Static load current Vcc gt 4 6 or 65 mA 2 7 volts as selected lecce lec fault current Class A B 5V and 3V 75 150 mA Class C 1 8 V 55 130 mA Isc Maximum current prior to Load current limit prior to Vcc 80 150 mA shut down shut down Load current limit prior to Vcc 60 130 mA shut down for Vcc 1 8 V Vs Vcc slew rate rise and C 0 5 pF 0 10 0 30 0 70 V us fall Rev 1 5 11 73S8009C Data Sheet DS_8009C_025 Viay Vcc ready voltage RDY 5 V operation Vcc rising 4 6 x V 1 3 V operation Vcc rising 2 75 V 1 8 V operation Vcc rising 1 65 V Vccr RDY 0 Vcc 5V 4 6 V Vcc voltage supervisor threshold Cvpe External filter cap for Vpc 8 0 10 0 12 0 uF Cvp External filter cap for VP 2 0 4 7 6 8 uF c External filter capacitor Cr should be ceramic with low 0 2 0 47 1 0 uF i Vcc to GND ESR lt 100 mo Cvpp VDD filter capacitor 0 2 1 0 uF Ivpcoff VPC supply current for Vpc 5 V Vcc 0 V off 400 LA Vcc 0 12 Rev 1 5 DS_8009C_025 73S8009C Data Sheet Symbol Parameter Conditio
5. power down condition using less than 20 uA from Vpp Note When using the VBUS input as the sole power source for an always on configuration ON OFF input not used the OFF ACK and ON OFF inputs must be connected to ground 18 Rev 1 5 DS_8009C_025 73S8009C Data Sheet o 3 ON OFF h O Debounce MTS and Latch ss OFF REQ e Pa 100K k E OFF_ACK e i b VPc M 1O0uF 0 1pF 2 E e 10uH T E c Linear M SE LIN Te Converter 3 5VREF VP lt lt lt S S S8 o 8 E E Delay ii m m m Circuit RDY MO SS Analog Mux CMDVCC3 i e CMDVCC5 Vi T Vcc Regulator 3 cc PRES Card RW Supply FE L UOUC E Di RSTIN i Ge Buffer CLKIN ur ii AUX1UC Signal AUX1 AUX2UC de SIE 33V Regulator VpD 0 1uF 0 1uF VP GND GND GND A ut WY Figure 4 73S8009C Logical Block Diagram Rev 1 5 19 73S8009C Data Sheet DS_8009C_025 3
6. 10 I O I OUC Delays Timing Diagram Rev 1 5 25 73S8009C Data Sheet DS_8009C_025 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the Pinout section 24K Figure 11 On_Off Pin VDD Output Disable Data From circuit Figure 12 Open Drain type OFF and RDY To Internal o circuits Figure 13 Power Input Output Circuit VDD LIN VPC VCC VP 26 Rev 1 5 DS_8009C_025 73S8009C Data Sheet From circuit Figure 14 Smart Card CLK Driver Circuit From circuit Figure 15 Smart Card RST Driver Circuit Rev 1 5 27 73S8009C Data Sheet DS_8009C_025 VCC STRONG NFET Figure 16 Smart Card IO AUX1 and AUX2 Interface Circuit VDD circuit circuit Figure 17 Smart Card I OUC AUX1UC and AUX2UC Interface Circuit 28 Rev 1 5 DS_8009C_025 73S8009C Data Sheet Pull up Disable Pull down Enable Note Pins CMDVCC5 CMDVCCS CS have the pull up enabled Pins RSTIN CLKIN PRES EXT_RST have the pull down enabled Pin OFF ACK has a 100 KO resistor connected to pin OFF_REQ internally Figure 18 General Input Circuit VDD STRONG PFET Output Disable STRONG NFET From circuit To OFF ACK pad Notes Strong PFET or NFET is approximately 100 Very strong PFET or NFET is approximately 50 Q Medium strength PFET is approximately 1 KQ Very w
7. 73S8009C Demo Board User Manual 8 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8009C contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email scr support teridian com For a complete list of worldwide sales offices go to http www teridian com Rev 1 5 31 73S8009C Data Sheet DS_8009C_025 Revision History Revision Date Description 1 0 2 15 2007 First publication 1 1 12 5 2007 Replaced 32QFN punched with SAWN Updated 32QFN package mark 1 2 1 21 2008 Changed the dimension of the bottom view 32 pin QFN package 1 3 8 28 2009 Added Pin Current LIN to Table 2 Added Section 2 7 Thermal Characteristics Added a note to the end of Section 3 6 Added Section 4 Equivalent Circuits Added Section 7 Related Documentation and Section 8 Contact Information section Formatted to new documentation style Miscellaneous editorial changes 1 4 1 5 2010 Changed the name of the ON OFF pin to ON OFF throughout the document In Figure 1 corrected the name of the IOUC pin to I OUC In Table 1 corrected the OFF_ACK name pin number and type information In Table 7 changed Ippmax tO lypmax At the end of Section 3 3 added a note about using VBUS input In Section 3 5 deleted A voltage supervisor checks the value of the voltage Vcc and
8. 8 V ViLorrAck Input low voltage for OFF REQ pin VDD 0 3 gt 0 7 V OFF ACK pin Vin Input High Voltage 1 8 Mon 0 3 V VoL Output Low Voltage lo 2 MA 0 45 V Von Output High Voltage lou 1 mA Vpop 0 45 z V Rour Pull up resistor OFF RDY 14 20 26 kQ Rack Resistor between 70 100 130 kQ OFF_REQ and OFF_ACK Ilias Input Leakage Current GND lt Vin Mon 5 pA ts Time from CS goes high to 50 ns interface active tpoz Time from CS goes low to 50 B ns interface inactive Hi Z tis Set up time control 50 ns signals to CS rising edge ts Hold time control signals 50 ns from CS rising edge tp Set up time control 50 B ES ns signals to CS fall toy Hold time control signals 50 ns from CS fall 14 Rev 1 5 DS_8009C_025 73S8009C Data Sheet 2 5 DC Characteristics Table 6 lists the DC characteristics Table 6 DC Characteristics Symbol Parameter Condition Min Nom Max Unit Vpp Von Supply Voltage 2 7v lt VPC lt 6 5v lyppgxr 3 0 3 3 3 6 V 40 mA Vpp Current to External IDDEXT pem 40 mA Vpc 2 7V Vcc Off Ibp 0 1 7 mA S VC t Vpc 3 3V Vcc Off Ibp 0 1 1 mA VPC TREO ance Vpc 5 0V Vcc Off Ip 0 0 7 mA OFF mode 0 01 1 pA VBUSon VBUS detection Vpp 3 3 V 3 5 3 9 4 3 V threshold V los VBUS discharge 0 5
9. Figure 12 Signal to controller indicating the 73S8009C is ready because Vcc is above the required value after CMDVCC5 and or CMDVCCS3 is asserted low A 20 kQ pull up resistor to Vpp is provided internally Pull up is disabled in Power down state and CS 0 modes Rev 1 5 DS_8009C_025 73S8009C Data Sheet Pin Name Pin QFN32 Type Equivalent Circuit Description ON_OFF 24 Figure 11 Power control pin Connected to normally open SPST switch to ground Closing switch for duration greater than de bounce period will turn 73S8009C circuit on If 73S8009C is on closing switch will turn 73S8009C to off state after the de bounce period and OFF_REQ OFF_ACK handshake OFF_REQ 11 Figure 19 Digital output Request to the host system controller to turn the 73S8009C off If ON OFF switch is closed to ground for de bounce duration and circuit is on OFF_REQ will go high Request to turn OFF Connected to OFF_ACK via 100 kQ internal resistor OFF_ACK Figure 18 Setting OFF_ACK high will power off all analog functions and disconnect the 73S8009C from Vgar or Vpc The pin has an internal 100 KQO resistor connection to OFF REQ so that when not connected or no host interaction is required the Acknowledge will be true and the circuit will turn off immediately with OFF REQ Rev 1 5 73S8009C Data Sheet DS_8009C_025 2 Electrical S
10. Vgus power when Vcc is off is less than 500 pA to conform to USB SUSPEND requirements APPLICATIONS e Handheld PINpad smart card readers for e commerce secure login e health Gov t ID and loyalty e Point of Sales amp Transaction Terminals e General Purpose Smart Card Readers ADVANTAGES e ideally suited to USB bus powered applications gt Ideal for combo bus powered and or self powered systems gt Automatic battery switchover in bus powered systems e Very low power mode sub uA with push button ON OFF switch input with de bounce e Provides 3 3 V 40 mA power to external circuitry host processor or peripheral circuits e The inductor based DC DC converter provides higher current and efficiency than usual charge pump capacitor based converters gt Ideal for battery powered applications Rev 1 5 2010 Teridian Semiconductor Corporation 73S8009C Data Sheet DS_8009C_025 FEATURES Smart card Interface e Complies with ISO 7816 3 and EMV 4 1 and derivative standards e A DC DC Converter provides 1 8 V 3 V 5 V to the card from a wide range of external power supply inputs e Provides up to 65 mA to the card e SO 7816 3 Card emergency deactivation sequencer e 2 voltage supervisors detect voltage drops on the Vcc card and Vpp digital power supplies e Card over current detection 150 mA max e 2 card detection inputs 1 for either user polarity e Auxiliary I O lines for synch
11. added and 40 mA for 1 8 V cards 1 5 2 4 2010 Removed all references to the 20QFN package Added C6 to the schematic in Figure 3 Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Simplifying System Integration is a trademark of Teridian Semiconductor Corporation This Data Sheet is proprietary to Teridian Semiconductor Corporation TSC and sets forth design goals for the described product The data sheet is subject to change TSC assumes no obligation regarding future manufacture unless agreed to in writing If and when manufactured and sold this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability Teridian Semiconductor Corporation TSC reserves the right to make changes in specifications at any time without notice Accordingly the reader is cautioned to verify that a data sheet is current before placing orders TSC assumes no liability for applications assistance Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com 32 Rev 1 5
12. and signal pins are configured normally When CS is set low CMDVCC5 RSTIN and CMDVCC3 are latched I OUC AUX1UC and AUX2UC are set to high impedance pull up mode and do not pass data to or from the smart card Signals RDY and OFF are disabled to prevent a low output and the internal pull up resistors are disconnected 32 Figure 12 Interrupt signal to the processor Active Low Multi function indicating fault conditions and card presence Open drain output configuration It includes an internal 20 KQ pull up to Vpp Pull up is disabled in Power down state and CS 0 modes IYOUC Figure 17 System controller data UO to from the card Includes a pull up resistor to Vpp AUX1UC Figure 17 System controller auxiliary data I O to from the card Includes a pull up resistor to Vpp AUX2UC Figure 17 System controller auxiliary data I O to from the card Includes a pull up resistor to Vpp CMDVCC5 CMDVCC3 Figure 18 Logic low on one or both of these pins will cause the LDO to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table CMDVCC5 CMDVCC3 Vcc Output Voltage 0 0 1 8 V 0 1 5 0 V 1 0 3 0 V 1 1 LDO Off Note See the description of the Card Power Supply for more detail on the operation of CMDVCC5 and CMDVCC3 RSTIN Figure 18 Reset Input This signal is the reset command to the card RDY
13. capacitor to GND GND 17 GND Card ground Miscellaneous Inputs and Outputs CLKIN 7 I Figure 18 Clock signal source for the card clock TESTI 10 E Factory test pin This pin must be tied to GND in typical applications TEST2 30 z Factory test pin This pin must be tied to GND in typical applications Power Supply and Ground VDD 29 PSO Figure 13 System interface supply voltage and supply voltage for companion controller circuitry Requires a minimum of two 0 1 uF capacitors to ground for proper decoupling VPC 26 PSI Figure 13 Power supply source for main voltage converter circuit A 10 pF and a 0 1 uF ceramic capacitor must be connected to this pin VBAT 25 Alternate power source input typically from two series cells V gt 4V Rev 1 5 7 73S8009C Data Sheet DS_8009C_025 Pin Name Pin QFN32 Type Equivalent Circuit Description VBUS 23 Alternate power source input from USB connector or hub LIN 27 PSI Figure 13 Connection to 10 uH inductor for internal step up converter Note inductor must be rated for 400 MA maximum peak current VP 15 PSO Figure 13 Intermediate output of main converter circuit Requires an external 4 7 uF low ESR filter capacitor to GND GND 28 31 Ground Microcontroller Interface CS 12 Figure 18 When CS 1 the control
14. up resistors of 20 kQ are disconnected With regard to de activation CS does not affect the operation of the fault sensing circuits and card sense input cs OFF I OUC HI Z STATE HI Z STATE AUX1UC AUX2UC d Figure 8 CS Timing Definitions Rev 1 5 23 73S8009C Data Sheet DS_8009C_025 3 9 O Circuitry and Timing The states of the I O AUX1 and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I O reception state See the Activation and De activation Sequence section for more details on when the I O reception is enabled The states of I OUC AUX1UC and AUX2UC are high after power on reset Within a card session and when the I O reception state is turned on the first UO line on which a falling edge is detected becomes the input I O line and the other becomes the output I O line When the input I O line rising edge is detected then both I O lines return to their neutral state Figure 9 shows the state diagram of how the I O and I OUC lines are managed to become input or output Neutral State VO v amp not ouc Y Figure 9 I O and I OUC State Diagram 24 Rev 1 5 DS_8009C_025 73S8009C Data Sheet The delay between the I O signals is shown in Figure 10 IQ HE t touc HL t IO LH VOUC LH Delay from I O to I OUC tro nL 100ns tro iu 15ns Delay from I OUC to I O tyouc_HL 100ns tyouc LH 15ns Figure
15. 1 0 3 mA current VBUSsrey VBUS standby current 370 500 UA 2 6 Voltage Temperature Fault Detection Circuits Table 7 lists the voltage temperature fault detection circuits Table 7 Voltage Temperature Fault Detection Circuits Symbol Parameter Condition Min Nom Max Unit IVpmax Vp over current fault 150 mA lccr Card overcurrent fault 80 150 mA lecrips Card overcurrent fault Voc 1 8 V 60 130 mA 2 7 Thermal Characteristics Table 8 lists the thermal characteristics Table 8 Thermal Characteristics Symbol Parameter Condition Min Nom Max Unit Tj Junction temperature 125 oc 0 ja Thermal Resistance 70 C W Junction to Ambient 0 jc Thermal Resistance 6 2 C W Junction to case Rev 1 5 15 73S8009C Data Sheet DS_8009C_025 3 Applications Information This section provides general usage information for the design and implementation of the 73S8009C The documents listed in Related Documentation provide more detailed information 3 1 Example 73S8009C Schematics Figure 3 shows a typical application schematic for the implementation of the 73S8009C with a main system switch Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information 16 Rev 1 5 DS_8009C_025 73S8009C Data Sheet VP See NOTE 2
16. 4 System Controller Interface Four separate digital inputs and two outputs allow direct control of the card interface from the host Pin CS Chip select control Pin CMDVCC3 and or CMDVCC5 When low starts an activation sequence Pin RSTIN controls the card RST signal Pin RDY Indicates when smart card power supply is stable and ready Pin OFF Indicator of card presence and any card fault conditions Interrupt output to the host When the card is not activated the OFF pin informs the host about the card presence only Low No card in the reader high card inserted When CMDVCC 3 5 signals is are set low card activation sequence requested from the host low level on OFF means a fault has been detected e g card removal during card session or voltage fault or thermal over current fault that automatically initiates a deactivation sequence The smart card pass through signals are enabled when the RDY conditions are met 3 5 Card Power Supply and Voltage Supervision The 73S8009C smart card interface IC incorporates an LDO voltage regulator for the card power supply Vcc Ve to Vcc conversion uses an internal LDO The voltage output is controlled by the digital input sequence of CMDVCC3 and CMDVCCS5 This regulator is able to provide 1 8V 3V or 5V card voltage sourced from the Ve power supply Internal digital circuitry is also powered by the Ve power supply except for the ON OFF circuitry which is powered from
17. 73S8009C Versatile Power Management and Smart Card Interface IC Simplifying System Integration DATASHEET DS 8009C 025 February 2010 EMVCo ISO IEC 7816 3 DESCRIPTION The Teridian 73S8009C is a versatile power management and single smart card interface circuit that is ideally suited for smart card reader products that are battery and or USB bus powered In addition to its EMV 4 1 and ISO 7816 3 compliant smart card to host interface circuitry it provides control conversion and regulation of power for a companion host processor circuit and power for the smart card The 73S8009C can operate from a single 2 7 V to 6 5 V source supply or a combination of battery power 4 0 V to 6 5 V and USB power 4 4 V to 5 5 V The 73S8009C supports 5 V 3 V and 1 8 V smart cards The smart card signals for RST CLK IO and auxiliary signals AUX1 and AUX2 are level shifted to the selected Vcc value Although the host controller is required to handle the detailed signal timing for activation and de activation under normal conditions the 7388009C blocks any spurious signals on CLK RST and IO during power up as Vcc rises and power down The 73S8009C contains two handshaking signals for the controller OFF indicates that a card is present and RDY indicates that Vcc is at an acceptable value The 73S8009C will perform emergency deactivation upon card removal voltage faults or over current events The power management circuitry
18. C POWER DOWN ON OFF map CLOCK BUFFER SMART CARD I O BUFFERS AND SIGNAL LOGIC Pin numbers reference the QFN32 package Figure 1 73S8009C Block Diagram Rev 1 5 3 73S8009C Data Sheet DS_8009C_025 Table of Contents li PINO IAA ninni iii 6 Electrical Specification ccccccsccseceesssssssssssssssenseenssesseensnensnensnnsccsnscenscensnenscsecssasseseseseseweseveescessseeees 10 2 1 Absolute Maximum RatingS e 10 2 2 Recommended Operating Condrons rrr rr rrr EI A EEEE 11 2 3 Smart Card Interface Requirements eene hhn nnne nnne hn nennen 11 2 4 Digital Signals Characteristics nennen nennen nnn nnns 14 2 5 DG Characteristics piis en nnde mea edendi ins 15 2 6 Voltage Temperature Fault Detection Circus 15 2 4 e ue NEE 15 3 Applications Tuten de EE 16 3 1 Example 398009 SENGA wka SAA shani makka akawa 16 3 2 Power Supply and EU i 18 3 3 Interface Function ON OFF Moes AAA 18 3 4 System Controller Interface AAA 20 3 5 Card Power Supply and Voltage Gupernsion eee eeeeeeeeeeeeeeaaaaeeeeeeeeeeesaaaaeneeeeees 20 3 6 Activation and De activation Sequence i 21 3 44 OFF and Se EE 22 3 8 Ee le le EE 23 3 9 WO Circuitry and Timitig 2 52 22 22 2 122 13 1 1 13 ERR ER RRER ER ERERER ERE RERER ER ERE ER ERE RARE RR RE ER RAM NAM MN a a a 24 4 Equivalent elle E 26 53 Mechanical Drawing ose cs ce we ss a xn ce we we es a xen Eno ws sv de Xue we ws v
19. Rev 1 5 DS_8009C_025 73S8009C Data Sheet Table 1 describes the pin functions for the device Table 1 73S8009C Pin Definitions Pin Pin Tune Equivalent Description Name QFN32 YP Circuit p Card Interface I O 22 IO Figure 16 Card I O Data signal to from card Includes a pull up resistor to Vcc AUX1 21 IO Figure 16 AUX1 Auxiliary data signal to from card Includes a pull up resistor to Vcc AUX2 20 IO Figure 16 AUX2 Auxiliary data signal to from card Includes a pull up resistor to Vcc RST 18 O Figure 15 Card reset provides reset RST signal to card RST is the pass through signal on RSTIN Internal control logic will hold RST low when card is not activated or VCC is too low CLK 16 O Figure 14 Card clock provides clock signal CLK to card CLK is the pass through of the signal on pin CLKIN Internal control logic will hold CLK low when card is not activated or VCC is too low PRES 14 I Figure 18 Card Presence switch active high indicates card is present Should be tied to GND when not used but it Includes a high impedance pull down current source PRES 13 I Figure 18 Card Presence switch active low indicates card is present Should be tied to Vpp when not used but it Includes a high impedance pull up current source VCC 19 PSO Figure 13 Card power supply logically controlled by sequencer output of LDO regulator Requires an external 0 47 uF low ESR filter
20. Vpc A card deactivation sequence is forced upon fault detected by an overcurrent condition or card removal event The voltage regulator can provide a card current of 65 mA in compliance with EMV 4 1 for 3 V and 5 V cards and 40 mA for 1 8 V cards The signals CMDVCCS and CMDVCC5 control the turn on output voltage value and turn off of Vcc When either signal is asserted low Vcc will ramp to the selected value or if both signals are asserted low within 400ns of each other Vcc will ramp to 1 8 V These signals are edge triggered If CMDVCC5 is asserted low to command Vcc to be 5 V and at a much later time greater than 2 us typically CMDVCC3 is asserted low it will be ignored and vice versa At the assertion low of either or both CMDVCC 3 5 signals Vcc will rise to the requested value When Vcc rises to an acceptable value and stays above that value for approximately 20 us RDY will be set high Approximately 510 us after the fall of CMDVCC 3 5 the circuit will check the see if Vcc is at or above the required minimum value indicated by RDY 1 and if not will begin an emergency deactivation sequence During the 510 us time card removal or de assertion of CMDVCC 3 5 shall also initiate an emergency deactivation sequence The circuit provides over current protection and limits Icc to 150 mA maximum for self protection When an over current condition is sensed the circuit will invoke a de activation sequence
21. e dene cca seamen iii 30 6 Ordering Informatio LEE 31 7 RIDE AA Aaaa Kazaa 31 8 ContactINformation ttiiiiieeeeeeeie eee eee 31 4 Rev 1 5 DS_8009 C_025 73S8009C Data Sheet Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 73S8009C Block Diagram e nen nee nennen enne keee Ee nnne nnn nnns 3 73S8009C 32 Pin QFN Pinout rennen nnn nnnnnnrrnn nnn nnn nnn ien nnne nnn 6 Typical 73S8009C Application Schematic cece cece eee tteee etter tees sada enters eeeeesaaaaeeeeeeeeeeeaaa 17 73S8009C Logical Block Diagram en nene nennen nennen nnns 19 Activation Seg ence einen een te lac ca Shall aa nb Ln er bl ILI RAN INED Se d d d EIU Eder 21 Deactivation Sequeribe s ele EXE ss HER Esa EE S DU EE RE 22 OFF Activity er RR RE eee 22 CS Timing Definitions 23 WO and I OUC State DiaQram mene nn neehhhhnnnnn nnne rns nnne nnns 24 UO I OUC Delays Timing Diagramm 25 On Off Pin PURI uin eis ipsa ris ua Ee sia Eris N AA WAN AAA AAA 26 Open Drain type OFF and RDY iii 26 Power Input Output Circuit VDD LIN VPC VCC VP 26 Smart Card CLK Driver Circuit UA AAA AUA AUWA 27 Smart Card RST Driver Circuit sees eee eeeenaaeeeeeee ee eeccaaeeeeeeeeeeeessaaeeaae
22. eak PFET or NFET is approximately 1 MO The diodes represent ESD protection devices that will conduct current if forward biased Figure 19 OFF REQ Interface Circuit Rev 1 5 29 73S8009C Data Sheet DS_8009C_025 5 Mechanical Drawings 0 85 NOM 0 9MAX 4 S gt gt gt 0 00 0 005 Let 2 5 gt M La 0 20 REF A 1 C KE 2 N a 3 Y o y NY SEATING PLANE TOP VIEW SIDE VIEW o 8 o H4 3 0 3 75 H S EB CHAMFERED re i Le 15 1875 0 30 I UUUUUUUT E A EH Net K 2 KC K 2 Fr NI TT A Ce E Cs LO CT 8 D w D i e pa Clu si PEE LO C C Y 0 2 MINA IT I CZE E EN UC C Ne see EI A ees COOOL e 0 5 0 25 BOTTOM VIEW Figure 20 32 Pin QFN Package Dimensions 30 Rev 1 5 DS_8009C_025 73S8009C Data Sheet 6 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8009C products Table 9 Order Numbers and Packaging Marks Part Description Order Number Packaging Mark 73S8009C 32QFN 73S8009C 321M F 73S8009C 32 pin Lead Free QFN 73S8009C 32QFN 73S8009C 32IMR F 73S8009C 32 pin Lead Free QFN Tape Reel 7 Related Documentation The following 73S8009C document is available from Teridian Semiconductor Corporation 73S8009C Data Sheet
23. eeeees 27 Smart Card IO AUX1 and AUX2 Interface Circuit 28 Smart Card I OUC AUX1UC and AUX2UC Interface Circuit 28 General Input CIFCU t MM 29 OFF_REQ Interface Circuit iii 29 Figure 20 32 Pin QFN Package Dimensions nnns 30 Tables Table T 47358009C Pir Definition eisini en EHE pa POSE Pere ERER ER EEE ESA PAGA FARA ASA POSA PAGANI eared 7 Table 2 Absolute Maximum Device Ratings nennen nennen nnn nnne nnn nnn nnn nnn nan 10 Table 3 Recommended Operating Condrgons i 11 Table 4 DC Smart Card Interface Requirements sse 11 Table 5 Digital Signals Characteristics esses nnne nennen 14 Table BADE CharacteriStics deii 3 3 ter E Tree ce ETE ERE EXP ERE EXE ERE EXE ERE cet v Fea e Fe ees 15 Table 7 Voltage Temperature Fault Detection CIFCUItS n 15 Table 8 Thermal Characteristics ENNEN 15 Table 9 Order Numbers and Packaging MarkS nene 31 Rev 1 5 73S8009C Data Sheet DS_8009C_025 1 Pinout The 73S8009C is supplied as a 32 pin QFN package E k Q Q t zg BS Ss RH a O O e gt O J gt gt dd o o N LO Di Mm N N N N N J ouc ON OFF AUX1UC VBUS AUX2UC I O oer TERIDIAN au CWDVCGS 73S8009C aux RSTIN vcc CLKIN RST RDY GND e ed N m st LO LO o ei ei ei ei ei ei ei e e e LI i o0 Vv n EH 6 lt d SS A u X c O IP o A LL LL LL LL O O Figure 2 73S8009C 32 Pin QFN Pinout
24. ion Vp is used by the smartcard interface circuits CLK RST IO AUX1 and AUX2 and is the source of the regulated smart card supply Vcc Vcc can be programmed for values of 5 V 3 V and 1 8 V Vpp is also produced from Vp Vpp is used by the 73S8009C circuit for logic input output buffering and analog functions as well as being capable of supplying up to 40 mA of current to external devices Figure 4 shows the block diagram of the 73S8009C 3 3 Power ON OFF When no power is applied to the Vgus pin a power ON OFF function is provided such that the circuit will be inoperative during the OFF state consuming minimum current from Vpc and Vgar If Vsus power is supplied the functions of the ON OFF switch and circuitry are overridden and the 73S8009C is in the ON state with Vp and Vpp available Without Vgus applied and in the OFF state the circuit responds only to the ON_OFF pin The ON_OFF pin shall be connected to a SPST switch to ground If the circuit is OFF and the switch is closed for a de bounce period of 50 100ms the circuit shall go into the ON state wherein all functions are operating in normal fashion If the circuit is in the ON state and the ON_OFF pin is connected to ground for a period greater than the de bounce period OFF_REQ will be asserted high and held Typically the OFF_REQ signal is presented to a host controller that will assert OFF_ACK high when it has completed all shutdown activities When OFF_ACK is se
25. ion sequences for non emergency situations The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC x B high RST goes low at the end of time t1 De assert CLK at the end of time t2 I O goes low at the end of time t3 Exit reception mode De assert internal VCC_ON at the end of time t4 After a delay VCC is de asserted BQ Note Since the 73S8009C does not control the waveshape of CLK it is determined by the input form the host CLKIN there is no guarantee that the duty cycle of the last CLK high pulse will conform to duty cycle requirements during an emergency deactivation Rev 1 5 21 73S8009C Data Sheet DS_8009C_025 CMDVCC RST CLK I O VCC_ON VCC Figure 6 Deactivation Sequence 3 7 OFF and Fault Detection There are two different cases that the system controller can monitor the OFF signal to query regarding the card presence outside card sessions or for fault detection during card sessions Outside a card session In this condition CMDVCC 3 5 are always high OFF is low if the card is not present and high if the card is present Because it is outside a card session no fault detection can occur and it will not act upon the OFF signal No deactivation is required during this time During a card session CMDVCC3 and or CMDVCCS is always low and OFF falls low if the card is ext
26. n Min Nom Max Unit Interface Requirements Data Signals I O AUX1 AUX2 and host interfaces IIOUC AUX1UC AUX2UC DP DM Loop IsHortH and Vinact requirements do not pertain to IIOUC AUX1UC AUX2UC Von Output level high I O loh O 0 9 Vec Vect0 1 V AUX1 AUX2 Vou Output level high I OUC lon 40 pA 0 75 Voc Vect0 1 V AUX1UC AUX2UC lou O 0 9 Vpp m Vpp 0 1 V Vor Output level low I O lou 40 pA 0 75 Von Vppt0 1 V AUX1 AUX2 lo 1 mA 015e V VoL Output level low OUC lo 1 mA B 0 3 V AUX1UC AUX2UC Vu Input level high I O 0 6 Vec Vect0 30 V AUX1 AUX2 Vu Input level high I OUC 0 6 Vbo 7 Vpp 0 30 V AUX1UC AUX2UC Vit Input level low I O 0 15 0 2 Vcc V AUX1 AUX2 Vu Input level low I OUC 0 15 0 2 Vpp V AUX1UC AUX2UC VINACT Output voltage when lo 0 Ke 0 1 V outside of session lo 2 1 mA i 0 3 V ILEAK Input leakage Vin Mee 10 uA lu Input current low I O Vu O 8 0 65 mA AUX1 AUX2 lu Input current low I OUC VL 0 0 7 mA AUX1UC AUX2UC IsHORTL Short circuit output For output low shorted to 15 mA current Vcc through 33 Q IsHORTH Short circuit output For output high shorted to 15 mA current ground through 33 Q tr te Output rise time fall For I O AUX1 AUX2 100 ns times C 80pF 10 to 9096 For I OUC AUX1UC AUX2UC CL 50Pf 10 to 90 tir te Input rise fall times 1 us Rpu Internal pull up resi
27. of the 73S8009C allows operation from a wide range of voltages from multiple sources Vpc is converted by using an inductive step up power converter to the intermediate voltage Vp Vp is used by linear voltage regulators and switches to create the voltages Vpp and as required Vcc Vpp is used by the 73S8009C and is also made available for the companion controller circuit or other external circuits The Vgar and Vgus pins provide inputs from alternate power sources as required An internal switch in the 73S8009C acts as a single pole double throw switch that selects either Vegart Or Vgus to be connected to Vpc When the voltage on Vous iS Zero Vgar is connected to Vpc When voltage is applied to Vgus the switch selects Veus as the source for power When power is supplied by Vpc or Vesar the 73S8009C is controlled by the ON OFF pin in the manner of a push on push off button action The OFF REQ and OFF ACK signals provide handshaking and control of the power off function by the controller A SPST momentary Switch to ground connected to ON OFF is all that is required for power control Alternatively the off state can be initiated from the host controller through OFF ACK When the 73S8009C is off the current is less than 1 pA When power is supplied via the Vgus pin the 73S8009C is unconditionally in the power on state regardless of the action of the ON OFF switch or OFF_ACK signal Power supply current operating from the
28. pecifications This section provides the following Absolute maximum ratings Recommended operating conditions Smart card interface requirements Digital signals characteristics Voltage temperature fault detection circuits Thermal characteristics 2 1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 7358009C Permanent device damage may occur if absolute maximum ratings are exceeded Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability The smart card interface pins are protected against short circuits to Vcc ground and each other Table 2 Absolute Maximum Device Ratings Parameter Rating Supply Voltage Vous 0 5 to 6 6 VDC Supply Voltage Var 0 5 to 6 6 VDC Supply Voltage Vpc 0 5 to 6 6 VDC Von 0 5 to 4 0 VDC Input Voltage for Digital Inputs 0 3 to Vpp 0 5 VDC Storage Temperature 60 to 150 C Pin Voltage except card interface 0 3 to Vpp 0 5 VDC Pin Voltage card interface 0 3 to Vcc 0 3 VDC Pin Voltage LIN pin 0 3 to 6 5 VDC ESD Tolerance Card interface pins 6 kV ESD Tolerance Other pins 2 kV Pin Current except LIN 200 mA Pin Current LIN 500 mA in 200 mA out Note ESD testing on smart card pins is HBM condition 3 pulses each polarity referenced to ground Note Smart Card pins are protected against shorts between any combina
29. racted or if any fault detection is detected At the same time that OFF is set low the sequencer starts the deactivation process and the host should stop all transitions on the signal lines Figure 7 shows the timing diagram for the signals CMDVCC 3 5 PRES and OFF during a card session and outside the card session OFF is low by OFF is low by card extracted any fault CMDVCC VCC within card session outside card session within card session Figure 7 OFF Activity 22 Rev 1 5 DS_8009C_025 73S8009C Data Sheet 3 8 Chip Selection The CS pin allows multiple circuits to operate in parallel driven from the same host control bus When CS is high the pins RSTIN CMDVCC5 CMDVCCS and CLKIN control the chip as described The pins IYOUC AUX1UC and AUX2UC have 11 KQ pull up resistors and operate to transfer data to the smart card via I O AUX1 and AUX2 when the smart card is activated The signals OFF and RDY have 20 kO pull up resistors When CS goes low the states of the pins RSTIN CMDVCC5 CMDVCC and CLKIN are latched and held internally The pull up for pins I OUC AUX1UC and AUX2UC become a very weak pull up of approximately 3 uA No transfer of data is possible between I OUC AUX1UC AUX2UC and the smart card signals 1 0 AUX1 and AUX2 The signals OFF and RDY are set to high impedance and the internal pull
30. ronous and ISO 7816 12 USB card support e Card CLK clock frequency up to 20 MHz e 6 kV ESD and short circuit protection on the card interface System Controller Interface e 5 Signal images of the card signals RSTIN CLKIN I OUC AUX1UC and AUX2UC e 2 Inputs activate and select the card voltage CMDVCC5 and CMDVCC3 e 2 Outputs interrupt to the system controller OFF and RDY to inform the system controller of the card presence faults and status of the interface e 1 Chip Select input e 2 Handshaking signals for proper shutdown sequencing of all output supply voltages OFF REQ OFF ACK ON OFF Main System Switch e Input for an SPST momentary switch to ground DC DC Converter e Step up converter e Generates an intermediary voltage Vp e Requires a single 10 uH Inductor System Power Supply requirements e When using VBUS Standard USB 5 input range 4 4 V to 5 5 V e When using Vgar 4 0 V to 6 5 V e When using Vac 2 7 V to 6 5 V e Automated detection of voltage presence Priority on VBUS over VBAT Power Supply Output e Vpp Supply output available to power up external circuitry 3 3 V 0 3 V 40mA Industrial temperature range Small format QFN package RoHS compliant 6 6 lead free package Rev 1 5 73S8009C Data Sheet DS_8009C_025 FUNCTIONAL DIAGRAM CS TEST1 TEST2 REFERENCE ON OF VCC FAULT VPC FAULT CMDVCC5 CMDVCC3 SWITCH LDO REGULATOR CONTROL LOGI
31. stor Output stable for gt 200ns 8 11 14 kQ FDmax Maximum data rate 1 MHz Trpio Delay I O to OUC AUX1 Edge from master to 60 100 200 ns TESE to AUX1UC AUX2 to slave measured at 50 15 ns AUX2UC I OUC to I O AUX1UC to AUX1 AUX2UC to AUX2 respectively falling edge to falling edge and rising edge to rising edge Cin Input capacitance 10 pF Rev 1 5 13 73S8009C Data Sheet DS_8009C_025 Symbol Parameter Condition Min Nom Max Unit Reset and Clock for card interface RST CLK Von Output level high lou 200 uA 0 9 Vec Vcc V VoL Output level low lo 200 uA 0 0 15 V Voc ViNACT Output voltage when lo O B 0 1 V outside of session Irst Lim Output current limit RST 30 mA lex Lim Output current limit CLK 70 mA tr te Output rise time fall time C 35pF for CLK 10 to 12 ns 9096 C 200pF for RST 1096 to 100 ns 90 hi Duty cycle for CLK C 35pF Ferk lt 20 MHz 45 55 Yo CLKIN duty cycle is 48 to 52 2 4 Digital Signals Characteristics Table 5 lists the 73S8009C digital signals characteristics Table 5 Digital Signals Characteristics Symbol Parameter Condition Min Nom Max Unit Digital I O except for I OUC AUX1UC AUX2UC see Smart Card Interface Requirements for those specifications Vi Input Low Voltage 0 3 0
32. t high the circuit will de activate the smart card interface if required and turn off all analog functions and the Vpp supply for the logic and companion circuits The OFF ACK pin is connected internally to OFF REQ with a resistor such that if OFF ACK is unconnected the action of OFF REQ will assert OFF ACK high In this configuration the circuit shall go into the OFF state immediately upon OFF REQ 1 The default state upon application of power is the OFF state unless power is supplied to the Vous supply Note that at any time the controller may assert OFF ACK and the 73S8009C will go into the OFF state when Vous is not present If power is applied to both Vgar and Vagus the circuit will automatically consume power from only the Vgus source The circuit will be unconditionally ON when Vous is applied If the Vgus source is removed the circuit will switchover to the VBAT input supply and remain in the ON state The controller circuit firmware is required to assert OFF ACK based on no activity or Vgus removal to reduce battery power consumption When operating from Vgus and not calling for Vcc the step up converter becomes a simple Switch connecting Veus to Vp in order to save power This condition is appropriate for the USB SUSPEND state The USB SUSPEND state requires the power supply current to be less than 500 pA In order to obtain and meet this low current limitation the companion controller must be configured into a
33. tions of Smart Card pins 10 Rev 1 5 DS_8009C_025 73S8009C Data Sheet 2 2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3 Table 3 Recommended Operating Conditions Parameter Rating Supply voltage Vpc 2 7 to 6 5 VDC Supply Voltage Vos 4 4 to 5 5 VDC Supply Voltage Var 4 0 to 6 5 VDC Ambient operating temperature 40 C to 85 C 2 3 Smart Card Interface Requirements Table 4 lists the 73S8009C Smart Card interface requirements Table 4 DC Smart Card Interface Requirements Symbol Parameter Condition Min Nom Max Unit Card Power Supply Vcc Regulator General Conditions 40C lt 85C 2 7 V lt Vpc lt 6 6 V Inactive mode 0 1 0 1 V Inactive mode lcc 1 mA 0 1 D 0 4 V Active mode Icc 65 mA 5 V 4 65 5 25 V Active mode Icc lt 65 mA 3 V 2 85 3 15 V Active mode Icc lt 40 MA 1 8V 1 68 1 92 V Active mode single pulse of 4 6 5 25 V 100 mA for 2 us 5 V fixed load 25 mA Active mode single pulse of 2 76 3 15 V Vec Card supply voltage 100 mA for 2 us 3 V fixed load including ripple and noise 25 mA Active mode current pulses of 4 6 5 25 V 40nAs with peak lcc 200 mA t 400 ns 5 V Active mode current pulses of 2 7 3 15 V 40nAs with peak lcc
Download Pdf Manuals
Related Search
TERIDIAN 73S8009C Manual