MAXIM MAX3987 Manual
Contents
1. ADDRESS NAME REGISTER BITS R W 1 XPE TX PE 8 R W 2 XLV TX Level 8 R W 3 XOP TX ON and Polarity 8 R W 4 SDM Signal Detect Mode 8 R W 5 OCS Offset Cancellation and Squelch 8 R W 6 SDS Signal Detect Status 8 R Table 6 Register 1 TX PE XPE Bit 7 6 5 4 3 2 1 0 2 2 1 1 SELECT 1 SELECTO SELECT 1 SELECTO SELECT 1 SELECT 0 SELECT 1 SELECT 0 Default TXPE1 TXPEO TXPE1 TXPEO TXPE1 TXPEO TXPE1 TXPEO PE SELECT FUNCTION BIT 1 0 FUNCTION dB 00 0 01 10 ey 11 11 Table 7 Register 2 TX Level XLV Bit 7 6 5 4 3 2 1 0 Function TX3 LEVEL TX3 LEVEL TX2 LEVEL TX2 LEVEL TX1 LEVEL TX1 LEVEL TXO LEVEL TXO LEVEL SELECT 1 SELECT 0 SELECT 1 SELECT 0 SELECT 1 SELECT 0 SELECT 1 SELECT 0 Default TXLV1 TXLVO TXLV1 TXLVO TXLV1 TXLVO TXLV1 TXLVO TX LEVEL SELECT FUNCTION BIT 1 0 FUNCTION mV 00 600 01 850 10 1050 11 Do not use Table 8 Register 3 TX ON and Polarity XOP Bit 7 6 5 4 3 2 1 0 Function TX3 ON TX2 ON TX1 ON TXO ON TX3 POL TX2 POL TX1 POL TXO POL Default TXEN TXEN TXEN TXEN 0 0 0 0 If TXEN is zero the output signal for that channel is off If TX 3 0 POL is zero there is no polarity inversion for that channel 18 MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive Table 9 Register 4 Signal Detect Mode SDM Bit 7 6 5 42. rcA h IA AX LIVI 8 5Gbps Quad Equalizer and Preemphasis Driver General Description Features Up to 8 5Gbps NRZ Data Speed Receive Equalization Up to 30in FR4 Preemphasis Drive Up to 30in FRA Global and Individual Programming of Preemphasis Output Drive Levels Polarity Inversion and Offset Cancellation For each channel the preemphasis level output drive qu level output polarity and powering down of unused out Compliant with SAS 2 and SATA Revision 3 puts are programmable through an 12 serial interface It Coding Independent 8B 10B 64B 66B can also be configured globally through pins Scrambled and Others The MAX3987 is a 4 channel receive and transmit equal izer EQ It compensates for transmission medium losses encountered with FR4 stripline microstrip and or high speed cable The device can be used at the begin ning middle or end of a channel The input equalization requires no setting and the output preemphasis PE is programmable 9 The device operates from 2 5V or 3 3V supply and is Differential CML Data Output Drive packaged in a 7mm x 7mm 48 pin TQFN 12 Serial Interface and Pin Programmable Software Power Down of Unused Outputs Applications 0 5W Typical Power Dissipation for Drive Level 1 Preemphasis and Receive Equalization at Vcc 2 5V Redrive High Performance Lead Free 7mm x 7mm 48 Pin FR4 and Cable Equaliza
3. C above 70 2 22W Storage Ambient Temperature Range 65 C to 150 C ESD Human Body Model Any 2000V Lead Temperature soldering 10s 300 C Soldering Temperature reflow 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability SPECIFICATION TABLES Typical values measured at Vcc 3 3V TA 25 C unless otherwise specified OPERATING CONDITIONS PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage 2 5V supply 2 375 2 5 2 625 1 3 3V supply 2 97 3 3 3 63 Operating Ambient 2 5V supply 0 425 485 m Temperature 3 3V supply 40 25 85 Supply Noise Tolerance 100kHz f 200MHz 50 mVP P AC Common Mode Noise at the 2MHz lt f lt 200MHz 150 imis Input Bit Rate NRZ data Note 2 8 5 Gbps CID Consecutive identical digits bits 100 Bits Time OUS Mark Space For continuous traffic 1 HS Ratio DC Blocking Capacitor For bursty tr
4. 04 04 5 5 E 03 o o B 5 5 Fd 02 gt 02 z 0 E B E 01 04 01 0 0 0 40 20 0 20 40 60 8 EMPERATURE C EMPERATURE C EMPERATURE C RECEIVER DETERMINISTIC JITTER RECEIVER DETERMINISTIC JITTER RECEIVER DETERMINISTIC JITTER vs TEMPERATURE Vin 400mVp p vs TEMPERATURE INPUT SIGNAL 400mVp p vs TEMPERATURE Vin 400mVp p MAXIM STRESS PATTERN 7 5Gbps PRBS7 7 5Gbps STRESS PATTERN 8 5Gbps 5 g 8 0 5 5 04 XR 04 5 5 E 03 o o o Ez B 02 02 Em E 1 04 0 0 40 20 0 20 4 6 8 EMPERATURE C EMPERATURE C EMPERATURE C MAXIM 11 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive _ Typical Operating Characteristics continued Vcc 3 3V TA 25 C unless otherwise noted RECEIVER DETERMINISTIC JITTER RECEIVER DETERMINISTIC JITTER RECEIVER DETERMINISTIC JITTER vs TEMPERATURE INPUT SIGNAL 400mVp p vs TEMPERATURE INPUT SIGNAL 400mVp p vs TEMPERATURE PRBS7 8 5Ghps MAXIM STRESS PATTERN 10 3Gbps Vin 400mVp p PRBS7 10 3Gbps 0 5 E 0 5 g 04 04 P E 0 3 0 3 e e e d z 02 z 02 5 0 1 0 1 0 0 40 20 0 2 40 60 8 EMPERATURE C EMPERATURE C EMPERATURE C 20
5. 17 RESET LVCMOS Signal to Reset the Device to Default Configuration When High 18 N C No Connection Leave this pin unconnected MAXIM 13 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive Pin Description continued PIN NAME FUNCTION 19 TEST Reserved for Manufacturing Test Connect to ground 20 23 ADDR 4 1 LVCMOS Signal for 12 Serial Interface Address 25 RX0 Positive CML Differential Data Input Signa 26 RXO Negative CML Differential Data Input Signal 28 RX1 Positive CML Differential Data Input Signa 29 RX1 Negative CML Differential Data Input Signal 32 RX24 Positive CML Differential Data Input Signa 33 RX2 Negative CML Differential Data Input Signal 35 RX34 Positive CML Differential Data Input Signa 36 RX3 Negative CML Differential Data Input Signal 38 SDSF LVCMOS Signal to Select Signal Detect Type 39 SQ LVCMOS Signal to Enable Disable Output Squelch and Signal Detect 40 OC_EN LVCMOS Signal to Enable Disable Offset Cancellation 41 TX EN LVCMOS Signal to Power On Off Transmitter 42 SDATA Analog 12 Serial Interface Data Input and Output 43 SCLK Analog 12C Serial Interface Clock Input 45 TX LVO LVCMOS Signal to Set Output Amplitude 46 TX LV1 LVCMOS Signal to Set Output Amplitude u EP Exposed Pad Signal and supply common For optimal thermal conductivity and sup ply return GND this
6. 8 5Gbps Quad Equalizer and Preemphasis Drive TRANSIENT SUPRESSOR Figure 8 Simplified Input Circuit Input and Output Buffers The input buffers and the output drivers are current mode logic CML The input buffers consist of a 50Q load resistor connected to Vcc and the input connected to a differential equalizer as shown in Figure 8 The output circuit is shown in Figure 9 The ESD protection for both the input and output circuitry consists of diodes con nected to a transient voltage suppressor clamp shown as a Schottky diode For more information about the function of the suppressor clamp refer to the Detailed Description section of the MAX3208E IC data sheet Using the MAX3987 in PCle Applications The MAX3987 does not support presence detection However it passes low frequency beacon signals and has signal detect and output squelch compatibility with the electrical idle state requirements MAXIM Voc TRANSIENT SUPRESSOR CLAMP 500 52 A TX TX E d i LEVEL O e o 0 9 CONTROL S TLV Q 6 5mA 3mA 2mA Figure 9 Standard Output Circuit Package and Exposed Pad The exposed pad 48 pin thin QFN package incorpo rates features that provide a very low thermal resistance path for heat removal from the IC The exposed pad on the MAX3987 must be soldered to the circuit board for proper thermal perf
7. Deterministic Jitter DIRX Note 8 Ul 8 5Gbps Notes 6 7 9 Less than 2in FR4 at the output max 04 reach 20in FR4 PRBS7 pattern Squelch Deassert Voltage for SDL 0 120 Slow Response Signal Detect VSQ DEAS S mVP P Notes 8 to 11 SDL 1 default state 170 Squelch Deassert Voltage for SDL 0 155 Fast Response Signal Detect VSQ DEAS F mVp P Notes 9 11 12 13 SDL 1 default state 220 Squelch Assert Voltage for Slow SDL 0 50 Response Signal Detect VSQ AS S mVP P Notes 8 to 11 SDL 1 default state 100 Squelch Assert Voltage for Fast SDL 0 65 Response Signal Detect VSQ AS mVP P Notes 9 11 12 SDL 1 default state 120 Slow signal detect and squelch is 200 Signal Detect and Squelch Ed enabled Note 8 E Delay Note 14 Fast signal detect and squelch is 55 F enabled Note 12 Voltage Input Swing Launched Offset cancellation off 400 1800 Differentially at the Source V mV Point A in Figure 2 before the PX signal encountering any loss Offset cancellation on 200 1800 Input Resistance RIN Between signal and Vcc 50 Q Differential Input Return Loss 50011 TQFN 100 2 to 4 25GHz 17 dB 4 MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive HIGH SPEED OUTPUTS PARAMETER SYMBOL CONDITIONS MN MAX UNITS PE 00 up to 2in FR4 PE 01 up to 015 0 20 Residual Determini
8. pad must be soldered to circuit board ground Detailed Description The MAX3987 is a 4 channel equalizer and preempha sis driver that accepts CML differential signals whose data rates vary from 1Gbps to 8 5Gbps Each channel has a fixed equalization network and programmable preemphasis driver All controls for preemphasis out put swing level signal detect squelch offset cancel lation output enable disable output polarity etc are programmed through the I2C interface These functions are implemented through a programming block on chip where control bits can be received through a serial bus or through control pins at the edge of the chip A block diagram is shown in Figure 5 14 Power On Reset The MAX3987 has a built in power on reset function After the power on reset or when RESET is asserted all 4 channels are configured to a default state Table 1 describes the functions that are controlled and the default state on reset if all the control pins are not connected Global and Individual Channel Programming The MAX3987 supports global programming through hardware pins only applicable to EQ PE and individual channel programming through 12C Table 1 describes the control pins and their function MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive Table 1 Function Table INTERNAL PIN NAME DEFAULT PIN VALUE 0 PIN VALUE X 1 Selec
9. 3 2 1 0 Function 503 502 501 500 SF3 SF2 SF1 SFO Default SF function 0 slow 1 fast A zero selects slow response signal detect a one selects fast signal detect SQ function O disables the squelch 1 enables squelch Table 10 Register 5 Offset Cancellation and Squelch OCS Bit 7 6 5 4 3 2 1 0 Function OC2 OC1 OCO SDL3 SDL2 SDL1 SDLO Default OCEN OCEN OCEN OCEN 1 1 1 1 If OCEN 1 offset cancellation is enabled if OCEN 0 offset cancellation is off If the SDL bit O the signal detect threshold level is low If the SDL bit 1 the signal detect threshold level is high Table 11 Register 6 Signal Detect Status SDS Bit 7 6 5 4 3 2 1 0 Function 503 502 501 SDO Default If the SD bit O the signal is present in the corresponding channel EQUALIZER AND AMPLIFIER CORE SIGNAL SQUELCH DETEC CONFIGURATION REGISTER CONTROL MAXIM MAX3987 PROGRAMMING BLOCK Figure 5 Functional Diagram MAXIM 19 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive Device Power Up and Reset and 2 Programming Power Up and Reset Default Condition The MAX3987 enters the default condition on power up or on assertion of the RESET sign
10. 60 STRESS PATTERN DATA RATE 6 25Ghps 100 600 go gt e 40 5 5 E E 5 200 2 s 0 0 5 10 45 20 25 3 0 5 10 45 20 2 30 FR4 BOARD LENGTH in FR4 BOARD LENGTH in MAXIM 9 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive _ Typical Operating Characteristics continued Vcc 3 3V TA 25 C unless otherwise noted VERTICAL EYE 0PENING vs LENGTH VERTICAL EYE 0PENING vs LENGTH Vin 200mVp p FR4 BOARD Vin 200mVp p FR4 BOARD OUTPUT OF 30in FRA WITHOUT PREEMPHASIS STRESS PATTERN DATA RATE 7 5Gbps STRESS PATTERN DATA RATE 8 5Gbps 6 25Gbps MAXIM STRESS PATTERN 600 2 600 e MAK3987 E z 400 400 10 E E i m z 5 200 2 20 DUE PE 00 0 0 0 5 1 15 20 25 30 0 5 1 15 20 25 30 30ps div FR4 BOARD LENGTH in FR4 BOARD LENGTH in OUTPUT OF 30in FR4 DRIVEN BY MAX3987 OUTPUT OF 30in FRA WITHOUT PREEMPHASIS OUTPUT OF 30in FR4 DRIVEN BY MAX3987 LV 10 PE 11 6 25Gbps MAXIM STRESS PATTERN 7 5Gbps MAXIM STRESS PATTERN LV 10 11 7 5Gbps MAXIM STRESS PATTERN MAX3987 toc20 3987 toc18 MAX3987 toc19 40mV div 40mV div 40mV div 30ps div 30ps div 30ps div OUTPUT OF 30in FR4 WITHOUT PREEMPHASIS OUTPUT OF 30in FRA DRIVEN BY MAX3987 8 5Gbps MAXIM STRESS PATTERN LV 10 PE 11 8 5Gbps MAXIM STRESS PATTER
11. LMAX Input Current Each I O Pin 0 1Vcc lt VI lt 0 9Vcc 10 10 HA SCLK Clock Frequency fSCL 400 kHz Note 1 2 5V covers 0 C to 85 C and 3 3V covers 40 C to 85 C Note 2 With offset cancellation off the minimum data rate is limited by the DC blocking capacitor value with offset cancellation on the minimum data rate is limited above 1Gbps Note 3 Supply voltage ramp up time of less than 200us Power on delay interval measured from the 50 level of the final volt age at the device side of filter to 50 of final current See Figure 1 for a typical supply filter Note 4 Guaranteed by design and characterization with a K28 7 pattern at 7 5Gbps PE 00 Note 5 inimum input amplitude to generate full output swing PE 00 squelch disabled Guaranteed by design and charac terization with 1010 clock pattern at 6Gbps Input sensitivity can be frequency dependent because of the input equaliza tion network Outputs reach within 90 of settled value at level 3 drive Note 6 Difference in deterministic jitter between reference data source and equalizer output Residual DJ Output DJ Source DJ The deterministic jitter at the output of the transmission line must be from media induced loss and not from clock source modulation Note 7 Input signal at point A in Figure 2 No more than 2in FR4 at the output PE setting 00 output drive at level 3 offset can cellation off Signal is applied differentially at input to a 6 mil wide loosel
12. M 8 5Gbps Quad Equalizer and Preemphasis Drive Typical Operating Characteristics continued Voc 3 3V TA 25 C unless otherwise noted DETERMINISTIC JITTER vs LENGTH DETERMINISTIC JITTER vs LENGTH DETERMINISTIC JITTER vs LENGTH 200mVp p MAXIM STRESS PATTERN Vin 200mVp p MAXIM STRESS PATTERN 200mVp p MAXIM STRESS PATTERN DATA 3 25Gbps DATA 6 25Gbps DATA 7 5Gbps 10 2 10 04 _ 08 2 _ 08 E 6 E 06 e 02 04 04 m m 02 2 0 0 0 0 5 10 45 20 25 3 0 5 1 15 20 25 3 0 5 10 1 20 25 3 FR4 BOARD LENGTH in FR4 BOARD LENGTH in FR4 BOARD LENGTH in DETERMINISTIC JITTER vs LENGTH VERTICAL EYE OPENING vs LENGTH Vin 200mVp p MAXIM STRESS PATTERN Vin 200mVp p FR4 BOARD MAXIM DATA RATE 8 5Gbps STRESS PATTERN DATA RATE 1 25Ghps 10 1000 8 PE 00 08 PE 01 E E 6 e 10 e 04 400 B E 02 11 0 0 5 10 1 20 25 3 0 5 10 15 20 2 30 FR4 BOARD LENGTH in FR4 BOARD LENGTH in VERTICAL EYE OPENING vs LENGTH VERTICAL EYE OPENING vs LENGTH Vin 200mVp p FR4 BOARD MAXIM Vin 200mVp p FRA BOARD STRESS PATTERN DATA RATE 3 25
13. N MAX3987 toc22 MAX3987 toc21 40mV div 40mV div 30ps div 30ps div 10 MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive Typical Operating Characteristics continued Voc 3 3V TA 25 C unless otherwise noted RECEIVER DETERMINISTIC JITTER vs LENGTH RECEIVER DETERMINISTIC JITTER INPUT SIGNAL 400mVp p RECEIVER DETERMINISTIC JITTER vs LENGTH vs TEMPERATURE INPUT SIGNAL 400mVp p MAXIM STRESS PATTERN Ta 27 C INPUT SIGNAL 400mVp p PRBS7 TA 27 C MAXIM STRESS PATTERN 3 125Ghps 1 0 5 10 5 08 08 04 s g 07 m 07 E 06 06 E 03 5 5 2 o 7 5Gbps 04 04 02 10 3Gbps t 03 8 5Gbps t 03 ta e 2 2 4 6 6Gb 0 5 0 0 0 0 5 0 1 5 2 2 3 30 BOARD LENGTH in BOARD LENGTH in EMPERATURE C RECEIVER DETERMINISTIC JITTER RECEIVER DETERMINISTIC JITTER RECEIVER DETERMINISTIC JITTER vs TEMPERATURE INPUT SIGNAL 400mVp p vs TEMPERATURE INPUT SIGNAL 400mVp p vs TEMPERATURE INPUT SIGNAL 400mVp p PRBS7 3 12560 STRESS PATTERN 6 6Gbps PRBS7 6 6Gbps 05 8 05 05 g
14. R SYMBOL CONDITIONS MIN TYP MAX UNITS _ 8 5 0 7 x VCC Input Voltage High VIH Voc 2 5V 5 3 3V 10 Vice 03 V 0 3 x Input Voltage Low VIL Voc 2 5V 5 3 3V 10 0 3 Voc V Input Current HH lL VIN Vcc or GND 200 200 HA HIGH SPEED INPUTS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Propagation Delay from Any Input to Any Output tPD Output at level 3 250 ps Output Channel to Channel Delay Skew tsKEW Output at level 3 Note 4 20 40 ps Offset cancellation off 75 Input Sensitivity at the Device VSENSITIVITY Point B in mVP p Pin Note 5 Figure 2 Offset cancellation on 50 Less than 2in FR4 at the output max iss 5 TENES reach 24in FR4 Maxim stress pattern 0 1 0 2 esidual Deterministic Jitter DIRX Note 8 Ul 6 5Gbps Notes 6 7 9 Less than 2in FR4 at the output max 0 07 reach 30in FR4 PRBS7 pattern MAXIM Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive HIGH SPEED INPUTS continued PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Less than 2in FR4 at the output max 2 reach 24in FR4 Maxim stress pattern 0 12 0 26 esidual Deterministic Jitter DJRX Note 8 Ul 7 5Gbps Notes 6 7 9 Less than 2in FR4 at the output max 0 07 reach 24in FR4 PRBS pattern Less than 2in FR4 at the output max nom reach 20in FR4 Maxim stress pattern 0 10 0 22 esidual
15. TOR Figure 2 Receive Equalizer Test Setup The points labeled A and B are referenced for AC parameter test conditions The filter is a lowpass fourth order Bessel Thompson or equivalent BW 0 75 x bit rate x 1096 DIFFERENTIAL INPUT SIGNAL VsQ DEAS MAX3987 TIME DELAY FROM INPUT SQUELCH ASSERT TO OUTPUT ENABLED MAXIM MN DIFFERE OUTPUT 90 FULL SWING DIFFERENTIAL P P 10 FULL SWING En SIGNAL tsp_sa TIME DELAY FROM INPUT SQUELCH ASSERT TO OUTPUT SQUELCHED Figure 3 Input Signal Detect and Output Squelch and Its Timing Definition 16 MAXIM 8 5Gbps Quad Equalizer and SIGNAL SOURCE SMA CONNECTOR lt L 2in A MAXIM 6 MIL MICROSTRIP 0 Pa MAX3987 4THOBT 6 MIL IN LPF EN Preemphasis Drive 1 SCOPEO ERROR DETECTO SMA FR4 CONNECTOR 4 0 lt ER lt 4 4 an 0 022 2in lt L lt 30in Figure 4 Preemphasis Test Setup The points labeled A and C are referenced for AC parameter test conditions The filter is a low pass fourth order Bessel Thompson or equivalent BW 0 75 x bit rate 10 Output Level Three different output levels can be programmed for all outputs The nominal level 1 output drive is approximate ly 600mVP P when level setting LV 00 The level 2 drive is approximately 850mVP P when level setting LV 01 and the level drive is approximat
16. affic such as SAS SATA 12 nF SUPPLY CHARACTERISTICS 2 5V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage Vcc 5 2 5 5 V Four outputs in level 3 drive squelch 320 385 turned on Four outputs in level 3 drive squelch 306 365 turned off Four outputs in level 2 drive squelch 286 340 S ly Current mA u PP Four outputs in level 2 drive squelch 271 325 turned off Four outputs in level 1 drive squelch 235 280 turned on Four outputs in level 1 drive squelch 221 265 turned off Inrush Current AICC Note 3 10 96 Power On Delay tPOWERON Note 3 100 ms 2 MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive SUPPLY CHARACTERISTICS 3 3V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage Vcc 10 3 3 10 V Four outputs in level 3 drive squelch 370 445 turned on Four outputs in level 3 drive squelch 354 430 turned off Four outputs in level 2 drive squelch 334 405 E we turned on u urren CC i ERE Four outputs in level 2 drive squelch 318 390 turned off Four outputs in level 1 drive squelch 272 330 turned on Four outputs in level 1 drive squelch 257 315 turned off Inrush Current Alcc Note 3 10 Power On Delay tPOWERON Note 3 100 ms LVCMOS INPUT ADDR 4 1 I2C EN SDSF SQ OC EN TX EN TX LVO TX LV1 TX PEO TX PE1 RESET TEST PARAMETE
17. al The RESET signal is active high When RESET is deasserted the power up sequence disables the MAX3987 for 100ms during which the MAX3987 does not respond to the 12 port At the end of the 100ms timeout the MAX3987 samples the control pins and programs the control registers according to the register map After power up the MAX3987 listens to the 12C bus and can be accessed for read or write at any time if the I2C_EN pin is asserted or for read access only if the 2 EN pin is not asserted Control The MAX3987 can be configured through the control pins or the 12C interface When 2 EN is asserted the control pin s only role is to set the default value of the control registers during power on reset Other than dur ing power on reset the control pins do not control the functionality of the chip The 12 interface can write and read the control registers When 12C EN is not asserted the MAX3987 is in pin control mode The control pins affect the functionality of the chip and each control pin controls all the channels The 2 interface can only read the control registers and only channel 0 bits are valid and apply to all channels All other bits are zero I C Programming The MAX3987 12 function implements only the manda tory fast mode slave functions Implemented features are START condition STOP condition acknowledge and 7 bit address The 12 address comprises a fixed address which is 100 an
18. d 4 bits of programmable address During the first I2C cycle the fixed address should match data in bits 7 5 and the programmable address should match bits 4 1 Bit O is the I2C R W bit A power on reset or assertion of the RESET signal or an 2 START or STOP condition always resets the register address to zero If I2C EN is asserted write and read access to the registers is enabled If I2C EN is not asserted only read access is enabled and the MAX3987 acknowledges a write cycle but does not write into any register Each 2C access starts with the address and read write byte The first access always addresses register O which is the XPE register For each subsequent access the MAX3987 autoincrements the register addresses The register address does not increment above address 6 If there are more than six consecutive read cycles the MAX3987 acknowledges and provides zero data If there are more than five consecutive write cycles the MAX3987 acknowledges and does not write into any register The MAX3987 internal registers change at the end of the write cycle when all 8 bits are written The control func tion changes approximately 200ns after the rising edge of SCLK which samples the 12C LSB START XC 100 0 x XPE X XLV X XOP x SDM X ocs x E X Figure 6 EQ Write Sequence START X 100 17 XPE X XLV X XOP X SDM X 0CS X 0 0 x 0 0 X STOP Figure 7 EQ Read Sequence 20 MAXIM
19. ecifications without notice at any time 22 2012 Maxim Integrated Products Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 Maxim is a registered trademark of Maxim Integrated Products Inc
20. ely 1050mVp p when level setting LV 10 This control can be programmed globally or individually See Table 4 Programming Interface An 2C serial interface is provided to support global and individual programming Hardware pins TX EN TX LVO TX LV1 TX PEO TX PE1 SDSF SQ OC EN Table 3 PE Pin Programming are also provided to support global programming includ ing output drive level PE level signal detect squelch selection outputs on off and offset cancellation Register Maps Table 5 details the register map showing the address name and function The detailed registers are shown in Tables 6 to 11 Input and Output Coupling All data input and output connections are AC coupled with typical 100nF for continuous traffic and 12nF maxi mum for bursty traffic such as SAS SATA PIN VALUE PE PREEMPHASIS VALUE dB TX PE120 TX PE0 20 00 0 TX 1 0 TX PEO 2 1 01 3 TX PE1 1 TX PE0 20 10 7 TX PE1 1 TX PEO 1 11 11 Table 4 Drive Level Pin Programming PIN VALUE LV OUTPUT DRIVE LEVEL TX LV120 TX_LVO 0 00 Level 1 Drive minimum TX LV120 TX LVO 1 01 Level 2 Drive TX LV1 1 TX_LVO 0 10 Level 3 Drive maximum TX LV1 1 TX_LVO 1 Do not use this mode MAXIM 17 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive Table 5 Register Map
21. in INPUT FR4 8 5Gbps MAXIM STRESS 24in INPUT FR4 6Gbps MAXIM STRESS 24in INPUT FR4 7 5Gbps MAXIM STRESS PATTERN PE 00 LV 00 PATTERN PE 00 LV 00 PATTERN PE 00 LV 00 MAX3987 toc35 I MAX3987 toc36 7 T on toc37 s 5 5 5 24ps div 30ps div 24ps div BER MEASUREMENT BER lt 16 12 24in INPUT FR4 10 3Gbps PRBS7 PATTERN 30in INPUT FR4 7 5Gbps PRBS7 PATTERN 18in INPUT AND OUTPUT FR4 INPUT PE 00 LV 00 PE 00 LV 00 SIGNAL 400mVp p 7 5Ghps PRBS31 MAX3987 toc38 3987 toc39 MAX3987 toc40 i Suffic Bits Auto Error Thresh 5 s 5 5 BER Measure Depth LL cte 22ps div 22ps div 12 MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive Pin Configuration TOP VIEW MAXIM MAX3987 EXPOSED PAD Pin Description PIN NAME FUNCTION 1 TX3 Negative CML Output Signa 2 TX3 Positive CML Output Signal 3 10 27 34 44 GND Negative Power Supply Ground 4 TX2 Negative CML Output Signa 5 TX2 Positive CML Output Signal EM E ps Fe Vcc Positive Power Supply All pins should be set at 3 3V or 2 5V 8 TX1 Negative CML Output Signa 9 TX1 Positive CML Output Signal 11 TXO Negative CML Output Signa 12 TXO Positive CML Output Signal 14 2 LVCMOS Signal to Enable Disable 12 Programming Interface 15 TX PE1 LVCMOS Signal to Set Output Preemphasis Levels 16 TX PEO LVCMOS Signal to Set Output Preemphasis Levels
22. l Detect and Internal Squelch Signal detect and internal squelch suit several applica tions like Fibre Channel PCle and SAS SATA Signal detect can be enabled and disabled for each individual input by sensing the presence of a valid input signal Signal detect controls the squelch of the corre sponding output see Table 2 Squelch can be enabled and disabled independently for each individual output that is controlled by a specific input The output power down overrides squelch When an output is squelched both terminals of the differential MAXIM Table 2 Signal Detect and Squelch Pin Programming PIN SIGNAL DETECT AND SQUELCH VALUE SELECTION SDSF 0 Select slow response signal detect 501 SDSF 1 Select fast response signal detect SD2 50 0 Signal detect and output squelch disabled SQ 1 Signal detect and output squelch enabled output are set to the common mode DC voltage differ ential zero voltage Signal detect and internal squelch have one setting for fast response applications such as SAS SATA and PCIe and another setting for slow response applications such as XAUI Fibre Channel and InfiniBand cable applica tions They are controllable through the 12 serial pro gramming interface or hardware pin 15 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive Signal detect status of each input can be monitored through the 12C interface Signal detect asser
23. load is 500 1 at each side output is configured for level drive The pattern is 11001100 50 edge density at 7 5Gbps AC common mode output is computed as VAC COM VN 2 where VP time domain voltage measured at true terminal VN time domain voltage measured at complementary terminal COM DC common mode voltage VP VN 2 Note 19 The maximum difference in the average DC voltage coM DC common mode voltage VP VN 2 component between data present and output on and data absent and output squelched PE lowest preemphasis load is 50Q x 196 at each side output is configured for level drive Note 20 The maximum difference in the average differential voltage DC offset component between data present and output on and data absent and output squelched PE lowest preemphasis load is 50O 1 at each side output is configured for level 3 drive Note 21 Guaranteed by design and characterization with a K28 7 pattern at 7 5Gbps with 100mVP p input swing Output set at level 3 drive offset cancellation off Note 22 Measured using a vector network analyzer VNA The VNA detects the signal at the output of the victim channel All other inputs and outputs are terminated with 50Q The obtained value excludes the forward gain of the victim amplifier 3 3V 2 5V SUPPLY Figure 1 Recommended Supply Filtering MAXIM 7 Z86EXVIN MAX3987 8 5Gbps Quad Eq
24. ormance and correct electrical grounding Refer to Application Note 862 HFAN O8 1 Thermal Considerations of QFN and Other Exposed Paddle Packages for additional information _ Package Information For the latest package outline information and land pat terns footprints go to www maxim ic com packages Note that a or in the package code indicates RoHS status only Package drawings may show a dif ferent suffix character but the drawing pertains to the package regardless of RoHS status PACKAGE PACKAGE DOCUMENT EE TYPE CODE NO NO 48 TQFN EP T487744 21 0144 90 0130 21 Z86 XVII MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 11 09 Initial release Corrected the naming convention for SAS SATA in the Applications and Features 1 sections 1 1 10 Added the soldering temperature line to the Absolute Maximum Ratings section 2 Added the EP description to the Pin Description table 14 Added the Using the MAX3987 in PCle Applications section 21 Corrected the storage ambient temperature range in the Absolute Maximum 2 4 12 2 Ratings section Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and sp
25. s 4 10 did gag 7 Differential Output Swing _ When output is enabled PE 00 Level 2 Drive VAC OU Vcc 3 3V 10 Notes 4 10 988 459 mvp P Differential Output Swing _ When output is enabled PE 00 Level 3 Drive VAC_OU Voc 3 3V 10 Notes 4 10 ae 1100 1230 mee Differential Output Swing E When output is powered down input at AC Output Disabled VAC_OU 7 5Gbps with D24 3 pattern 59 AC Common Mode Voltage Change VAC COM Note 18 40 mVP P DC Common Mode Voltage VDC COM Note 19 25 425 mVP P Change MAXIM 5 Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive HIGH SPEED OUTPUTS continued PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Average DC Offset Voltage Change AVOFFSET Note 20 25 25 mVp p Output Resistance ROUT Between signal and Vcc 50 Q Differential Output Return 022 100MHz to 4 25GHz output on 11 47 dB Loss LV 10 Random Jitter tRJ Note 21 1 PSRMS Channel Isolation SDDIso Up to 5GHz Note 22 38 dB 2 CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0 3 x Low Level Input Voltage V 0 5 V p g IL vec 0 7 x High Level Input Voltage VIH 0 5 V At loL 3mA sink current 0 0 4 Low Level Output Voltage V V OU 6mA 0 0 6 SDATA Leakage Current ILEAKAGE 12 output high 0 10 HA Output Fall Time VIHMAX to tOF 60 250 VI
26. stic Jitter PE 11 up to 30in FR4 Maxim stress 6 5Gbps DJTX Pattern Ul Notes 6 8 9 15 16 17 PE 00 up to 2in FR4 PE 01 up to 10in FR4 PE 10 up to 18in FR4 0 09 PE 11 up to 30in FR4 PRBS7 pattern PE 00 up to 2in FR4 PE 01 up to POE RS NEE 0 15 0 23 Residual Deterministic Jitter PE 11 up to 24in FR4 Maxim stress 7 5Gbps DJTX pattern Ul Notes 6 8 9 15 16 17 PE 00 up to 2in FR4 PE 01 up to 10in FR4 PE 10 up to 16in FR4 0 12 PE 11 up to 24in FR4 PRBS7 pattern PE 00 up to 2in FR4 PE 01 up to 22 10in FR4 PE 10 up to 18 PE 0 10 0 15 Residual Deterministic Jitter 11 up to 24in FR4 Maxim stress pattern 8 5Gbps DJTX Ul Notes 6 8 9 15 16 17 PE 00 up to 2in FR4 PE 01 up to 10in FR4 PE 10 up to 18in FR4 PE 0 06 11 up to 24in FR4 PRBS7 pattern Serial Data Output Rise and 20 to 80 of settled value level 3 30 50 E Fall Time ji drive Note 4 P Differential Output Swing When output is enabled PE 00 Level 1 Drive VAC OU Voc 2 5V 5 Notes 4 10 EE ME ME Differential Output Swing When output is enabled 00 Level 2 Drive VAC_OU Vcc 2 5V 5 Notes 4 10 749 40 220 WME Differential Output Swing E When output is enabled PE 00 Level 3 Drive VAC_OU Vcc 2 5V 5 Notes 4 10 309 1009 1150 mvp P Differential Output Swing _ When output is enabled PE 00 Level 1 Drive VAC_OU Vcc 3 3V 10 Note
27. t deassert has two programmable levels for each individual channel They are accessible only through the 12 interface The default threshold level for signal detect is high Input Equalization One fixed universal input equalization level of approxi mately 15dB compensates any length up to 30in 6 mil wide FR4 microstrip up to 8 5Gbps The device can also compensate up to 8m to 10m 24 AWG twin axial cable Input Offset Cancellation Each input path has an option to enable and disable offset cancellation for high sensitivity applications It is SIGNAL SOURCE 6 MIL MICROSTRIP 4THOBT LPF SMA CONNECTOR 2in lt L lt 30in programmable through pin or 12C interface It typically requires signal detect and squelch turned off to realize its full benefits When offset cancellation is on the minimum data rate is 1Gbps It is suggested that offset cancellation be turned off for SAS SATA or PCIe bursty applications Output Preemphasis Four different levels of preemphasis at the driver out put are selectable to compensate for driving different lengths of PCB routing or cables The PE levels 3dB 7dB and 11dB The PE level can be set either for all the outputs globally or for each output individually See Table 3 SCOPE OR ERROR DETECTOR 0 FRA 40 lt ER 44 tan 0 022 MAXIM MAX3987 IN SMA CONNEC
28. tion TQFN Package XAUI and XAUI2 Fibre Channel Interlaken u f InfiniBandTMSM SAS 2 and SATA Revision Ordering Information PCle Compatible PART TEMP RANGE PIN PACKAGE MAX3987ETM 40 C to 85 C 48 TQFN EP InfiniBand is a trademark service mark of InfiniBand Trade Association PCle is a registered trademark of PCI SIG Corp Denotes a lead Pb free ROHS compliant package EP Exposed pad Typical Application Circuit MAXIM MAX3987 FABRIC AS AI BACKPLANE CARD EQUALIZER MIDPLANE SerDes t i in AAAXIMI i i 2in lt L lt 30in T MAX3997 2in lt L lt 30in AS A DRIVER MAAILM Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com Z86EXVIN MAX3987 8 5Gbps Quad Equalizer and Preemphasis Drive ABSOLUTE MAXIMUM RATINGS Termination Supply Voltage Range 0 5V to 3 9V Signal Voltage Range on Any One Signal Wire TTL Signal Voltage Range on Any One Signal Wire CML 0 5V to Vcc 0 3V CML Output Loading Shorted to 90mA Operating Ambient Temperature Range 40 C to 85 C Continuous Power Dissipation TA 70 C 48 TQFN derate 27 8mW
29. ts the pin configuration mode TX EN TX LVO TX LV1 TX PEO Selects the 2 serial interface for 2 EN 0 TX PE1 SDSF SQ OC EN In this programming Registers can be read and mode 12C read of pin settings is write for full configuration supported SDSF 0 See Table 2 SQ 1 See Table 2 OC EN 0 Offset cancellation turned off Offset cancellation turned on TX EN 1 All outputs powered off All outputs powered on TX LVO 0 TX LV1 1 See Table 4 TX PEO 1 TX PE1 0 Global output preemphasis control See Table 3 SDATA SCLK See the Device Power Up and Reset and 2 Programming section The device is reset After releasing reset upon the falling edge of RESET the MAX3987 The device is in normal operation h RESET 0 made acquires a startup configuration depending on whether it is an EQ PE or a crosspoint independent of the 2 EN signal status ADDR4 0 2 address bit 0 2 address bit 1 ADDR3 0 2 address bit 0 2 address bit 1 ADDR2 0 2 address bit 0 2 address bit 1 ADDR1 0 2 address bit 0 2 address bit 1 Default is set by internal pullup or pulldown resistors of 40kQ Software Power Down of Individual Output With the software power down feature unused outputs can be turned off by programming a hardware pin or through 12 It is recommended that any change in pro gramming that affects power be executed only as part of an initialization sequence Signa
30. ualizer and Preemphasis Drive Typical Operating Characteristics Vcc 3 3V TA 25 C unless otherwise noted LOSS MEASUREMENT OF TRACE BOARDS POWER SUPPLY CURRENT INPUT RETURN GAIN SDD11 INPUT POWER OF OdBm vs TEMPERATURE Vcc 3 3V INPUT POWER OF 40dBm x x 0 8 1 x 40 5 e 2 PREEMPHASIS 1108 S 3 LEVEL 3 OUTPU e 2 21 S 2 amp 5 5 300 is PREEMPHASIS 00 E s 2 LEVEL 1 OUTPU g 4 200 40 012 3 4 5 67 8 9 10 40 20 0 2 40 60 8 0 2 4 6 8 10 FREQUENCY GHz EMPERATURE C FREQUENCY GHz INPUT RETURN GAIN SDD22 INPUT CHANNEL TO CHANNEL ISOLATION INPUT POWER OF 40dBm INPUT POWER OdBm PART ENABLED 3 EL RX1 TO 2 10 S amp 4 5 5 60 30 lt 70 40 80 0 2 4 6 8 10 0 2 4 6 8 1 1m FREQUENCY MHz FREQUENCY GHz DETERMINISTIC JITTER vs LENGTH TRANSIENT RESPONSE Vin 200mVp p MAXIM STRESS PATTERN 3 125Gbps 1010 PATTERN LV 10 DATA RATE 1 25Gbps 06 8 02 E 3 2 01 01 0 0 0 1 z 02 FG 03 a EJ 05 LJ 0 200ps div 0 5 1 15 20 25 3 FR4 BOARD LENGTH in 8 MAXI
31. y coupled microstrip up to 30in Note 8 Maxim stress pattern is 464 bits PRBS 27 100 zeros 1010 PRBS 27 100 ones 0101 Note 9 All four channels are populated with traffic of the same data pattern to the channel under test with outputs set at level 3 Note 10 Guaranteed by test at 7 5Gbps Note 11 Less than 2in FRA at the input and less than 2in FR4 at the output Note 12 Guaranteed at 1 5Gbps and 3Gbps Note 13 Tested with ALIGN 0 pattern at 6 0Gbps Note 14 For the channel under test time from the input differential peak to peak level rising above the squelch deassert voltage dropping below the squelch assert voltage to the output data reaching 90 of maximum differential peak to peak level for input transition from idle to active 1096 of maximum differential peak to peak level for inputs transition from active to idle Squelch of individual output is completed see Figure 3 Note 15 No more than 2in FR4 at the input Output drive is applied differentially to a 6 mil wide loosely coupled differential microstrip up to 30in Output measured at the point in Figure 4 Input level 100mVp p MAXIM 8 5Gbps Quad Equalizer and Preemphasis Drive Note 16 The output PE level is defined as the ratio of peak to peak voltage of a transition bit to the peak to peak voltage of a non transition bit Note 17 For lowest level 1 drive Tx DJ spec must be met for PE 00 and 01 only Note 18 PE maximum preemphasis
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MAXIM MAX3987 Manual