MAXIM MAX9181 Low-Jitter Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package handbook
Contents
1. 0 5ns min Transition Time Minimizes Radiated Noise 400Mbps Guaranteed Data Rate Low 10mA Supply Current Conforms to ANSI EIA TIA 644 LVDS Standard High Impedance Inputs and Outputs in Power Down Mode gt gt gt Ordering Information PIN TOP PACKAGE MARK 6 SC70 6 ABI PART TEMP RANGE MAX9181EXT T 40 C to 85 C Pin Configuration TOP VIEW MAXIM MAX9181 Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com L8 LGOXVN MAX9181 Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package ABSOLUTE MAXIMUM RATINGS Vec to GND IN IN to GND OUT OUT to GND Short Circuit Duration OUT OUT Continuous Power Dissipation Ta 70 C 6 Pin SC70 derate 3 1mW C above 70 C Operating Temperature Range Storage Temperature Range JUNCTION Elte ESD Protection Human Body Model IN IN OUT OUT 8kV e 245mW Lead Temperature soldering 1Oei ET Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maxim2. Input Noninverting LVPECL Compatible Input Power Supply Bypass Vcc to GND with a 0 01uF ceramic capacitor Noninverting LVDS Output Table 1 Function Table Figure 2 INPUT Vip OUTPUT Vop gt 50mV High lt 5OmV Low 50mV gt Vip gt 50mV Indeterminate Open High Note Vip IN IN Vop OUT OUT High 450mV Vop 250mV Low 250mV Vop 450mV MAKIM DIFFERENTIAL OUTPUT VOLTAGE vs LOAD RESISTOR MAX9181 toc10 DIFFERENTIAL OUTPUT VOLTAGE mV 25 50 m mm 1235 ep LOAD RESISTOR Q Detailed Description The LVDS interface standard is a signaling method intended for point to point communication over a con trolled impedance medium as defined by the ANSI TIA EIA 644 and IEEE 1596 3 standards The LVDS standard uses a lower voltage swing than other com mon communication standards achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise The MAX9181 is a 400Mbps LVDS translator intended for high speed point to point low power applications The MAX9181 accepts differential LVPECL inputs and produces an LVDS output The input voltage range includes signals from GND up to Vcc allowing interop eration with 3 3V LVPECL devices The MAX9181 provides a high output when the inputs are open See Table 1 L8 LGOXVN MAX9181 Low Jitter Low Noise LVPE
3. to 3 6V RL 1002 1 CL 10pF Mul 0 15V to Vcc Vom IVip 2l to Vcc lVip 2l Ta 40 C to 85 C unless otherwise noted Typical values are at Vcc 3 3V Ta 25 C Notes 3 4 5 Figures 3 4 PARAMETER SYMBOL CONDITIONS Differential Propagation Delay High to Low tPHLD Differential Propagation Delay Low to High NW 400Mbps 2 1 PRBS data pattern Notes 6 11 Added Random Jitter fin 200MHz Notes 7 11 Differential Part to Part Skew Note 8 Differential Part to Part Skew Note 9 Switching Supply Current 12 2 18 mA Fall Time 0 5 0 66 1 0 ns Input Frequency Note 10 200 MHz Added Deterministic Jitter Note 1 All devices are 100 tested at Ta 25 C Limits over temperature are guaranteed by design and characterization Note 2 Current into a pin is defined as positive Current out of a pin is defined as negative All voltages are referenced to ground except VTH VTL VoD and AVop Note 3 Guaranteed by design and characterization Note 4 Signal generator output unless otherwise noted frequency 200MHz 50 duty cycle Ro 50Q tR 1 5ns and tF 1 5ns 0 to 100 Note 5 C includes scope probe and test jig capacitance Note 6 Signal generator output for tpu Vop 150mV Vos 1 2V tpg includes pulse duty cycle skew Note 7 Signal generator output for try Vop 150mV Vos 1 2V Note 8 tskpp1 is the magnitude difference of any different
4. 0 75 100 125 150 175 200 225 250 40 Ap 10 35 60 85 30 31 32 33 34 35 INPUT FREQUENCY MHz TEMPERATURE C SUPPLY VOLTAGE V OUTPUT LOW VOLTAGE OUTPUT HIGH VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE 12 z 550 e 21 1 525 2 ZS S 2 2 eer 1 500 Z 20 Se 2 Z 5 1475 S 1 09 S S 5 1 450 a 19 1 08 x 5 5 1 425 E gt 1 07 E S 1 400 Zig 06 375 05 350 17 30 31 32 33 34 35 36 an 31 32 33 34 35 36 30 31 32 33 34 35 SUPPLY VOLTAGE V SUPPLY VOLTAGE V SUPPLY VOLTAGE V DIFFERENTIAL PROPAGATION DELAY TRANSITION TIME vs TEMPERATURE vs SUPPLY VOLTAGE 25 5 z Z 23 2 a T Z w S 21 2 5 S 19 2 17 a 15 40 15 10 35 60 85 an 31 32 33 34 35 36 TEMPERATURE C SUPPLY VOLTAGE V 4 dl d Slab Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package Typical Operating Characteristics continued Vec 3 3V RL 1002 1 CL 10pF Vipl 0 2V Vem 1 2V Ta 25 C unless otherwise noted Signal generator output frequency 200MHz 50 duty cycle Ro 50Q tR 1 5ns and tF 1 5ns 0 to 100 unless otherwise noted TRANSITION TIME vs TEMPERATURE 800 MAX9181 toc09 750 700 650 600 550 TRANSITION TIME ps 500 450 400 40 15 10 35 60 85 TEMPERATURE C Pin Description FUNCTION Inverting LVDS Output Ground Inverting LVPECL Compatible
5. 19 2415 Rev 1 2 04 Low Jitter Low Noise LVPECL to LVDS Level MA AALS Translator in an SC70 Package General Description The MAX9181 is an LVPECL to LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output It is ideal for interfacing between LVPECL and LVDS interfaces in systems that require minimum jitter noise power and space Ultra low 23psp p added deterministic jitter and 0 6psRms added random jitter ensure reliable commu nication in high speed links that are highly sensitive to timing errors especially those incorporating clock and data recovery PLLs serializers or deserializers The MAX9181 s switching performance guarantees a 400Mbps data rate but minimizes radiated noise by guaranteeing 0 5ns minimum output transition time The MAX9181 operates from a single 3 3V supply and consumes only 10mA supply current over a 40 C to 85 C temperature range It is available in a tiny 6 pin SC70 package half the size of a SOT23 Refer to the MAX9180 data sheet for a low jitter low noise LVDS repeater in an SC70 package Applications Digital Cross Connects Add Drop Muxes Network Switches Routers Cellular Phone Base Stations DSLAMs Multidrop Buses Typical Operating Circuit EEN MAXIM MAX9181 LVDS SIGNALS MAKIM Features Tiny SC70 Package Ultra Low Jitter 23psp p Added Deterministic Jitter 2 1 PRBS 0 6psrRms Added Random Jitter
6. CL to LVDS Level Translator in an SC70 Package Applications Information Supply Bypassing Bypass Vcc with a high frequency surface mount ceramic 0 01uF capacitor as close to the device as possible Differential Traces Input and output trace characteristics affect the perfor mance of the MAX9181 Use controlled impedance dif ferential traces Ensure that noise couples as common mode by running the traces within a differential pair close together Maintain the distance within a differential pair to avoid discontinuities in differential impedance Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities Cables and Connectors The LVDS standards define signal levels for intercon nect with a differential characteristic impedance and termination of 1002 Interconnects with a characteristic impedance and termination of 90Q to 132Q impedance are allowed but produce different signal levels see Termination LVPECL signals are typically specified for 50 single ended characteristic impedance interconnect terminat ed through 50Q to Vcc 2V Use cables and connectors that have matched differen tial impedance to minimize impedance discontinuities Termination For point to point LVDS links the termination resistor should be located at the LVDS receiver input and match the differential characteristic impedance of the transmission line Each line of a differential LVPECL link should be termi
7. ial propagation delays between devices operating over rated conditions at the same supply voltage input common mode voltage and ambient temperature Note 9 tskpp2 is the magnitude difference of any differential propagation delays between devices operating over rated conditions Note 10 Device meets Vop DC specifications and AC specifications while operating at fMAX Note 11 Jitter added to the input signal MAXIM 3 L8 LGOXVN MAX9181 Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package frequency 200MHz 50 duty cycle Ro 50Q tr 1 5ns and tF 1 5ns 0 to 100 Typical Operating Characteristics Vec 3 3V RL 1002 1 CL 10pF IVipl 0 2V Vem 1 2V Ta 25 C unless otherwise noted Signal generator output unless otherwise noted MAX9181 toc03 3 6 MAX9181 toc06 3 6 SUPPLY CURRENT SWITCHING SUPPLY CURRENT OUTPUT SHORT CIRCUIT CURRENT vs INPUT FREQUENCY vs TEMPERATURE vs SUPPLY VOLTAGE 21 Z 3 00 3 5 10 18 S 2 75 S E _ Sam 15 e PS gt zZ 12 25 Zem S S eh 12 00 CH Ei gt 9 gt E 5 07 741 75 a Ee B 6 T CO 1 50 5 T 5 06 3 1 25 2 0 1 00 5 05 0 25 5
8. most current specifications For the latest package outline information go to www maxim ic com packages 2 W D d SYMBOL MIN Max S e 0 65 BSC Ke D 1 80 2 20 L1 b 0 15 0 30 E 1 15 1 35 HE 1 80 2 40 Q1 0 10 0 40 A2 0 80 1 00 HE Al 0 00 0 10 A 0 80 1 10 c 0 10 0 18 L 0 10 0 30 H L1 0 425 TYP PIN 1 DOT l l T SEE NOTE 6 i i U l DIN 1 1 i ls 1 ALL DIMENSIONS ARE IN MILLIMETERS 2 DIMENSIONS ARE INCLUSIVE OF PLATING 3 DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH amp METAL BURR l 4 ALL SPECIFICATIONS COMPLY TO EA SC70 5 COPLANARITY 4 MILS MAX 6 PIN 1 1 D DOT SV Al sl dei PROPRIETARY INFORMATION TITLE PACKAGE QUTLINE SC70 6L APPROVAL DOCUMENT CONTROL NO REV 1 21 0077 B A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 8 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2004 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
9. nated through 50Q to Vcc 2V or be replaced by the Thevinin equivalent The LVDS output voltage level depends upon the differ ential characteristic impedance of the interconnect and the value of the termination resistance The MAX9181 is guaranteed to produce LVDS output levels into 1002 With the typical 3 6mA output current the MAX9181 pro duces an output voltage of 360mV when driving a 100 transmission line terminated with a 100Q termination resistor 3 6mA x 1002 360mV For typical output lev els with different loads see the Differential Output Voltage vs Load Resistor curve in the Typical Operating Characterics Chip Information TRANSISTOR COUNT 401 PROCESS CMOS MAXIM Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package Test Circuits and Timing Diagrams PULSE GENERATOR Figure 1 LVPECL Input Bias Figure 3 Transition Time and Propagation Delay Test Circuit Figure 2 DC Load Test Circuit Vom IN IN 2 V DIFFERENTIAL d OV DIFFERENTIAL tPHLD Xo DIFFERENTIAL Xo DIFFERENTIAL ke ei OV DIFFERENTIAL OV DIFFERENTIAL 20 20 Vg Wor OUT buts Figure 4 Transition Time and Propagation Delay Timing Diagram MAXIM LSL6EXVIN MAX9181 Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package Package Information The package drawing s in this data sheet may not reflect the
10. um rating conditions for extended periods may affect device reliability DC ELECTRICAL CHARACTERISTICS Vcc 3 0V to 3 6V RL 1002 1 Mul 0 05V to Vcc Vem Mm 2I to Vcc WM 2l Ta 40 C to 85 C unless otherwise noted Typical values are at Vcc 3 3V Ta 25 C Notes 1 2 PARAMETER SYMBOL CONDITIONS MAX UNITS LVPECL INPUT Differential Input High Threshold VTH Differential Input Low Threshold VTL nput Resistor nput Current Figure 1 IN 3 6V IN OV IN OV IN 3 6V Power Off Input Current Vcc OV Figure 1 IN 3 6V IN OV IN OV IN 3 6V LVDS OUTPUT Differential Output Voltage Differential Output Voltage Offset Common Mode Voltage Change in Vos for Complementary Output States Figure 2 Figure 2 Figure 2 Figure 2 0 008 25 mV 1 125 1 25 1 375 V Output High Voltage Output Low Voltage Differential Output Voltage Power Off Output Leakage Current Vcc OV IN IN open T 3 6V other output open 10 0 02 10 OUT 3 6V other output open 10 0 02 10 Differential Output Resistance Vcc 3 6V or OV 100 260 400 Output Short Current POWER SUPPLY Supply Current Vip 50mV OUT GND 5 15 Vip 50mV OUT GND dl d Sa Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package AC ELECTRICAL CHARACTERISTICS Vcc 3 0V
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MAXIM MAX9181 Low Jitter Low Noise LVPECL to LVDS Level Translator in an SC70 Package handbook