FAIRCHILD 74F08 Quad 2-Input AND Gate handbook
Contents
1. 14 13 9 8 37 1 5 01 ALL LEAD TIPS PIN 1 IDENT 9 27 TYP NEUE ERUNT LAND PATTERN RECOMMENDATION ALL LEAD TIPS v odi SEE DETAIL A 8 0 Am DIMENSIONS ARE IN MILLIMETERS NOTES 0 1 GAGE PLANE 0 8 0 25 A CONFORMS EDR 7320 REGISTRATION ESTABLISHED IN DECEMBER 1998 B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS 0 60 0 15 SEATING PLANE M 4DRevB1 Ie DETAIL A 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide Package Number M14D www fairchildsemi com 4 Physical Dimensions inches millimeters unless otherwise noted Continued 0 740 0 770 18 80 19 56 a 200 2 286 INDEX AREA 0 250 0 010 IDENT 6 350 t 0 254 PIN NO 1 IDENT 0 092 pi 04030 MAX 2 337 0 762 DEPTH OPTION 1 OPTION 02 0 135 0 005 0 300 0 320 3 428 0 127 5202 87128 0145 0200 7 620 8 128 8 683 5 080 mx OPTIONAL 1691 0 008 0 016 95 5 0 008 0 016 0 020 90 4 3 0203 0406 0 508 20 125 0 150 xr 0 075 0 015 3 175 3 810 i805 0381 im 0 014 0 023 bin aped 0014 0023 xa 0 356 0 584 x 0 100 0 010 ryp MIN 52. April 1988 FAIRCHILD Revised September 2000 SEMICONDUCTOR 1M 74F08 Quad 2 Input AND Gate General Description This device contains four independent gates each of which performs the logic AND function Ordering Code Order Number Package Number Package Description 7AF08SC M14A 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 120 0 150 Narrow 7AF08SJ M14D 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide 7AF08PC N14A 14 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Logic Symbol Connection Diagram IEEE IEC 0 Bo 1 0 Bi 2 0 B2 3 B3 Unit Loading Fan Out U L Input lj ly Pin Names Description HIGH LOW Output loH loL An Bn Inputs 1 0 1 0 20 0 6 mA On Outputs 50 33 3 1 mA 20 mA 2000 Fairchild Semiconductor Corporation 05009457 www fairchildsemi com 1induj z 903r 74F08 Absolute Maximum Ratings o e 1 Recommended Operating Storage Temperature 65 C to 150 Conditions Ambient Temperature under Bias 55 C to 125 Free Air Ambient Temperature 0 to 70 Junction Temperature under Bias 55 C to 150 Supply Voltage 4 5V to 45 5V Voc Pin Potential to Ground Pin 0 5V to 7 0
3. Input Voltage Note 2 0 5V to 7 0V Input Current Note 2 30 to 45 0 mA Voltage Applied to Output in HIGH State with Vcc OV Standard Output 0 5V to Note 1 Absolute maximum ratings are values beyond which the device m may be damaged or have its useful life impaired Functional operation S STATE Output 0 5V to 5 5 under these conditions is not implied Current Applied to Output Note 2 Either voltage limit or current limit is sufficient to protect inputs in LOW State Max twice the rated loj mA ESD Last Passing Voltage Min 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max Units Vec Conditions Vin Input HIGH Voltage 2 0 V Recognized as a HIGH Signal Input LOW Voltage 0 8 V Recognized as a LOW Signal Vcp Input Clamp Diode Voltage 1 2 V Min ly 718 mA Output HIGH 10 Vcc 2 5 Miis 1 mA Voltage 5 Vcc 2 7 lou 1 mA Vi Output LOW 10 V 9t er 0 5 v Min 20 mA Voltage li Input HIGH 5 0 uA Max 2 7V Current lgyi Input HIGH Current 7 0 uA Max Vn 7 0V Breakdown Test lcEx Output HIGH 50 uA Max Vour Vcc Leakage Current Vip Input Leakage 455 OU 1 9 uA Tes All Other Pins Grounded Output Leakage 150 mV v m 3 75 uA 0 0 S Circuit Current All Other Pins Grounded li Input LOW Current 0 6 mA Max 0 5V los Output Short Circuit Curren
4. 3050250 HM 0 040 1 270 0 254 0 325 _ 12016 nass eon REV F 14 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com 9je5 1induj z 903r
5. t 60 150 mA Max 0V Power Supply Current 55 8 3 mA Max Vo HIGH Power Supply Current 8 6 12 9 mA Vo9 LOW AC Electrical Characteristics 25 55 C to 125 Ta 0 C 70 Vec 5 0 Vec 5 0 Vec 5 0 Symbol Parameter ee ve Units C 50 pF C 50 pF C 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 3 0 4 2 5 6 2 5 7 5 3 0 6 6 R An Bn to On 2 5 4 0 5 8 2 0 7 5 2 5 6 3 www fairchildsemi com 2 Physical Dimensions inches millimeters unless otherwise noted 0 335 0 344 8 509 8 738 1 0 228 0 244 TQ N 30 5 791 198 P LEAD NO 1 7 IDENT Y 0 150 0 157 3 810 3 988 0 010 0 020 0 053 0 063 10 254 0 508 x45 1 846 1 753 8 0 004 0 010 ALL LEADS 0 102 0 254 yt h i ud ov i PLANE 0 014 0 008 0 010 MM ERES Fog Rb dim 9 D 1 0 203 0 254 0 016 0 050 0 356 i 7 0 355 0 508 TYP ALL LEADS 0 004 0 406 1 270 0208 10 102 ALL LEADS 0 203 ALL LEAD TIPS MIA REV 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 120 0 150 Narrow Package Number M14A 3 www fairchildsemi com 804 74F08 Physical Dimensions inches millimeters unless otherwise noted Continued 10 2 0 1 14 TYP IS 14 8
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FAIRCHILD 74F08 Quad 2 Input AND Gate handbook