TEXAS INSTRUMENTS TLC5615C TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS Manual
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1. The reference voltage input is buffered which makes the DAC input resistance not code dependent Therefore the REFIN input resistance is 10 MO and the REFIN input capacitance is typically 5 pF independent of input code The reference voltage determines the DAC full scale output LOGIC INTERFACE The logic inputs function with either TTL or CMOS logic levels However using rail to rail CMOS logic achieves the lowest power dissipation The power requirement increases by approximately 2 times when using TTL logic levels SERIAL CLOCK AND UPDATE RATE Figure 1 shows the TLC5615 timing The maximum serial clock rate is w cH ftSCLK max F or approximately 14 MHZ The digital update rate is limited by the chip select period which is pics 16 x tac cu tw cs and is equal to 820 ns which is a 1 21 MHz update rate However the DAC settling time to 10 bits of 12 5 us limits the update rate to 80 kHz for full scale input step transitions SERIAL INTERFACE When chip select CS is low the input data is read into a 16 bit shift register with the input data clocked in most significant bit first The rising edge of the SLCK input shifts the data into the input register The rising edge of CS then transfers the data to the DAC register When CS is high input data cannot be clocked into the input register All CS transitions should occur when the SCLK input is low If the daisy chain cascading function see daisy ch2. NOTE A The DOUT SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired Figure 12 Microwire Connection MOSI SPI QSPI O Port MISO CPOL 0 CPHA 0 NOTE A The DOUT MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer Figure 13 SPI QSPI Connection DAISY CHAINING DEVICES DACs can be daisy chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain providing that the setup time tsucss CS low to SCLK high is greater than the sum of the setup time tsups plus the propagation delay time tpqoout for proper timing see digital input timing requirements section The data at DIN appears at DOUT delayed by 16 clock cycles plus one clock width DOUT is a totem poled output for low power DOUT changes on the SCLK falling edge when CS is low When CS is high DOUT remains at the value of the last data bit and does not go into a high impedance state 10 35 TEXAS INSTRUMENTS TLC5615C TLC5615l www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 LINEARITY OFSET AND GAIN ERROR USING SINGLE ENDED SUPPLIES When an amplifier is operated from a single supply the voltage offset can still be either positive or negative With a positive offset the output voltage changes on the first code change With a negative offset the output voltage may not change with the first code dep
3. 35 TEXAS INSTRUMENTS www ti com TLC561 5C TLC561 5l SLAS142D OCTOBER 1996 REVISED AUGUST 2003 10 BIT DIGITAL TO ANALOG CONVERTERS FEATURES e Settling Time to 0 5 LSB 12 5 us Typ e 10 Bit CMOS Voltage Output DAC in an e Monotonic Over Temperature 8 Terminal Package e Pin Compatible With the Maxim MAX515 e 5 V Single Supply Operation e 3 Wire Serial Interface e High Impedance Reference Inputs APPLICATIONS e Battery Powered Test Instruments e Voltage Output Range 2 Times the Refer e Digital Offset and Gain Adjustment ence Input Voltage e Battery Operated Remote Industrial Controls e Internal Power On Reset e Machine and Motion Control Devices e Low Power Consumption 1 75 mW Max e Cellular Telephones e Update Rate of 1 21 MHz D P OR DGK PACKAGE TOP VIEW DESCRIPTION The TLC5615 is a 10 bit voltage output digital to analog converter DAC with a buffered reference input high impedance The DAC has an output voltage range that is two times the reference voltage and the DAC is monotonic The device is simple to use running from a single supply of 5 V A power on reset function is incorporated to ensure repeatable start up conditions Digital control of the TLC5615 is over a three wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices The device receives a 16 bit data word to produce the analog output The digital inputs feature Schmitt t
4. 60 120 80 40 0 60 40 20 0 20 40 60 80 100 120 140 t Temperature C Figure 4 lo Output Source Current mA G Relative Gain dB 4i TEXAS INSTRUMENTS www ti com OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE Vppz5V VReEFIN 2 048 V TA 25 C 0 5 48 46 44 42 4 38 36 34 32 3 Vo Output Pullup Voltage V Figure 3 Vgeri TO Mum RELATIVE GAI vs INPUT FREQUENCY 4 Vpp 5 V 2 VREFIN 0 2 Vpp 2 048 V dc TA 25 C 0 2 4 6 8 10 12 14 1 100 1k 10k 100 k fj Input Frequency Hz Figure 5 Wy TEXAS INSTRUMENTS www ti com TLC5615C TLC56151 SLAS142D OCTOBER 1996 REVISED AUGUST 2003 TYPICAL CHARACTERISTICS continued Differential Nonlinearity LSB Integral Nonlinearity LSB SIGNAL TO NOISE DISTORTION vs INPUT FREQUENCY AT REFIN Figure 8 Integral Nonlinearity With Input Code 70 Vppz5V 60 Ta 25 C H m Vrerin 4 Vpp 5 50 S o a 40 b o 30 z e 5 20 D 2 10 0 1k 10k 100 k 300 k Frequency Hz Figure 6 255 511 767 1023 Input Code Figure 7 D
5. METER MIN NOM MAX UNIT tsu Ds Setup time DIN before SCLK high 45 ns th DH Hold time DIN valid after SCLK high 0 ns tsucss Setup time CS low to SCLK high 1 ns tsu cs Setup time CS high to SCLK high 50 ns th csHo Hold time SCLK low to CS low 1 ns n csH1 Hold time SCLK low to CS high 0 ns twcs Pulse duration minimum chip select pulse width high 20 ns tw CL Pulse duration SCLK low 25 ns tw CH Pulse duration SCLK high 25 ns OUTPUT SWITCHING CHARACTERISTICS PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tod DOUT Propagation delay time DOUT C 50 pF 50 ns OPERATING CHARACTERISTICS over recommended operating free air temperature range Vpp 5 V 596 Ver 2 048 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT DYNAMIC PERFORMANCE C 100 pF T SR Output slew rate T 25 C R 10 ko 0 3 0 5 Vius 35 TEXAS INSTRUMENTS TLC5615C TLC5615l www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 OPERATING CHARACTERISTICS continued over recommended operating free air temperature range Vpp 5 V 5 Vie 2 048 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT DYNAMIC PERFORMANCE ae To 0 5 LSB C 100 pF t Output settling time R 10 KQ See 1 12 5 us Glitch energy DIN All Os to all 1s 5 nVes REFERENCE INPUT REFIN Reference feedt
6. N R Power ON Reset Control Logic cs 4 SCLK Dummy Bi DIN Bits 16 Bit Shift Register DOUT Terminal Functions TERMINAL WANE NO I O DESCRIPTION DIN 1 l Serial data input SCLK 2 l Serial clock input cs 3 Chip select active low DOUT 4 0 Serial data output for daisy chaining AGND 5 Analog ground REFIN 6 Reference input OUT 7 0 DAC analog voltage output Vpp 8 Positive power supply ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 1 UNIT Supply voltage Vpp to AGND 7V Digital input voltage range to AGND 0 3 V to Vpp 0 3 V Reference input voltage range to AGND 0 3 V to Vpp 0 3 V Output voltage at OUT from external source Vpp 0 3 V Continuous current at any terminal 20 mA Operating free air temperature range TA TLC5615C 0 C to 70 C TLC56151 40 C to 85 C Storage temperature range Tg 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 35 TEXAS I
7. NSTRUMENTS TLC5615C TLC5615l www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage Vpp 4 5 5 5 5 V High level digital input voltage Vi 2 4 V Low level digital input voltage Vii 0 8 V Reference voltage Vie to REFIN terminal 2 2 048 Vpp 2 V Load resistance 2 ko Operating free air temperature TA ee 2 TLC56151 40 85 C ELECTRICAL CHARACTERISTICS over recommended operating free air temperature range Vpp 5 V 5 Vef 2 048 V unless otherwise noted STATIC DAC SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 10 bits Integral nonlinearity end point adjusted INL Vef 2 048 V See 1 1 LSB Differential nonlinearity DNL Viet 2 048 V See 2 0 1 0 5 LSB Ezs Zero scale error offset error at zero scale Viet 2 048 V See 3 3 LSB Zero scale error temperature coefficient Viet 2 048 V See 4 3 ppm C Ec Gain error Viet 2 048 V See 5 3 LSB Gain error temperature coefficient Viet 2 048 V See 6 1 ppm C PSRR Power supply rejection ratio Zero genio See 7 8 at dB Gain 80 Analog full scale output R 100 ko 2V 1023 1024 V 1 2 3 4 5 6 7 8 The relative accuracy or integral nonlinearity INL sometimes referred to as linearity error is the maximum deviation of the
8. aining devices section is not used a 12 bit input data sequence with the MSB first can be used as shown in Figure 10 12 Bits MSB 2 Extra Sub LSB Bits x don t care Figure 10 12 Bit Input Data Sequence or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first 16 Bits lt MSB 2 Extra Sub LSB Bits x don t care Figure 11 16 Bit Input Data Sequence 3 TEXAS TLC5615C TLC56151 INSTRUMENTS www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 The data from DOUT requires 16 falling edges of the input clock and therefore requires an extra clock width When daisy chaining multiple TLC5615 devices the data requires 4 upper dummy bits because the data transfer requires 16 input clock cycles plus one additional input clock falling edge to clock out the data at the DOUT terminal see Figure 1 The two extra sub LSB bits are always required to provide hardware and software compatibility with 12 bit data converter transfers The TLC5615 three wire interface is compatible with the SPI QSPI and Microwire serial standards The hardware connections are shown in Figure 12 and Figure 13 The SPI and Microwire interfaces transfer data in 8 bit bytes therefore two write cycles are required to input data to the DAC The QSPI interface which has a variable input data length from 8 to 16 bits can load the DAC input register in one write cycle SO Microwire Port
9. couple to the output through internal stray capacitance Analog feedthrough is tested by holding CS high setting the DAC code to all Os sweeping the frequency applied to REFIN and monitoring the DAC output 12 MECHANICAL DATA MPDI001A JANUARY 1995 REVISED JUNE 1999 P R PDIP T8 PLASTIC DUAL IN LINE 0 400 10 60 0 355 9 02 5 0 260 6 60 0 240 6 10 0 070 1 78 MAX 0 325 8 26 0 300 7 62 0 020 0 51 MIN 4 J 0 015 0 38 Gage Plane 0 200 5 08 MAX J Seating Plane T 0 125 3 18 MIN 0 010 0 25 NOM NAE 0 100 2 54 M 0 430 10 92 gt 0 021 0 53 MAS 0 015 0 38 0 010 0 25 4040082 D 05 98 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Falls within JEDEC MS 001 For the latest package information go to http www ti com sc docs package pkg info htm 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 MECHANICAL DATA DGK S PDSO G8 PLASTIC SMALL OUTLINE PACKAGE lt 1 4 3 10 2 90 Y EEE L 1 10 MAX L Bi ES 4073329 D 12 03 NOTES All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions
10. cts to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties condi
11. do not include mold flash or protrusion Falls within JEDEC MO 187 variation AA 3 TEXAS INSTRUMENTS www ti com MECHANICAL DATA D R PDSO G8 PLASTIC SMALL OUTLINE PACKAGE Pin 1 Index Area 0 020 0 51 0 012 0 31 0 010 0 25 0 050 1 27 Y m 0 25 0 069 1 75 Max 0 004 0 10 C 0 004 0 10 Gauge Plane 7 Seating Plane 0 010 0 25 4040047 2 F 07 2004 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MS 012 variation AA 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware produ
12. ending on the magnitude of the offset voltage The output amplifier attempts to drive the output to a negative voltage However because the most negative supply rail is ground the output cannot drive below ground and clamps the output at 0 V The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage resulting in the transfer function shown in Figure 14 Output Voltage 0v Negative 1 2 DAC Code Offset Pa Figure 14 Effect of Negative Offset Single Supply This offset error not the linearity error produces this breakpoint The transfer function would have followed the dotted line if the output buffer could drive below the ground rail For a DAC linearity is measured between zero input code all inputs 0 and full scale code all inputs 1 after offset and full scale are adjusted out or accounted for in some way However single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function So the linearity is measured between full scale code and the lowest code that produces a positive output voltage For the TLC5615 the zero scale offset error is plus or minus 3 LSB maximum The code is calculated from the maximum specification for the negative offset POWER SUPPLY BYPASSING AND GROUND MANAGEMENT Printed circuit boards that use separate analog and digital ground planes of
13. fer the best system performance Wire wrap boards do not perform well and should not be used The two ground planes should be connected together at the low impedance power supply source The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane A 0 1 uF ceramic capacitor bypass should be connected between Vpp and AGND and mounted with short leads as close as possible to the device Use of ferrite beads may further isolate the system analog supply from the digital power supply Figure 15 shows the ground plane layout and bypassing technique 3 TEXAS TLC5615C TLC56151 INSTR MENTS www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 Analog Ground Plane Figure 15 Power Supply Bypassing SAVING POWER Setting the DAC register to all Os minimizes power consumption by the reference resistor array and the output load when the system is not using the DAC AC CONSIDERATIONS Digital Feedthrough Even with CS high high speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough Digital feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT Analog Feedthrough Higher frequency analog input signals may
14. hrough REFIN 1 V5 at 1 kHz 2 048 Vdc see 2 80 dB Reference input B bandwidth f 3dB REFIN 0 2 V5 2 048 Vdc 30 kHz 1 Settling time is the time for the output signal to remain within 0 5 LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex 2 Reference feedthrough is measured at the DAC output with an input code 000 hex and a V input 2 048 Vdc 1 Vpp at 1 kHz PARAMETER MEASURMENT INFORMATION th csHo tsu css lwcs gt tw CH is gt d tw CL th CSH1 x4 IR tsu cs1 sox REN 7 7 NSN See Note A See Note C See Note A tsups 9 tnr l DIN RRR RRR EK Previous LSB LSB DOUT See Note B NOTES A The input clock applied at the SCLK terminal should be inhibited low when CS is high to minimize clock feedthrough B Data input from preceeding conversion cycle C Sixteenth SCLK falling edge Figure 1 Timing Diagram TLC5615C TLC56151 SLAS142D OCTOBER 1996 REVISED AUGUST 2003 TYPICAL CHARACTERISTICS Ip Output Sink Current mA lpp Supply Current pA OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE Vpp 5 VReFIN 2 048 V Ta 25 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 08 0 9 1 1 1 1 2 Vo Output Pulldown Voltage V Figure 2 SUPPLY CURRENT vs TEMPERATURE 280 240 200 1
15. ifferential Nonlinearity With Input Code 255 511 767 1023 Input Code 3 TEXAS TLC5615C TLC56151 INSTRUMENTS www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 APPLICATION INFORMATION GENERAL FUNCTION The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10 bit digital data to analog voltage levels see functional block diagram and Figure 9 The output of the TLC5615 is the same polarity as the reference input see Table 1 An internal circuit resets the DAC register to all zeros on power up DIN SCLK CS DOUT REFIN g Resistor String DAC OUT 0 1 uF Figure 9 TLC5615 Typical Operating Circuit Table 1 Binary Code Table 0 V to 2 Vggrj Output Gain 2 INPUT 1 OUTPUT 1111 1111 11 00 AVARERNE 1000 0000 01 00 Verein aS 1000 0000 00 00 512 2 Vecrin 1024 VREFIN 0111 1111 11 00 0000 0000 01 00 Veer dm 0000 0000 00 00 OV 1 A 10 bit data word with two bits below the LSB bit sub LSB with 0 values must be written since the DAC input latch is 12 bits wide BUFFER AMPLIFIER The output buffer has a rail to rail output with short circuit protection and can drive a 2 kQ load with a 100 pF load capacitance Settling time is 12 5 us typical to within 0 5 LSB of final value 35 TEXAS INSTR MENTS TLC5615C TLC5615l www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 EXTERNAL REFERENCE
16. nge R 10 kQ 0 Vpp 0 4 V Output load regulation accuracy Vo our 2 V RL22kQ 0 5 LSB losc Output short circuit current OUT to Vpp or AGND 20 mA Vot ow Output voltage low level lo ouT S 5 mA 0 25 V VoH nigg Output voltage high level lo our 5 mA 4 75 V REFERENCE INPUT REFIN Vi Input voltage 0 Vpp 2 V fj Input resistance 10 MO TLC5615C TLC56151 SLAS142D OCTOBER 1996 REVISED AUGUST 2003 VOLTAGE OUTPUT OUT continued ki TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ci Input capacitance 5 pF DIGITAL INPUTS DIN SCLK CS Vin High level digital input voltage 2 4 V Vi Low level digital input voltage 0 8 V li High level digital input current Vi 1 pA lit Low level digital input current Vv 0 1 yA Ci Input capacitance 8 pF DIGITAL OUTPUT DOUT VoH Output voltage high level lo 2 mA Vpp 1 V VoL Output voltage low level lg 2 mA 0 4 V POWER SUPPLY Vop Supply voltage 4 5 5 5 5 V iso aso ma Power supply current Vop 55 V No load All inputs O Vor Voo Vef 2 048 V 230 350 HA ANALOG OUTPUT DYNAMIC PERFORMANCE Vier 1 Vpp at 1 kHz 2 048 Vdc Signal to noise distortion S N D code 111111 1111 60 dB See 1 1 The limiting frequency value at 1 Vpp is determined by the output amplifier slew rate DIGITAL INPUT TIMING REQUIRMENTS SEE FIGURE 1 PARA
17. output from the line between zero and full scale excluding the effects of zero code and full scale errors see text Tested from code 3 to code 1024 The differential nonlinearity DNL sometimes referred to as differential error is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes Monotonic means the output voltage changes in the same direction or remains constant as a change in the digital input code Tested from code 3 to code 1024 Zero scale error is the deviation from zero voltage output when the digital input code is zero see text Zero scale error temperature coefficient is given by Ezs TC Ezs Tmax Ezs Tmin VrerX 10 Tmax Tmin Gain error is the deviation from the ideal output Vef 1 LSB with an output load of 10 kQ excluding the effects of the zero scale error Gain temperature coefficient is given by Eg TC Eg Tmax Ec Tmin Vrer 108 T max Tmin Zero scale error rejection ratio EZS RR is measured by varying the Vpp from 4 5 V to 5 5 V dc and measuring the proportion of this signal imposed on the zero code output voltage Gain error rejection ratio EG RR is measured by varying the Vpp from 4 5 V to 5 5 V dc and measuring the proportion of this signal imposed on the full scale output voltage after subtracting the zero scale change VOLTAGE OUTPUT OUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vo Voltage output ra
18. riggers for high noise immunity Digital communication protocols include the SPI QSPI and Microwire standards The 8 terminal small outline D package allows digital control of analog functions in space critical applications The TLC5615C is characterized for operation from 0 C to 70 C The TLC5615l is characterized for operation from 40 C to 85 C AVAILABLE OPTIONS PACKAGE 1 SMALL OUTLINE PLASTIC SMALL OUTLINE PLASTIC DIP 1 D DGK P 0 C to 70 C TLC5615CD TLC5615CDGK TLC5615CP 40 C to 85 C TLC5615ID TLC5615IDGK TLC5615IP 1 Available in tape and reel as the TLC5615CDR and the TLC5615IDR SPI QSPI are trademarks of Motorola Inc Microwire is a trademark of National Semiconductor Corporation Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 1996 2003 Texas Instruments Incorporated Products conform to specifications perthe terms of Texas Instruments standard warranty Production processing does not necessarily in cludetesting ofall parameters 3 TEXAS TLC5615C TLC56151 INSTRUMENTS www ti com SLAS142D OCTOBER 1996 REVISED AUGUST 2003 FUNCTIONAL BLOCK DIAGRAM OUT Voltage Output AGND REFIN DAC M
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TEXAS INSTRUMENTS TLC5615C TLC5615I 10 BIT DIGITAL TO ANALOG CONVERTERS Manual