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ANALOG DEVICES OP470 handbook

1. 100 N E OP11 gt E I OP400 w Q 10 g OP471 4 E y OP470 T RESISTOR NOISE ONLY 1 100 1k 10k 100k Rs SOURCE RESISTANCE Q Figure 5 Total Noise vs Source Resistance Including Resistor Noise at 10 Hz 0P470 Figure 6 shows peak to peak noise versus source resistance over the 0 1 Hz to 10 Hz range Once again at low values of Rs the voltage noise of the OP470 is the major contributor to peak to peak noise with current noise the major contributor as Rg increases The crossover point between the OP470 and the OP400 for peak to peak noise is at Rg 17 kQ The OP471 is a higher speed version of the OP470 with a slew rate of 8 V us Noise of the OP471 is only slightly higher than the OP470 Like the OP470 the OP471 is unity gain stable 1000 OP11 E OP400 gt 1 o OP471 g lt 100 H E I a OP470 e f Y RESISTOR q NOISE ONLY a 10 100 ik 10k 100k Rg SOURCE RESISTANCE Q Figure 6 Peak To Peak Noise 0 1 Hz to 10 Hz vs Source Resistance Includes Resistor Noise For reference typical source resistances of some signal sources are listed in Table I e D2 Y P 1N4148 Table I Device Source Impedance Comments Strain ga
2. MHz 0P470 Ta 25 C Vg 15V THD 1 PEAK TO PEAK AMPLITUDE V 1k 10k 100k 1M FREQUENCY Hz 10M TPC 19 Maximum Output Swing vs Frequency 360 Ta 25 C Vg 15V 300 7 w U 240 3 H 180 H E 2 120 5 Ay 100 o 60 Ay 1 d 100 1k 10k 100k 1M MOmiMooi FREQUENCY Hz TPC 22 Output Impedance vs Frequency 1 Ta 25 C Vg 15V Vo 10V p p R 2kQ 0 1 I z o 5 o A 0 01 Ay 10 3 Ay 1 0 001 10 100 1k 10k FREQUENCY Hz TPC 25 Total Harmonic Distortion vs Frequency MAXIMUM OUTPUT V 00 1k LOAD RESISTANCE Q 10k TPC 20 Maximum Output Voltage vs Load Resistance 4 0 3 5 3 0 2 5 2 0 e Saki 75 50 25 0 2550 75 TEMPERATURE C SLEW RATE V us 400 125 TPC 23 Slew Rate vs Temperature OVERSHOOT 0 200 400 600 800 CAPACITIVE LOAD pF 1000 TPC 21 Small Signal Overshoot vs Ca CHANNEL SEPARATION dB pacitive Load 170 160 150 140 130 120 110 100 90 80 70 60 50 10 100 1k 10k 100k 1M FREQUENCY
3. 5V Figure 7 Peak To Peak Voltage Noise Test Circuit 0 1 Hz to 10 Hz 10 REV B 0P470 4 The test time to measure 0 1 Hz to 10 Hz noise should not ex The OP470 is a monolithic device with four identical amplifiers ceed 10 seconds As shown in the noise tester frequency response The noise voltage density of each individual amplifier will match curve of Figure 8 the 0 1 Hz corner is defined by only one pole giving The test time of 10 seconds acts as an additional pole to elimi nate noise contribution from the frequency band below 0 1 Hz eour 101 la e 101 2 en 5 A noise voltage density test is recommended when measuring noise on a large number of units A 10 Hz noise voltage density NOISE MEASUREMENT CURRENT NOISE DENSITY measurement will correlate well with a 0 1 Hz to 10 Hz The test circuit shown in Figure 10 can be used to measure peak to peak noise reading since both results are determined current noise density The formula relating the voltage output to by the white noise and the location of the 1 f corner frequency current noise density is 6 Power should be supplied to the test circuit by well bypassed low noise supplies e g batteries These will minimize output 9 e 2 ise i i i i OUT 40nV INH noise introduced via the amplifier supply pins G n z 1 100 EHF Rs where 80
4. P Suffix NC NO CONNECT The OP470 offers excellent amplifier matching which is impor tant for applications such as multiple gain blocks low noise instrumentation amplifiers guad buffers and low noise active filters The OP470 conforms to the industry standard 14 lead DIP pingit Afis pih Compatible with the LM148 149 HA4741 e HA5104 and RM4176 guad op amps and can be used to up grade systems using these devices For higher speed applications the OP471 with a slew rate of 8 V us is recommended SIMPLIFIED SCHEMATIC REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 O Analog Devices Inc 2002 0P470 SPECIFICATIONS ELECTRICAL CHARACTERISTICS at V 15 V T 25 C unless otherwise noted OP470A E OP470F OP470G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE Vos 0 1 0 4 0 2 0 8 0 4 1 0 mV INPUT OFFSET CURRENT Ios Vcy 0 V 3 10 6 20 12 30 nA INPUT
5. F 0 325 8 26 0 200 5 08 0 015 0 38 0 310 7 87 MAX VOR A 0 150 0 015 029 0 300 62 0 150 3 81 0 200 5 08 3 81 0 135 3 43 0 125 3 18 Sig MIN at 0 015 0 38 0 180 4 57 0 120 3 05 0 023 0 58 0 070 1 78 F 15 0 008 0 20 MAX y AA AAA A 0 014 0 36 _ 0 030 0 76 0 150 3 81 ON seie g 0 130 3 30 gt ja 0 015 0 38 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETERS DIMENSIONS ld dad A PLANE IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR 0 110 2 79 0 022 0 56 0 060 1 52 0 010 0 25 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0 018 0 46 0 050 1 27 0 008 0 20 0 014 0 36 0 045 1 14 COMPLIANT TO JEDEC STANDARDS MO 095 AB CONTROLLING DIMENSIONS ARE IN INCH MILLIMETERS DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 16 Lead Standard Small Outline Package SOIC Wide Body RW 16 Dimensions shown in millimeters and inches y d d 7 69 0 2998 7 40 0 2913 10 65 0 4193 10 00 0 3937 je 3 1 27 0 0500 2 65 0 1043 0 75 0 0295 _ BSC 2 35 0 0925 z 0 25 0 0098 0 30 0 0118 E 0 51 0 0201 d o gt oh ie COPLANARITY 5 33 SEH PLANE 9 32 0 0126 1 27 0 0500 0 10 H 0 23 0 0091 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES AR
6. Hz Ty 25 C Vg 15V Vo 20V p p TO 10kHz 10M TPC 24 Channel Separation vs Frequency TPC 26 Large Signal Transient Response TPC 27 Small Signal Transient Response REV B 0P470 O V 20V p p V4 CHANNEL SEPARATION 20 LOG 4750 Figure 2 Channel Separation Test Circuit Figure 3 Burn tn Circult APPLICATIONS INFORMATION Voltage and Current Noise The OP470 is a very low noise quad op amp exhibiting a typi cal voltage noise of only 3 2 nVVHz 1 kHz The exceptionally low noise characteristics of the OP470 are in part achieved by operating the input transistors at high collector currents since the voltage noise is inversely proportional to the square root of the collector current Current noise however is directly propor tional to the square root of the collector current As a result the outstanding voltage noise performance of the OP470 is gained at the expense of current noise performance which is typical for low noise amplifiers To obtain the best noise performance in a circuit it is vital to understand the relationship between voltage noise e current noise ip and resistor noise e TOTAL NOISE AND SOURCE RESISTANCE The total noise of an op amp can be calculated by El RAY e where E total input referred noise up amp voltage noise 1 Op amp current noise e source resistance thermal noise Rs so
7. TIME Secs FREQUENCY Hz SUPPLY VOLTAGE V TPC 1 Voltage Noise Density vs TPC 2 Voltage Noise Density vs TPC 3 0 1 Hz to 10 Hz Noise Freguency Supply Voltage 10 0 140 10 Ta 25 C Vg 15V 9 Vg 15V R 120 a E 2 8 I 1 u w 100 2 7 I 5 S 6 8 9 80 o 1 0 R D 5 E 60 ir E E o 4 S z g E 40 uw 3 5 z 2 z 2 T VE CORNER 200Hz 20 I 04 M 0 1 0 0 10 100 1k 10k 75 50 25 50 25 50 751000125 0 1 2 3 4 5 FREQUENCY Hz TEMPERATURE C TIME Mins TPC 4 Current Noise Density vs TPC 5 Input Offset Voltage vs TPC 6 Warm Up Offset Voltage Drift Frequency Temperature 20 9 Vg 15V 3 Vom 0V lt lt 8 E l i 15 E m w g w SG g E 7 g 2 g 2 10 2 o E o DI br DI lt 2 lt 6 m U m o 5 E 5 a 5 gt a F a Z 5 a z 0 0 4 75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125 2125 75 25 25 75 125 TEMPERATURE C TEMPERSTURE C COMMON MODE VOLTAGE V TPC 7 Input Bias Current vs TPC 8 Input Offset Current vs TPC 9 Input Bias Current vs Temperature Temperature Common Mode Voltage 6 REV B 130 120 110 100 Ta 25 C Vg 15V CMR dB 1 10 100 1k 10k FREQUENCY Hz 100k 1M TPC 10 CMR vs Frequency 140 130 120 110 100 Ta 25 C PSR PSR dB 50 PSR 10 U 1 10 100 ik 10k 100k 1M 10M 100M FREQUENCY Hz TPC 13
8. case mounting conditions i e ja is specified for device in socket for TO CerDIP PDIP packages 0 is specified for device soldered to printed circuit board for SOIC packages IN A OUT A OUTD IN D INC HIN C IN D DIE SIZE 0 163 x 0 106 INCH 17 278 SQ mm 4 14 x 2 69 mm 11 14 SQ mm Figure 1 Dice Characteristics ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the OP470 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING mad ESD SENSITIVE DEVICE REV B 0P470 Typical Performance Characteristics 10 9 8 7 z AT 10Hz 5 S gt S 1 4 AT 1kHz w w o o O SCH 2 5 u Q lt w 2 5 9 3 8 S s gt z 1 1 10 100 1k 0 5 10 15 20
9. to eliminate this effect is shown in Figure 11 The added components C1 and R3 decouple the amplifier from the load capacitance and provide additional stability The values of C1 and R3 shown in Figure 11 are for a load capaci tance of up to 1000 pF when used with the OP470 PLACE SUPPLY DECOUPLING CAPACITORS AT OP470 Figure 11 Driving Large Capacitive Loads In applications where the OP470 s inverting or noninverting inputs are driven by a low source impedance under 100 or connected to ground if V is applied before V or when V is disconnected excessive parasitic currents will flow Most applica tions use dual tracking supplies and with the device supply pins properly bypassed power up will not present a problem A source resistance of at least 100 Q in series with all inputs Figure 11 will limit the parasitic currents to a safe level if V is discon nected It should be noted that any source resistance even 100 Q adds noise to the circuit Where noise is required to be kept at a minimum a germanium or Schottky diode can be used to clamp the V pin and eliminate the parasitic current flow instead of using series limiting resistors For most applications only one diode clamp is required per board or system UNITY GAIN BUFFER APPLICATIONS When Rf lt 100 Q and the input is driven with a fast large signal pulse gt 1 V the output waveform will look as shown in Figure 12 a 2 R1 V ZX OP470 O X 2V
10. 2 G gain of 10000 Rs 100 kQ source resistance m 60 a R3 5 1 24kQ 40 i 20 O en OUT TO SPECTRUM ANALYZER 0 0 01 0 1 1 10 100 FREQUENCY Hz Figure 8 0 1 Hz to 10 Hz Peak to Peak Voltage Noise Test Circuit Frequency Response GAIN 50 000 Vs 5V Figure 10 Current Noise Density Test Circuit NOISE MEASUREMENT NOISE VOLTAGE DENSITY The circuit of Figure 9 shows a quick and reliable method of measuring the noise voltage density of quad op amps Each individual amplifier is series connected and is in unity gain save the final amplifier which is in a noninverting gain of 101 Since the ac noise voltages of each amplifier are uncorrelated they add in rms fashion to yield tour 101 Ven e p ec ew O eouT TO SPECTRUM ANALYZER eouT NVVHZ 101 2e Vg 15V Figure 9 Noise Voltage Density Test Circuit REV B 11 0P470 CAPACITIVE LOAD DRIVING AND POWER SUPPLY CONSIDERATIONS The OP470 is unity gain stable and is capable of driving large capacitive loads without oscillating Nonetheless good supply bypassing is highly recommended Proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the OP470 In the standard feedback amplifier the op amp s output resistance combines with the load capacitance to form a low pass filter that adds phase shift in the feedback network and reduces stability A simple circuit
11. ANALOG DEVICES Very Low Noise Quad Operational Amplifier 0P470 FEATURES Very Low Noise 5 nV vHz 1 kHz Max Excellent Input Offset Voltage 0 4 mV Max Low Offset Voltage Drift 2 p V C Max Very High Gain 1000 V mV Min Outstanding CMR 110 dB Min Slew Rate 2 V s Typ Gain Bandwidth Product 6 MHz Typ Industry Standard Quad Pinouts Available in Die Form GENERAL DESCRIPTION The OP470 is a high performance monolithic quad operational amplifier with exceptionally low voltage noise 5 nV VHz at 1 kHz max offering comparable performance to ADI s industry standard OP27 The OP470 features an input offset voltage below 0 4 mV excellent for a quad op amp and an offset drift under 2 uV C guaranteed over the full military temperature range Open loop gain of the OP470 is over 1 000 000 into a 10 kQ load ensuring excellent gain accuracy and linearity even in high gain applica tions Input bias current is under 25 nA which reduces errors due to signal source resistance The OP470 SfEMRof ovef 110 dB and PSRR of less than1 8 UV WVsignificantiyredute errors due to ground noise and power supplyfluctwations Power consumption of the quad OP470 is half that of four OP27s a significant advantage for power conscious applications The OP470 is unity gain stable with a gain bandwidth product of 6 MHz and a slew rate of 2 V us PIN CONNECTIONS 14 Lead Hermetic DIP 16 Lead SOIC Package Y Suffix S Suffix 14 Lead Plastic DIP
12. BIAS CURRENT Ig Vem 0V 6 25 15 50 25 60 nA INPUT NOISE VOLTAGE Capp 0 1 Hz to 10 Hz 80 200 80 200 80 200 nV p p Note 1 INPUT NOISE fo 10 Hz 3 8 6 5 38 6 5 3 8 6 5 Voltage Density n fo 100 Hz 3 3 55 33 5 5 33 55 nVVHz fo 1 kHz 3 2 5 0 3 2 5 0 3 2 5 0 Note 2 INPUT NOISE fo 10 Hz 1 7 1 7 1 7 Current Density la fo 100 Hz 0 7 0 7 07 pAVHz fo 1 kHz 0 4 0 4 0 4 LARGE SIGNAL V 10V Voltage Gain Avo Rr 10 kQ 1000 2300 800 1700 800 1700 V mV Rr 2 kQ 500 1200 400 900 400 900 INPUT VOLTAGE RANGE IVR Note 3 11 212 11 12 11 12 V OUTPUT VOLTAGE i V SWING Vo RYZ 240 12 18 412 415 12 13 V COMMON MODE REJECTION CMR Vem 11V 110 125 100 120 100 120 dB POWER SUPPLY REJECTION RATIO PSRR Vs 4 5 V to 18 V 0 56 1 8 1 0 5 6 1 0 5 6 uv v SLEW RATE SR 1 4 2 14 2 14 2 V us SUPPLY CURRENT All Amplifiers Isy No Load 9 11 9 11 9 11 mA GAIN BANDWIDTH PRODUCT GBW Ay 10 6 6 6 MHz CHANNEL SEPARATION CS Vo 20 V p p 125 155 125 155 125 155 dB fo 10 Hz Note 1 INPUT CAPACITANCE Cx 2 2 2 pF INPUT RESISTANCE Ry 0 4 0 4 0 4 MQ Differential Mode INPUT RESISTANCE Common Mode Rincm 11 11 11 GQ Ay 1 SETTLING TIME ts to 0 1 5 5 5 5 5 5 us to 0 01 6 0 6 0 6 0 NOTES Guaranteed but not 100 tested Sample tested Guaranteed by CMR test 2 REV B ELECTRICAL CHARACTERISTICS atVs 15 V 55 C lt T lt 125 C for OP470A unless otherwise noted 0P470 OP470A Parame
13. E ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV B 15 ADV611 ADV612 Revision History Location Page 10 02 Data Sheet changed from REV A to REV B Reuter Lea SOLG z tz SAS V r dasad o ced aula e asa rains Ek zalo z o de dee by do dde edito 1 Edits to ELECTRICAL CHARACTERISTICS cees 570 vaks As a bln Runa a bag p s lik p i R I GO B S E Ra IE TER 3 Edits to ABSOLUTE MAXIMUM RATINGS 1 12 4 1145 8 4 A 7 i S A al teen ne R A S R RT A enna 5 Updated OU PEINE DIMENSIONS 7530 sko s R id A sl a al aros 15 4 02 Data Sheet changed from REV 0 to REV A 28 Tead LCC RE Sufhixiideleted it sab A A A A ia Slee aE A LAG Ka al e A Ae ERC 1 28 Lead LCG LC Suffix deleted k is Va Ve ska vask ak A EE 1 Edits to ABSOLUTE MAXIMUM RATINGS 11 7 14 25 5 ata s state tenn r a aa 4 Edits to ORDERINE GUIDE ein ass ads a RT E alar Cate R 4 Edits tO PACKAGE TYPE oi A KEE a EE ee a a a ee 4 16 REV B C00305 0 10 02 B PRINTED IN U S A
14. ON RATIO PSRR Vs 4 5 V to 18 V 0 7 5 6 1 8 10 1 8 10 uv v SUPPLY CURRENT All Amplifiers Isy No Load 9 2 11 92 11 93 11 mA Guaranteed by CMR test REV B 3 OP470 SPECIFICATIONS WAFER TEST LIMITS at V 15 V 25 C unless otherwise noted OP470GBC Parameter Symbol Conditions Limit Unit INPUT OFFSET VOLTAGE Vos 0 8 mV Max INPUT OFFSET CURRENT los Vem 0V 20 nA Max INPUT BIAS CURRENT Ip Vom 0V 50 nA Min LARGE SIGNAL Vo 10 V Voltage Gain Ayo RL 10 kQ 800 V mV Min Rr 2 kQ 400 INPUT VOLTAGE RANGE IVR 11 V Min OUTPUT VOLTAGE SWING Vo R22 kQ 12 V Min COMMON MODE REJECTION CMR Vem 3 11 V 100 dB POWER SUPPLY REJECTION RATIO PSRR Vs 4 5 V to 18 V 5 6 uV V Max SUPPLY CURRENT All Amplifiers Isy No Load 11 mA Max NOTE Guaranteed by CMR test Electrical tests are performed at wafer probe to the limits shown Due to variations in assembly methods and normal yield loss yield after packaging is not guaran teed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing REV B 0P470 ABSOLUTE MAXIMUM RATINGS Supply Voltage eee ene 18 V Differential Input Voltage 1 0V Differential Input Current 0000 25 mA Input Voltage Supply Voltage Output Short Circuit Duration Continuous Storage Tem
15. PSR vs Frequency 80 100 120 140 160 GAIN dB 180 200 220 5 6 7 8910 1 2 3 4 FREQUENCY MHz TPC 16 Open Loop Gain Phase Shift vs Frequency REV B PHASE SHIFT Degrees TOTAL SUPPLY CURRENT mA 0 5 10 15 SUPPLY VOLTAGE V 20 TPC 11 Total Supply Current vs Supply Voltage 140 130 120 110 d EI Noe o oo a o OPEN LOOP GAIN dB o o o RB o o N o o o 1 10 100 ik 10k 100k 1M 10M 100M FREQUENCY Hz TPC 14 Open Loop Gain vs Frequency 5000 4000 w o o OPEN LOOP GAIN V mV N E 1000 0 5 10 15 SUPPLY VOLTAGE V 20 25 TPC 17 Open Loop Gain vs Supply Voltage TOTAL SUPPLY CURRENT mA 25 0 TEMPERSTURE C 25 50 75 100 125 TPC 12 Total Supply Current vs Supply Voltage 80 60 40 20 CLOSED LOOP GAIN dB 20 1k 10k 100k 1M FREQUENCY Hz 10M TPC 15 Closed Loop Gain vs Frequency PHASE MARGIN Degrees 40 0 75 50 25 0 25 50 75 100 125 150 TEMPERATURE C TPC 18 Gain Bandwidth Product Phase Margin vs Temperature GAIN BANDWIDTH PRODUCT
16. ge lt 500 0 Typically used in low freguency applications Magnetic lt 1500 Q Low Ig very important to reduce tapehead self magnetization problems when direct coupling is used OP470 I can be neglected Magnetic lt 1500 Q Similar need for low Ip in direct phonograph coupled applications OP470 cartridges will not introduce any self magnetization problem Linear variable lt 1500 O Used in rugged servo feedback differential applications Bandwidth of transformer interest is 400 Hz to 5 kHz For further information regarding noise calculations see Minimization of Noise in Op Amp Applications Application Note AN 15 NOISE MEASUREMENTS PEAK TO PEAK VOLTAGE NOISE The circuit of Figure 7 is a test setup for measuring peak to peak voltage noise To measure the 200 nV peak to peak noise speci fication of the OP470 in the 0 1 Hz to 10 Hz range the following precautions must be observed TsThe device must be Warniedmipfor at least five minutes As shown infth Kamp drift cule the offset voltage typi Cally changes 5 uN due to Mer dsing chip temperature after power up In the 10 second measurement interval these temperature induced effects can exceed tens of nanovolts 2 For similar reasons the device must be well shielded from air currents Shielding also minimizes thermocouple effects 3 Sudden motion in the vicinity of the device can also feedthrough to increase the observed noise GAIN 50 000 Vs
17. of the peak detector Vp falls below the threshold voltage VTH set by R8 the comparator formed by op amp C switches from V to V This drives the gate of the N channel FET high turning it ON re ducing the gain of the inverting amplifier formed by op amp A to Zero 2N5434 1 4 a OP470E A L R4 O Vout 5Vin T 1 SECOND R7 C2 10kQ 10u4F gal 100 Figure 17 Squelch Amplifier 14 FIVE BAND LOW NOISE STEREO GRAPHIC EQUALIZER The graphic equalizer circuit shown in Figure 18 provides 15 dB of boost or cut over a 5 band range Signal to noise ratio over a 20 kHz bandwidth is better than 100 dB referred to a 3 V rms input Larger inductors can be replaced by active inductors but this reduces the signal to noise ratio O Vout TANTALUM c R7 6800 9 22pF TANTALUM C5 R9 6800 0 047nF I TANTALUM c6 R11 6800 0 022uF TANTALUM Figure 18 Five Band Low Noise Graphic Equalizer REV B 0P470 OUTLINE DIMENSIONS 14 Lead Ceramic Dip Glass Hermetic Seal CERDIP 14 Lead Plastic Dual in Line Package PDIP Q 14 N 14 Dimensions shown in inches and millimeters Dimensions shown in inches and millimeters 0 685 17 40 0 005 0 13 MIN 0 098 2 49 MAX 0 665 16 89 0 295 7 49 gia EE 0 645 16 38 0 285 7 24 0 310 7 87 0 275 6 99 0 220 5 59 gt be 0 320 8 13 0 100 2 54 BSC 0 290 7 37 gt 0 785 19 94 MAX 0 060 1 52
18. perature Range P ET EEN 65 C to 150 C Lead Temperature Range Soldering 60 sec 300 C Junction Temperature Tj 65 C to 150 C Operating Temperature Range OPA TOA u ans da AR alas Bk dk 55 C to 125 C OP470E OP470F 25 C to 85 C OP470G inde i end sade tah aa 40 C to 85 C ORDERING GUIDE Package Options Ta 25 C Operating Vos max Cerdip Temperature pV 14 Pin Plastic Range 400 MIL 400 OP470AY MIL 400 OP470EY IND 800 OP470FY IND 1000 OP470GP XIND 1000 OP470GS XIND Not for new design obsolete April 2002 For military processed devices plea e fefer to the standard Microcircuit Drawing SMP available at www dscc dla mil programs milspec default asp SMD Part Number ADI Equivalent 59628856501CA OP470AYMDA 596288565012A OP470ARCMDA 596288565013A OP470ATCMDA Not for new designs obsolete April 2002 CAUTION Package Type Ba c Unit 14 Lead Hermetic DIP Y 94 10 C W 14 Lead Plastic DIP P 76 33 C W 16 Lead SOIC S 88 23 C W NOTES Absolute Maximum Ratings apply to both DICE and packaged parts unless otherwise noted The OP470 s inputs are protected by back to back diodes Current limiting resistors are not used in order to achieve low noise performance If differential voltage exceeds 1 0 V the input current should be limited to 25 mA a is specified for worst
19. ter Symbol Conditions Min Typ Max Unit INPUT OFFSET VOLTAGE Vos 0 14 0 6 mV AVERAGE INPUT Offset Voltage Drift TCVos 0 4 2 uv c INPUT OFFSET CURRENT Ios Vem 0V 5 20 nA INPUT BIAS CURRENT Ip Vom 0V 15 20 nA LARGE SIGNAL Vo 10V Voltage Gain Avo Rr 10 kQ 750 1600 V mV Rr 2 kQ 400 800 INPUT VOLTAGE RANGE IVR 11 12 V OUTPUT VOLTAGE SWING Vo R gt 2 kQ 12 13 V COMMON MODE REJECTION CMR Vcm 11 V 100 120 dB POWER SUPPLY REJECTION RATIO PSRR Vs 4 5 V to 18 V 1 0 5 6 uv v SUPPLY CURRENT All Amplifiers Isy No Load 9 2 11 mA Guaranteed by CMR test ELECTRICAL CHARACTERISTICS H at Vs 15 V 25 C ST lt 85 for OP4706 0B470EF 40 C lt T lt 85 C for 0P4706 unless otherwise noted OP470E OP470F OP470G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE Vos 0 12 0 5 0 24 1 0 0 5 1 5 mV AVERAGE INPUT Offset Voltage Drift TCVos 0 4 2 0 6 4 2 uV C INPUT OFFSET CURRENT los Vem 0V 4 20 7 40 20 50 nA INPUT BIAS CURRENT Ig Vem 0 V 11 50 20 70 40 75 nA LARGE SIGNAL Vo 10V Voltage Gain Avo Rr 10 kQ 800 1800 600 1400 600 1500 V mV Ry 2 kQ 400 900 300 700 300 800 INPUT VOLTAGE RANGE IVR 11 12 11 12 11 12 V OUTPUT VOLTAGE SWING Vo Rr 22 kQ 12 13 12 13 12 13 V COMMON MODE REJECTION CMR Vem 11V 100 120 90 115 90 110 dB POWER SUPPLY REJECTI
20. ts two of the DAC 8408 s four DACs drive current to voltage converters built from a single quad OP470 The amplifiers have complementary outputs with the amplitudes dependent upon the digital code applied to the DAC Figure 16 shows the comple mentary outputs for a 1 kHz input signal and digital ramp applied to the DAC data inputs Distortion of the digital panning con trol is less than 0 01 SIDE A IN O DAC DATA BUS q PINS 9 LSB 16 MSB 1kQ 5V 1kQ DAC SELECT DGND a i AAA E ene Figure 16 Digital Panning Control Output Gain error due to the mismatching between the internal DAC ladder resistors and the current to voltage feedback resistors is eliminated by using feedback resistors internal to the DAC Of the four DACs available in the DAC 8408 only two DACs A and C actually pass a signal DACs B and D are used to pro vide the additional feedback resistors needed in the circuit If the VREFB and VREFD inputs remain unconnected the current to voltage converters using RFBB and RFBD are unaf fected by digital data reaching DACs B and D y ReBA Figure 15 Digital Panning Control Circuit REV B 13 0P470 SQUELCH AMPLIFIER The circuit of Figure 17 is a simple squelch amplifier that uses a FET switch to cut off the output when the input signal falls below a preset limit The input signal is sampled by a peak detector with a time constant set by C1 and R6 When the output
21. urce resistance REV B The total noise is referred to the input and at the output would be amplified by the circuit gain Figure 4 shows the relationship between total noise at 1 kHz and source resistance For Rs lt 1 kQ the total noise is dominated by the voltage noise of the OP470 As Rs rises above 1 kQ total noise increases and is dominated by resistor noise rather than by voltage or current noise of the OP470 When Rg exceeds 20 kQ current noise of the OP470 becomes the major contributor to total noise Figure 5 also shows the relationship between total noise and source resistance but at 10 Hz Total noise increases more quickly than shown in Figure 4 because current noise is inversely proportional to the square root of frequency In Figure 5 current noise of the OP470 dominates the total noise when Rs gt 5 kQ From Figures 4 and 5 it can be seen that to reduce total noise source resistance must be kept to a minimum In applications with a high source resistance the OP400 with lower current noise than the OP470 will provide lower total noise 100 N E gt OP11 l 10 OP400 o OP471 H E g 0P470 M 1 RESISTOR NOISE ONLY 1 100 1k 10k 100k Rs SOURCE RESISTANCE Q Figure 4 Total Noise vs Source Resistance Including Resistor Noise at 1 kHz
22. us Figure 12 Pulsed Operation During the fast feedthrough like portion of the output the input protection diodes effectively short the output to the input and a current limited only by the output short circuit protection will be drawn by the signal generator With Rf lt 500 O the output is capable of handling the current reguirements IL lt 20 mA at 10 V the amplifier will stay in its active mode and a smooth transition will occur When Rf gt 3 kQ a pole created by Rf and the amplifier s input capacitance 2 pF creates additional phase shift and reduces phase margin A small capacitor 20 pF to 50 pF in parallel with Rf helps eliminate this problem APPLICATIONS Low Noise Amplifier A simple method of reducing amplifier noise by paralleling amplifiers is shown in Figure 13 Amplifier noise depicted in Figure 14 is around 2 nV VHz 1 kHz R T I Gain for each paralleled amplifier and the entire circuit is 1000 The 200 Q resistors limit circulating cugrents and provide an effective out put resistance of50Q2 The amplifier is stable with a 10 nF capacitive load and can supply up4a 30 mA of output drive O Vout 1000Vx Figure 13 Low Noise Amplifier REV B NOISE DENSITY 0 58nV Hz DIV REFERRED TO INPUT Figure 14 Noise Density of Low Noise Amplifier G 1000 DIGITAL PANNING CONTROL Figure 15 uses a DAC 8408 quad 8 bit DAC to pan a signal between two channels The complementary DAC current out pu

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