MAXIM MXL1543 Manual
Contents
1. LD FLASH SVIAAISVI TRUSIONS N EED 5mm 006 INFORMATION N MILLIM PACKAGE OUTLINE SSOP 5 3x 65mm APPROVAL DOCUMENT CONTROL NO 21 0056 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 18 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2001 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products2. MI AALS Features 9 MXL1543 MXL1544 MAX3175 and MXL1344A Chipset Is Pin Compatible with LTC1543 LTC1544 and LTC1344A 9 Supports 5 232 RS 449 EIA 530 EIA 530A V 35 V 36 and X 21 9 Software Selectable Cable Termination Using the MXL1344A Complete DTE or DCE Port with MXL1544 MAX3175 and MXL1344A 5V Single Supply Operation 0 5pA No Cable Mode TUV Certified NET1 NET2 and TBR1 TBR2 Compliant 9 9 Ordering Information TEMP RANGE PIN PACKAGE 0 to 70 C 28 SSOP PART MXL1543CAl Pin Configuration appears at end of data sheet Typical Operating Circuit XC SCTE MAXIM MXL1344A A 83195 80 DB 25 CONNECTOR AVLAZCLAI ELI V 3198 01 v OXL Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com EVS LIXIN 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers ABSOLUTE MAXIMUM RATINGS All Voltages Referenced to Unless Otherwise Noted Supply Voltages Receiver Input RUN TSOUITEUTINL sati ti 15V to 15V IE 0 3V to 6V Continuous Power Dissipation TA 70 C 0 3V to 7 3V 28 Pin SSOP derate 11 1mW C above 70 C 889mW EE 0 3V to 6 5V Operating Temperature Range
3. Figure 12 Typical V 11 Interface V 11 and V 35 modes If the differential receiver input voltage B A is gt 25mV OUT is logic HIGH If B A is 200mV R OUT is logic LOW In the case of a terminated bus with all transmitters disabled the receiver s differential input voltage is pulled to zero by the termination With the receiver thresholds of the MXL 1543 this results in a logic HIGH with a 25mV mini mum noise margin Applications Information Capacitor Selection The capacitors used for the charge pumps as well as for supply bypassing should have a low equivalent series resistance ESR and low temperature coeffi cient Multilayer ceramic capacitors with an X7R dielec tric offer the best combination of performance size and cost The flying capacitors C1 C2 and the bypass capacitor C4 should have a value of while the reservoir capacitors C3 C5 should have a minimum value of 4 7uF Figure 10 To reduce the rip ple present on the transmitter outputs capacitors C3 and C5 can be increased The values of C1 and C2 should not be increased Cable Termination The MXL1344A software selectable resistor network is designed to be used with the MXL 1543 The MXL1344A multiprotocol termination network provides V 11 and V 35 compliant termination while V 28 receiver termina tion is internal to the MXL 1543 These cable termination networks provide compatibility with V 11 V 28 and V 35 prot
4. MEE NOS Wns a 13V MXIEIBASG AI Logic Input 0 2 Junction Temperature MO M1 M2 DCE DTE 1 0 3V to 6V Storage Temperature Range es Logic Output Voltages Lead Temperature soldering 10s 300 C mos ET 0 3V to Vcc 0 3V Transmitter Outputs TOUT lacas ca iz 15V to 15V Short Circuit Duration esses Continuous Note 1 Vpp and absolute difference cannot exceed 13V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vcc 5 0V C1 C2 C4 C5 4 7uF Figure 10 Ta Tmin to Tmax Typical values are at TA 25 C unless oth erwise noted PARAMETER DC CHARACTERISTICS Vcc Operating Range Vcc SYMBOL CONDITIONS RS 530 RS 530A X 21 no load RS 530 RS 530A X 21 full load DCE Mode V 35 mode no load Digital Inputs GND or V 35 mode full load Vcc V 28 mode no load Transmitter Outputs Static V 28 mode full load No cable mode RS 530 RS 530A
5. 25V power off or no cable mode Rise or Fall Time Transmitter Input to Output Delay Figures 3 6 igures 3 6 Data Skew igures 3 6 Output to Output Skew tSKEW igures 3 6 V 35 RECEIVER Differential Input Voltage Input Hysteresis 2V lt Vom lt 2V Figure 3 Receiver Input Current 10V lt VA B lt 10V Receiver Input Resistance 10V lt VA p lt 10V Rise or Fall Time Figures 3 7 Receiver Input to Output Delay Data Skew V 28 TRANSMITTER Figures 3 7 Figures 3 7 Output Voltage Swing Figure 4 Open circuit RL 3kQ Short Circuit Current Output Leakage Current 0 25V VOUT lt 0 25V power off or no cable mode Output Slew Rate RL 2500pF Figures 4 8 Transmitter Input to Output Delay RL CL 2500pF Figures 4 8 Transmitter Input to Output Delay V 28 RECEIVER RL 2500pF Figures 4 8 nput Threshold Low nput Threshold High nput Hysteresis nput Resistan Rise or Fall Time Receiver Input to Output Delay 15V VIN 4 15V Figures 5 9 Figures 5 9 Receiver Input to Output Delay Figures 5 9 MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Typical Operating Characteristics Vcc 5 0V C1
6. C2 CA 1uF C5 4 7uF Figure 10 TA Tmin to Tmax TA 25 C unless otherwise noted V 11 SUPPLY CURRENT V 28 SUPPLY CURRENT V 35 SUPPLY CURRENT vs DATA RATE vs DATA RATE vs DATA RATE 160 5 100 g E MODE ALL TRANSMITTERS 5 180 8 14 OPERATING AT THE SPECIFIED DATA RATE 13 E 80 FR CL 2500pF 160 m E 140 100 5 amp 60 g 120 8 9 z S 10 2 8g 21 40 Zi 80 a az 3 60 20 40 20 DCE MODE R 500 ALL TRANSMITTERS DCE MODE FULL LOAD ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE 20 OPERATING AT THE SPECIFIED DATA RATE 0 0 0 04 10 00 000 10 000 0 50 100 150 200 250 01 041 10100 1000 10 000 DATA RATE kbps DATA RATE kbps DATA RATE kbps V 11 DRIVER DIFFERENTIAL OUTPUT V 28 OUTPUT VOLTAGE V 35 OUTPUT VOLTAGE VOLTAG
7. Output Differential Voltage R 500 Figure Common Mode Output Voltage R 500 F Change in Magnitude of Output Common Mode Voltage Short Circuit Current Vour GN 0 25V lt VouT lt 0 25V power off or Output Leakage Current necati moda Rise or Fall Time tr t Figures 2 6 Transmitter Input to Output Delay tPHL tPLH Figures 2 6 Data Skew ItPHL tPLHI Figures 2 6 Output to Output Skew tSKEW Figures 2 6 V 11 RECEIVER Differential Threshold Voltage 7 lt lt 7 Input Hysteresis 7 lt lt 7 Receiver Input Current 10V lt VA B lt 10V Receiver Input Resistance 10V lt VA p 10V Rise or Fall Time Figures 2 7 Receiver Input to Output Delay tPHL tPLH Figures 2 7 80 Data Skew ItPHL tPLHI Figures 2 7 16 V 35 TRANSMITTER Open circuit Figure 3 7 With load 4V lt Vom lt 4V Figure 3 0 44 055 0 66 Differential Output Voltage Output High Current Output Low Current MAXIM 3 EVS LIXIN 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers ELECTRICAL CHARACTERISTICS continued MXL1543 Vcc 5 0V C1 2 CA 1pF C5 4 7pF Figure 10 TA TMIN to Tmax Typical values are at TA 25 C unless oth erwise noted PARAMETER SYMBOL CONDITIONS Output Leakage Current 0 25V VouT lt 0
8. X 21 full load V 35 mode full load V 28 mode full load Any mode except no cable mode no load V 28 mode with load V 28 V 35 modes with load IDD 10mA V 28 V 35 no load V 28 mode full load V 35 mode full load RS 530 RS 530A X 21 full load Supply Rise Time tr No cable mode or power up to turn on LOGIC INPUTS MO M1 M2 DCE DTE T1IN T2IN T3IN Input High Voltage Supply Current Internal Power Dissipation DCE Mode Positive Charge Pump Output Voltage Negative Charge Pump Output Voltage Input Low Voltage T1IN T2IN MO M1 M2 DCE DTE GND MO M1 M2 DCE DTE Vcc Logic Input Current 2 AVLAZCLAVI 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers ELECTRICAL CHARACTERISTICS continued Vcc 5 0V C1 C2 CA tpF C5 4 7pF Figure 10 TA Tmin to Tmax Typical values are at TA 25 C unless oth erwise noted PARAMETER SYMBOL CONDITIONS LOGIC OUTPUTS R1OUT R20UT R3OUT Output High Voltage ISOURCE 4mA Output Low Voltage VoL ISINK 4mA Output Short Circuit Current O lt Vour lt Vcc Output Pullup Current VOUT 0 no cable mode V 11 TRANSMITTER Open Circuit Differential Output Voltage Open circuit 1 95kQ Figure 1 Loaded Differential Output R 500 Figure 1 TA 25 C Voltage 500 Figure Change in Magnitude of
9. 00pF Ry 3kQ Tour Rin 1us div vs TEMPERATURE V 35 LOOPBACK OPERATION MXL1543 10011 MXL1543 toc12 i FULL LOAD 5V div TIN 5V div 5V div OUT RIN 5V div 5V div Rour 200ns div V 11 RECEIVER PROPAGATION DELAY vs TEMPERATURE MXL1543 toc14 MXL1543 1015 SLEW RATE PROPAGATION DELAY ns a 80 7 E g 60 x n 35 a amp 4 30 522 E y PHL RL 3kQ 1 TRANSMITTER SWITCHING AT 250kbps 10 OTHER TRANSMITTERS SWITCHING AT 15kbps 0 1000 2000 3000 4000 5000 0 0 20 30 40 50 6 CLoap pF TEMPERATURE C V 35 TRANSMITTER PROPAGATION DELAY vs TEMPERATURE 80 e 70 3 E Z 60 gt gt 5 5 3 e 5 40 5 30 2 a a o amp 20 amp 10 0 0 10 20 30 40 50 60 TEMPERATURE C 70 0 70 0 10 20 30 40 50 60 70 TEMPERATURE V 35 RECEIVER PROPAGATION DELAY vs TEMPERATURE MXL1543 toc17 0 10 20 30 40 50 60 70 TEMPERATURE C MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Test Circuits Figure 1 V 11 DC Test Circuit Figure 2 V 11 AC Test Circuit Figure 4 V 28 Driver Test Circuit Figu
10. 19 1929 Rev 1 9 01 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers General Description The MXL1543 is a three driver three receiver multipro tocol transceiver that operates from a 5V single sup ply The MXL1543 along with the MXL1544 MAX3175 and the MXL1344A form a complete software selec table data terminal equipment DTE or data communi cation equipment DCE interface port that supports the V 28 RS 232 V 10 V 11 RS 449 V 36 EIA 530 EIA 530A 21 and V 35 protocols The MXL 1543 trans ceivers carry the high speed clock and data signals while the MXL1544 MAX3175 carry the control signals The MXL 1543 can be terminated by the MXL1344A software selectable resistor termination network or by discrete termination networks An internal charge pump and a proprietary low dropout transmitter output stage allow V 11 V 28 and V 35 compliant operation from a 5V single supply A no cable mode is entered when all mode pins MO M1 and M2 are pulled high or left unconnected In no cable mode supply current decreases to 0 5uA all transmitter and receiver outputs are disabled high impedance Short circuit current limiting and thermal shutdown circuitry protect the drivers against excessive power dissipation Applications Data Networking PCI Cards CSU and DSU Telecommunications Data Routers Equipment DCD DIR RTS CA MAXIM MXL1544 057 A MAX3175
11. E DTE DCE DTE M2 0 Figure 19 Multiprotocol DCE DTE Port MAXIM 15 EVS LIXIN 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers SERIAL MAXIM MAXIM MAXIM MAXIM SERIAL CONTROLLER MXL1543 MXL1344A MXL1344A MXL1543 CONTROLLER TXD TXD MAXIM MAXIMA MXL1544 MXL1544 MAX3175 MAX3175 AY X A Figure 20 DCE to DTE X 21 Interface MXL1544 MAX3175 generate the control signals and Compliance Testing local loopback LL The MXL1344A is used to termi A European Standard EN 45001 test report is pending nate the clock and data signals to support the V 11 pro for the MXL1543 MXL1544 MXL1344A chipset A copy tocol for cable termination The control signals do not of the test report will be available from Maxim upon need external termination completion 16 MAXIM TRANSISTOR COUNT 2619 PROCESS BiCMOS MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Chip Information TOP VIEW MAXIM MXL1543 Pin Configuration UTA RTINA UTB R1INB 17 EPSI1XW 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Package Information MILL IM MIN 1 73 0 05 0 25 0 09 IATI 5 20 0 65 7 65 0 63 0 SSOP EPS
12. E vs TEMPERATURE vs TEMPERATURE vs TEMPERATURE 5 10 a 2004 L DCEMODE R 500 DCE MODE Ri 3kQ 8 e em zu E 3 6 E E z 2 4 1 2 9 8 z 0 20 4 2 2 2 5 E 2 4 m d 6 eE Vour 4 8 5 10 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 0 10 2 30 40 50 60 70 TEMPERATURE C TEMPERATURE C TEMPERATURE C V 35 DIFFERENTIAL OUTPUT VOLTAGE V 11 V 35 RECEIVER INPUT CURRENT V 28 RECEIVER INPUT CURRENT 1 vs COMMON MODE VOLTAGE vs INPUT VOLTAGE vs INPUT VOLTAGE oog 5 300 g 25 8 590 g DCE MODE 5 20 DCE MODE m sin 5 gw 2 is E E E 10 8 sm 100 5 5 05 E s EU 20 2 zi 550 05 E 2 100 E 10 amp 540 3 e amp 940 9 82 15 200 T S 580 2 0 520 300 2 5 4 3 2 4 0 1 2 3 4 10 8 6 4 2 02 4 6 8 10 10 8 6 4 2 0 2 4 6 8 10 COMMON MODE VOLTAGE V NPUT VOLTAGE V NPUT VOLTAGE V MAKIM 5 EVS LIXIN 11543 Tour R V us 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers 5 0V C1 Rou Typical Operating Characteristics continued C2 C4 1pF C5 A7yF Figure 10 TA 25 C unless otherwise noted V 11 LOOPBACK OPERATION MXL1543 toc10 5V div TIN eed 5V div Rour 200ns div V 11 TRANSMITTER PROPAGATION DELAY V 28 SLEW RATE vs CLoan V 28 LOOPBACK OPERATION C 25
13. ceivers UNBALANCED a GENERATOR gt INTERCONNECTING gt CABLE Figure 17 Typical V 28 Interface CABLE TERMINATION p gt RECEIVER gt MAXIM MAXIM MXL1344A MXL1543 RECEIVER Figure 18 V 28 Termination and Internal Resistance Networks load termination networks The V 35 receiver is sensi tive to 200 differential signals at receiver inputs A and B The V 35 receiver rejects common mode sig nals developed across the cable referenced from C to of up to 44 allowing for error free reception in noisy environments In Figure 16 the MXL1344A is used to implement the resistive T network that is needed to properly terminate the V 35 driver and receiver Internal to the MXL 13444 51 and S2 are closed to connect the T network resis tors to the circuit The V 28 termination resistor internal to the MXL1543 is disabled by opening S3 to avoid interference with the T network impedance V 28 Interface The V 28 interface is an unbalanced single ended inter face Figure 17 The V 28 driver generates a minimum of 5V across a 3kQ load impedance between A and C The V 28 receiver has a single ended input To aid 14 in rejecting system noise the MXL1543 s V 28 receiver has a typical hysteresis of 0 05V Figure 18 shows the MXL1344A s termination network disabled by opening S1 and S2 The MXL1543 s in
14. cted to a terminated transmission line with all the drivers disabled This is done by setting the receivers threshold between 25mV and 200mv in the MAXIM MXL1543 Figure 10 Charge Pump MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers C6 8 100pF 100pF 100pF MAXIM E MXL1344A 9 LATCH 19120 DTE DCE TXDA RXDA SCTEA SCTEB RXCB DTE_TXD DCE_RXD DTE_SCTE DCE_RXC DTE_TXC DCE_TXC IXCB TXCB RXCA SCTEA DTE_RXC DCE_SCTE RXCB 5 RXDA XDA RXDB TXDB MAXIM SG MXL1543 2 DCE DTE DTE RXD DCE TXD SHIELI DTE RTS DCE C DTE DTR DCE DSR DTE DCD DCE DCD DTE DSR DCE DTR DTE CTS DCE RTS MAXIM 0 MXL1544 MAGIS 2 DCE DTE INVERT Figure 11 Cable Selectable Multiprotocol DTE DCE Port MAXIM 11 EVS LIXIN 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers BALANCED INTERCONNECTING GENERATOR CABLE LOAD CABLE TERMINATION RECEIVER
15. ernally pulled up to Vcc to ensure a logic HIGH if left unconnected No Cable Mode The MXL1543 will enter no cable mode when the mode select pins are left unconnected or connected high MO M1 M2 1 In this mode the multiproto col drivers and receivers are disabled and the supply current drops to 5 The receivers outputs enter high impedance state in no cable mode which allow these output lines to be shared with other receivers outputs the receivers outputs have internal pullup resistors to pull the outputs HIGH if not driven Also in no cable mode the transmitter outputs enter a high impedance state so that these output lines can be shared with other devices Dual Charge Pump Voltage Converter The MXL 1543 s internal power supply consists of a reg ulated dual charge pump that provides positive and negative output voltages from a 5V supply The charge pump operates in discontinuous mode If the output voltage is less than the regulated voltage the charge pump is enabled If the output voltage exceeds the regulated voltage the charge pump is disabled 10 V 28 V 28 Each charge pump requires a flying capacitor C1 C2 and a reservoir capacitor C3 C5 to generate the and supplies Figure 10 shows charge pump con nections Fail Safe Receivers The MXL1543 guarantees a logic high receiver output when the receiver inputs are shorted or open or when they are conne
16. ocols Using the MXL1344A termination net works provide the advantage of not having to build expensive termination networks out of resistors and relays manually changing termination modules or building custom termination networks 12 Figure 13 Receiver Input Impedance Cable Selectable Mode A cable selectable multiprotocol interface is shown in Figure 11 The mode control lines MO M1 and DCE DTE are wired to the DB 25 connector To select the serial interface mode the appropriate combination of MO M1 and DCE DTE are grounded within the cable wiring The control lines that are not grounded are pulled high by the internal pullups on the MXL 1543 The serial interface protocol of the MXL 1543 MXL1544 MAX3175 and MXL1344A is selected based on the cable that is connected to the DB 25 interface V 11 Interface As shown in Figure 12 the V 11 protocol is a fully bal anced differential interface The V 11 driver generates a minimum of 2V between nodes A and B when a 1000 min resistance is presented at the load The V 11 receiver is sensitive to 200mvV differential signals at receiver inputs A and B The V 11 receiver rejects common mode signals developed across the cable referenced from C to of up to 7V allowing for error free reception in noisy environments The receiver inputs must comply with the impedance curve shown in Figure 13 For high speed data transmission the V 11 specifica tion recommends termina
17. ode Select Pin nternal Pullup to Vcc 0 1 2 13 14 DCE DTE 5 6 7 8 CE DTE Mode Select Pin with Internal Pullup to oninverting Receiver Input R3INB R3INA nverting Receiver Input R2INB oninverting Receiver Input 20 T3OUTA R1INA nverting Transmitter Output Inverting Receiver Input 21 T20UTB oninverting Transmitter Output 22 T20UTA nverting Transmitter Output 2 3 T1OUTB oninverting Transmitter Output 24 T1OUTA nverting Transmitter Output 25 GND Ground 6 2 Generated Negative Supply Connect a 4 7uF ceramic capacitor to ground 27 Capacitor C2 Negative Terminal Connect a 1uF ceramic capacitor between C24 and C2 28 Capacitor C2 Positive Terminal Connect a 1uF ceramic capacitor between C2 and C2 Detailed Description The MXL 1543 is a three driver three receiver multipro tocol transceiver that operates from a single 5V sup ply The 1543 along with the MXL1544 MAX3175 MXL1344A form a complete software selectable DTE or DCE interface port that supports the V 28 RS 232 V 10 V 11 RS 449 V 36 EIA 530 EIA 530A X 21 and V 35 protocols The MXL1543 transceivers carry the high speed clock and data signals while the 1544 MAX3175 transceivers carry serial interface control signaling The MXL 1543 can be terminated by the MXL1344A software selectable resistor termination network or by a discrete termination netw
18. ork The 1543 features a 0 5pA no cable mode true fail AVLAZCLAVI safe operation and thermal shutdown circuitry Thermal shutdown protects the drivers against excessive power dissipation When activated the thermal shutdown cir cuitry places the driver outputs into a high impedance state Mode Selection The state of the mode select pins MO M1 and M2 determines which serial interface protocol is selected Table 1 The state of the DCE DTE input determines whether the transceiver will be configured as a DTE or DCE serial port When the DCE DTE input is logic HIGH driver T3 is activated and receiver H1 is dis abled When the DCE DTE input is logic LOW driver T3 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Table 1 Mode Selection MXL1543 MODE NAME z N z o Not Used Default V 11 RS 530A RS 530 X 21 z ojojojo RS 449 V 36 V 28 RS 232 No Cable Not Used Default V 11 RS 530A RS 530 V 11 X 21 V 11 V 11 V 35 RS 449 V 36 V 35 V 35 V 11 V 11 gt gt lolo V 28 RS 232 No Cable 1 53 34 olo 14 1 0 1 0 1 1 10 1 10 N N N N 3 1 1 1 41 41 41 41 1 is disabled and receiver R1 is activated MO M1 M2 and DCE DTE are int
19. re 5 V 28 Receiver Test Circuit MAXIM EVS LIXIN 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Timing Diagrams 1MHz t lt 10ns t lt 10ns VorrF V A V B 1 2 E SKEW SKEW Figure 6 V 11 35 Driver Propagation Delays Vo B A p f 1MHz tr lt 10ns 1 lt 1008 INPUT Vo aura _ R 15V OUTPUT 15V VoL Figure 7 V 11 V 35 Receiver Propagation Delays 1 7V 24 Figure 9 V 28 Receiver Propagation Delays 8 MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers Pin Description PIN NAME FUNCTION 1 C1 Capacitor C1 Negative Terminal Connect a 1uF ceramic capacitor between C1 and C1 C14 Capacitor C1 Positive Terminal Connect a 1uF ceramic capacitor between C1 and 1 VDD Generated Positive Supply Connect a 4 7uF ceramic capacitor to ground Voc 5V Supply Voltage 45 Decouple with 1uF capacitor to ground Transmitter 1 TTL Compatible Input T2IN Transmitter 2 TTL Compatible Input Transmitter 3 TTL Compatible Input R10UT Receiver 1 CMOS Output 2 3 4 5 TAIN 6 7 8 9 R2OUT Receiver 2 CMOS Output R3OUT Receiver 3 CMOS Output MO ode Select Pin with Internal Pullup to ode Select Pin nternal Pullup to Vcc EVS LIXIN with with M1 M2
20. ter nal 5 V 28 termination is enabled by closing S3 DTE vs DCE Operation Figure 19 shows a DCE or DTE controller selectable interface DCE DTE pin 14 switches the port s mode of operation See Table 1 This application requires only one DB 25 connector but separate cables for DCE or DTE signal routing See Figure 19 for complete signal routing in DCE and DTE modes Complete Multiprotocol X 21 Interface A complete DTE to DCE interface operating in X 21 mode is shown in Figure 20 The MXL1543 is used to generate the clock and data signals and the MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers C6 8 100pF 100pF 100pF 11 13 MAXIM E MXL1344A 1 E Add E 2 8 DTE DCE DTE_TXD TXDA RXDB DTE 50 SCTEA RXCA SCTEB RXCB 5 9 DTE_TXC DCE_TXC TXCB RXCA SCTEA DTE 0 SCTE RXCB SCTEB RXDA TXDA DTE RXD DCE TXD TXDB MAXIM 86 mo MXL1543 SHIELD DB 25 CONNECTOR CE DT DCE RTS L DCE LL MAXIM MXL1544 MO MAX3175 1 MI INVERT DC
21. ting the cable at the receiver with a 100Q resistor This resistor although not required prevents reflections from corrupting transmit ted data In Figure 14 the MXL1344A is used to termi nate the V 11 receiver Internal to the MXL1344A 51 is closed and 52 is open to present a 1000 minimum dif ferential resistance The MXL1543 s internal V 28 termi nation is disabled by opening S3 V 35 Interface Figure 15 shows a fully balanced differential standard V 35 interface The generator and the load must both present a 1000 100 differential impedance and a 1500 150 common mode impedance as shown by the resistive T networks in Figure 15 The V 35 driver generates a current output 11mA typ that develops an output voltage of 550mV across the generator and MAXIM 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Transceivers MAXIMA MXL1543 MAXIM MXL1344A RECEIVER Figure 14 V 11 Termination and Internal Resistance Networks BALANCED GENERATOR a INTERCONNECTING gt CABLE CABLE TERMINATION e RECEIVER Figure 15 Typical V 35 Interface MAXIM MXL1543 MAXIM RI MXL1344A 520 RECEIVER Figure 16 V 35 Termination and Internal Resistance Networks MAXIM 13 EVS LIXIN 11543 5V Multiprotocol 3Tx 3Rx Software Selectable Clock Data Trans
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MAXIM MXL1543 Manual