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PHILIPS TDA4841PS I 2 C-bus autosync deflection controller for PC monitors handbook

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1. Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT232 1 ET 95 02 04 ISSUE DATE 2002 Jun 24 55 Philips Semiconductors I2C bus autosync deflection controller for PC monitors SOLDERING Introduction to soldering through hole mount packages This text gives a brief insight to wave dip and manual soldering A more in depth account of soldering ICs can be found in our Data Handbook IC26 Integrated Circuit Packages document order number 9398 652 90011 Wave soldering is the preferred method for mounting of through hole mount IC packages on a printed circuit board Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C solder at this temperature must not be in contact with the joints for more than 5 seconds Product specification TDA4841PS The total contact time of successive solder waves must not exceed 5 seconds The device may be mounted up to the seating plane but the temperature of the plastic body must not exceed the specified maximum storage temperature T stg max If the printed circuit board has been pre heated forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit Manual soldering Apply the soldering iron
2. 2002 Jun 24 48 Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors TDS SYMBOL INTERNAL CIRCUIT yr su MBG565 x MBG566 power ground connected to substrate MGM089 MBK381 MGM090 MBG570 2002 Jun 24 49 Philips Semiconductors Product specification I C bus autosync deflection controller for TDA4841PS PC monitors SYMBOL INTERNAL CIRCUIT VOUT2 MBG571 MBG572 14 VSYNC 100 Q 14 4 1 4V Ta 7 3 V MBG573 15 HSYNC 1 28 V 850 i 15 1 4 7 3V MBG574 16 CLBL Co MBG575 2002 Jun 24 50 Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors TDA4841PS SYMBOL INTERNAL CIRCUIT HUNLOCK MGM091 MGMO92 19 SDA r MGMO93 20 ASCOR 480 Q MGMO94 21 VSMOD O 250 Q m m MGM095 2002 Jun 24 51 Philips Semiconductors Il2C bus autosync deflection controller for PC monitors SYMBOL INTERNAL CIRCUIT Product specification TDA4841PS VAGC 2
3. Ed y Co MBG581 MBG582 MBG583 signal ground MGM096 2002 Jun 24 52 Philips Semiconductors Product specification FE I C bus autosync deflection controller for TDA4841PS PC monitors SYMBOL INTERNAL CIRCUIT HBUF MGM097 H pa x p Co 6 25 V MGMO98 2002 Jun 24 53 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors SYMBOL INTERNAL CIRCUIT HSMOD MGM099 K 2 X CJ MGM100 Electrostatic discharge ESD protection 7 3 V MBG559 MBG560 Fig 30 ESD protection for pins 4 11 to 13 Fig 31 ESD protection for pins 2 3 5 18 to 24 16 and 17 and 26 to 32 2002 Jun 24 54 Philips Semiconductors Product specification I2C bus autosync deflection controller for TDA4841PS PC monitors PACKAGE OUTLINE SDIP32 plastic shrink dual in line package 32 leads 400 mil SOT232 1 seating plane A lari DIMENSIONS mm are the original dimensions A A Ao max min max UNIT b mm 4 7 0 51 3 8
4. If the I2C bus master transmits data to another register an acknowledge is given after the chip address and the subaddress an acknowledge is not given after the data This indicates that data can be stored into normal registers only in soft start mode If the supply voltage drops below 8 1 V the deflection controller leaves normal operation and changes to standby mode The microcontroller can check this state by sending data into a register with the subaddress OXH The acknowledge will only be given on the data if the IC is active Due to this behaviour the start up of the TDA4841PS is defined as follows the first data that is transferred to the deflection controller must be sent to the control register with subaddress 1AH Any other subaddress will not lead HUNLOCK indicates that the frequency to voltage converter is out of lock is floating HIGH via external pull up resistor to an acknowledge This is a limitation in checking the 2C busses of the monitor during start up CLBL provides a continuous blanking signal VOUT1 and VOUT2 vertical outputs are floating The capacitor at HPLL2 is discharged If the soft start procedure is activated via the I C bus all of these actions will be performed in a well defined sequence see Figs 22 and 23 2002 Jun 24 13 Philips Semiconductors Product specification Il2C bus autosync deflection controller for TDA4841P PC monitors LIMITING VALUES In accordance with t
5. Isink int internal sink current 7 7 ocke l max maximum external load current VHuxLock 1 V leakage current VHUNLOCK 5 V in case of unlocked PLL1 and or protection active PLL1 phase comparator and frequency locked loop pins HPLL1 and HBUF VV HSYNC max maximum vvidth of horizontal sync pulse referenced to line period lock HPLL1 total lock in time of PLL1 letrl HPLL1 control currents notes 4 and 5 locked mode level 1 locked mode level 2 buffered f v voltage at HBUF pin 27 minimum horizontal frequency maximum horizontal frequency 2002 Jun 24 17 Philips Semiconductors I C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS Product specification TDA4841PS Phase adjustments and corrections via PLL1 and PLL2 HPOS HPINBAL horizontal position referenced to horizontal period horizontal pin unbalance correction via HPLL2 referenced to horizontal period register HPOS 0 register HPOS 127 register HPOS 255 register HPINBAL 0 note 6 register HPINBAL 63 note 6 register HPINBAL 32 note 6 HPARAL horizontal parallelogram correction referenced to horizontal period register HPARAL 0 note 6 register HPARAL 63 note 6 register HPARAL 32 note 6 HMOIRE relative modulation of horizontal position by 1 2 horizontal frequency phase alte
6. 24 V or less to the lead s of the package either below the seating plane or not more than 2 mm above it If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds If the bit temperature is between 300 and 400 C contact may be up to 5 seconds Suitability of through hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS DIP HDIP SDIP SIL suitable Note suitable 1 1 For SDIP packages the longitudinal axis must be parallel to the transport direction of the printed circuit board DATA SHEET STATUS PRODUCT STATUS Development DATA SHEET STATUSU Objective data Preliminary data Qualification product Product data Production Notes DEFINITIONS This data sheet contains data from the objective specification for product development Philips Semiconductors reserves the right to change the specification in any manner without notice This data sheet contains data from the preliminary specification Supplementary data will be published at a later date Philips Semiconductors reserves the right to change the specification without notice in order to improve the design and supply the best possible This data sheet contains data from the product specification Philips Semiconductors reserves the right to make changes at any time in order to improve the design manufacturing and supply Ch
7. 46 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors Printed circuit board layout further connections to other components or ground paths are not allowed x external components of external components of horizontal section vertical section lt pin 25 should be the star point for all small signal components external components of horizontal section no external ground tracks connected here TDA4841PS 47 pF 100 uF external components B drive line in parallel of driver stages to ground ae only this path may be connected to general ground of PCB MHB605 SMD For optimum performance of the TDA4841PS the ground paths must be routed as shown Only one connection to other grounds on the PCB is allowed Note The tracks for HDRV and BDRV should be kept separate Fig 29 Hints for Printed Circuit Board PCB layout 2002 Jun 24 47 Philips Semiconductors Product specification FEE I C bus autosync deflection controller for TDA4841PS PC monitors INTERNAL PIN CONFIGURATION SYMBOL INTERNAL CIRCUIT HFLB MBG561 2 XRAY HE bn MBG562 3 BOP R 5 3V MBG563 4 BSENS MBG564
8. HREF also defines the integration time constant of the vertical sync integration Calculation of line frequency range First the oscillator frequencies fmin and fmax have to be calculated This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies fsync min and fsync max The oscillator is driven by the currents in Runer and Rypue Table 1 describes a 31 45 to 90 kHz application Table 1 Calculation of total spread spread of for fmax for fmin IC 3 5 CHCAP 2 2 Rurer RHBUF 2 2 Total 7 9 Thus the typical frequency range of the oscillator in this example is f x 1 07 96 3 kHz sync max fs i _ ync min 109 28 4 kHz min The resistors Runer and RHBurpar Can be calculated with the following formulae 2 61 kQ R 78 x KHz x kQ HREF f 2 min 0 0012 x fmin KHZ 78 x KHz x kQ TshIT 726 Q 2 fmax 0 0012 x finaxl KHZ RHBUFpar m The resistor RuBurpar S calculated as the value of Rurer and Rupur in parallel Philips Semiconductors I2C bus autosync deflection controller for PC monitors The formulae for Rupur additionally takes into account the voltage swing across this resistor Rurer X RHBUFpar x 0 8 805 Q Rurer RHBUFpar RHBUF a PLL1 phase detector The phase detector is a standard type using switched current sources which are independent of the horizontal frequency It compares the middle of
9. MGM069 VOUT1 VEVVDRV n VOUT2 YHPIN EVVDRV 1 Al is the maximum amplitude setting at register VSIZE 127 and register VOVSCN 0 Al Aly VLINBAL 2x AL x 100 Fig 8 Parabola amplitude at pin EWDRV as a Fig 7 lvour1 and lvour2 as functions of time function of time MGM070 MGM071 v VEWDRV I EWDRV I YHCOR EVVDRV i I V i i j HA t t Fig 9 Influence of corner correction at pin EWDRV Fig 10 Influence of trapezium at pin EWDRV 2002 Jun 24 29 Philips Semiconductors Product specification Il2C bus autosync deflection controller for I TDA4841PS PC monitors MGM072 MGM073 VEwDRV VASCOR Pa L i Vc ASCOR y 1 HPARAL ASCOR VHSIZE EWDRV 2 2 4 b NA 27 VHEHT EVVDRV g m t t Fig 11 Influence of HSIZE and EHT compensation at pin EWDRV Fig 12 Adjustment of parallelogram at pin ASCOR MGM074 VHPINBAL ASCOR Fig 13 Adjustment of pin balance at pin ASCOR 2002 Jun 24 30 Philips Semiconductors I17 C bus autosync deflection controller for PC monitors Pulse diagrams Product specification TDA4841PS vertical oscillator sawtooth at VCAP pin 24 vertical sync pulse internal trigger inhibit window typical 4 ms vertical blanking pulse at CLBL pin 16 vertical blanking pulse at HUNLOCK pin 17 differential output
10. STDBY 1 2 Starting the soft start sequence by setting control bit SOFTST 1 bit STDBY don t care see L3 of Fig 18 for continuation ue BiG 3 Decreasing the supply voltage below 8 1 V Standby mode Standby mode XXXX XX01 i STDBY 1 e Set control bit STDBY 1 SOFTST 0 e Driver outputs are floating same as protection mode all other register contents are random e Supply current is 9 mA Only the 12C bus section and protection circuits are L2 1 Manse operative Contents of all registers are lost except the value of bit STDBY and bit SOFTST See L2 of Fig 18 for continuation 1 See Fig 18 Fig 19 12C bus flow for standby mode and protection mode 2002 Jun 24 39 Philips Semiconductors Il2C bus autosync deflection controller for PC monitors ANY Mode Voc lt 8 1V Power Down Mode no acknowledge is given by IC all register contents are random MGM079 1 See Fig 18 Power down mode Power dip of Vcc lt 8 6 V e The soft down sequence is started first e Then the soft start sequence is generated internally Power dip of Vcc lt 8 1 V or Vcc shut down e This function is independent from the operating mode therefore it works under any condition e All driver outputs are immediately disabled e IC enters standby mode Standby mode detection Execute data transmission twice to assure that there was no data transfer error 2002
11. This mode should be used if a single register has to be changed while the picture is visible so i e for user adjustments One received 1 C bus data byte is stored in an internal 8 bit buffer before it is passed to the DAC section The first internal vertical blanking pulse VBL after end of transmission is used to synchronize the adjustment change with the vertical flyback So the actual change of the picture size position geometry etc will take place during the vertical flyback period and will thus be invisible The IC gives acknowledge for chip address subaddress and data of a buffered transmission Only one 12C bus transmission is accepted after each vertical blank After one buffered transmission the IC gives no acknowledge for further transmissions until next VBL pulse has occurred The buffered mode is disabled while the IC is in standby mode Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors List of 12C bus controlled switches I7C bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress e SADT is the register subaddress to be used for transmissions in direct mode e SAD2 is the register subaddress to be used for transmissions in buffered mode Table 5 Controlled svvitches notes 1 and 2 REGISTER ASSIGNMENT CONTROL FUNCTION SAD1 SAD2 BIT HEX HEX BLKDIS 0 vertical protection and horizontal
12. a se a Sara RF v Protection mode XXXX XX00 STDBY 0 SOFTST 0 registers are pre set Y no all registers defined 5 Y yes SL eon ee jf v Soft start sequence XXXX XX10 STDBY 0 SOFTST 1 Y gt Operating mode XXXX XX10 STDBY 0 SOFTST 1 Y Y no no t enangerretresh of data gt lt SOFTST 0 gt y yes y yes LEE a see P zr FF MGL791 1 See Fig 19 Fig 18 12C bus flow for start up 2002 Jun 24 38 Start up procedure Voc lt 8 3 V e As long as the supply voltage is too low for correct operation the IC will give no acknowledge due to internal Power On Reset POR e Supply current is 9 mA or less Voc gt 8 3 V e Internal POR has ended and the IC is in standby mode e Control bits STDBY and SOFTST are reset to their start values All other register contents are random e Pin HUNLOCK is at HIGH level Setting control bit STDBY 0 e Enables internal power supply e Supply current increases from 9 to 68 mA e When Vcc lt 8 6 V register SOFTST cannot be set by the 12C bus e Output stages are disabled e Pin HUNLOCK is at HIGH level Setting all registers to defined values e Due to the hardware configuration of the IC no auto increment any register setting needs a complete 3 byte 1 C bus data transfer as follows START IC address subaddress data STOP Setting cont
13. integrator V 12 Open loop gain is vy at f 0 with no resistive load and Cgop 10 nF from BOP pin 3 to GND BIN 13 The recommended value for the pull up resistor at pin 6 BDRV is 1 kO 2002 Jun 24 27 Philips Semiconductors Il2C bus autosync deflection controller for PC monitors Vertical and EW adjustments MBG590 VOUT1 I VOUT2 i AL Y 1 Al is the maximum amplitude setting at register VSIZE 127 register VGAIN 63 control bit VOVSCN 0 VSIZE x100 AE o Ab VSMOD x 100 Al Fig 3 Adjustment of vertical size Product specification TDA4841PS MGS274 IVOUT1 VOUT2 1 Al is the maximum amplitude setting at register VSIZE 127 register VGAIN 63 control bit VOVSCN 0 Al VGAIN x 100 Al Fig 4 Adjustment of vertical size MBG592 VOUT1 VOUT2 1 Al is the maximum amplitude setting at register VSIZE 127 and register VGAIN 63 VPOS d 100 2xAL a VOFFS 35 100 2x Al 2 4 Fig 5 Adjustment of vertical position MBG594 VOUT1 VOUT2 Alz At 1 Al is the maximum amplitude setting at register VSIZE 127 and VLIN 0 Al Al VLIN AT x 10096 Fig 6 lyout1 and your as functions of time 2002 Jun 24 28 Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors MGMO068
14. pin XRAY 2002 Jun 24 43 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors APPLICATION INFORMATION oe Vi R60 L V Veprv D2 gt H INVERTING BUFFER 77 D1 D horizontal bl flyback pulse R5 R1 Vesens R4 c IF C4 R2 c2 c 7 MGMO80 l BOP gt 10 nF gt EWDRV For f lt 50 kHz and C2 lt 47 nF calculation formulas and behaviour of the OTA are the same as for an OP An exception is the limited output current at BOP pin 3 See Chapter Characteristics subheading B control section see Figs 25 and 26 1 The recommended value for R6 is 1 kO a Feedback mode application D horizontal flyback pulse VupRv L L L L Vgprv tott min VBSENS VBOP VBSENS ff vaesrar ssens VSTOP BSENS MBG600 b Waveforms for normal operation c Waveforms for fault condition Fig 25 Application and timing for feedback mode 2002 Jun 24 44 Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors TDA4841PS Voc horizontal flyback pulse ram INVERTING BUFFER HORIZONTAL OUTPUT gt STAGE EHT VEDRV transfo
15. using the code 9398 393 40011 2002 Jun 24 57 Philips Semiconductors Product specification I17 C bus autosync deflection controller for TDA4841P PC monitors gt NOTES 2002 Jun 24 58 Philips Semiconductors Product specification I17 C bus autosync deflection controller for TDA4841P PC monitors gt NOTES 2002 Jun 24 59 Philips Semiconductors a worldwide company Contact information For additional information please visit http www semiconductors philips com Fax 31 40 27 24825 For sales offices addresses send e mail to sales addresses www semiconductors philips com Koninklijke Philips Electronics N V 2002 SCA74 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 753504 02 pp60 Date of release 2002 Jun 24 Document order number 9397 750 09802 lets make things better 7 amp PHILIPS
16. 2S 78 T DA4841PSf hy FS INTEGRATED CIRCUITS DATA SHEET TDA4841PS 2C bus autosync deflection controller for PC monitors Product specification 2002 Jun 24 Supersedes data of 1999 Oct 25 Philips PHILIPS Semiconductors DH l LI E Philips Semiconductors Product specification I C bus autosync deflection controller for PC monitors TDA4841PS FEATURES Concept features Full horizontal plus vertical autosync capability Extended horizontal frequency range from 15 to 130 kHz Comprehensive set of I2C bus driven geometry adjustments and functions including standby mode Very good vertical linearity Moire cancellation Start up and switch off sequence for safe operation of all power components X ray protection Power dip recognition Flexible switched mode B supply function block for feedback and feed forward converter Internally stabilized voltage reference Drive signal for focus amplifiers with combined horizontal and vertical parabola waveforms DC controllable inputs for Extremely High Tension EHT compensation SDIP32 package Synchronization Can handle all sync signals horizontal vertical composite and sync on video Output for video clamping leading trailing edge selectable by 12C bus vertical blanking and protection blanking Output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube Horiz
17. E CIRCUIT PINBSENS VSTOP BSENS discharge stop level capacitive load IBSENS 0 5mA ldch BSENS Vih BSENS restart discharge current threshold voltage for restart VBSENS gt 2 5V fault condition CBSENS min Internal reference supply voltage soft start and Vec stab minimum value of capacitor at BSENS pin 4 external supply voltage for complete stabilization of all internal references protection PSRR supply current standby supply current power supply rejection ratio of internal supply voltage STDBY 1 VPLL2 lt 1V 3 5 V lt Vcc lt 13 2 V f 1 kHz Vectblank Vec olank min 2002 Jun 24 supply voltage level for activation of continuous blanking minimum supply voltage level for function of continuous blanking supply voltage level for activation of HDRV BDRV VOUT1 VOUT2 and HUNLOCK supply voltage level for deactivation of BDRV VOUT1 VOUT2 and HUNLOCK also sets register SOFTST Voc decreasing from 12 V Voc decreasing from 12 V Vcc increasing from below typical 8 1 V Voc decreasing from above typical 8 3 V 25 8 2 2 5 3 5 4 0 7 9 8 3 8 7 7 7 8 1 8 5 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors SYMBOL PARAMETER CONDITIONS THRESHOLDS DERIVED FROM HPLL2 VOLTAGE VHPLL2 blank ul upper limit for continuous VHPLL2 bduty upper limit for va
18. EWDRV horizontal trapezium correction voltage register HTRAP 63 note 8 register HTRAP 32 note 8 VHsiZE EVVDRV horizontal size voltage register HSIZE 255 note 8 register HSIZE 0 note 8 VHEHT EWDRV li HSMOD Ri HSMOD EHT compensation on horizontal size via HSMOD pin 31 input current pin 31 input resistance lusmop 0 note 8 lusmop 120 HA note 8 VHEHT 0 02 V VHEHT 0 69 V Vref HSMOD ro HSMOD reference voltage at input roll off frequency 3 dB iHsMOD 0 li HSMOD 60 LA 15 LA RMS 2002 Jun 24 22 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors SYMBOL CONDITIONS TRACKING OF EWDRV OUTPUT SIGNAL WITH HORIZONTAL FREQUENCY PROPORTIONAL VOLTAGE PARAMETER H MULTI VPAR EVVDRV LEewprv Output for asymmetric EW corrections pin ASC horizontal frequency range for tracking parabola amplitude at EWDRV pin 11 linearity error of horizontal frequency tracking HREF 1 052 mA fy 31 45 kHz control bit FHMULT 1 note 10 HREF 2 341 mA fy 70 kHz control bit FHMULT 1 note 10 function disabled control bit FHMULT 0 note 10 OR see Figs 12 and 13 VHPARAL ASCOR vertical sawtooth voltage for EW parallelogram correction register HPARAL 0 note 8 register HPARAL 63 note 8 regis
19. Jun 24 40 Vcc asoft down sequency followed by a BEM 8 6V soft start sequence is generated internally Vcc C enters standby mode f 86V a 81V Fig 20 12C bus flow for any mode Product specification TDA4841PS Normal operation 1 I2C bus transmission chip address subaddress data s 8CH A OXH A XXH A P acknowledge was given on data I2C bus transmission chip address subaddress data s 8CH A OXH A XXH A P acknowledge was given on data Standby mode MGS276 Fig 21 Possible standby mode detection Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors Start up and shut down sequences MGM082 Voc 8 6 V continuous blanking off PLL2 soft start soft down enabled 8 3V data accepted from l2C bus video clamping pulse enabled if control bit STDBY 0 3 5 V continuous blanking pin 16 and 17 activated time a Start up sequence MGM 83 Voc 8 6 V continuous blanking pin 16 and 17 activated PLL2 soft down sequence is triggered 8 1 V no data accepted from I C bus video clamping pulse disabled 3 5V continuous blanking disappears time b Shut down sequence 1 See Fig 23a 2 See Fig 23b Fig 22 Activation of start up and shut down sequence
20. K pin 17 is floating The capacitor connected to HPLL2 pin 30 is discharged Horizontal output stage HDRV is floating B control driver stage BDRV is floating Vertical output stages VOUT1 and VOUT2 are floating CLBL provides a continuous blanking signal There are two different ways to restart the IC 1 XSEL pin 9 is open circuit or connected to ground The control bit SOFTST must be set to logic 1 via the 12C bus The IC then returns to normal operation via soft start 2 XSEL is connected to Vcc via an external resistor The supply voltage of the IC must be switched off for a certain time before the IC can be restarted again using the standard power on procedure Vertical oscillator and amplitude control This stage is designed for fast stabilization of vertical size after changes in sync frequency conditions The free running frequency fiv is determined by the resistor Ryner connected to pin 23 and the capacitor Cycap connected to pin 24 The value of Ryrer is not only optimized for noise and linearity performance in the whole vertical and EW section but also influences several internal references Therefore the value of Ryger must not be changed Capacitor Cycap should be used to select the free running frequency of the vertical oscillator in accordance with the following formula 1 fro 10 8 x Ryrer X Cycap To achieve a stabilized amplitude the free running frequency fry without adjustment should be at
21. L HUNLOCK MHB604 Fig 2 Pin configuration FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction HSYNC pin 15 is the input for horizontal synchronization signals which can be DC coupled TTL signals horizontal or composite sync and AC coupled negative going video sync signals Video syncs are clamped to 1 28 V and sliced at 1 4 V This results in a fixed absolute slicing level of 120 mV related to sync top For DC coupled TTL signals the input clamping current is limited The slicing level for TTL signals is 1 4 V The separated sync signal either video or TTL is integrated on an internal capacitor to detect and normalize the sync polarity Normalized horizontal sync pulses are used as input signals for the vertical sync integrator the PLL1 phase detector and the frequency locked loop 2002 Jun 24 Product specification TDA4841PS Vertical sync integrator Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses The integration time is dependent on the horizontal oscillator reference current at HREF pin 28 The integrator output directly triggers the vertical oscillator Vertical sync slicer and polarity correction Vertical sync signals TTL applied to VSYNC pin 14 are sliced at 1 4 V The output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity The o
22. N The TDA4841PS provides extended functions e g as a flexible B control an extensive set of geometry control facilities and a combined output for horizontal and vertical focus signals Together with the 12C bus driven Philips TDA488x video processor family a very advanced system solution is offered The TDA4841PS is a high performance and efficient solution for autosync monitors All functions are controllable by the 12C bus The TDA4841PS provides synchronization processing horizontal and vertical synchronization with full autosync capability and very short settling times after mode changes External power components are given a great deal of protection The IC generates the drive waveforms for DC coupled vertical boosters such as TDA486x and TDA835x QUICK REFERENCE DATA SYMBOL PARAMETER MIN Voc supply voltage 9 2 loc supply current _ VSIZE vertical size 6 VPOS vertical position vertical linearity S correction VLINBAL vertical linearity balance VHPIN horizontal pincushion voltage EW parabola horizontal size modulation voltage VHCORT horizontal corner correction at top of picture HPOS horizontal position _ HPINBAL EW pin unbalance ORDERING INFORMATION GE PACKAGE NUMBER NAME DESCRIPTION VERSION TDA4841PS SDIP32 plastic shrink dual in line package 32 leads 400 mil SOT232 1 2002 Jun 24 3 Product specification Philips Semiconductors TDA4841PS Il2C
23. ONDITIONS Product specification TDA4841PS fro VSMOD roll off frequency 3 dB VSMOD 760 HA 15 LA RMS ADJUSTMENT OF VERTICAL POSITION see Figs 3 to 7 vertical position referenced to 100 vertical size register VOFFS 0 register VOFFS 15 register VOFFS 8 vertical position referenced to 100 vertical size ADJUSTMENT OF VERTICAL LINEARITY see Figs 6 and register VPOS 0 register VPOS 127 register VPOS 64 27 VLIN vertical linearity S correction register VLIN 0 control bit VSC 0 note 8 register VLIN 15 control bit VSC 0 note 8 register VLIN X control bit VSC 1 note 8 symmetry error of S correction maximum VLIN ADJUSTMENT OF VERTICAL LINEARITY BALANCE see Fig 7 VLINBAL vertical linearity balance referenced to 100 vertical size register VLINBAL 0 note 8 register VLINBAL 15 note 8 register VLINBAL 8 note 8 modulation of vertical picture position by vertical frequency related to 10096 vertical size register VMOIRE 0 control bit MOD 0 register VMOIRE 63 control bit MOD 0 Vertical output st A VOUT nom p p moire cancellation off age pin VOUT1 and VOUT2 se nominal differential output current peak to peak value control bit MOD 1 e Fig 27 Alvour vourt VoUT2 nominal settings note 8 lo VOUT max VVOUT maximum output current at pins
24. PS I2C bus autosync deflection controller for PC monitors GOWSA PUE SOdA NOSAOA IZISA GOWSA PUE SOdA NOSAOA IZISA ZIS BOILJOA e00 4 40 67 LF 9 0 V eoueeq TVANITA Aueeul eona Aueeul eona 1 sJJO eOILI A 001 0102 ureb fE HH N GOWSA PQ L I 001 0 09 uollisod B91118A ZIS EIA SOdA pue NOSAOA 3ZISA ponad JEJUOZIOY JO ez lr TWENIdH eouejeq uld MI SOdA pue NOSAOA 3ZISA GOWSH pue 3ZISH SOdA NOSAOA IZISA ponad JEJUOZIOY JO g b apny due ejoqeied JO 9 01 SL wesbojey ered je UOZOH aunjoid Jo ulol loq ye U01981109 1 U109 e uozluoH TVHVdH GOWSH pue 3ZISH SOdA NOSAOA IZISA apny due ejoqeied JO 9 01 SL einjoid Jo do Je U01921109 18109 e UOZHOH GOWSH pue 3ZISH SOdA NOSAOA IZISA d d Aw 00S U01981109 wnizedell e U0ZLI0H GOWSH pue 3ZISH SOdA NOSAQA AZISA A cv 010 ponad JEJUOZHOY JO SELF uolusnould eluozluoH uollisod eluozluoH HLIM SHOVEL NOILONNA AQE OH l O A9NVH LNAWNDSISSV 411S1924 X3H X3H gavs LAYS ZIS IE UOZLOH NOILONNA Z pue sajou suonouny peyjoyu0g 9 lqEL poul p u Jjnq ul SUOISSILUSUE 40 p sn aq o SSeuppegns 1811601 eu S ZAYS e poul 1981IP ul SUOISSILUSUBJ JO p sn q o ssaippeqns 1 s 6 1 OU SI LGVS ssap
25. VOUT1 and VOUT2 allowed voltage at outputs control bit VOVSCN 1 E offset max V maximum offset error of vertical output currents nominal settings note 8 LEvimax maximum linearity error of nominal settings note 8 1 5 vertical output currents 2002 Jun 24 21 Philips Semiconductors I2C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS Product specification TDA4841PS EW drive output EW DRIVE OUTPUT STAGE PIN EVVDRV see Figs 8 to 11 Vo const EWDRV Vo EWDRV max bottom output voltage at pin EWDRV internally stabilized maximum output voltage register HPIN 0 register HTRAP 32 register HSIZE 255 control bit VSC 1 l EVVDRV TCEWDRV load current temperature coefficient of output signal VHPIN EWDRV VHCORT EWDRV horizontal pincushion voltage horizontal corner correction voltage at top of picture register HPIN 0 control bit VSC 1 note 8 register HPIN 63 control bit VSC 1 note 8 register HCORT 0 control bit VSC 0 note 8 register HCORT 63 control bit VSC 0 note 8 register HCORT X control bit VSC 1 note 8 VHCORB EWDRV horizontal corner correction voltage at bottom of picture register HCORB 0 control bit VSC 0 note 8 register HCORB 63 control bit VSC 0 note 8 register HCORB X control bit VSC 1 note 8 VHTRAP
26. also provides the correct tracking of all other related waveforms see Section Tracking of vertical adjustments this register should be used for user adjustments 3 For the VGA350 mode the register VOVSCN can activate a 17 step in vertical size 4 VSMOD pin 21 can be used for a DC controlled EHT compensation of vertical size by correcting the differential output currents at VOUT1 and VOUT2 VSMOD does not affect the EW waveforms vertical focus pin unbalance and parallelogram corrections Philips Semiconductors I2C bus autosync deflection controller for PC monitors Adjustment of vertical position vertical linearity and vertical linearity balance Register VOFFS provides a DC shift at the sawtooth output VOUT1 and VOUT2 pins 13 and 12 without affecting any other output waveform This adjustment is meant for factory alignments Register VPOS provides a DC shift at the sawtooth output VOUT1 and VOUT2 with correct tracking of all other related waveforms see Section Tracking of vertical adjustments This register should be used for user adjustments Due to the tracking the whole picture moves vertically while maintaining the correct geometry Register VLIN is used to adjust the amount of vertical S correction in the output signal This function can be switched off by control bit VSC Register VLINBAL is used to correct the unbalance of vertical S correction in the output signal Tracking of vertical adjust
27. anges will be communicated according to the Customer Product Process Change Notification CPCN procedure SNW SQ 650A 1 Please consult the most recently issued data sheet before initiating or completing a design 2 The product status of the device s described in this data sheet may have changed since this data sheet was published The latest information is available on the Internet at URL http www semiconductors philips com 2002 Jun 24 Philips Semiconductors I2C bus autosync deflection controller for PC monitors DEFINITIONS Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable f
28. bus autosync deflection controller for PC monitors BLOCK DIAGRAM NOLLVOTTddV z IOH1NOO 4 LLNOA eLNOA 098HW Jovis ind no WLNOZIHOH el e TOXLNOD P WOILYSA ANY WLNOZIHOH snoos NOILO3H409 M3 OIHLANNASY ind no AVHX 13SX n s uoneordde pue wesbeip yoojg p g14H duel LYVLS 1408 ANY SONVIVENN Nid NVH OTAT VVd 211d NOLLOZLOHd AVEH X Sdit8rval NOILISOd YOLVTIIDSO WLNOZIHOH YOLOSLAG AONSNDAYS H019313G AONACIONIOD SH31S1934 snas ozl JHVLS 140S ANY NOILO3LOHd TV INOZ HOH 9z pue gz s 1 s 2 Bue Aouenbal ull jo uone noj eo uon9es s Bue1 HJ jo uolle noje5 v 404 1 NOIL93HH09 AL HVTOd ANY LNdNI ONAS O H NV Alddfis 4ONVTV8 AL HVANIT TVOILH3A AL HVANIT TVOILH3A 1Nd1NO WOILLYAA 3ZIS TV NOZ HOH WNIZ3dvHL WLNOZIHOH HANMHO 1WLNOZIHOH NOIHSNONId TWLNOZIHOH 1Nd1NO M3 ZIS EJUOZHIOU BIA uonesu dulo2 IH3 3ZIS TVOILH3A 3ZIS IWLNOZIHOH NOLLVSN4d1NO LH3 ZIS EO H A BIA uolesu duio5 Hy NOSAOA IZIS TVOLLHBA NOILISOd TVOILH3A 99 ANY YOLVTIIOSO IVOI1H3A HO1VH931NI OINAS WOILYAA 1Nd1NO MOOINNH YINV Ig TWOILYSA NV SNIdNV19 OJIA NOILOSYHOO ALIWV10d ANY LAdNI ONAS WOILYSA se ANOS 39N343434 111 MOOINNH Ino WT Suruelq Buidwejo I8A9 111 2002 Jun 24 Philips Semiconduct
29. currents VOUT1 pin 13 and VOUT2 pin 12 EW drive waveform at EVVDRV pin 11 ____ 4 0 V_ automatic trigger level 3 8 V synchronized trigger level 2 DC shift 3 6 V maximum ae o G 7 0 V maximum low level 1 2 V fixed Fig 14 Pulse diagram for vertical part MGMO75 2002 Jun 24 31 Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors TDA4841PS horizontal oscillator sawtooth at HCAP pin 29 horizontal sync pulse PLL1 control current at HPLL1 pin 26 video clamping pulse at CLBL pin 16 vertical blanking level triggered on trailing edge of horizontal sync line flyback pulse at HFLB pin 1 PLL2 control current T LL pi at HP pin 30 PLL2 control range gt line drive pulse at HDRV pin 8 lt 45 to 52 of line period horizontal focus parabola at FOCUS pin 32 MGS275 Fig 15 Pulse diagram for horizontal part 2002 Jun 24 32 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors MGMO77 relative tHDRV OFF tH 524 454 15 30 110 130 fy kHz Fig 16 Relative torr time of HDRV as a function of horizontal frequency composite sync TTL on ml F R n o at HSYNC pin 15 internal integration of co
30. e of resistor at VREF pin 23 may not be changed 2002 Jun 24 26 Philips Semiconductors Product specification Fe I C bus autosync deflection controller for TDA4841PS PC monitors 8 All vertical and EW adjustments are specified at nominal vertical settings unless otherwise specified which means a VSIZE 100 register VSIZE 127 VGAIN 63 and control bit VOVSCN 0 VSMOD 0 no EHT compensation VPOS centred register VPOS 64 VLIN 0 register VLIN X and control bit VSC 1 VLINBAL 0 register VLINBAL 8 f FHMULT 0 g HPARAL 0 register HPARAL 32 h HPINBAL 0 register HPINBAL 32 i Vertical oscillator synchronized 9 The output signal at EVVDRV pin 11 may consist of horizontal pincushion corner correction DC shift trapezium correction If the VOVSCN control bit is set and the VPOS adjustment is set to an extreme value the tip of the parabola may be clipped at the upper limit of the EWDRV output voltage range The waveform of corner correction will clip if the vertical sawtooth adjustment exceeds 110 of the nominal setting 10 If fu tracking is enabled the amplitude of the complete EWDRV output signal horizontal pincushion corner correction DC shift trapezium will be changed proportional to Ihrer The EWDRV low level of 1 2 V remains fixed 11 First pole of transconductance amplifier is 5 MHz without external capacitor will become the second pole if the OTA operates as an
31. figuration allows easy applications for different B control concepts See also Application Note AN96052 B converter Topologies for Horizontal Deflection and EHT with TDA4855 58 GENERAL DESCRIPTION The non inverting input of the OTA is connected internally to a high precision reference voltage The inverting input is connected to BIN pin 5 An internal clamping circuit limits the maximum positive output voltage of the OTA The output itself is connected to BOP pin 3 and to the inverting input of the voltage comparator The non inverting input of the voltage comparator can be accessed via BSENS pin 4 B drive pulses are generated by an internal flip flop and fed to BDRV pin 6 via an open collector output stage This flip flop will be set at the rising edge of the signal at HDRV pin 8 The falling edge of the output signal at BDRV has a defined delay of tagprv to the rising edge of the HDRV pulse When the voltage at BSENS exceeds the voltage at BOP the voltage comparator output resets the flip flop and therefore the open collector stage at BDRV is floating again Philips Semiconductors I2C bus autosync deflection controller for PC monitors An internal discharge circuit allows a well defined discharge of capacitors at BSENS BDRV is active ata LOW level output voltage see Figs 25 and 26 thus it requires an external inverting driver stage The B function block can be used for B deflection modulators in
32. he voltage at BSENS reaches the threshold voltage VRESTART BSENS the discharge circuit will be disabled automatically and the flip flop will be set immediately This behaviour allows a definition of the maximum duty cycle of the B control drive pulse by the relationship of charge current to discharge current 2002 Jun 24 12 Product specification TDA4841PS Supply voltage stabilizer references start up procedures and protection functions The TDA4841PS provides an internal supply voltage stabilizer for excellent stabilization of all internal references An internal gap reference especially designed for low noise is the reference for the internal horizontal and vertical supply voltages All internal reference currents and drive current for the vertical output stage are derived from this voltage via external resistors If either the supply voltage is below 8 3 V or no data from the I2C bus has been received after power up the internal soft start and protection functions do not allow any of those outputs HDRV BDRV VOUT1 VOUT2 and HUNLOCK see Fig 22 to be active For supply voltages below 8 3 V the internal 1 C bus will not generate an acknowledge and the IC is in standby mode This is because the internal protection circuit has generated a reset signal for the soft start register SOFTST Above 8 3 V data is accepted and all registers can be loaded If the SOFTST register has received a set from the I2C bus the interna
33. he Absolute Maximum Rating System IEC 60134 all voltages measured with respect to ground SYMBOL PARAMETER supply voltage input voltage pin BIN pins HSYNC VSYNC VREF HREF VSMOD and HSMOD pins SDA SCL and XRAY output voltage pins VOUT2 VOUT1 and HUNLOCK pins BDRV and HDRV input output voltages at pins BOP and BSENS HDRV horizontal driver output current li HFLB horizontal flyback input current lo CLBL video clamping pulse vertical blanking output current BOP B control OTA output current BDRV B control driver output current EWDRV EW driver output current Vo EvvpRv maximum EW driver output voltage focus driver output current ambient temperature junction temperature storage temperature C note 1 150 150 V Notes 1 Machine model 200 pF 0 75 uH 10 Q 2 Human body model 100 pF 7 5 uH 1500 Q THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rihii a thermal resistance from junction to ambient in free air 55 K W QUALITY SPECIFICATION In accordance with URF 4 2 59 601 EMC emission immunity test in accordance with DIS 1000 4 6 IEC 801 6 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Vemc emission test note 1 1 5 mv immunity test note 1 2 0 V Note 1 Tests are performed with application reference board Tests with other boards will have different results 2002 Jun 24 14 Phil
34. he required effect on the screen pin ASCOR must now be fed to the DC amplifier which controls the DC shift of the horizontal deflection This option is useful for applications which already use a DC shift transformer If the tube does not need HPINBAL and HPARAL then pin ASCOR can be used for other purposes i e fora simple dynamic convergence 2002 Jun 24 11 Product specification TDA4841PS Dynamic focus section FOCUS pin 32 This section generates a complete drive signal for dynamic focus applications The amplitude of the horizontal parabola is internally stabilized thus it is independent of the horizontal frequency The amplitude can be adjusted via register HFOCUS Changing horizontal size may require a correction of HFOCUS To compensate for the delay in external focus amplifiers a pre correction for the phase of the horizontal parabola has been implemented see Fig 28 The amount of this pre correction can be adjusted via register HFOCAD The amplitude of the vertical parabola is independent of frequency and tracks with all vertical adjustments The amplitude can be adjusted via register VFOCUS FOCUS pin 32 is designed as a voltage output for the superimposed vertical and horizontal parabolas B control function block The B control function block of the TDA4841PS consists of an Operational Transconductance Amplifier OTA a voltage comparator a flip flop and a discharge circuit see Fig 25 This con
35. horizontal pincushion amplitude corner and trapezium correction track with the horizontal picture size which is adjusted via register HSIZE and the analog modulation input HSMOD If the DC component in the EVVDRV output signal is increased via HSIZE or HsMOD the pincushion corner and trapezium component of the EVVDRV output will be reduced by a factor of Vusize Vusize Vusir 1 ws 14 4V The value 14 4 V is a virtual voltage for calculation only The output pin can not reach this value but the gain and DC bias of the external application should be such that the horizontal deflection is reduced to zero when EWDRV would reach 14 4 V HSMOD pin 31 can be used for a DC controlled EHT compensation by correcting horizontal size horizontal pincushion corner and trapezium The control range at this pin tracks with the actual value of HSIZE For an increasing DC component Vusi ze in the EWDRV output signal the DC component VHeHr caused by lysmop will be V Hsize reduced by a factor of 1 144 V as shown in the equation above The whole EWDRV voltage is calculated as follows Veworvo 1 2 V Vhsize VHeHr X f HSIZE Vipin Vicor VHrnaP X g HS ZE HSMOD x h IHngr where isMOD Ver 120 HA x 0 69 Vusize f HSIZE 1 755 Vusize Vusize Visri1 144 E g HSIZE HSMOD 1 T4 4 V HREF hilal HREF at f 70 kHz Philips Semiconductors I2C bus autosync deflection cont
36. horizontal sync with a fixed point on the oscillator sawtooth voltage The PLL1 loop filter is connected to HPLL1 pin 26 See also Section Horizontal position adjustment and corrections Horizontal position adjustment and corrections Via register HPOS the I C bus allows a linear adjustment of the relative phase between the horizontal sync and oscillator sawtooth in PLL1 loop Once adjusted the relative phase remains constant over the whole frequency range Via registers HPARAL and HPINBAL correction of pin unbalance and parallelogram is achieved by modulating the phase between oscillator sawtooth and horizontal flyback in loop PLL2 If those asymmetric EW corrections are performed in the deflection stage both registers can be disconnected from horizontal phase via control bit ACD This does not change the output at pin ASCOR Horizontal moire cancellation To achieve a cancellation of horizontal moire also known as video moire the horizontal frequency is divided by two for a modulation of the horizontal phase via PLL2 The amplitude is controlled by register HMOIRE To avoid a visible structure on screen the polarity changes with half the vertical frequency Control bit MOD disables the moire cancellation function PLL2 phase detector The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB pin 1 with the oscillator sawtooth voltage The control currents are indepe
37. ips Semiconductors Product specification I17 C bus autosync deflection controller for TDA4841P PC monitors CHARACTERISTICS Voc 12 V Tamb 25 C peripheral components in accordance with Fig 1 unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Horizontal sync separator INPUT CHARACTERISTICS FOR DC COUPLED TTL SIGNALS PIN HSYNC Vi HSYNC sync input signal voltage 1 7 z VHsYNCisi slicing voltage level 1 2 1 4 1 6 H HSYNC rise time of sync pulse HHSYNC fall time of sync pulse 10 tw HSYNC min minimum width of sync pulse li HSYNC input current m 0 8V 200 F INPUT CHARACTERISTICS FOR AC COUPLED VIDEO SIGNALS aa ON VIDEO NEGATIVE SYNC POLARITY sync amplitude of video input Resource 50 O signal voltage VHSYNC AC s slicing voltage level Resource 50 2 measured from top sync Velamp HSYNC top sync clamping voltage level Rgource 50 O Ich HSYNC charge current for coupling Vi HSYNC gt Velamp HSYNC capacitor tw HSYNC min minimum width of sync pulse Rsource max maximum source resistance duty cycle 7 Ri diff HSYNC differential input resistance during sync Automatic polarity correction for horizontal sync horizontal sync pulse vvidth related to tu ta HPOL delay time for changing polarity Vertical sync integrator int V integration time for generation fy 15 625 kHz of a vertical trigger p
38. is concept it is not allowed to load HPLL1 The frequency dependent voltage at this pin is fed internally to HBUF pin 27 via a sample and hold and buffer stage The sample and hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage An external resistor connected between pins HBUF and HREF defines the frequency range Out of lock indication pin HUNLOCK Pin HUNLOCK is floating during search mode or if a protection condition is true All this can be detected by the microcontroller if a pull up resistor is connected to its own supply voltage For an additional fast vertical blanking at grid 1 of the picture tube a 1 V signal referenced to ground is available at this output Also the continuous protection blanking see Section Video clamping vertical blanking generator is available at this pin Via I C bus control the control bit BLKDIS can switch off horizontal unlock blanking while vertical blanking is maintained 2002 Jun 24 Product specification TDA4841PS Horizontal oscillator The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP pin 29 For optimum jitter performance the value of 10 nF must not be changed The minimum oscillator frequency is determined by a resistor connected between pin HREF and ground A resistor connected between pins HREF and HBUF defines the frequency range The reference current at pin
39. izontal unlock blanking can be switched off by control bit BLKDIS while vertical blanking is maintained Philips Semiconductors I2C bus autosync deflection controller for PC monitors Frequency locked loop The frequency locked loop can lock the horizontal oscillator over a wide frequency range This is achieved by a combined search and PLL operation The frequency range is preset by two external resistors and the A i f nax recommended maximum ratio is m 6 5 min This can for instance be a range from 15 625 to 90 kHz with all tolerances included Without a horizontal sync signal the oscillator will be free running at fmin Any change of sync conditions is detected by the internal coincidence detector A deviation of more than 4 between horizontal sync and oscillator frequency will switch the horizontal section into search mode This means that PLL1 control currents are switched off immediately The internal frequency detector then starts tuning the oscillator Very small DC currents at HPLL1 pin 26 are used to perform this tuning with a well defined change rate When coincidence between horizontal sync and oscillator frequency is detected the search mode is first replaced by a soft lock mode which lasts for the first part of the next vertical period The soft lock mode is then replaced by a normal PLL operation This operation ensures a smooth tuning and avoids fast changes of horizontal frequency during catching In th
40. l soft start procedure is released which activates all outputs which are mentioned above If during normal operation the supply voltage has dropped below 8 1 V the protection mode is activated and HUNLOCK pin 17 changes to the protection status and is floating This can be detected by the microprocessor This protection mode has been implemented in order to protect the deflection stages and the picture tube during start up shut down and fault conditions This protection mode can be activated as shown in Table 3 Philips Semiconductors I2C bus autosync deflection controller for PC monitors Table 3 Activation of protection mode ACTIVATION RESET Low supply voltage at pin 10 increase supply voltage reload registers soft start via I2C bus Power dip below 8 1 V reload registers soft start via I C bus or via supply voltage X ray protection XRAY pin 2 triggered HPLL2 pin 30 externally pulled to ground reload registers soft start via I2C bus release pin 30 When the protection mode is active several pins of the TDA4841PS are forced into a defined state HDRV horizontal driver output is floating BDRV B control driver output is floating Product specification TDA4841PS Power dip recognition In standby mode the I C bus will only answer with an acknowledge when data is sent to the control register 1AH This register contains the standby and soft start control bit
41. least 10 lower than the minimum trigger frequency The contributions shown in Table 2 can be assumed 2002 Jun 24 Product specification TDA4841PS Table 2 Calculation of ftv total spread Contributing elements Minimum frequency offset between fry and 10 lowest trigger frequency Spread of IC 3 Spread of Ryrer 1 Spread of CvcAP 5 Total 19 Result for 50 to 160 Hz application _ 50 Hz r 42Hz The AGC of the vertical oscillator can be disabled by setting control bit AGCDIS via the I C bus A precise external current has to be iniected into VCAP pin 24 to obtain the correct vertical size This special application mode can be used when the vertical sync pulses are serrated shifted this condition is found in some display modes e g when using a 100 Hz upconverter for video signals Application hint VAGC pin 22 has a high input impedance during scan Therefore the pin must not be loaded externally otherwise non linearities in the vertical output currents may occur due to the changing charge current during scan Adjustment of vertical size VGA overscan and EHT compensation There are four different ways to adjust the amplitude of the differential output currents at VOUT1 and VOUT2 1 Register VGAIN changes the vertical size without affecting any other output signal of the IC this adjustment is meant for factory alignments 2 Register VSIZE changes not only the vertical size but
42. many different ways Two popular application combinations are e Boost converter in feedback mode see Fig 25 In this application the OTA is used as an error amplifier with a limited output voltage range The flip flop will be set at the rising edge of the signal at HDRV A reset will be generated when the voltage at BSENS taken from the current sense resistor exceeds the voltage at BOP If no reset is generated within a line period the rising edge of the next HDRV pulse forces the flip flop to reset The flip flop is set immediately after the voltage at BSENS has dropped below the threshold voltage VRESTART BSENS Buck converter in feed forward mode see Fig 26 This application uses an external RC combination at BSENS to provide a pulse width which is independent from the horizontal frequency The capacitor is charged via an external resistor and discharged by the internal discharge circuit For normal operation the discharge circuit is activated when the flip flop is reset by the internal voltage comparator The capacitor will now be discharged with a constant current until the internally controlled stop level Vsrop Bsens is reached This level will be maintained until the rising edge of the next HDRV pulse sets the flip flop again and disables the discharge circuit If no reset is generated within a line period the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip flop When t
43. ments The adjustments via registers VSIZE VOVSCN and VPOS also affect the waveforms of horizontal pincushion vertical linearity S correction vertical linearity balance focus parabola pin unbalance and parallelogram correction The result of this interaction is that no readjustment of these parameters is necessary after an user adjustment of vertical picture size and vertical picture position Adjustment of vertical moire cancellation To achieve a cancellation of vertical moire also known as scan moire the vertical picture position can be modulated by half the vertical frequency The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD Horizontal pincushion including horizontal size corner correction and trapezium correction EVVDRV pin 11 provides a complete EW drive waveform The components horizontal pincushion horizontal size corner correction and trapezium correction are controlled by the registers HPIN HSIZE HCORT HCORB and HTRAP The corner correction can be adjusted separately for the top HCORT and bottom HCORB part of the picture The pincushion EW parabola amplitude corner and trapezium correction track with vertical picture size VSIZE and also with the adjustment for vertical picture 2002 Jun 24 Product specification TDA4841PS position VPOS The corner correction does not track with horizontal pincushion HPIN Further the
44. mping pulse triggered on leading edge of horizontal sync control bit CLAMP 1 measured at V g 3 V Vblank CLBL top voltage level of vertical blanking pulse notes 1 and 2 blank CLBL Vscan CLBL width of vertical blanking pulse at pins CLBL and HUNLOCK temperature coefficient of Vblank CLBL output voltage during vertical scan control bit VBLK 0 control bit VBLK 1 TCscan sink CLBL temperature coefficient of Vscan CLBL internal sink current IL CLBL 2002 Jun 24 external load current 16 Product specification TDA4841PS Philips Semiconductors Product specification I C bus autosync deflection controller for PC monitors DAL SYMBOL PARAMETER CONDITIONS Horizontal oscillator pins HCAP and HREF fr H free running frequency without Rypur c PLL1 action for testing only RuneF 2 4 kO Cucap 10 nF note 3 spread of free running frequency excluding spread of external components temperature coefficient of free running frequency maximum oscillator frequency VHREF voltage at input for reference current Unlock blanking detection pin HUNLOCK Vscan HUNLOCK low level voltage of HUNLOCK saturation voltage in case of locked PLL1 internal sink current 1mA Vblank HUNLOCK blanking level of HUNLOCK TCblank temperature coefficient of Vblank HUNLOCK TCsink temperature coefficient of I sink HUNLOCK
45. mposite sync internal vertical LU trigger pulse PLL1 control voltage JN at HPLL1 pin 26 clamping and blanking I pulses at CLBL pin 16 MGC947 a Reduced influence of vertical sync on horizontal phase composite sync TTL JL 4S Le _ at HSYNC pin 15 clamping and blanking pulses at CLBL pin 16 MBG596 b Generation of video clamping pulses during vertical sync with serration pulses Fig 17 Pulse diagrams for composite sync applications 2002 Jun 24 33 Philips Semiconductors I17 C bus autosync deflection controller for PC monitors 12C BUS PROTOCOL Data format The format of data for the 12C bus is given in Table 4 Table 4 Data format SU SLAVE ADDRESS AG SUBADDRESSU Product specification TDA4841PS A DATA AG Notes 1 S START condition 2 SLAVE ADDRESS MAD 1000 1100 3 and 8 0 V for shut down procedure 4 SUBADDRESS SAD 5 performed 6 P STOP condition It should be noted that clock pulses according to the 400 kHz specification are accepted for 3 3 V and 5 V applications reference level 1 8 V Default register values after power up are random All registers have to be preset via software before the soft start is enabled It should be noted that if register contents are changed during the vertical scan this might result in a visible interference on the screen The cause for thi
46. ndent of the horizontal frequency The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV pin 8 output pulse An external modulation of the PLL2 phase is not allowed because this would disturb the pre correction of the H focus parabola 2002 Jun 24 Product specification TDA4841PS Soft start and standby If HPLL2 is pulled to ground either by an external DC current or by resetting the register SOFTST horizontal output pulses and B control driver pulses are inhibited This means that HDRV pin 8 BDRV pin 6 VOUT 1 pin 13 and VOUT2 pin 12 are floating in this state PLL2 and the frequency locked loop are disabled CLBL pin 16 provides a continuous blanking signal and HUNLOCK pin 17 is floating This option can be used for soft start protection and power down modes When the HPLL2 pin is released again an automatic soft start sequence on the horizontal drive as well as on the B drive output will be performed see Fig 22 A soft start can only be performed if the supply voltage for the IC is 8 6 V at minimum The soft start timing is determined by the filter capacitor at HPLL2 pin 30 which is charged with an constant current during soft start If the voltage at pin 30 HPLL2 reaches 1 1 V the vertical output currents are enabled At 1 8 V the horizontal driver stage generates very small output pulses The width of these pulses increa
47. ontal section 2C bus controllable wide range linear picture position pin unbalance and parallelogram correction via horizontal phase Frequency locked loop for smooth catching of horizontal frequency Simple frequency preset of fmin and fmax by external resistors Low jitter Soft start for horizontal and B control drive signals 2002 Jun 24 BUS i Vertical section l C bus controllable vertical picture size picture position linearity S correction and linearity balance Output for 1 C bus controllable vertical sawtooth and parabola for pin unbalance and parallelogram Vertical picture size independent of frequency Differential current outputs for DC coupling to vertical booster 50 to 160 Hz vertical autosync range East West EW section 2C bus controllable output for horizontal pincushion horizontal size corner and trapezium correction Optional tracking of EW drive waveform with line frequency selectable by 12C bus Focus section 2C bus controllable output for horizontal and vertical parabolas Vertical parabola is independent of frequency and tracks with vertical adjustments Horizontal parabola independent of frequency Adjustable pre correction of delay in focus output stage Philips Semiconductors Product specification 2 n flection controller for I C bus autosy c deflection controller fo TDA4841PS PC monitors GENERAL DESCRIPTIO
48. or the specified use without further testing or modification PURCHASE OF PHILIPS I2C COMPONENTS Product specification TDA4841PS DISCLAIMERS Life support applications These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Purchase of Philips I2C components conveys a license under the Philips I C patent to use the components in the 12C system provided the system conforms to the 12C specification defined by Philips This specification can be ordered
49. ors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors PINNING SYMBOL PIN DESCRIPTION HFLB 1 horizontal flyback input X ray protection input BSENS 4 1 B control comparator input B control driver output horizontal driver output select input for X ray reset 1 supply voltage 11 EW waveform output 12 vertical output 2 ascending sawtooth 13 vertical output 1 descending sawtooth 14 vertical synchronization input 15 horizontal composite synchronization input L 17 horizontal synchronization unlock protection vertical blanking output SCL 19 SDA 19 12C bus data input 2 input for EHT compensation via vertical size external capacitor for vertical amplitude control HUNLOCK external resistor for vertical oscillator external capacitor for vertical oscillator signal ground external filter for PLL1 reference current input for horizontal oscillator external filter for PLL2 soft start input for EHT compensation via horizontal size FOCUS 32 output for horizontal and vertical focus 2002 Jun 24 5 Philips Semiconductors Il2C bus autosync deflection controller for PC monitors HFLB XRAY FOCUS HSMOD BOP HPLL2 BSENS HCAP BIN BDRV 6 PGND HDRV 8 TDA4841PS XSEL 9 Voc 10 EWDRV HREF HBUF HPLL1 SGND VCAP VREF VAGC VOUT2 VSMOD VOUT1 ASCOR VSYNC SDA HSYNC SCL CLB
50. pegns 19 S1691 ey JO SIN 24 Aq pauyap SI pue apow paJayjng 10 421p u p llluusue1 q ueo erep snq O i suonoun p lonuo snq 2 l JO 1S T 36 2002 Jun 24 Product specification Philips Semiconductors TDA4841PS Il2C bus autosync deflection controller for PC monitors paaJSUBd aq 1snuu suoln un uloq 40 s nieA 1Iq aU passauippe SI 19481691 au JI uonounj 1 uloue Aq p ldnooo si yq SI Z 2189 1 U0p X S9 0N SU 0G 010061 AGED 38 30 GYOO zH STOO H u01991109 91d SNDO e uozluoH snoo eluozuoH SOdA pue NOSAOA 3ZISA A FL010 ponad JeJUOZLOY 10 462070 COW SNOOSAA AYIOWH snoo EOMH AN uon sod pluozuou BIA UOREI UB AON opnyjdwe jeolien 10 968070 010 GOW 3dIONWA uollisod 2911184 BIA UOREI UB SION HLIM SHOVEL NOILONNA LNAWNDSISSV YALSIDSY X3H X3H gavs LAYS 3IWVN NOILONNA 37 2002 Jun 24 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors Power down mode XXXX XXXX no acknowledge is given by IC all register contents are random v Voc gt 8 3 V Standby mode XXXX XX01 STDBY 1 SOFTST 0 all other register contents are random Y LES A io A Y Protection mode XXXX XX00 STDBY 0 SOFTST 0 all other register contents are random gt E sos
51. register VFOCUS 15 note 8 lo Focus 0 lo Focus 0 lo FOCUS max CL FOCUS max maximum output current maximum capacitive load B control section see Figs 25 and 26 TRANSCONDUCTANCE AMPLIFIER PINS BIN AND BOP Vi BIN input voltage li BIN max Vref int maximum input current reference voltage at internal non inverting input of OTA Vo BOP min Vo BOP max minimum output voltage maximum output voltage lo BOP lt 1 mA lo BOP max Qm OTA maximum output current transconductance of OTA note 11 Gv oi CBOP min open loop voltage gain minimum value of capacitor at BOP pin 3 note 12 2002 Jun 24 24 Philips Semiconductors Product specification I C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS TDA4841PS VOLTAGE COMPARATOR PIN BSENS Vi BSENS Vi BoP voltage range of positive comparator input voltage range of negative comparator input L BSENS max maximum leakage current OPEN COLLECTOR OUTPUT STAGE PIN BDRV lo BDRV max maximum output current discharge disabled note 13 ILO BDRV output leakage current Veprav 16 V Vsat BDRV toff BDRV min saturation voltage minimum off time lo BDRV lt 20mA td BDRV HDRV delay between BDRV pulse and HDRV pulse measured at VHorv Vepr_v 3 V BSENS DISCHARG
52. riation of blanking BDRV duty cycle VHPLL2 bduty lower limit for variation of BDRV duty cycle VHPLL2 hduty upper limit for variation of VHPLL2 hduty lower limit for variation of HDRV HDRV duty cycle duty cycle VHPLL2 stby lower limit for VOUT1 and VOUT2 to be active via I C bus soft start VHPLL2 stby ul upper limit for standby voltage VHPLL2 stby I lower limit for VOUT1 and VOUT2 to be active via external DC current Notes 1 For duration of vertical blanking pulse see Vertical oscillator oscillator frequency in application without adjustment of free running frequency fu Continuous blanking at CLBL pin 16 will be activated if one of the following conditions is true a No horizontal flyback pulses at HFLB pin 1 within a line b X ray protection is triggered c Voltage at HPLL2 pin 30 is low during soft start d Supply voltage at Vcc pin 10 is low e PLL1 unlocked while frequency locked loop is in search mode Oscillator frequency is fmin when no sync input signal is present no continuous blanking at pins 16 and 17 Loading of HPLL1 pin 26 is not allowed Voltage at HPLL1 pin 26 is fed to HBUF pin 27 via a buffer Disturbances caused by horizontal sync are removed by an internal sample and hold circuit All vertical and EW adjustments according note 8 but VSIZE 80 register VSIZE 63 VGAIN 63 and control bit VOVSCN 0 Valu
53. rigger pulse and start of ramp at VCAP pin 24 width of vertical blanking pulse amplitude control current external capacitor at VAGC pin 22 control bit VBLK 0 control bit VBLK 1 control bit AGCDIS 0 120 control bit AGCDIS 1 Differential vertical current outputs ADJUSTMENT OF VERTICAL SIZE INCLUDING VGA AND EHT COMPENSATION see Figs 3 to 7 vertical size without VGA overscan referenced to nominal vertical size register VGAIN 0 register VSIZE 127 bit VOVSCN 0 note 8 register VGAIN 63 register VSIZE 127 bit VOVSCN 0 note 8 VSIZEvGA vertical size without VGA overscan referenced to nominal vertical size vertical size with VGA overscan referenced to nominal vertical size EHT compensation on vertical size via VSMOD pin 21 referenced to 100 vertical size register VSIZE 0 register VGAIN 63 bit VOVSCN 0 note 8 register VSIZE 127 register VGAIN 63 bit VOVSCN 0 note 8 register VSIZE 0 register VGAIN 63 bit VOVSCN 1 note 8 register VSIZE 127 register VGAIN 63 bit VOVSCN 1 note 8 l vsmon 0 livsmop 120 pA livsmoD input current pin 21 VSMOD 0 VSMOD 7 RiwvsMoD Vref VSMOD input resistance reference voltage at input 2002 Jun 24 20 Philips Semiconductors I C bus autosync deflection controller for PC monitors SYMBOL PARAMETER C
54. rmer A D2 ImosFET EHT adjustment R1 b VBIN R3 D1 t MGM081 Vesens TR2 power down c1 CBSENS J gt 2 nF CBoP gt 10 nF 1 The recommended value for R4 is 1 KQ a Forvvard mode application D horizontal fiyback pulse viav T LT Le J Ll f Ww s gt lt d BDRV lott discharge time of CBSENS VBOP VBOP i E 65 A VasENs Z Fe VRESTART BSENS VSTOP BSENS IMOSFET 0 1 MBG602 Veprav b VVaveforms for normal operation c VVaveforms for fault condition Fig 26 Application and timing for feed forward mode 2002 Jun 24 45 Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors Vertical linearity error VOUT MBG551 0 1 lvout vouri Ivourz 2 h lvour at Vvcap 1 9 V 415 3 l2 lvour at Vvcap 2 6 V 4 4 l3 VouT at VvcAP 3 3 V li l 2 Which means l tsa 1 12 12 15 Vertical linearity error 1 max r or 0 0 Fig 27 Definition of vertical linearity error H focus pre correction MGS282 tprecor 450 ns 1 Line flyback pulse at HFLB pin 1 tprecor 300 ns 2 Horizontal focus parabola at FOCUS pin 32 Fig 28 Definition of H focus pre correction 2002 Jun 24
55. rnates with T vertical frequency register HMOIRE 0 control bit MOD 0 register HMOIRE 63 control bit MOD 0 moire cancellation off PLL2 phase detector pins HFLB and HPLL2 PLL2 control advance of horizontal drive with respect to middle of horizontal flyback control bit MOD 1 maximum advance register HPINBAL 32 register HPARAL 32 minimum advance register HPINBAL 32 register HPARAL 32 letri PLL2 PPLL2 PLL2 control current relative sensitivity of PLL2 phase shift related to horizontal period VPROT HPLL2 max maximum voltage for PLL2 protection mode soft start lch PLL2 ldch PLL2 charge current for external capacitor during soft start discharge current for external capacitor during soft down Vhpiio lt 3 7 V Vhpiio lt 3 7 V 2002 Jun 24 18 Philips Semiconductors I C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS Product specification TDA4841PS HORIZONTAL FLYBACK INPUT PIN HFLB V pos HFLB Vneg HFLB positive clamping level negative clamping level li HFLB 5 mA l HFLB 1 MA bos HFLB Ineg HFLB negative clamping current VsI HFLB positive clamping current slicing level Output stage for line driver pulses pin HDRV OPEN COLLECTOR OUTPUT STAGE Vsat HDRV ILO HDRV saturation voltage output leakage cu
56. rol bit SOFTST 1 e Before enabling the soft start sequence a delay of minimum 80 ms is necessary to obtain correct function of the horizontal drive e HDRV duty cycle increases e BDRV duty cycle increases e VOUT1 and VOUT2 are enabled e PLL1 and PLL2 are enabled IC in full operation e Pin HUNLOCK is at LOW level when PLL1 is locked e Any change of the register content will result in an immediate change of the output behaviour e Setting control bit SOFTST 0 is the only way except power down via pin Vcc to leave the operating mode Soft down sequence e See L4 of Fig 19 for starting the soft down sequence Philips Semiconductors Product specification OR I C bus autosync deflection controller for TDA4841PS PC monitors Protection and standby mode Soft down sequence e Start the sequence by setting control bit SOFTST 0 e BDRV duty cycle decreases Leon a an oon FP e HDRV duty cycle decreases Soft down sequence XXXX XX00 Protection mode STDBY 0 SOFTST 0 e Pins HDRV and BDRV are floating Y e Pins VOUT1 and VOUT2 are floating Protection mode XXXX XX00 e Continuous blanking on pin CLBL is active STDBY 0 i i i AE rer 0 e Pin HUNLOCK is floating registers are set e PLL1 and PLL2 are disabled e Register contents are kept in internal memory Protection mode can be left by 3 ways 1 Entering standby mode by setting control bit SOFTST 0 and bit
57. roller for PC monitors Via control bit FHMULT two different modes of operation can be chosen for the EW output waveform 1 Mode 1 Horizontal size is controlled via register HSIZE and causes a DC shift at the EWDRV output The complete waveform is also multiplied internally by a signal proportional to the line frequency which is detected via the current at HREF pin 28 This mode is to be used for driving EW diode modulator stages which require a voltage proportional to the line frequency Mode 2 The EW drive waveform does not track with the line frequency This mode is to be used for driving EW modulators which require a voltage independent of the line frequency Output stage for asymmetric correction waveforms ASCOR pin 20 This output is designed as a voltage output for superimposed waveforms of vertical parabola and sawtooth Via the I C bus the registers HPARAL and HPINBAL allow to change amplitude and polarity of both signals Application hint The TDA4841PS offers two possibilities to control HPINBAL and HPARAL 1 Control bit ACD 1 The two registers now control the horizontal phase by means of internal modulation of the PLL2 horizontal phase control The ASCOR output pin 20 can be left unused but it will always provide an output signal because the ASCOR output stage is not influenced by the control bit ACD Control bit ACD 0 The internal modulation via PLL2 is disconnected In order to obtain t
58. rrent lo HDRV 20 mA lo HDRV 60 mA Vupav 16 V AUTOMATIC VARIATION OF DUTY CYCLE HDRV OFF H X ray protection VxRAY s relative torr time of HDRV output measured at VupRv 3 V HDRV duty cycle is modulated by the relation IHREF IVREF pin XRAY slicing voltage level for latch lo HDRV 20 mA fy 31 45 kHz see Fig 16 lo HDRV 20 mA H 58 kHz see Fig 16 lo HDRV 20 mA fy 110 kHz see Fig 16 VV XRAY min Ri XRAY minimum width of trigger pulse input resistance at XRAY pin 2 reset of X ray latch VXRAY lt 6 38 V VBE VXRAY gt 6 38 V VBE standby mode pin 9 open circuit or connected to GND RxsEL kO 5 _ kQ set control bit SOFTST via 12C bus Voc xRAY min Vcc xRAY max RxsEL minimum supply voltage for correct function of the X ray latch maximum supply voltage for reset of the X ray latch external resistor at pin 9 pin 9 connected to Vcc via RxsEL pin 9 connected to Vcc via RxsEL no reset via I C bus 2002 Jun 24 19 Philips Semiconductors I C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS Product specification TDA4841PS free running frequency vertical frequency catching range Ryner 22 kO Cvcap 100 nF constant amplitude note 7 50 Cyacc voltage at reference input for vertical oscillator delay between t
59. s interference is the abrupt change of picture geometry which takes effect at random locations within the visible picture To avoid this kind of interference at least the adjustment of some critical geometry parameters should be synchronized with the vertical flyback The TDA4841PS offers a feature to synchronize any 12C bus adjustment with the internal vertical flyback pulse For this purpose the IC offers two different modes for the handling of I C bus data e Direct mode e Buffered mode Direct mode The direct mode is selected by setting the MSB of the I2C bus register subaddress to logic 0 Any 2C bus command is executed immediately after it was received so the adjustment takes effect immediately after the end of 12C bus transmission 2002 Jun 24 34 A acknowledge generated by the slave No acknowledge is given if the supply voltage is below 8 2 V for start up DATA byte If more than 1 byte of DATA is transmitted then no auto increment of the significant subaddress is This mode should be used if many register values have to be changed subsequently i e during start up mode change etc and while there is no picture visible on the screen blanked The number of transmissions per V period is not limited Buffered mode The buffered mode is selected by setting the MSB of the I2C bus register subaddress to logic 1 This mode is designed to avoid visible interferences on the screen during the 1 C bus adjustments
60. s via supply voltage 2002 Jun 24 41 Philips Semiconductors Product specification Il2C bus autosync deflection controller for TDA4841PS PC monitors Soft start and soft down sequences MHB495 VHPLL2 4 6 V continuous blanking off PLL2 enabled frequency detector enabled HDRV HFLB protection enabled 4 0 V BDRV duty cycle has reached nominal value 3 2V BDRV duty cycle begins to increase HDRV duty cycle has reached nominal value 1 8V HDRV duty cycle begins to increase 1 0 V VOUT1 and VOUT2 enabled time a Soft start sequence for Vcc gt 8 6 V MHB496 V HPLL2 4 6V continuous blanking pin 16 and 17 activated PLL2 disabled frequency detector disabled HDRV HFLB protection disabled 40V BDRV duty cycle begins to decrease 1 2 8 V BDRV floating HDRV duty cycle begins to decrease 1 8 V HDRV floating 1 0 V VOUT1 and VOUT2 floating time b Soft down sequence for Vcc gt 8 6 V 1 Pins HDRV and BDRV are floating for Vcc lt 8 6 V Fig 23 Activation of PLL2 soft start and soft down sequences via the I C bus 2002 Jun 24 42 Philips Semiconductors Product specification Il2C bus autosync deflection controller for PC monitors X ray latch triggered Y VXRAY I b VHUNLOCK 230 0 BDRV duty cycle 2 j S o ul HDRV duty cycle tating VOUT1 VOUT2 igs o approximately 25 ms mn MGM087 Fig 24 Activation of soft down sequence via
61. ses with the voltage at HPLL2 until the final duty cycle is reached The voltage at HPLL2 increases further and performs a soft start at BDRV pin 6 as well After BDRV has reached full duty cycle the voltage at HPLL2 continues to rise until HPLL2 enters its normal operating range The internal charge current is now disabled Finally PLL2 and the frequency locked loop are activated If both functions reach normal operation HUNLOCK pin 17 switches from the floating status to normal vertical blanking and continuous blanking at CLBL pin 16 is removed Output stage for line drive pulses HDRV pin 8 An open collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0 3 V at 20 mA To protect the line deflection transistor the output stage is disabled floating for low supply voltage at Vcc see Fig 26 The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency This ensures optimum drive conditions over the whole frequency range Philips Semiconductors I2C bus autosync deflection controller for PC monitors X ray protection The X ray protection input XRAY pin 2 provides a voltage detector with a precise threshold If the input voltage at XRAY exceeds this threshold for a certain period of time control bit SOFTST is reset which switches the IC into protection mode In this mode several pins are forced into defined states HUNLOC
62. ter HPARAL 32 note 8 VHPINBAL ASCOR vertical parabola for pin unbalance correction register HPINBAL 0 note 8 register HPINBAL 63 note 8 register HPINBAL 32 note 8 Vo ASCOR max p p Vo ASCOR max maximum output voltage swing peak to peak value maximum output voltage Vc ASCOR Vo ASCOR min centre voltage minimum output voltage lo ASCOR max sink ASCOR max 2002 Jun 24 maximum output current maximum output sink current Vo ASCOR gt 1 9 V Vo ASCOR gt 1 9 V 23 Philips Semiconductors I C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS Product specification TDA4841PS Focus section pin FOCUS see Figs 15 and 28 tprecor tW hfb min yV hfb max pre correction of phase for horizontal focus parabola minimum vvidth of horizontal flyback pulse maximum width of horizontal flyback pulse register HFOCAD 0 see Fig 28 register HFOCAD 1 see Fig 28 register HFOCAD 2 see Fig 28 register HFOCAD 3 see Fig 28 operation without pre correction VHFOCUS p p amplitude of horizontal focus parabola peak to peak value register HFOCUS 0 register HFOCUS 31 VvFOCUS p p Vo FOCUS max Vo FOCUS min amplitude of vertical parabola peak to peak value maximum output voltage minimum output voltage register VFOCUS 0 note 8
63. ulse HREF 0 52 mA fy 31 45 kHz HREF 1 052 mA H 64 kHz IHREF 2 141 mA fy 100 kHz IHREF 3 345 mA Vertical sync slicer DC coupled TTL compatible pin VSYNC Vi VSYNC sync input signal voltage Vvsync si slicing voltage level l vsyc input current OV lt Vi VSYNC lt 5 5V 2002 Jun 24 15 Philips Semiconductors I2C bus autosync deflection controller for PC monitors SYMBOL PARAMETER CONDITIONS Automatic polarity correction for vertical sync VSYNC max d VPOL maximum width of vertical sync pulse delay time for changing polarity Video clamping vertical blanking output pin CLBL clamp CLBL vvidth of video clamping pulse measured at Vc_p_ 3 V Velamp CLBL top voltage level of video clamping pulse temperature coefficient of Velamp CLBL steepness of slopes for clamping pulse Ri 1 MQ C 20 pF d HSYNCt CLBL delay betvveen trailing edge of horizontal sync and start of video clamping pulse clamp max d HSYNCI CLBL clamp max maximum duration of video clamping pulse referenced to end of horizontal sync delay between leading edge of horizontal sync and start of video clamping pulse maximum duration of video clamping pulse referenced to end of horizontal sync clamping pulse triggered on trailing edge of horizontal sync control bit CLAMP 0 measured at V g 3 V cla
64. unlock blanking available on pins CLBL and HUNLOCK 1 only vertical and protection blanking available on pins CLBL and HUNLOCK AGCDIS 0 AGC in vertical oscillator active 1 AGC in vertical oscillator inhibited bi FHMULT 0 EVV output independent of horizontal 8B D7 frequency 7 1 EW output tracks with horizontal frequency 77 VSC 0 VLIN HCORT and HCORB adjustments 82 X enabled i 1 VLIN HCORT and HCORB adjustments x forced to centre value MOD 8B OA 02 0 horizontal and vertical moire cancellation 08 88 enabled 1 horizontal and vertical moire cancellation disabled 0 vertical size 100 OF 1 vertical size 116 8 for VGA350 0 trailing edge for horizontal clamp 09 1 leading edge for horizontal clamp VBLK 0 vertical blanking 260 us ME needs ACD 0 ASCOR disconnected from PLL2 04 gt I AsConnenaysoveosswa paz 1 STDBY6 10 internal power supply enabled 1 9A TN zamam dus SOFTSTO 0 soft start not released pin HPLL2 pulled to 1A 9A X ground 7 1 soft start is released povver up via pin HPLL2 77 Notes 1 X don t care 2 this bit is occupied by another function If the register is addressed the bit values for both functions must be transferred 3 Bits STDBY and SOFTST can be reset by the internal protection circuit 2002 Jun 24 35 Product specification Philips Semiconductors TDA4841
65. utput signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator Video clamping vertical blanking generator The video clamping vertical blanking signal at CLBL pin 16 is a two level sandcastle pulse which is especially suitable for video ICs such as the TDA488x family but also for direct applications in video output stages The upper level is the video clamping pulse which is triggered by the horizontal sync pulse Via I C bus control either the leading or trailing edge can be selected by setting control bit CLAMP The width of the video clamping pulse is determined by an internal single shot multivibrator The lower level of the sandcastle pulse is the vertical blanking pulse which is derived directly from the internal oscillator waveform It is started by the vertical sync and stopped with the start of the vertical scan This results in optimum vertical blanking Via I C bus control two different vertical blanking times are accessible by control bit VBLK Blanking will be activated continuously if one of the following conditions is true Soft start of horizontal and B drive voltage at HPLL2 pin 30 pulled down externally or by the 12C bus PLL1 is unlocked while frequency locked loop is in search mode No horizontal flyback pulses at HFLB pin 1 X ray protection is activated Supply voltage at Vcc pin 10 is low see Fig 22 Via I C bus control hor

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