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TEXAS INSTRUMENTS ADS8517 Manual

1. ADS85171 ADS85171B PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT REFERENCE Internal reference voltage No load 2 48 2 5 2 52 2 48 2 5 2 52 V Internal reference source current 1 1 uA must use external buffer Internal reference drift 8 8 ppm C EI oltage range 23 25 27 2 3 2 5 27 v External reference current drain External 2 5 V reference 100 100 uA DIGITAL INPUTS Vit Low level input voltage 9 Voig 1 65 V to 5 5 V 0 3 0 6 0 3 0 6 V Vin High level input voltage Voie 1 65 V to 5 5 V 0 5 x Vpig Voie 0 3 0 5 x Vpig Vpia 0 3 V li Low level input current Vi 20V 10 10 uA lia High level input current Va 5V 10 10 uA DIGITAL OUTPUTS Data format Parallel 16 bits in 2 bytes Serial Data coding Binary twos complement or straight binary Vo Low level output voltage ne nus 0 45 045 V Vou High level output voltage VUE voa me Voie 0 45 Voie 0 45 V Leakage current Solis aa Vora 5 5 uA Output capacitance High Z state 15 15 pF DIGITAL TIMING Bus access time Ri 3 3 KO C 50 pF 83 83 ns Bus relinquish time Ri 3 3 KQ C 10 pF 83 83 ns POWER SUPPLIES VpiG Interface voltage 1 65 1 8 5 5 1 65 1 8 5 5 V VANA ADC core voltage 4 5 5 5 5 4 5 5 5 5 V Ibia Interface current Voig 5 V 0 3 0 3 mA lana ADC core current Vana 5 V 9 9 mA ka rim 5V 47 60 47 60 mW Power dissipation REFD high with BUF on 42 42 mW PWRD and REFD high 50 50 HW TEMPERATURE RANGE Specified performance 40 485 40 85 C Derated perfor
2. www ti com TYPICAL CHARACTERISTICS continued At fs 200 kHz Vpig Vana 5 V and using internal reference see Figure 39 unless otherwise specified UNIPOLAR OFFSET ERROR vs FREE AIR TEMPERATURE Unipolar 4 V Range Submit Documentation Feedback 125 gp GHL Offset mV 0 05 UNIPOLAR OFFSET ERROR vs FREE AIR TEMPERATURE Unipolar 5 V Range 25 50 100 125 Temperature C Figure 8 75 UNIPOLAR FULL SCALE ERROR vs FREE AIR TEMPERATURE Unipolar 5 V Range 25 50 75 100 125 Temperature C Figure 10 SIGNAL TO NOISE DISTORTION vs FREE AIR TEMPERATURE fn 10 kHz 0 dB 25 50 Temperature C Figure 12 Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 I TEXAS INSTRUMENTS www ti com SINAD dB SINAD dB THD dB ADS8517 SLAS527 SEPTEMBER 2008 TYPICAL CHARACTERISTICS continued At fs 200 kHz Vpis Vana 5 V and using internal reference see Figure 39 unless otherwise specified SIGNAL TO NOISE DISTORTION vs INPUT FREGUENCY AND INPUT AMPLITUDE 100 90 80 70 60
3. 50 40 30 20 10 0 2 4 6 8 10 12 14 16 18 20 Input Signal Frequency kHz Figure 13 SIGNAL TO NOISE DISTORTION vs INPUT FREQUENCY 100 90 80 1 10 100 Input Sampling Frequency kHz Figure 15 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 70 80 90 100 110 120 1 10 100 Input Sampling Frequency kHz Figure 17 Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 B SFDR SINAD and SNR d SNR dB 100 90 80 110 100 80 70 SIGNAL TO NOISE RATIO vs INPUT FREQUENCY 10 nput Sampling Frequency kHz Figure 14 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 100 10 nput Sampling Frequency kHz Figure 16 AC PARAMETERS vs CAP PIN CAPACITOR ESR fin 10 kHz 0 dB ESR 2 Figure 18 Submit Documentation Feedback 100 ap GHL ADS8517 SLAS527 SEPTEMBER 2008 SFDR SINAD and SNR dB 10 I TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued At fg 200 kHz Vpig Vana 5 V and using internal reference see Figure 39 unless otherwise specified AC PARAMETERS vs POWER SUPPLY VOLTAGE 110 70 fin 10 kHz 0 dB 105 75 SFDR 100 80 a amp
4. 95 85 5 SNR d 8 90 90 5 85 SINAD 935 8 5 THD 2 80 100 o 75 105 70 110 4 00 4 25 4 50 4 75 5 00 5 25 5 50 Power Supply Voltage V Figure 19 CONVERSION TIME vs FREE AIR TEMPERATURE 2 40 T q 235 a EA S 2 E ja E 5 2 30 x 5 E gt un S O 2 25 S z 2 20 50 25 0 25 50 75 100 125 Temperature C Figure 21 INTEGRAL LINEARITY ERROR a ry a 5 m E z z a All Codes INL 0 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 23 Submit Documentation Feedback Product Folder Link s OUTPUT REJECTION vs POWER SUPPLY RIPPLE FREQUENCY 20 30 40 50 60 70 80 10 100 1k 10k 100k 1M Power Supply Ripple Freguency Hz Figure 20 INTEGRAL LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs POWER SUPPLY VOLTAGE 4 00 4 25 4 50 4 75 5 00 5 25 5 50 Power Supply Voltage V Figure 22 DIFFERENTIAL LINEARITY ERROR 3 2 1 0 1 2 All Codes DNL O 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 24 Copyright O 2008 Texas Instruments Incorporated ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 TYPICAL CHARACTERISTICS continued At fs 200 kHz Vpis Vana 5 V and using internal reference see Figure 39 unless ot
5. Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS 8 no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS 8 no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous
6. Read After Conversion Discontinuous External DATACLK PACIEN C o iz AeF R C N tay R tw2 BUSY ee las p lato taat _ __R ee _ tsu3 je teonv tco t w3 m le twa External 1 tant lg le su DATACLK 0 1 2 3 4 5 10 11 12 13 14 15 Nih Conversion Data ta bi je tag B on MD INE DN DAN D D ON OD EXT INT tied high CS and TAG tied low Rising DATACLK change DATA tw1 tsu1 Starts READ TAG is not recommended for this mode There is not enough time to do so without violating tg11 Figure 36 Read During Conversion Discontinuous External DATACLK Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com TAG FEATURE The TAG feature allows data from multiple ADS8517 converters to be read on a single serial line The converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in Figure 37 The DATA pin of the last converter drives the processor serial data input Data are then shifted through each converter synchronous to the externally supplied data clock onto the serial data line The internal clock cannot be used for this configuration The preferred timing uses the discontinuous external data clock during the sampling period Data must b
7. 37 Timing of TAG Feature With Single Conversion Using External DATACLK DATA gt DATA 22 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s 4058517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 ANALOG INPUTS The ADS8517 offers three analog input ranges as shown in Table 1 The offset specification is factory calibrated with internal resistors The gain specification is factory calibrated with 0 196 0 25 W external resistors as shown in Figure 38 and Figure 39 The external resistors can be omitted if a larger gain error is acceptable or if using software calibration The hardware trim circuitry shown in Figure 38 and Figure 39 can reduce the error to zero Figure 39 Circuit Diagrams Without Gain Adjust Trim Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s ADS8517 ADS8517 SLAS527 SEPTEMBER 2008 I TEXAS INSTRUMENTS www ti com Analog input pins R1 and R2y have 25 V overvoltage protection The input signal must be referenced to AGND1 This referencing minimizes ground loop problems typical to analog designs The analog input should be driven by a low impedance source A typical driving circuit using the OPA627 or OPA132 is shown in Figure 40 24 2 2 uF HSV 22 pF j ADS8517 2ko 100 nF AV Ri
8. 40 40 ns Aperture jitter 20 20 ps Transient response FS step 5 5 us Overvoltage recovery 9 750 750 ns LSB means Least Significant Bit One LSB for the 10 V input range is 305 pV 3 Typical rms noise at worst case transitions Full scale error is the worst case of Full Scale or Full Scale untrimmed deviation from ideal first and last code transitions divided by the transition voltage not divided by the full scale range and includes the effect of offset error 5 This is the time delay after the ADS8517 is brought out of Power Down mode until all internal settling occurs and the analog input is acquired to rated accuracy A Convert command after this delay will yield accurate results Copyright O 2008 Texas Instruments Incorporated All specifications in dB are referred to a full scale input Product Folder Link s ADS8517 7 Usable bandwidth defined as full scale input frequency at which Signal to Noise Distortion degrades to 60 dB Recovers to specified performance after 2 x FS input overvoltage Submit Documentation Feedback ADS8517 SLAS527 SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS continued I TEXAS INSTRUMENTS www ti com At T4 40 C to 85 C fs 200 kHz Vpig Vana 5 V using internal reference see Figure 39 unless otherwise noted
9. 50 100 150 200 Sampling Frequency kHz Figure 3 BIPOLAR POSITIVE FULL SCALE ERROR vs FREE AIR TEMPERATURE Bipolar 10 V Range 50 0 25 50 75 Temperature C Figure 5 100 125 Copyright O 2008 Texas Instruments Incorporated Offset mV Negative Full Scale Error 96 Internal Reference Voltage V INTERNAL REFERENCE VOLTAGE vs FREE AIR TEMPERATURE 2 520 2 515 2 510 2 505 2 500 2 495 2 490 2 485 2 480 50 25 0 25 50 75 Temperature C Figure 2 100 125 BIPOLAR OFFSET ERROR vs FREE AIR TEMPERATURE Bipolar 10 V Range 25 0 25 50 75 Temperature C Figure 4 100 125 BIPOLAR NEGATIVE FULL SCALE ERROR vs FREE AIR TEMPERATURE Bipolar 10 V Range 0 05 0 10 50 125 45 0 25 50 75 Temperature C Figure 6 100 Submit Documentation Feedback Product Folder Link s 4058517 ADS8517 SLAS527 SEPTEMBER 2008 B SFDR SINAD and SNR d 50 25 0 25 50 75 100 125 Temperature C Figure 7 UNIPOLAR FULL SCALE ERROR vs FREE AIR TEMPERATURE 0 10 Unipolar 4 V Range 0 05 E E uU 0 2 o 0 05 0 10 50 25 0 25 50 75 100 Temperature C Figure 9 AC PARAMETERS vs FREE AIR TEMPERATURE 110 fin 10 kHz 0 dB 105 100 95 90 85 80 50 25 0 25 50 75 100 125 Temperature C Figure 11 I TEXAS INSTRUMENTS
10. I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam t a during storage or handling to prevent electrostatic damage to the MOS gates PACKAGE ORDERING INFORMATION MINIMUM RELATIVE NO MINIMUM SPECIFIED ACCURACY MISSING SINAD TEMPERATURE PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT LSB CODE dB RANGE LEAD DESIGNATOR NUMBER MEDIA QTY ADS8517IBDW Tube 20 SO 28 DW ADS8517IBDWR Tape and Reel 1000 ADS85171B 1 5 16 87 40 C to 85 C ADS85171BPW Tube 50 TSSOP 28 PW ADS85171BPWR Tape and Reel 2000 ADS85171DW Tube 20 SO 28 DW ADS8517IDWR Tape and Reel 1000 ADS85171 3 15 85 40 C to 85 C ADS8517W Tube 50 TSSOp 28 PW ADS8517IPWR Tape and Reel 2000 1 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI website at www ti com 2 TSSOP 28 PW package available Q2 2009 ABSOLUTE MAXIMUM RATINGS Over operating free air temperature range unless otherwise noted PARAMETER UNIT R1in 25 V Analog inputs R2in 25 V REF Vana 0 3 V to AGND2 0 3 V DGND AGND2 0 3 V Ground voltage differences VANA Voig to Vana 0 3 V Void 6V Digital inputs 0 3 V to Vpig 0 3 V Maximum junction temperature
11. Link s ADS8517 KB Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 13 Nov 2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty ADS8517IBDW ACTIVE SOIC DW 28 20 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br ADS8517IBDWG4 ACTIVE SOIC DW 28 20 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br ADS8517IBDWR ACTIVE SOIC DW 28 1000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS8517IBDWRG4 ACTIVE SOIC DW 28 1000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS8517IBPW PREVIEW TSSOP PW 28 50 TBD Call TI Call TI ADS85171BPWR PREVIEW TSSOP PW 28 2000 TBD Call TI Call TI ADS85171DW ACTIVE SOIC DW 28 20 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS85171DWG4 ACTIVE SOIC DW 28 20 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br ADS8517IDWR ACTIVE SOIC DW 28 1000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS8517IDWRG4 ACTIVE SOIC DW 28 1000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS85171PW PREVIEW TSSOP PW 28 50 TBD Call TI Call TI ADS85171PWR PREVIEW TSSOP PW 28 2000 TBD Call TI Call TI The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND
12. compared to other converters This input circuit not only reduces the power consumption on the signal conditioning op amp but it also works as a buffer to attenuate any charge injection resulting from the operation of the CDAC FET sample switches even though the design of those FET switches is optimized to give minimal charge injection Another benefit provided by the ADS8517 high impedance front end is assured 25V overvoltage protection In most cases this internal protection eliminates the need for external input protection circuitry INTERMEDIATE LATCHES The ADS8517 does have 3 state outputs for the parallel port but intermediate latches should be used if the bus is active during conversion If the bus is not active during conversion the 3 state outputs can be used to isolate the A D converter from other peripherals on the same bus Intermediate latches are beneficial on any monolithic A D converter The ADS8517 has an internal LSB size of 38 uV with a 2 5 V internal reference Transients from fast switching signals on the parallel port even when the A D converter is 3 stated can be coupled through the substrate to the analog circuitry causing degradation of converter performance Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link s ADS8517 ADS8517 1 TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com APPLICATION INFORMATION TRANSITION NOISE Apply a dc input to
13. conversions While this configuration is perfectly acceptable there is a possible problem when using an external data clock At an indeterminate point from 12 us after the start_of conversion N until BUSY rises the internal logic shifts the results of conversion N into the output register If CS is low R C high and the external clock is high at this point data are lost Consequently with CS low either R C and or DATACLK must be low during this period to avoid losing valid data External Data Clock After a Conversion After conversion N is completed and the output registers have been updated BUSY pin 24 goes high With CS low and R C high valid data from conversion N are output on SDATA pin 19 synchronized to the external data clock input on DATACLK pin 18 The MSB is valid on the first falling edge and the second rising edge of the external data clock The LSB is valid on the 16th falling edge and 17th rising edge of the data clock TAG pin 20 inputs a bit of data for every external clock pulse The first bit input on TAG is valid on SDATA on the 17th falling edge and the 18th rising edge of DATACLK the second input bit is valid on the 18th falling edge and the 19th rising edge etc With a continuous data clock TAG data is output on SDATA until the internal output registers are updated with the results from the next conversion Refer to Table 6 and Figure 35 for more information External Data Clock During a Conversion Aft
14. 165 C Storage temperature range 65 C to 150 C Internal power dissipation 700 mW Lead temperature soldering 1 6 mm from case 10 seconds 260 C 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods may affect device reliability 2 All voltage values are with respect to network ground terminal ELECTRICAL CHARACTERISTICS At T4 40 C to 85 C fs 200 kHz Vpig Vana 5 V using internal reference see Figure 39 unless otherwise noted ADS85171 ADS85171B PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT Resolution 16 16 Bits ANALOG INPUT 10 10 10 10 Voltage ranges See Table 1 0 5 0 5 V 0 4 0 Impedance See Table 1 Capacitance 45 45 pF 1 Shaded cells indicate different specifications for high grade version of the device 2 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 I TEXAS INSTRUMENTS www ti com ELECTRICAL CHARACTERISTICS continued ADS8517 SLAS527 SEPTEMBER 2008 At T4 40 C to 85 C fs 200 kHz Vpig Vana 5 V using internal reference see Figure 39 unless otherwise noted ADS85171 ADS85171B PARAMETER TEST CONDI
15. 19 TEXAS ts INSTRUMENTS www ti com ADS8517 4 osos SLAS527 SEPTEMBER 2008 16 Bit 200 kSPS Low Power Sampling ANALOG TO DIGITAL CONVERTER with Internal Reference and Parallel Serial Interface FEATURES e 200 kHz Minimum Sampling Rate e 4 V 5 V and 10 V Input Ranges with High Impedance Input e 1 5 LSB Max INL e 41 5 1 LSB Max Min DNL 16 Bits NMC e 2 mV Max BPZ 0 6 ppm C BPZ Drift e 2 mV Max UPZ 0 15 ppm C UPZ Drift e 88 8 dB SINAD with 10 kHz Input e SPI Compatible Serial Output With Daisy Chain TAG SPI Master Slave Feature e Full Parallel Interface e Binary Twos Complement or Straight Binary Output Code Formats Single 4 5 V to 5 5 V Analog Supply 1 65 V to 5 5 V Interface Supply Uses Internal 2 5 V or External Reference e No External Precision Resistors Required Low Power Dissipation ADC REF BUF 47 mW Typ 60 mW Max at 200 kSPS e 50 uW Max Power Down Mode e Pin Compatible with 16 Bit ADS7807 and ADS8507 and 12 Bit ADS7806 and ADS8506 e SO 28 Package TSSOP 28 Available Q2 2009 APPLICATIONS Portable Test Equipment e USB Data Acquisition Module e Medical Equipment Industrial Process Control Digital Signal Processing e Instrumentation DESCRIPTION The ADS8517 is a complete low power single 5 V supply 16 bit sampling analog to digital A D converter It contains a complete 16 bit capacitor based successive approximation register SA
16. 4 0 10 7 0 004 0 10 Gauge Plane A Seating Plane 0 010 0 25 4040000 6 F 06 2004 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 D Falls within JEDEC MS 013 variation AE 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PINS SHOWN 0 15 NOM i t casera a LI Seating Plane tL EA 20 MAX 0 15 1j 10 10 0 05 PINS DIM A MAX A MIN 4040064 F 01 97 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 gow 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service wit
17. AGND1 R2w EXT INT 2 2 uF 2 2 uF DGND mal 45V a GND GND GND GND GND GND Figure 40 Typical Driving Circuit 10 V No Trim Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 REFERENCE The ADS8517 can operate with the internal 2 5 V reference or an external reference An external reference connected to pin 5 REF bypasses the internal reference The external reference must drive the 6 kO resistor that separates pin 5 from the internal reference see the front page diagram The load varies with the difference between the internal and external reference voltages The internal reference is approximately 2 5 V range is from 2 48 V to 2 52 V The external reference voltage can vary from 2 3 V to 2 7 V The reference whether internal or external is buffered internally with the output on pin 4 CAP Figure 41 shows characteristic impedances at the input and output of the buffer with all combinations of power down and reference power down The reference voltage determines the size of the least significant bit LSB The larger reference voltages produce a larger LSB which can improve SNR Smaller reference voltages can degrade SNR ZCAP CAP O Pin 4 PWRDO PWRDO PWRD 1 PWRD 1 REFD 0 REFD 1 REFD 0 REFD 1 1 1 e mw ee ow F
18. All convert commands are ignored while BUSY is low The ADS8517 begins tracking the input signal at the end of the conversion Allowing 5 us between convert commands assures accurate acquisition of a new signal O 1 8 V 10 V e e O 5y zz 0 1 uF 0 1 uF 10 uF V V gt AXAt I BUSY 22 uF Convert Pulse RE bi 40 ns min I PV SDATA c p DATACLK No No No ADS8517 NOTE 1 NC not connected Figure 29 Basic 10 V Operation with Serial Output Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s ADS8517 ADS8517 i I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com STARTING A CONVERSION The combination of CS pin 23 and R C pin 22 held low for a minimum of 40 ns puts the sample and hold of the ADS8517 in the hold state and starts conversion N BUSY pin 24 goes low and stays low until conversion N completes and the internal output register has been updated All new convert commands received while BUSY is low are ignored The ADS8517 begins tracking the input signal at the end of the conversion Allowing 5 us between convert commands assures accurate acquisition of a new signal Refer to Table 2 and Table 3 for a summary of CS R C and BUSY states and Figure 30 through Figure 36 for timing diagrams Table 2 Control Functions When
19. Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPA Reel Reel A0 mm BO mm KO mm P1 WwW Pini Type Drawing Diameter Width mm mm Quadrant mm W1 mm ADS8517IBDWR SOIC DW 28 1000 330 0 32 4 11 35 18 67 3 1 16 0 32 0 Q1 ADS8517IDWR SOIC DW 28 1000 330 0 32 4 11 35 18 67 3 1 16 0 32 0 Q1 Pack Materials Page 1 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 6 Nov 2008 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS8517IBDWR SOIC DW 28 1000 346 0 346 0 49 0 ADS8517IDWR SOIC DW 28 1000 346 0 346 0 49 0 Pack Materials Page 2 MECHANICAL DATA DW R PDSO G28 PLASTIC SMALL OUTLINE PACKAGE 0 713 18 10 0 697 17 70 4 0 020 0 51 0 012 0 31 10 010 0 25 Pin 1 0 050 1 27 Index Area A L 0 104 2 65 Max ine 0 30 0 00
20. R A D converter with sample and hold clock reference and data interface The converter can be configured for a variety of input ranges including 10 V 4 V and 5 V For most input ranges the input voltage can swing to 25 V or 25 V without damage to the device An SPl compatible serial interface allows data to be synchronized to an internal or external clock A full parallel interface using the selectable BYTE pin is also provided to allow the maximum system design flexibility The ADS8517 is specified at a 200 kHz sampling rate over the industrial 40 C to 85 C temperature range Parallel O BYTE and O BUSY Serial o CS Data Out R C and O SB BTC Control O TAG Comparator O DATACLK REF AM O EXT INT 2 5N Internal Reference O REED A Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet SPI is a trademark of Motorola Inc All other trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2008 Texas Instruments Incorporated ADS8517 i
21. R C to control the read and convert modes This configuration has no effect when using the internal data clock in the serial output mode However when using an active external data clock the parallel and serial outputs are affected whenever R C goes high refer to the Heading Data section for more information In the internal clock mode data are clocked out every convert cycle regardless of the states of CS and R C The conversion result is available as soon as BUSY returns to high Therefore data always represent the previously completed conversion even when read during a conversion 14 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 READING DATA The ADS8517 outputs serial or parallel data in straight binary SB or binary twos complement data output format If SB BTC pin 7 is high the output is in SB format if it is low the output is in BTC format Refer to Table 4 for the ideal output codes The first conversion immediately following a power up does not produce a valid conversion result The parallel output can be read without affecting the internal output registers however reading the data through the serial port shifts the internal output registers one bit per data clock pulse As a result data can be read on the parallel port before reading the same data on the serial port but data cannot be read thr
22. TIONS MIN TYP MAX MIN TYP MAX UNIT THROUGHPUT SPEED Conversion time 2 5 2 5 us Complete cycle Acquire and convert 5 HS Throughput rate 200 200 kHz DC ACCURACY INL Integral linearity error 3 1 5 15 LSB DNL Differential linearity error 2 1 15 LSB No missing codes 15 16 Bits Transition noise 0 9 0 8 LSB Gain error 10 2 011 96 Internal reference 0 75 0 75 0 75 0 75 96 Full scale error External 2 5 V reference 0 75 0 75 0 75 0 75 96 Internal reference i9 9 ppm C Full scale error drift External 2 5 V reference 1 1 ppm C BPZ Bipolar zero error 10 V range 5 1 5 2 x 2 mV Bipolar zero error drift 10 V range 10 6 0 6 ppm C UPZ Unipolar zero error 0 Vto 5V 0 V to 4 V ranges 3 0 1 3 2 0 1 2 mV Unipolar zero error drift 0 V to 5 V 0 V to 4 V ranges 0 15 0 15 ppm C a ld rated accuracy 2 2 uF capacitor to CAP 1 1 ms Power supply sensitivity 4 75 V lt Vana lt 5 25 V 8 8 6 6 LSB Voie Vana Vs 44 5 V lt Vana lt 5 5 V 20 20 12 412 AC ACCURACY SFDR Spurious free dynamic range fin 10 kHz 10 V 92 100 96 101 dB 9 THD Total harmonic distortion fin 10 kHz 10 V 97 92 98 95 dB fin 10 kHz 10 V 85 88 87 88 5 SINAD _ Signal to noise distortion dB 60 dB Input 29 29 SNR Signal to noise ratio fin 10 kHz 10 V 85 88 88 89 dB SNR usable bandwidth fin 10 kHz 10 V 130 130 kHz SNR full power bandwidth 3 dB fin 10 kHz 10 V 600 600 kHz SAMPLING DYNAMICS Aperture delay
23. Using Parallel Output DATACLK Tied Low EXT INT Tied High cs R C BUSY OPERATION 1 X X None Data bus is in High Z state l 0 1 Initiates conversion N Data bus remains in High Z state 0 l 1 Initiates conversion N Data bus enters High Z state 0 1 1 Conversion N completed Valid data from conversion N on the data bus Al 1 1 Enables data bus with valid data from conversion N l 1 0 Enables data bus with valid data from conversion N 1 Conversion N in progress 0 1 0 Enables data bus with valid data from conversion N 1 Conversion N in progress 0 0 1 New conversion initiated without acguisition of a new signal Data are invalid CS and or R C must be high when BUSY goes high X X 0 New convert commands ignored Conversion N in progress 1 See Figure 30 and Figure 31 for constraints on data valid from conversion N 1 CS and R C are internally ORed and level triggered It does not matter which input goes low first when initiating a conversion If however it is critical that CS or R C initiates conversion N be sure the less critical input is low at least tsy2 2 10 ns before the initiating input If EXT INT pin 8 is low when initiating conversion N serial data from conversion N 7 is output on SDATA pin 19 following the start of conversion N See Internal Data Clock in the Reading Data section for more information To reduce the number of control pins CS can be tied low using
24. aining byte to be read All convert commands are ignored while BUSY is low The ADS8517 begins tracking the input signal at the end of the conversion Allowing 5 us between convert commands assures accurate acquisition of a new signal 10 Vo O 41 8V o e o45V 0 1uF V 0 1 uF 10 uF V VY gt E I BUSY 2 2uF 22uF 7s e Convert Pulse RE LL apsesi7 m BYTE gt 40 ns min nc E Pin 21 B15 B14 B13 B12 B11 B10 B9 B8 LOW MSB Pin 21 B7 B6 B5 B4 B3 B2 B1 BO HIGH LSB NOTE 1 NC not connected Figure 28 Basic 10 V Operation Both Parallel and Serial Output 12 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 SERIAL OUTPUT Figure 29 shows a basic circuit to operate the ADS8517 with a 10 V input range and serial output Taking R C pin 22 low for 40 ns 5 us max initiates a conversion and outputs valid data from the previous conversion on SDATA pin 19 synchronized to 16 clock pulses output on DATACLK pin 18 BUSY pin 24 goes low and stays low until the conversion completes and the serial data have been transmitted Data are output in BTC format MSB first and are valid on both the rising and falling edges of the data clock BUSY going high can be used to latch the data
25. bsolute Maximum Ratings for details The analog supply should be powered on before the digital supply used for the interface It is important that the voltage difference between Vpig and the digital inputs does not exceed the limit of 0 3V to Vpig 0 3V All digital inputs should be kept inactive logic low until the digital interface supply is steady GROUNDING Three ground pins are present on the ADS8517 DGND is the digital supply ground AGND2 is the analog supply ground AGND1 is the ground to which all analog signals internal to the A D converter are referenced AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply To achieve optimum performance all the ground pins of the A D converter should be tied to an analog ground plane separated from the system digital logic ground Both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible This configuration helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground SIGNAL CONDITIONING The ADS8517 features high impedance inputs as the result of the resistive input attenuation circuit For 10V OV to 5V and OV to 4V inputs the equivalent input impedances are 45 7kO 20kO and 21 4kO respectively Lower cost op amps may be used to drive the ADC inputs because the driving requirement is not as high
26. cale range 10 OVto5V OVto4V HEX Least significant bit LSB 305 uV 76 uV 61 uV BINARY CODE CODE BINARY CODE HEX CODE Full scale FS 1LSB 9 999695 V 4 999924 V 3 999939 V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF Midscale OV 2 5 V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 1 LSB below midscale 305 uV 2 499924 V 1 999939 V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF Full scale 10V OV OV 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 Parallel Output To use the parallel output tie EXT INT pin 8 high and DATACLK pin 18 low SDATA pin 19 should be left unconnected The parallel output is active when R C pin 22 is high and CS pin 23 is low Any other combination of CS and R C 3 states the parallel output Valid conversion data can be read in two 8 bit bytes on D7 DO pins 9 13 and 15 17 When BYTE pin 21 is low the eight most significant bits are valid with the MSB on D7 When BYTE is high the eight least significant bits are valid with the LSB on DO BYTE can be toggled to read both bytes within one conversion cycle Upon initial device power up the parallel output contains indeterminate data Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s ADS8517 ADS8517 i I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com Parallel Output After a Conversion After conversion N is completed and the output registers have b
27. cts in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP
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29. e read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the ty constraint see the External Data Clock section The sampling period must be sufficiently long enough to allow all data words to be read before starting a new conversion Note that in Figure 37 the state of the DATA pin at the end of a READ cycle reflects the state of the TAG pin at the start of the cycle for each converter The ADS8517 works the same way when it is running in external or internal clock mode That is the state of the TAG pin is shown on the DATA pin at the 17th clock after all 16 bits have shifted out However it is only practical to use the TAG feature with the external clock mode when multiple ADS8517s are daisy chained so that they are running at the same clock speed For example when two converters ADS8517A and ADS8517B are cascaded together the 17th external clock cycle brings the MSB data of ADS8517A onto the DATA pin of ADS8517B ADS8517A ADS8517B Processor A00 A15 DATA A TAG B BOO B15 DATA B DATACLK R C both A and B BUSY both A and B SYNC both A and B Data JAN 2N 3774 M 15 16 17 18 19 20 21 32 33 34 LIUU ED D p DD TAGA Nth Conversion Data D ZIU Bo Boo Id man 0 EXT INT tied high CS of both converter A and B TAG input of converter A are tied low Figure
30. een updated BUSY pin 24 goes high Valid data from conversion N are available on D7 DO pin 9 13 and 15 17 BUSY going high can be used to latch the data Refer to Table 5 Figure 30 and Figure 31 for timing specifications Uu gt ti R C X X li t5 gt 3 t4 ts gt e BUSY A 7 tg Pie ts 14 Db tg lie t pid ts gt gt fe to t11 gt gt tio ma m t12 Parallel Previous Low Byte Hi Z High Byte Data Bus High Byte Valid Valid Valid t2 gt gt et 9 tg gt k h oo taha gt uo BYTE X Figure 30 Conversion Timing With Parallel Output CS and DATACLK Tied Low EXT INT Tied High to1 PI id t A M toy to1 9 ta ie R C t21 gt to1 je cs N N t k ta gt BUSY Y y 121 DEE t tor PI le tor Di le tai gt Ke ta fe ts gt Ie to Ie Figure 31 CS to Control Conversion and Read Timing With Parallel Outputs 16 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 Parallel Output During a Conversion After conversion N has been initiated valid data from conversion N 7 can be read and are valid up to 2 2 us after the start of conversion N Do not attempt to read data beyond 2 2 us after the start of conversion N u
31. er conversion N has been initiated valid data from conversion N 7 can be read and are valid up to 2 2 us after the start of conversion N Do not attempt to clock out data from 2 2 us after the start of conversion N until BUSY pin 24 rises doing so results in data loss NOTE For the best possible performance when using an external data clock data should not be clocked out during a conversion The switching noise of the asynchronous data clock can cause digital feedthrough degrading converter performance Refer to Table 6 and Figure 36 for more information 18 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 13 TEXAS INSTRUMENTS www ti com ADS8517 SLAS527 SEPTEMBER 2008 Table 6 Timing Requirements T4 40 C to 85 C PARAMETER MIN TYP MAX UNIT tui Pulse duration convert 0 04 5 us tai Delay time BUSY from R C low 20 85 ns two Pulse duration BUSY low 2 3 2 5 us tae Delay time BUSY after end of conversion 90 ns tas Delay time aperture 40 ns conv Conversion time 2 0 2 2 24 us lacq Acquisition time 2 6 2 7 us toonv tacg Cycle time 5 us taa Delay time R C low to internal DATACLK output 171 ns te Cycle time internal DATACLK 92 96 98 ns tas Delay time data valid to internal DATACLK high 2 3 5 ns tae Delay time data valid after internal DATACLK lo
32. herwise specified FFT FFT 4096 Point FFT 0 4096 Point FFT fin 1 kHz 0 dB 20 fin 10 kHz 0 dB I A o a o Amplitude dB Amplitude dB ML BET LM yag uH Vy Jn 130 A m llb de caen ia ct ben Bo 0 25 50 75 100 Frequency kHz Frequency kHz Figure 25 Figure 26 FFT 4096 Point FFT fi 20 kHz 0 dB Amplitude dB Lan Ae ie I M B M y j i UE y AC Toss Ml Der oa Tan Malen ce AAVA td ra fica cte e 0 25 50 75 100 Frequency kHz Figure 27 Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link s ADS8517 ADS8517 1 TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com BASIC OPERATION PARALLEL OUTPUT Figure 28 shows a basic circuit for operating the ADS8517 with a 10 V input range and parallel output Taking R C pin 22 low for a minimum of 40 ns 5 us max initiates a conversion BUSY pin 24 goes low and stays low until the conversion completes and the output register updates If BYTE pin 21 is low the eight most significant bits MSBs will be valid when BUSY rises if BYTE is high the eight least significant bits LSBs will be valid when BUSY rises Data are output in binary twos complement BTC format BUSY going high can be used to latch the data After the first byte has been read BYTE can be toggled allowing the rem
33. hout notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under
34. igure 41 Characteristic Impedances of the Internal Buffer The ADS8517 is factory tested with 2 2 uF capacitors connected to pin 4 CAP and pin 5 REF Each capacitor should be placed as close as possible to the pin The capacitor on pin 5 band limits the internal reference noise A smaller capacitor can be used but it may degrade SNR and SINAD The capacitor on pin 4 stabilizes the reference buffer and provides switching charge to the CDAC during conversion Capacitors smaller than 1 uF may cause the buffer to become unstable and not hold sufficient charge for the CDAC The devices are tested to specifications with 2 2 uF making larger capacitors unnecessary Figure 42 shows how capacitor values larger than 2 2 uF have little effect on improving performance The equivalent series resistance ESR of these compensation capacitors is also critical keep the total ESR under 3 O See the Typical Characteristics section concerning how ESR affects performance 7000 Power Up Time us 0 1 1 10 100 CAP Pin Value uF Figure 42 Power Down to Power Up Time versus Capacitor Value on CAP Neither the internal reference nor the buffer should be used to drive an external load Such loading can degrade performance as shown in Figure 41 Any load on the internal reference causes a voltage drop across the 6 kO resistor and affects gain The inter
35. m an external trigger source or a trigger generated by the microcontroller The ADS8517 internal SCLK provides 2 ns min of setup time and 41 ns min of hold time on the SDATA output see tys and tyg in Table 6 allowing the microcontroller to sample data on either the rising or falling edge of SCLK Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Link s ADS8517 ADS8517 i I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com ADS8517 AS AN SPI SLAVE DEVICE INT EXT TIED HIGH Figure 45 shows another interface between the ADS8517 and an SPl equipped microcontroller or DSP in which the host processor acts as an SPI master device Microcontroller ADS8517 Vs 6 R C EXT INT BUSY SDATA DATACLK s SPI Slave NOTE CPOL 0 inactive SCLK is LOW CPHA 1 data valid on SCLK falling edge Figure 45 ADS8517 as SPI Slave In this configuration the data transfer from the ADS8517 is triggered by the rising edge of the serial data clock provided by the SPI master The SPI interface should be configured to read valid SDATA on the falling edge of SCLK When a minimum of 17 SCLKs are provided to the ADS8517 data can be strobed to the host processor on the rising SCLK edge providing a 2ns min hold time see tag in Table 6 When using an external interrupt to facilitate serial data transfers as shown in Figure 45 there are two options for the configuration of the interru
36. mance 55 125 55 125 C Storage temperature 65 150 65 150 C TSSOP 62 62 OJA Thermal impedance C W SO 46 46 9 TTL compatible at 5V supply Table 1 Analog Input Range Connections see Figure 38 and Figure 39 ANALOG INPUT RANGE CONNECT R1 VIA 200 O TO CONNECT R2y VIA 100 Q TO IMPEDANCE 10 V Vin CAP 45 7 ka OVto5V AGND Vin 20 0 ka OVto4V Vin Vin 21 4 ka Submit Documentation Feedback Product Folder Link s ADS8517 Copyright 2008 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com PIN CONFIGURATION DW PW PACKAGES SO 28 TSSOP 28 ADS8517 SLAS527 SEPTEMBER 2008 TOP VIEW Riin Vois AGND1 M ANA R2in REFD CAP PWRD REF BUSY AGND2 cs SB BTC R C E ADS8517 EXT INT BYTE D7 TAG D6 SDATA D5 DATACLK D4 DO D3 D1 DGND D2 1 TSSOP 28 PW package available Q2 2009 Pin Assignments EN DIGITAL NAME NO yo DESCRIPTION R N 1 Analog Input AGND1 2 Analog sense ground Used internally as ground reference point Minimal current flow R2in 3 Analog Input CAP 4 Reference buffer output 2 2 uF tantalum capacitor to ground REF 5 Reference input output Outputs internal 2 5 V reference Can also be driven by external system reference In both cases bypass to ground with a 2 2 uF tantalum capacitor AGND2 6 Analog ground E Output mode select Selects straight binary or binary twos complement for output data forma
37. material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 X3 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 13 Nov 2008 Addendum Page 2 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 6 Nov 2008 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS A Reel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length
38. nal buffer is capable of driving 2 mA loads but any load can cause perturbations of the reference at the CDAC thus degrading performance Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com POWER DOWN The ADS8517 has analog power down and reference power down capabilities via PWRD pin 25 and REFD pin 26 respectively PWRD and REFD high powers down all analog circuitry maintaining data from the previous conversion in the internal registers provided that the data have not already been shifted out through the serial port Typical power consumption in this mode is 50 uW Power recovery is typically 1 ms using a 2 2 uF capacitor connected to CAP Figure 42 shows power down to power up recovery time relative to the capacitor value on CAP With 5 V applied to Vpig the digital circuitry of the ADS8517 remains active at all times regardless of PWRD and REFD states PWRD PWRD high powers down all of the analog circuitry except for the reference Data from the previous conversion are maintained in the internal registers and can still be read With PWRD high a convert command yields meaningless data REFD REFD high powers down the internal 2 5 V reference All other analog circuitry including the reference buffer is active REFD should be high when using an external reference to minimize power consumpti
39. nd CS pin 23 low initiates conversion N and activates the internal data clock typically a 900 kHz clock rate The ADS8517 outputs 16 bits of valid data MSB first from conversion N 1 on SDATA pin 19 synchronized to 16 clock pulses output on DATACLK pin 18 The data are valid on both the rising and falling edges of the internal data clock The rising edge of BUSY pin 24 can be used to latch the data After the 16th clock pulse DATACLK remains low until the next conversion is initiated while SDATA returns to the state of the TAG pin input sensed at the start of transmission Refer to Table 6 and Figure 33 for more information Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s ADS8517 ADS8517 19 TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com External Data Clock To use an external data clock tie EXT INT pin 8 high The external data clock is not and cannot be synchronized with the internal conversion clock care must be taken to avoid corrupting the data To enable the output mode of the ADS8517 CS pin 23 must be low and R C pin 22 must be high DATACLK must be high for 20 to 70 of the total data clock period the clock rate can be between dc and 10 MHz Serial data from conversion N can be output on SDATA pin 19 after conversion N completes or during conversion N 1 An obvious way to simplify control of the converter is to tie CS low and use R C to initiate
40. ng edge on CS initiates a new CS 23 l conversion If EXT INT is low this same falling edge will start the transmission of serial data results from the previous conversion BUSV 24 o Busy output At the start of a conversion BUSY goes low and stays low until the conversion is completed and the digital outputs have been updated PWRD 25 Power down input If high conversions are inhibited and power consumption is significantly reduced Results from the previous conversion are maintained in the output shift register REFD 26 Reference disable REFD high shuts down the internal reference The external reference is required for conversions VANA 27 ADC core supply Nominally 5 V Decouple with 0 1 uF ceramic and 10 4F tantalum capacitors VDIG 28 I O supply Nominally 1 8 V 6 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s 4058517 l TEXAS INSTRUMENTS www ti com Positive Full Scale Error ADS8517 SLAS527 SEPTEMBER 2008 TYPICAL CHARACTERISTICS At fs 200 kHz Vpig Vana 5 V and using internal reference see Figure 39 unless otherwise specified POWER SUPPLY CURRENT vs FREE AIR TEMPERATURE 10 0 lt E 95 t g 3 gt 9 0 E a gt i 85 o a 8 0 50 25 0 25 50 75 100 125 Temperature C Figure 1 POWER SUPPLY CURRENT vs SAMPLING FREQUENCY 10 0 lt E 95 t g 3 gt 9 0 a a d 85 o a 8 0
41. ntil BUSY pin 24 goes high doing so may result in reading invalid data Refer to Table 5 Figure 30 and Figure 31 for timing constraints Table 5 Conversion and Data Timing with Parallel Interface at Ta 40 C to 85 C SYMBOL DESCRIPTION MIN TYP MAX UNITS ty Convert pulse width 0 04 5 us to Data valid delay after R C low 2 3 2 5 us t3 BUSY delay from start of conversion 20 85 ns t4 BUSY low 2 3 2 5 us ts BUSY delay after end of conversion 90 ns te Aperture delay 40 ns t Conversion time 1 8 2 2 us tg Acquisition time 2 7 us to Bus relinquish time 10 83 ns to BUSY delay after data valid 20 60 ns iu Previous data valid after start of conversion 1 8 2 2 us toy R C to CS setup time 10 ns t7 tg Throughput time 5 us Serial Output Data can be clocked out with the internal data clock or an external data clock When using the serial output be careful with the parallel outputs D7 DO pins 9 13 and 15 17 because these pins come out of a High Z state whenever CS pin 23 is low and R C pin 22 is high The serial output cannot be 3 stated and is always active Refer to the Applications Information section for specific serial interfaces If an external clock is used the TAG input can be used to daisy chain multiple ADS8517 data pins together Internal Data Clock During a Conversion To use the internal data clock tie EXT INT pin 8 low The combination of R C pin 22 a
42. on and the loading effects on the external reference See Figure 41 for the characteristic impedance of the reference buffer input for both REFD high and low The internal reference consumes approximately 5 mW 26 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 LAYOUT POWER For host processors that are able to advantage of a lower interface supply voltage the ADS8517 offers a wide range of voltages from 5 5V to as low as 1 65V The ADS8517 should be considered as an analog component because as noted in the Electrical Characteristics it uses 9596 of its power for the analog circuitry If the interface is at the same 5V as the analog supply the two 5 V supplies should be separate Connecting Vpic pin 28 directly to a digital supply can reduce converter performance because of switching noise from the digital logic For best performance the 5 V supply should be produced from whichever analog supply is present for the rest of the analog signal conditioning If a 12 V or 15 V suppy is present in the system a simple 5 V regulator can be used Although it is not suggested if the digital supply in the system must be used to power the converter be sure it is properly filtered POWER ON SEQUENCE Care must be taken with power sequencing when the interface and analog supplies are different Refer to the A
43. ough the serial port before reading the same data on the parallel port Table 3 Control Functions When Using Serial Output cs R C BUSY EXT NT DATACLK OPERATION l 0 1 0 Output Initiates conversion N Valid data from conversion N 1 clocked out on SDATA l 1 0 Output Initiates conversion N Valid data from conversion N 1 clocked out on SDATA J 0 1 1 Input Initiates conversion N Internal clock still runs conversion process l 1 1 Initiates conversion N Internal clock still runs conversion process J 1 1 1 Input Conversion N completed Valid data from conversion N clocked out on SDATA synchronized to external data clock l 1 0 1 Input Valid data from conversion N 1 output on SDATA synchronized to external data clock Conversion N in progress 0 1 0 1 Input Valid data from conversion N 1 output on SDATA synchronized to external data clock Conversion N in progress 0 0 t X Input New conversion initiated without acquisition of a new signal Data are invalid CS and or R C must be high when BUSY goes high X X 0 X X New convert commands ignored Conversion N in progress 1 See Figure 34 Figure 35 and Figure 36 for constraints on data valid from conversion N 1 Table 4 Output Codes and Ideal Input Voltages DIGITAL OUTPUT BINARY TWOS COMPLEMENT CEP DESCRIPTION ANALOG INPUT SB BTC LOW STRAIGHT BINARY SB BTC HIGH Full s
44. pt service routine ISR falling edge triggered or rising edge triggered A falling edge triggered transfer would initiate an SPI transfer after the falling edge of BUSY providing the host controller with the previous conversion results while the current conversion cycle is underway The timing for this type of interface is described in detail in Figure 36 Care must be taken to ensure the entire 16 bit conversion result is retrieved from the ADS8517 before BUSY returns high to avoid the potential corruption of the current conversion cycle A rising edge triggered transfer is the preferred method of obtaining the conversion results This timing is depicted in Figure 35 This method of obtaining data ensures that SCLK is static during the conversion cycle and provides the host processor with current cycle conversion results 8 BIT SPI INTERFACE For microcontrollers that only support 8 bit SPI transfers it is recommended to configure the ADS8517 for SPI slave operation as depicted in Figure 45 With the microcontroller configured as the SPI master two 8 bit transfers are required to obtain full 16 bit conversion results from the ADS8517 The eight MSBs of the conversion result are considered valid on the falling SCLK edges of the first transfer with the remaining four LSBs being valid on the first four falling SCLK edges in the second transfer 30 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder
45. requencies near dc For ac signals a digital filter can be used to low pass filter and decimate the output codes This action works in a similar manner to averaging for every decimation by 2 the signal to noise ratio improves by 3 dB 28 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 ADS8517 AS AN SPI MASTER DEVICE INT EXT TIED LOW Figure 44 shows a simple interface between the ADS8517 and an SPl eguipped microcontroller or TMS320 series digital signal processor DSP when using the internal serial data clock This interface assumes that the microcontroller or DSP is configured as an SPI slave is capable of receiving 16 bit transfers and that the ADS8517 is the only serial peripheral on the SPI bus Microcontroller ADS8517 DATACLK EXT INT 5 SPI Master NOTE CPOL 0 inactive SCLK is LOW CPHA 0 or 1 data valid on either SCLK edge Figure 44 ADS8517 as SPI Master To maintain synchronization with the ADS8517 the microcontroller slave select SS input should be connected to the BUSY output of the ADS8517 When a transition from high to low occurs on BUSY indicating the current conversion is in process the ADS8517 internal SCLK begins shifting the previous conversion data into the MOSI pin of the microcontroller In this scenario the CONV input to the ADS8517 can be controlled fro
46. signments continued DO 17 oO Data bit 0 LSB if BYTE is high Data bit 8 if BYTE is low High Z when CS is high and or R C is low Data clock Either an input or an output depending on the EXT INT level Output data are DATACLK 18 y o synchronized to this clock If EXT INT is low DATACLK transmits 16 pulses after each conversion and then remains low between conversions Serial data output Data are synchronized to DATACLK with the format determined by the level of SB BTC In the external clock mode after 16 bits of data the ADC outputs the level input on SDATA 19 O TAG as long as CS is low and R C is high If EXT INT is low data are valid on both the rising and falling edges of DATACLK and between conversions SDATA stays at the level of the TAG input when the conversion was started TAG 20 Tag input for use in the external clock mode If EXT is high digital data input from TAG is output on DATA with a delay that depends on the external clock mode BYTE 24 Byte select Selects the eight most significant bits low or eight least significant bits high on parallel output pins Read convert input With CS low a falling edge on R C puts the internal sample and hold circuit R C 22 into the hold state and starts a conversion With EXT INT is low the transmission of the data results from the previous conversion is initiated t Chip select Internally ORed with R C If R C is low a falli
47. t If SB BTC 7 l high data are output in a straight binary format If low data are output in a binary twos complement format External internal data select Selects external internal data clock for transmitting data If high EXT INT 8 data is output synchronized to the clock input on DATACLK If low a convert command initiates the transmission of the data from the previous conversion along with 16 clock pulses output on DATACLK D7 9 o Data bit 7 if BYTE is high Data bit 15 MSB if BYTE is low High Z when CS is high and or R C is low Leave unconnected when using serial output D6 10 O Data bit 6 if BYTE is high Data bit 14 if BYTE is low High Z when CS is high and or R C is low D5 11 O Data bit 5 if BYTE is high Data bit 13 if BYTE is low High Z when CS is high and or R C is low D4 12 O Data bit 4 if BYTE is high Data bit 12 if BYTE is low High Z when CS is high and or R C is low D3 13 O Data bit 3 if BYTE is high Data bit 11 if BYTE is low High Z when CS is high and or R C is low DGND 14 Digital ground D2 15 O Data bit 2 if BYTE is high Data bit 10 if BYTE is low High Z when CS is high and or R C is low D1 16 O Data bit 1 if BYTE is high Data bit 9 if BYTE is low High Z when CS is high and or R C is low Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 Submit Documentation Feedback 5 ADS85 17 SLAS527 SEPTEMBER 2008 I TEXAS INSTRUMENTS www ti com Pin As
48. tati N D l tant status mene Ela CI Gomer El t t t t lq conv pit acq pi conv re acq P taa tet taa Internal DATACLK Lil tasa el SDATA TAG 0 KEK XN TAG 0 XX XO TAG 0 EM mu N4 th Conversion Data Nth Conversion Data CS EXT INT and TAG are tied low 8 starts READ Figure 33 Basic Conversion Timing Internal DATACLK Read Previous Data During Conversion 4 twi tw1 R C N tai 4 t tai t lt w2 w2 gt BUSY N 1 th A N 2 th gi er ta2 tas le o taii tas ke lati STATUS External DATACLK No more No more SDATA 748 0 po b TAG 0 Nth Data mesh Gale TG 0 TAG 0 EXT INT tied high CS and TAG are tied low twi tsu1 starts READ Figure 34 Basic Conversion Timing External DATACLK 20 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s ADS8517 ADS8517 I TEXAS INSTRUMENTS www ti com SLAS527 SEPTEMBER 2008 id tout tai tai BUSY n A NC r tae tas 1 ie tati gt J tas le STATUS EEST e t Pi Hisus t k conv a acg d toe tsu1 External tw3 Re twa IK DATACLK 9M 1N 2N 8N 4N 5 N 10 11 12 13 14 15 s SYNC 0 te Se lae s Nth Conversion Data DATA UUTE EO OOS E Eb E E GE TAG IILI SSE OKOXOOD EXT INT tied high CS tied low DADA AID AD TIDU gt tw1 tsu1 starts READ Figure 35
49. the ADS8517 and initiate 1000 conversions The digital output of the converter varies in output codes because of the internal noise of the ADS8517 This variance is true for all 16 bit SAR converters The transition noise specification found in the Electrical Characteristics section is a statistical figure that represents the one sigma limit or rms value of these output codes Using a histogram to plot the output codes the distribution should appear bell shaped with the peak of the bell curve representing the nominal output code for the input voltage value The 10 20 and 30 distributions represent 68 3 95 5 and 99 7 respectively of all codes Multiplying the transition noise TN by 6 yields the 80 distribution or 99 7 of all codes Statistically up to three codes could fall outside the five code distribution when executing 1000 conversions The ADS8517 has a TN of 0 8 LSBs which yields five output codes for a 30 distribution Figure 43 shows 16 384 conversion histogram results 7FFD 7FFE 7FFF 8000 8001 8002 8003 Figure 43 Histogram of 16 384 Conversions with Vy 0 V in 10 V Bipolar Range AVERAGING The noise of the converter can be compensated by averaging the digital codes By averaging conversion results transition noise is reduced by a factor of 1 4n where n is the number of averages For example averaging four conversion results reduces the TN by 1 2 to 0 4 LSBs Averaging should only be used for input signals with f
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51. w 41 43 ns tco Cycle time external DATACLK 35 ns tw3 Pulse duration external DATACLK high 15 ns tw4 Pulse duration external DATACLK low 15 ns tsu1 Setup time R C rise fall to external DATACLK high 15 ns tsu2 Setup time R C transition to CS transition 10 ns tag Delay time data valid from external DATCLK high 2 25 40 ns tag Delay time CS rising edge to external DATACLK rising edge 15 ns lato Delay time previous data available after CS R C low 1 8 2 2 us tsu3 Setup time BUSY transition to first external DATACLK 5 ns tai Delay time final external DATACLK to BUSY rising edge 825 ns tsud Setup time TAG valid before rising edge of DATACLK 2 ns tht Hold time TAG valid after rising edge of DATACLK 2 ns cs e 40 R C NN L a E tag EGNED GE EA URN DCZ tsu US tsui tsu1 JA re tsu1 External KJ Ur External X oa NJ DATACLK DATACLK CS Set Low Discontinuous Ext DATACLK R C Set Low Discontinuous Ext DATACLK cs E BUSY X IR e a Pae _ iia External 1 s RC RN K DATACLK A NJ KEE CS Set Low Discontinuous Ext DATACLK Figure 32 Critical Timing Parameters Copyright O 2008 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link s 4058517 ADS8517 i I TEXAS INSTRUMENTS SLAS527 SEPTEMBER 2008 www ti com tut ql tut 9 R C N 2 tai t tai te t Eu gt 4 we gt BUSY N 1 th N 2 th feo taz ke t tas p ke tas gt d2 k

TEXAS INSTRUMENTS ADS8517 Manual

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