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ANALOG DEVICES - AD650 handbook

1. PIN 1 gt 0 100 254 BSC 0 320 8 13 0 765 19 43 MAX 0 290 7 37 0 200 5 08 MA 0 060 1 52 im 0 015 0 38 A PN A za Van Usa 0 150 k 3 81 0 200 5 08 MIN 0 125 3 18 SEATING 0 015 0 38 D ale 0 070 1 78 PLANE 0 008 0 20 0 023 0 58 0 030 0 76 0 014 0 36 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 23 14 Lead Side Brazed Ceramic Dual In Line Package SBDIP D 14 Dimensions shown in inches and millimeters 0 775 19 69 0 750 19 05 0 735 18 67 0 280 7 11 0 250 6 35 0 24 0 060 T9 0 19 95 533 0 130 3 30 0 115 2 92 ers S 0 38 0 015 0 i 0 130 3 30 Mi GAUGE DAIO 270 0 014 0 36 0 110 2 79 TN SEATING NE PLANE L 6888 020 0 022 0 56 4 0 005 0 13 0 430 Maa 032 92 0 018 0 46 ER WN 019 MAX 0 014 0 36 0 070 1 78 0 050 1 27 0 045 1 14 COMPLIANT TO JEDEC STANDARDS MS 001 AA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS Figure 24 14 Lead Plastic Dual In Line Package PDIP N 14 Dimensions shown in inches and millimeters Rev D Page 19 of 20 AD650 AD650 0 048 1 22 0
2. 00797 006 Vs INPUT 20kQ OFFSET TRIM 15V O VLocic DIGITAL GROUND 00797 003 Figure 4 Connection Diagram for V F Conversion Positive Input Voltage 00797 007 I tos e T4 Figure 8 Voltage Across Cir Rev D Page 7 of 20 AD650 The positive input voltage develops a current Im Vin Ruy that charges the integrator capacitor Cmr As charge builds up on the output voltage of the integrator ramps downward towards ground When the integrator output voltage Pin 1 crosses the comparator threshold 0 6 V the comparator triggers the one shot whose time period tos is determined by the one shot capacitor Cos Specifically the one shot time period is tos Cos x6 8x10 sec F 3 0x10 sec 1 The reset period is initiated as soon as the integrator output voltage crosses the comparator threshold and the integrator ramps upward by an amount dV t AV tos x 1 I 2 o n ce mA 14 0 After the reset period has ended the device starts another integration period as shown in Figure 8 and starts ramping downward again The amount of time required to reach the comparator threshold is given as os imA Iy AV Cir ImA T1 1 3 dt The output n yu DEN S OUT to T tg x1mA 4 FxHz Vin Cos 44x10 0 15 Note that Cnr the integration capacitor has no effect on the t
3. 042 1 07 0 050 042 1 07 IDENTIFIER H 157 Topview Bsc 0 048 1 22 0 042 1 07 PINS DOWN 1 0 180 4 57 0 165 4 19 0 056 1 42 0 042 1 07 0 20 0 51 0 020 0 50 MIN R 3 0 021 0 53 0 013 0 33 0 33 8 38 0 032 0 81 0 290 7 37 F 0 026 0 66 BOTTOM HBD i VIEW 4g PINS UP 0 020 a p o a E a 0 045 1 14 0 51 0 356 9 04 0 025 10 G4 R Al 0 350 5999 ES 0 025 0 64 0 120 3 04 0 395 10 03 SQ L 0 090 2 29 0 385 9 78 COMPLIANT TO JEDEC STANDARDS MO 047 AA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 25 20 Lead Plastic Leaded Chip Carrier PLCC P 20A Dimensions shown in inches and millimeters ORDERING GUIDE Gain Tempco 1 MHz Temperature Package Model 100 kHz Linearity Range Package Description Option AD650JN 150 typ 0 1 typ 0 C to 70 C 14 Lead Plastic Dual In Line Package PDIP N 14 AD650JNZ 150 typ 0 196 typ 0 C to 70 C 14 Lead Plastic Dual In Line Package PDIP N 14 AD650KN 150 typ 0 1 max 0 C to 70 C 14 Lead Plastic Dual In Line Package PDIP N 14 AD650KNZ 1 04196 m 4 Le amp d PlastigsQua i e P N 14 AD650JP 1 96t 20 Lead Plafic Leg PL P 20A AD650JPZ 0 96t Pla i 20 AD650AD 150 max 0 1 typ 25 C to 85 C 14 Lea
4. MHz in addition to having very high linearity 2 Can be configured to accommodate bipolar unipolar or differential input voltages or unipolar input currents 3 TTLor CMOS compatibility is achieved by using an open collector frequency output The pull up resistor can be connected to voltages up to 30 V 4 same components used for V F conversion can also be used for F V conversion by adding a simple logic biasing network and reconfiguring the AD650 5 Separate analog and digital grounds prevent ground loops in real world applications 6 Available in versions compliant with MIL STD 883 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD650 TABLE OF CONTENTS Features 1 Functional Block Diagram seen 1 Product Description seen 1 Product Highlights eerte 1 REVISION A 2 Specifications ee pe ta er o i MOERS 3 Absolute Maximum Ratings eene 5 ESD Ca tion ice ete nettes 5 Pin Configurations and Function Descriptions 6 Circuit Operation pa eire 7 Unipolar Configuration a 7 Component Selection sees 8 Bipolar VIE HERE RR 10 Unipolar V F Negative Input Voltage revsion M WAL BDI 3 06
5. Rev C to Rev D Updated Format e dre Universal Changes to Product Highlights a 1 Changes to Tables diss sts ehe hetero ien eet 3 Added Pin Function Descriptions Table oo cesses 6 Updated Outline Dimensions see 18 Changes to Ordering Guide sse 19 E UTE High Frequency Operation sse Decoupling and Grounding sss Temperature Coefficients ssssseeeeeenten Nonlinearity Specification seen Other Circuit Considerations sse Applications tete see teg iv tet OR eer usai Differential Voltage to Frequency Conversion AUtOZero CITCUIE eie teer tei best e eitis Phase Locked Loop F V Conversion ee Outline DiIMensIions a nedentenenenenenei eee PH Ordering Glide eter ie diea C com AD Rev D Page 2 of 20 SPECIFICATIONS T 25 C Vs 15 V unless otherwise noted AD650 Table 1 AD650J AD650A AD650K AD650B AD650S Model Min Typ Max Min Typ Max Min Typ Max Units DYNAMIC PERFORMANCE Full Scale Frequency Range 1 1 1 MHz Nonlinearity 10 kHz 0 002 0 005 0 002 0 005 0 002 0 005 fmax 100 kHz 0 005 0 02 0 005 0 02 0 005 0 02 500 kHz 0 02 0 05 0 02 0 05 0 02 0 05 fmax 1 MHz 0 1 0 05 0 1 0 05 0 1 Full Scale Calibration Error 100 kHz 5 5 5 1 MH
6. activated by connecting a 1 24 kQ resistor between Pin 4 and the negative supply The resulting current delivered to the op amp noninverting input is nominally 0 5 mA and has a tolerance of 10 This current is then used to provide an offset voltage when Pin 2 is tied to ground through a resistor The 0 5 mA that appears at Pin 2 is also flowing through the 1 24 resistor An external resistor is used to activate the bipolar offset current source to provide the lowest tolerance and temperature drift of the resulting offset voltage It is possible to use other values of resistance between Pin 4 and Vs to obtain a bipolar offset current different from 0 5 mA Figure 19 shows the relationship between the bipolar offset current and the value of the resistor used to activate the source pA BIPOLAR OFFSET CURRENT o 1 3500 4000 00797 020 Figure 19 Bipolar Offset Current vs External Resistor Rev D Page 15 of 20 AD650 APPLICATIONS DIFFERENTIAL VOLTAGE TO FREQUENCY CONVERSION The circuit in Figure 20 accepts a true floating differential input signal The common mode input Voy can be in the range 15 V to 5 V with respect to analog ground The signal input Vin can be 5 V with respect to the common mode input Both inputs are low impedance the source that drives the common mode input must supply the 0 5 mA drawn by the bipolar offset current source and the source that drives the signal input m
7. desired output signal and not a voltage In this case the AD650 offers compact size and wide dynamic range FREQUENCY OUTPUT COMPARATOR FREQUENCY OUTP 0 1 00797 022 15V 15V GND Figure 21 Autozero Circuit D TYPE FLIP FLOP D PR INPUT CARRIER INPUT Q CARRIER 1 2 7474 2 AD650 1MHz FULL SCALE Riy 16 9k Cos 51pF Cir 1000pF UNIPOLAR INPUT Q4 1 2 7474 ij CLOCK CLEAR 13 4 ae 1 1 1 4 7400 D PR CLEAR C R 51pF 140kQ SD211 DMOSFET 71 5kQ VOLTS INPUT TO AD650 FIV VOLTAGE OUTPUT 00797 023 Figure 22 Phase Locked Loop F V Conversion Rev D Page 17 of 20 AD650 In signal recovery applications of a PLL the desired output signal is the voltage applied to the oscillator In these situations a linear relationship between the input frequency and the output voltage is desired the AD650 makes a superb oscillator for FM demodulation The wide dynamic range and outstanding linearity of the AD650 VFC allow simple embodiment of high performance analog signal isolation or telemetry systems The circuit shown in Figure 22 uses a digital phase detector that also provides proper feedback in the event of unequal frequencies Such phase frequency detectors PFDs are available in integrated form For a full discussion of phase lock loop circuits see Phase Lock Techniques 3 Edition by EM Gardner John W
8. resistor it should be chosen to limit the current through the output transistor to 8 mA ifa TTL maximum Vor of 0 4 V is desired For example if a 5 V logic supply is used R2 should be no smaller than 5 V 8 mA or 625 A larger value can be used if desired Rm and Cos are the only two parameters available to set the full scale frequency to accommodate the given signal range The swing variable that is affected by the choice of Rw and Cos is nonlinearity The selection guides of Figure 9 and Figure 10 show this quite graphically In general larger values of Cos and lower full scale input currents higher values of Rx provide better linearity In igure 10 the implications of es of R are shown h unipolar 4 ion the results r a N ignal ranges Fora wi frequency of 100 kHz corresponding to 10 V input among the available choices Rin 20 and Cos 620 pF gives the lowest nonlinearity 0 0038 In addition the highest frequency that gives the 20 ppm minimum nonlinearity is approximately 33 kHz 40 2 kO and 1000 pF For input signal spans other than 10 V the input resistance must be scaled proportionately For example if 100 is called out for a 0 V to 10 V span 10 kO would be used with a 0 V to 1 V span or 200 kO with a 10 V bipolar connection The last component to be selected is the integration capacitor Cir In almost all cases the best value for can be calculated
9. than 10 kHz dynamic errors become much more important than the static drift of the dc reference Ata full scale TC For exa ale fi 2 0 k and Cos 330 p t g icd 80 50 ppm C but at an ambient temperature near 125 C the gain TC tends to be more positive and is typically 15 50 ppm C This information is presented in a graphical form in Figure 15 The gain TC always tends to become more positive at higher temperatures Therefore it is possible to adjust the gain TC of the AD650 by using a one shot capacitor with an appropriate TC to cancel the drift of the circuit For example consider the 100 kHz full scale frequency An average drift of 100 ppm C means that as temperature is increased the circuit produces a lower frequency in response to a given input voltage This means that the one shot capacitor must decrease in value as temperature increases in order to compensate the gain TC of the AD650 that is the capacitor must have a TC of 100 ppm C Now consider the 1 MHz full scale frequency TEMPERATURE C 50 75 100kHz GAIN TC ppm C 1MHz 00797 016 Figure 15 Gain TC vs Temperature AD650 It is not possible to achieve much improvement in performance unless the expected ambient temperature range is known For example in a constant low temperature application such as gathering data in an Arctic climate approximately 20 C a Cos with a drift of 310 ppm C is c
10. used in isolated analog signal transmission applications phased locked loop circuits and precision stepper motor speed controllers In the F V mode the AD650 can be used in precision tachometer and FM demodulator circuits The input signal range and full scale output frequency are user programmable with two external capacitors and one resistor Input offset voltage can be trimmed to zero with an external potentiometer Rev D Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM OFFSET NULL OFFSET NULL Vs BIPOLAR OFFSET 4 CURRENT DIGITAL s GND ONE S HOT COMPARATOR INPUT FourPUT 00797 001 NC NO CONNECT Figure 1 The AD650JN and AD650KN are offered in plastic 14 lead DIP packages The AD650JP is available in a 20 lead plastic leaded chip carrier PLCC Bot ceramic packages The ADGSOSD i is specified for the full 55 C to 125 C extended temperature range PRODUCT HIGHLIGHTS 1 Can operate at full scale output frequencies up to 1
11. 0 100 100 nA Voltage Range 0 36 0 36 0 36 V Rev D Page 3 of 20 AD650 AD650J AD650A AD650K AD650B AD650S Model Min Typ Max Min Typ Max Min Typ Max Units AMPLIFIER OUTPUT F V CONVERSION Voltage Range 1500 O Min Load Resistance 0 10 0 10 0 10 V Source Current 750 O Max Load Resistance 10 10 10 mA Capacitive Load Without Oscillation 100 100 100 pF POWER SUPPLY Voltage Rated Performance 9 18 9 18 9 18 V Quiescent Current 8 8 8 mA TEMPERATURE RANGE Rated Performance N Package 0 70 0 70 25 85 25 85 55 125 C Nonlinearity is defined as deviation from a straight line from zero to full scale expressed as a fraction of full scale Full scale calibration error adjustable to zero 3 Measured at full scale output frequency of 100 kHz Refer to F V conversion section of the text 5 Referred to digital ground Specifications shown in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing quality levels All min and max specifications are guaranteed although only those shown in boldface are tested on all production units ww BDI C com Rev D Page 4 of 20 AD650 ABSOLUTE MAXIMUM RATINGS Parameter Rating Stresses above those listed under Absolute Maximum Ratings Total Supply Voltage 36V may cause permanent damage to the device This is a s
12. 240 NOTES 1 Voy IS THE COMMON MODE INPUT 15V TO 5V WITH RESPECT TO ANALOG GROUND 2 Vin IS THE SIGNAL INPUT 5 WITH RESPECT TO Voy 00797 021 Figure 20 Differential Input Rev D Page 16 of 20 PHASE LOCKED LOOP F V CONVERSION Although the F V conversion technique shown in Figure 13 is quite accurate and uses only a few extra components it is very limited in terms of signal frequency response and carrier feed through If the carrier or input frequency changes instantaneously then the output cannot change very rapidly due to the integrator time constant formed by Cmr and Ruy While it is possible to decrease the integrator time constant to provide faster settling of the F to V output voltage the carrier feedthrough then becomes larger For signal frequency response in excess of 2 kHz a phase locked F V conversion technique such as the one shown in Figure 22 is recommended INPUT VOLTAGE O CONTROL INPUT 5 VOLTS o VFC NORMAL GND AUTO ZERO AD650 In a phase locked loop circuit the oscillator is driven to a frequency and phase equal to an input reference signal In applications such as a synthesizer the oscillator output frequency is first processed through a programmable divide by N before being applied to the phase detector as feedback Here the oscillator frequency is forced to be equal to N times the reference frequency It is this frequency output that is the
13. ANALOG DEVICES Voltage to Frequency and Frequency to Voltage Converter AD650 FEATURES V F conversion to 1 MHz Reliable monolithic construction Very low nonlinearity 0 002 typ at 10 kHz 0 005 typ at 100 kHz 0 07 typ at 1 MHz Input offset trimmable to zero CMOS or TTL compatible Unipolar bipolar or differential V F V F or F V conversion Available in surface mount MIL STD 883 compliant versions available PRODUCT DESCRIPTION The AD650 V F V voltage to frequency or frequency to voltage converter provides a combination of high frequency I and low nonlinearity previously The inhere t M F d the AD650 A flexible infit voltage and current formats to be used and an open collector output with separate digital ground allows simple interfacing to either standard logic families or opto couplers The linearity error of the AD650 is typically 20 ppm 0 00296 of full scale and 50 ppm 0 00596 maximum at 10 kHz full scale This corresponds to approximately 14 bit linearity in an analog to digital converter circuit Higher full scale frequencies or longer count intervals can be used for higher resolution conversions The AD650 has a useful dynamic range of six decades allowing extremely high resolution measurements Even at 1 MHz full scale linearity is guaranteed less than 1000 ppm 0 196 on the AD650KN BD and SD grades In addition to analog to digital conversion the AD650 can be
14. D NC 3 NC 3 e Foureur 5 INPUT ONE SHOT COMPARATOR CAPACITOR 00797 011 NC NO CONNECT Figure 3 P 20A Pin Configuration Pin No D 14 N 14 P 20A Mnemonic Description 1 2 Vour Output of Operational Amplifier The operational amplifier along with is used in the integrate stage of the V to F conversion 2 3 IN Positive Analog Input 3 4 IN Negative Analog Input 4 6 BIPO gn Chi nt Source This can be used jn conjggcti an external UR Psistdfto remove t e Aims ofi 5 Vs Power Suply In 6 ONE Was he Ca Cos is deter e time period CAPACITOR for the one shot 7 1 5 7 10 11 15 17 NC No Connect 8 12 Foureur Frequency Output from AD650 9 13 COMPARATOR INPUT Input to Comparator When the input voltage reaches 0 6 V the one shot is triggered 10 14 DIGITAL GND Digital Ground 11 16 ANALOG GND Analog Ground 12 18 TVs Positive Power Supply Input 13 14 19 20 OFFSET NULL Offset Null Pins Using an external potentiometer the offset of the operational amplifier can be removed Rev D Page 6 of 20 AD650 CIRCUIT OPERATION UNIPOLAR CONFIGURATION Cint Cos INTEGRATOR The AD650 is a charge balance voltage to frequency converter In the connection diagram shown in Figure 4 or the block COMPARATOR dee diagram of Figure 5 the input signal is converted into an equivalent current by the input resistance This current is exactly balanced b
15. The first step in determining nonlinearity is to connect the endpoints of the operating range typically at 10 mV and 10 V with a straight line This straight line is then the ideal relationship that is desired from the circuit The second step is to find the difference between this line and the actual response of the circuit at a few points between the endpoints typically ten intermediate points suffices The difference between the actual and the ideal response is a frequency error measured in hertz Finally these frequency errors are normalized to the full scale frequency and expressed either as parts per million of full scale ppm or parts per hundred of full scale 96 For example a 100 kHz full scale if the maximum frequency error is 5 Hz the nonlinearity is specified as 50 ppm or 0 005 Typically on the 100 kHz scale the nonlinearity is positive and the maximum value occurs at about midscale Figure 16 At higher full scale frequencies 500 kHz to 1 MHz the nonlinearity becomes S shaped and the maximum value can be either positive or negative Typically on the 1 MHz scale Rm 16 9 kO Cos 51 pF the nonlinearity is positive below about 2 3 scale and is negative above this point This is shown graphically in Figure 17 Rev D Page 13 of 20 AD650 OUTPUT FREQUENCY Hz OUTPUT FREQUENCY Hz PSRR 100k 100 ACTUAL 50 IDEAL 10mV 10V INPUT VOLTAGE Figure 16 Exaggera
16. alled for in order to compensate the gain drift of the AD650 However if that circuit should see an ambient temperature of 75 C then the Cos capacitor would change the gain TC from approximately 0 ppm to 310 ppm C The temperature effects of these components are the same when the AD650 is configured for negative or bipolar input voltages and for F V conversion as well NONLINEARITY SPECIFICATION The linearity error of the AD650 is specified by the endpoint method That is the error is expressed in terms of the deviation from the ideal voltage to frequency transfer relation after calibrating the converter at full scale and zero The nonlinearity varies with the choice of one shot capacitor and input resistor see Figure 10 Verification of the linearity specification requires the availability of a switchable voltage source or a DAC having a linearity error below 20 ppm and the use of very long measurement intervals to minimize count uncertainties Every AD650 is automatically tested for linearity and it is not usually necessary to perform this verification i it is required to incoming quality automated bench top tester proves usefuf Such a system based on Analog Devices LTS 2010 is described in V F Converters Demand Accurate Linearity Testing by L DeVito Electronic Design March 4 1982 The voltage to frequency transfer relation is shown in Figure 16 and Figure 17 with the nonlinearity exaggerated for clarity
17. d Side Brazed Ceramic Dual In Line Package SBDIP D 14 AD650BD 150 max 0 196 max 25 C to 85 C 14 Lead Side Brazed Ceramic Dual In Line Package SBDIP D 14 AD650SD 200 max 0 1 max 55 C to 125 C 14 Lead Side Brazed Ceramic Dual In Line Package SBDIP D 14 AD650SD 883B 200 max 0 1 max 55 C to 125 C 14 Lead Side Brazed Ceramic Dual In Line Package SBDIP D 14 AD650ACHIPS Die 17 Pb free part 2006 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners C00797 0 3 06 D ANALOG DEVICES Rev D Page 20 of 20 www analog com
18. ference into sensitive analog circuits The best solution to these problems is proper bypassing of the logic supply at the AD650 package A 1 uF to 10 tantalum capacitor should be connected directly to the supply side of the pull up resistor and to the digital ground Pin 10 The pull up resistor should be connected directly to the frequency output Pin 8 The lead lengths on the bypass capacitor and the pull up resistor should be as short as possible The capacitor supplies or absorbs the current transients and large ac signals flows in a physically small loop through the capacitor pull up resistor and frequency output transistor It is important that the loop be physically small for two reasons first there is less self inductance if the wires are short and second the loop does not radiate RFI efficiently The digital ground Pin 10 should be separately connected to the power supply ground Note that the leads to the digital power supply are only carrying dc current and cannot radiate RFI There can also be a dc ground drop due to the difference in currents returned on the analog and digital grounds This does not cause any problem In fact the AD650 tolerates as much as 0 25 V dc potential difference between the analog and digital grounds These features greatly ease power distribution and ground management in large systems Proper technique for grounding requires separate digital and analog ground returns to the power supply A
19. ge across the total signal range must be equated to the maximum input voltage in the unipolar configuration In other words the value of the input resistor Ri is determined by the input voltage span not the maximum input voltage A diode from Pin 1 to ground is also recommended This is further discussed in the Other Circuit Considerations section As the unipolar circuit Rx and Cos must have low temperature coefficients to minimize the overall gain drift The 1 24 resistor used to activate the 0 5 mA offset current should also have a low temperature coefficient The bipolar offset current has a temperature coefficient of approximately 200 ppm C Figure 12 shows i negative input vof g t n frequency occurs at negative full scale input and zero output frequency corresponds with zero input voltage A very high impedance signal source can be used because it only drives the noninverting integrator input Typical input impedance at this terminal is 1 GO or higher For V F conversion of positive input signals using the connection diagram of Figure 4 the signal generator must be able to source the integration current to drive the AD650 For the negative V F conversion circuit of Figure 12 the integration current is drawn from ground through and R3 and the active input is high impedance Circuit operation for negative input voltages is very similar to positive input unipolar conversion described in the Unipolar Co
20. iley amp Sons Inc 1979 An analysis of this circuit must begin at the 7474 Dual D flip flop When the input carrier matches the output carrier in both phase and frequency the Q outputs of the flip flops rise at exactly the same time With two zeros and then two ones on the inputs of the exclusive or XOR gate the output remains low keeping the DMOS FET switched off Also the NAND gate goes low resetting the flip flops to zero Throughout this entire cycle the DMOS integrator gate remains off allowing the voltage at the integrator output to remain unchanged from the previous cycle However if the input carrier leads the output carrier by a few degrees the gate is turned for the time span that t i low during the integrator causinWfits increases the frequency of the AD650 slightly driying the system towards synchronization In a similar manner if the input carrier lags the output carrier the integrator is forced down slightly to synchronize the two signals Using a mathematical approach the 25 uA pulses from the phase detector are incorporated into the phase detector gain Ka 25 i 4x10 amperes radian 9 Also the V F converter is configured to produce 1 MHz in response to a 10 V input so its gain Ko is 6 i K Hz radians 10 10V volt xsec The dynamics of the phase relationship between the input and output signals can be characterized as a second order system with natu
21. ks 1 mA to the negative supply There is no pulldown stage at the output other than the 1 mA current source used for the V to F conversion The op amp sources a great deal of current from the positive supply and it is internally protected by current limiting The output of the op amp can be driven to within 3 V of the positive supply when it is not sourcing external current When sourcing 10 mA the output voltage can be driven to within 6 V of the positive supply A third difference between this op amp and a normal device is that the inverting input Pin 3 is bias current compensated and the noninverting input is not bias current compensated The bias current at the inverting input is nominally zero but can be as much as 20 nA in either direction The noninverting input typically has a bias current of 40 nA that always flows into the node an npn input transistor Therefore it is not possible to match input voltage drops due to bias currents by matching input resistors The op amp has provisions for trimming the input offset voltage A potentiometer of 20 kO is connected from Pin 13 to Pin 14 and the wiper is connected to the positive supply through a 250 resistor A potential of about 0 6 V is established across the 250 resistor and the 3 uA current is current required 15 Very technique is shown in the Applications section of this data sheet the autozero circuit uses this technique AD650 The bipolar offset current is
22. log grounds are provided on the AD650 The emitter of the open collector frequency output transistor is the only node returned to the digital ground AII other signals are referred to analog ground The purpose of the two separate grounds is to allow isolation between the high precision analog signals and the digital section of the circuitry currents associated with the frequency output signal At 1 MHz full scale it is necessary to use a pull up resistor of about 500 in order to get the rise time fast enough to provide well defined output pulses This means that from a 5 V logic supply for example the open collector output draws 10 mA This much current being switched causes ringing on long ground runs due to the self inductance of the wires For instance 20 gauge wire has an inductance of about 20 nH per inch a current of 10 mA being switched in 50 ns at the end of 12 inches of 20 gauge wire produces a voltage spike of 50 mV The separate digital ground of the AD650 easily handles these types of switching transients A problem remains from interference caused by radiation of electromagnetic energy from these fast transients Typically a voltage spike is produced by inductive switching transients these spikes can capacitively couple into other sections of the circuit Another problem is ringing of ground lines and power supply lines due to the distributed capacitance and inductance of the wires Such ringing can also couple inter
23. lso the signal ground must be referred directly to analog ground Pin 11 at the package All of the signal grounds should be tied directly to Pin 11 especially the one shot capacitor More information on proper grounding and TEMPERATURE COEFFICIENTS The drift specifications of the AD650 do not include temperature effects of any of the supporting resistors or capacitors The drift of the input resistors R1 and R3 and the timing capacitor Cos directly affect the overall temperature stability In the application of Figure 5 a 10 ppm C input resistor used with a 100 ppm C capacitor can result in a maximum overall circuit gain drift of 150 ppm C AD650A 100 ppm C Cos 10 ppm C Rw 260 ppm C In bipolar configuration the drift of the 1 24 kO resistor used to activate the internal bipolar offset current source directly affects the value of this current This resistor should be matched to the resistor connected to the op amp noninverting input Pin 2 see Figure 11 That is the temperature coefficients of these two resistors should be equal If this is the case then the effects of the temperature coefficients of the resistors cancel each other and the drift of the offset voltage developed at the op amp noninverting input is solely determined by the AD650 Under these conditions the TC of the bipolar offset voltage is typically 200 ppm C and is a maximum of 300 ppm C The offset voltage always decreases in magni
24. nfiguration section For best operating results use Equation 7 and Equation 8 in the Component Selection section F V CONVERSION The AD650 also makes a very linear frequency to voltage converter Figure 13 shows the connection diagram for F V conversion with TTL input logic levels Each time the input signal crosses the comparator threshold going negative the one shot is activated and switches 1 mA into the integrator input for a measured time period determined by Cos As the frequency increases the amount of charge injected into the integration capacitor increases proportionately The voltage across the integration capacitor is stabilized when the leakage current through R1 and R3 equals the average current being switched into the integrator The net result of these two effects is an average output voltage that is proportional to the input frequency Optimum performance can be obtained by selecting components using the same guidelines and equations listed in the Bipolar V F section For a more complete description of this application refer to Analog Devices Application Note AN 279 GH FREQUENCY engths must be kept as shof as possible especially on the one shot and integration capacitors and at the integrator summing junction In addition at maximum output frequencies above 500 kHz a 3 6 pull down resistor from Pin 1 to Vs is required see Figure 14 The additional current drawn through the pulldown
25. norm mode the SHA is in the hold mode and the hold capacitor is very large 0 1 uF which holds the AD650 offset constant for a long period of time When the circuit is in the autozero mode the SHA is in sample mode and behaves like an op amp The circuit is a variation of the classical two amplifier servo loop where the output of the device under test DUT here the DUT is the AD650 op amp is forced to ground by the feedback action of the control amplifier the SHA Because the input of the VFC circuit is connected to ground during the autozero mode the input current that can flow is determined by the offset voltage of the AD650 op amp Because the output of the integrator stage is forced to ground it is known that the voltage is not changing it is equal to ground potential Therefore if the output of the integrator is constant its input current must be zero so the offset voltage has been forced to be zero Note that the output of the DUT could have been forced to any convenient voltage er than ground All that is i knowgfto BO Na current amp the i ES ulled in Mis circuit 200 resistor is compensation for the two amplifier servo loop Two integrators in a loop require a single zero for compensation The 3 6 resistor from Pin 1 of the AD650 to the negative supply is not part of the autozero circuit but rather it is required for VFC operation at 1 MHz gputput voltage of the bias 10V ZENER 1N5
26. ral frequency wn o 0 4 1 and damping factor is _RyCK Ka 12 2 For the values shown in Figure 22 these relations simplify to a natural frequency of 35 kHz with a damping factor of 0 8 For a simple approach to determine component values for other PLL frequencies and VFC full scale voltage follow these steps 1 Determine K in units of radians per volt second from the maximum input carrier frequency fmax in hertz and the maximum output voltage Vmax K 2x Fmax o 13 Vuax 2 Calculate a value for C based upon the desired loop bandwidth fa Note that this is the desired frequency range of the output signal The loop bandwidth fn is not the maximum carrier frequency fmax The signal can be very narrow even though it is transmitted over a 1 MHz carrier CO wheres C units farads fa units hertz K units rad volt x sec 3 Calculate R to yield a damping factor of approximately 0 8 using this equation RadxQ x2 5x10 15 where R units ohms fa units hertz K units rad volt x sec If in actual operation the PLL overshoots or hunts excessively before reaching a final value the damping factor can be raised by increasing the value of R Conversely if the PLL is overdamped a smaller value of R should be used Rev D Page 18 of 20 OUTLINE DIMENSIONS 0 005 0 13 M MIN 0 080 2 gt 0 310 7 87 0 220 5 59
27. ransfer relation but merely determines the amplitude of the sawtooth signal out of the integrator One Shot Timing A key part of the preceding analysis is the one shot time period given in Equation 1 This time period can be broken down into approximately 300 ns of propagation delay and a second time segment dependent linearly on timing capacitor Cos When the one shot is triggered a voltage switch that holds Pin 6 at analog ground is opened allowing that voltage to change An internal 0 5 mA current source connected to Pin 6 then draws its current out of Cos causing the voltage at Pin 6 to decrease linearly At approximately 3 4 V the one shot resets itself thereby ending the timed period and starting the V F conversion cycle over again The total one shot time period can be written mathematically as AV Cog tos I Toate DELAY 5 DISCHARGE substituting actual values quoted in Equation 5 3 4 V x Cos to 7 300 10 6 90 _05x10 A 6 This simplifies into the timed period equation see Equation 1 COMPONENT SELECTION Only four component values must be selected by the user These are input resistance Rw timing capacitor Cos logic resistor R2 and integration capacitor Cir The first two determine the input voltage and full scale frequency while the last two are determined by other circuit considerations Of the four components to be selected R2 is the easiest to define As a pull up
28. resistor reduces the op amps output impedance and improves its transient response 00797 012 Figure 11 Connections for 5 V Bipolar V F with 0 kHz to 100 kHz TTL Output Rev D Page 10 of 20 AD650 00797 013 Figure 12 Connection Diagram for V F Conversion Negative Input Voltage 15V O 2kQ 5000 00797 014 OFFSET ADJUST ANALOG V GND PLANE DIGITAL GND O 5V oFour OMHz TO 1MHz 00797 015 Figure 14 1 MHz V F Connection Diagram Rev D Page 11 of 20 AD650 DECOUPLING AND GROUNDING It is effective engineering practice to use bypass capacitors on the supply voltage pins and to insert small valued resistors 10 O to 100 Q in the supply lines to provide a measure of decoupling between the various circuits in a system Ceramic capacitors of 0 1 uF to 1 0 uF should be applied between the supply voltage pins and analog signal ground for proper bypassing on the AD650 In addition a larger board level decoupling capacitor of 1 uF to 10 pF should be located relatively close to the AD650 on each power supply line Such precautions are imperative in high resolution data acquisition applications where users expect to exploit the full linearity and dynamic range of the AD650 Although some types of circuits can operate satisfactorily with power supply decoupling at only one location on each circuit board such practice is strongly discouraged in high accuracy analog design Separate digital and ana
29. t 100 kHz Rm 40 Cos 330 pF the PSRR is typically 80 40 ppm and at 1 MHz Rw 16 9 Cos 51 pF the PSRR is 350 50 ppm This information is summarized graphically in Figure 18 OTHER CIRCUIT CONSIDERATIONS The 2 a Pin 3 is nota i c didesigmhas been mize s of an integrator or level shift stage Consequently the voltage on the output Pin 1 must always be more positive than 2 V below the inputs Pin 2 and Pin 3 For example in the F to V conversion mode Figure 13 the noninverting input of the op amp Pin 2 is grounded which means that the output Pin 1 is not able to go below 2 V Normal operation of the circuit shown in Figure 13 never calls for a negative voltage at the output but users can imagine an arrangement calling for a bipolar output voltage for example 10 V by connecting an extra resistor from Pin 3 to a positive voltage However this does not work Care should be taken under conditions where a high positive input voltage exists at or before power up These situations can cause a latch up at the integrator output Pin 1 This is a nondestructive latch and as such normal operation can be restored by cycling the power supply Latch up can be prevented by connecting two diodes for example 1N914 or 1N4148 as shown in Figure 11 thereby preventing Pin 1 from swinging below Pin 2 Rev D Page 14 of 20 A second major difference is that the output only sin
30. ted Nonlinearity at 100 kHz Full Scale 1M 1k 1k 100 10 ACTUAL VOLTAGE TO FREQUENCY TRANSFER RELATION 600ppm 600ppm IDEAL RELATION 10mV 10V INPUT VOLTAGE Figure 17 Exaggerated Nonlinearity at 1 MHz Full Scale 10k 100k 1M FULL SCALE FREQUENCY Hz Figure 18 PSRR vs Full Scale Frequency 00797 017 00797 018 00797 019 PSRR The power supply rejection ratio is a specification of the change in gain of the AD650 as the power supply voltage is changed The PSRR is expressed in units of parts per million change of the gain per percent change of the power supply ppm For example consider a VFC with a 10 V input applied and an output frequency of exactly 100 kHz when the power supply potential is 15 V Changing the power supply to 12 5 V isa 5 V change out of 30 V or 16 7 If the output frequency changes to 99 9 kHz then the gain has changed 0 1 or 1000 ppm The PSRR is 1000 ppm divided by 16 7 which equals 60 ppm The PSRR of the AD650 is a function of the full scale operating frequency At low full scale frequencies the PSRR is determined by the stability of the reference circuits in the device and can be very effective At higher frequencies there are dynamic errors that become more important than the static reference signals and consequently the PSRR is not quite as effective The values of PSRR are typically 0 20 ppm at 10 kHz full scale frequency Rm 40 Cos 3300 pF A
31. the integrator output stage requires approximately 3 V headroom for proper operation only 0 5 V margin remains for integrating extraneous noise on the signal line A negative noise pulse at this time could saturate the integrator causing an error in signal integration Increasing Cr to 1500 pF or 2000 pF provides much more noise margin thereby eliminating this potential trouble spot ww FREQUENCY FULL SCALE 100kHz NS Kt NY AN 1000 PICAL NONLINEARITY ppm C Rev D Page 9 of 20 00797 008 Cos pF Figure 9 Full Scale Frequency vs Cos INPUT RESISTOR ONE SHOT CAPACITOR Cos pF Figure 10 Typical Nonlinearity vs Cos 00797 009 AD650 BIPOLAR V F Figure 11 shows how the internal bipolar current sink is used to provide a half scale offset for a 5 V signal range while providing a 100 kHz maximum output frequency The nominally 0 5 mA 10 offset current sink is enabled when a 1 24 resistor is connected between Pin 4 and Pin 5 Thus with the grounded 10 nominal resistance shown a 5 V offset is developed at Pin 2 Because Pin 3 must also be at 5 V the current through Rin is 10 V 40 0 25 mA at Vw 5 V and 0 mA at Vin 5 V Components are selected using the same guidelines outlined for the unipolar configuration with one alteration The volta
32. tress Storage Temperature Range 55 C to 150 C rating only functional operation of the device at these or any Differential Input Voltage 10V other conditions above those indicated in the operational Maximum Input Voltage Vs section of this specification is not implied Exposure to absolute Open Collector Output Voltage 36V maximum rating conditions for extended periods may affect Above Digital GND device reliability Current 50 mA Amplifier Short Circuit to Ground Indefinite Comparator Input Voltage Vs ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit 4 electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance a SERS NE DEVICE degradation or loss of functionality ww BDT conf Rev D Page 5 of 20 AD650 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BIBOLAR OFFSET CU Table 2 Pin Function Descriptions RRENT ONE SHOT CAPACITOR NC NO CONNECT 14 OFFSET NULL 13 OFFSET NULL COMPARATOR INPUT 8 Foureur 00797 010 Figure 2 0 14 N 14 Pin Configurations N Vs NC NC BIPOLAR OFFSET AD650 CURRENT TOP VIEW ANALOG GND NC Not to scale NC Vs DIGITAL GN
33. tude as temperature is increased Rev D Page 12 of 20 Other circuit components do not directly influence the accuracy of the VFC over temperature changes as long as their actual values are not as different from the nominal value as to preclude operation This includes the integration capacitor Cir A change in the capacitance value of Cr simply results in a different rate of voltage change across the capacitor During the integration phase see Figure 8 the rate of voltage change across Cr has the opposite effect that it does during the reset phase The result is that the conversion accuracy is unchanged by either drift or tolerance of Cmr The net effect of a change in the integrator capacitor is simply to change the peak to peak amplitude of the sawtooth waveform at the output of the integrator The gain temperature coefficient of the AD650 is not a constant value Rather the gain TC is a function of both the full scale frequency and the ambient temperature At a low full scale frequency the gain TC is determined primarily by the stability of the internal reference a buried Zener reference This low speed gain TC can be quite effective at 10 kHz full scale the gain TC near 25 C is typically 0 50 ppm C Although the gain TC changes with ambient temperature tending to be more positive at higher temperatures the drift remains within a 75 ppm C window over the entire military temperature range At full scale frequencies higher
34. using the equation x 1000 pF minimum 7 MAX When the proper value for is used the charge balance architecture of the AD650 provides continuous integration of the input signal therefore large amounts of noise and interference can be rejected If the output frequency is measured by counting pulses during a constant gate period the integration provides infinite normal mode rejection for frequencies corresponding to the gate period and its harmonics However if the integrator stage becomes saturated by an excessively large noise pulse then the continuous integration of the signal is interrupted allowing the noise to appear at the output Rev D Page 8 of 20 If the approximate amount of noise that appears on Cmr is known Vwowz then the value of Cmr can be checked using the following inequality tos x1x10 A uu 9 8 Vs o Vyoise For example consider an application calling for a maximum frequency of 75 kHz a 0 V to 1 V signal range and supply voltages of only 9 V The component selection guide of Figure 9 is used to select 2 0 for Rin and 1000 pF for Cos This results in a one shot time period of approximately 7 us Substituting 75 kHz into Equation 7 yields a value of 1300 pF for Cmr When the input signal is near zero 1 mA flows through the integration capacitor to the switched current sink during the reset phase causing the voltage across Cmr to increase by approximately 5 5 V Because
35. ust supply the integration current If less common mode voltage range is required then a lower voltage Zener can be used For example if a 5 V Zener is used the Vcw input can be in the range 10 V to 5 V If the Zener is not used at all the common mode range is 5 V with respect to analog ground If no Zener is used the 10 kO pulldown resistor is not needed and the integrator output Pin 1 is connected directly to the comparator input Pin 9 AUTOZERO CIRCUIT In order to exploit the full dynamic range of the AD650 VFC very small input voltages need to be converted For example a six decade dynamic range based on a full scale of 10 V requi accurate measusm wg to situations a wel constant offset volg 5 shifts all of the frequency readings by a few hertz However if the offset should change it is not possible to distinguish between a small change in a small input voltage and a drift of the offset voltage Therefore the usable dynamic range is less The circuit shown in Figure 21 provides automatic adjustment of the op amp offset voltage The circuit uses an AD582 sample al SI and hold amplifier to control the offset and the input voltage to the VFC is switched between ground and the signal to be measured via an AD7512DI analog switch The offset of the AD650 is adjusted by injecting a current into or drawing a current out of Pin 13 Note that only one of the offset null pins is used During the VFC
36. y an internal feedback current delivered in short timed bursts from the switched 1 mA internal current source These bursts of current can be thought of as precisely AD650 Q 1 20 defined packets of charge The required number of charge tosl e packets each producing one pulse of the output transistor Vs depends upon the amplitude of the input signal Because the number of charge packets delivered per unit time is dependent on the input signal amplitude a linear voltage to frequency transformation is accomplished The frequency output is furnished via an open collector transistor Figure 5 Block Diagram A more rigorous analysis demonstrates how the charge balance voltage to frequency conversion takes place A block diagram of the device arranged as a V to F converter is shown in Figure 5 The unit is comprised of an input integrator a current source and steering switch a comparator and a one Vg shot When the output of the one shot is low the current 00797 005 Figure 6 Reset Mode steering switch S diverts all the curre us es amp this isa off peri 4 t has been WAUN hig th f all the current to the summing junction of the op amp this is called the reset period The two different states are shown in Figure 6 and Figure 7 along with the various branch currents It should be noted that the output current from the op amp is the same for either state thus minimizing transients
37. z 10 10 10 of vs Supply 0 015 0 015 0 015 0 015 0 015 0 015 FSR V vs Temperature A B and S Grades at 10 kHz 75 75 75 ppm C at 100 kHz 150 150 200 ppm C Jand K Grades at 10 kHz 75 75 ppm C at 100 kHz 150 150 ppm C BIPOLAR OFFSET CURRENT Activated by 1 24 kQ Between C 5 0 45 C oni 0 55 mA Full Scale Step Input 1 pulse of new frequency plus 1 us 1 pulse of new frequency plus 1 us 1 pulse of new frequency plus 1 us Overload Recovery Time Step Input 1 pulse of new frequency plus 1 us 1 pulse of new frequency plus 1 us 1 pulse of new frequency plus 1 us ANALOG INPUT AMPLIFIER V F CONVERSION Current Input Range Figure 4 0 0 6 0 0 6 0 0 6 mA Voltage Input Range Figure 12 10 0 10 0 10 0 V Differential Impedance 2 MQ 10 pF 2 MQ 10 pF 2 MQ 10 pF Common Mode Impedance 1000 MQ 10 pF 1000 MQ 10 pF 1000 MQ 10 pF Input Bias Current Noninverting Input 40 100 40 100 40 100 nA Inverting Input 8 20 8 20 8 20 nA Input Offset Voltage Trimmable to Zero 4 4 4 mV vs Temperature to Tmax 30 30 30 uV C Safe Input Voltage Vs Vs Vs V COMPARATOR F V CONVERSION Logic 0 Level Vs 1 Vs 1 Vs 1 V Logic 1 Level 0 Vs 0 Vs 0 Vs V Pulse Width Range 0 1 0 3 x tos 0 1 0 3 x tos 0 1 0 3 X tos us Input Impedance 250 250 250 kQ OPEN COLLECTOR OUTPUT V F CONVERSION Output Voltage in Logic 0 Isink lt 8 MA Twin tO Tmax 0 4 0 4 0 4 V Output Leakage Current in Logic 1 10

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