intersil ISL43681/ISL43741 handbook
Contents
1. i T TTTTIT T T TT 8 Vs 5V 0 2 to 5Vp p z 3 lt 15143741 0 N ISL43681 1 3 lt tc o 2 0 n as tc ISL43681 15143741 90 0 135 2 180 R 500 1 10 100 600 FREQUENCY MHz FIGURE 18 FREQUENCY RESPONSE 10 10 V 3V to 12V or 20 Vs 52V to 5V 20 500 30 30 40 40 a S 50 50 2 x o 5 60 60 ISOLATION o 70 70 9 tc o CROSSTALK 80 80 90 90 100 100 ALL HOSTILE CROSSTALK 110 110 1k 10k 100k 1M 10M 100M 500M FREQUENCY Hz FIGURE 20 CROSSTALK AND OFF ISOLATION Die Characteristics SUBSTRATE POTENTIAL POWERED UP GND TRANSISTOR COUNT 15143681 193 15143741 193 PROCESS Si Gate CMOS NORMALIZED GAIN dB Q pC D e T TTTTTT T T T T Vs 3V Vin 0 2Vp p to 4Vp_p 1 3 15143741 GAIN 0 15143681 0 PHASE o ISL43681 45 15143741 90 a 1352 amp 180 500 1 10 100 600 FREQUENCY MHz FIGURE 19 FREQUENCY RESPONSE 5 2 5 0 2 5 5 7 5 10 12 FIGURE 21 CHARGE INJECTION vs SWITCH VOLTAGE 16 intersil ISL43681 ISL43741 Quad Flat No Lead Plast2. TEMP MIN MAX PARAMETER TEST CONDITIONS C 4 TYP NOTE 4 UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range VANALOG Full 0 V V ON Resistance RoN V 4 5V Icom 1 0mA Vyo or 3 5V 25 gt 81 90 Q See Figure 6 Full 120 Q Ron Matching Between Channels V 4 5V Icom 1 0mA Vyo or Note 5 25 2 2 4 Q ARON Full 3 6 Ron Flatness RF_LAT ON V 4 5V Icom 1 0 Vyno or 1V 2V 25 11 5 17 Q Note 6 Full 5 24 Q NO or NC OFF Leakage Current V 5 5V Vcom 1V 4 5V Vyno or 4 5V 1V 25 0 1 0 002 0 1 nA or Note 7 NO OFF OF INC OFF Full 25 25 COM OFF Leakage Current V 5 5V Voom 1V 4 5V VNo or 4 5V 1V 25 0 1 0 002 0 1 nA Note 7 COMOFF paler Full 2 5 2 5 nA COM ON Leakage Current V 5 5V Vcom Vno Or Vnc 4 5V Note 7 25 0 1 0 002 0 1 nA conn Full 2 5 2 5 nA DIGITAL INPUT CHARACTERISTICS Input Voltage High VINH VADDH Full 2 4 Input Voltage Low VADDL Full 0 8 Input Current lAppL ENH V 5 5V VApp OV or V Full 0 5 0 5 IENL Input Current IENH V 5 5V OV or V Full 1 5 1 5 Input Current IENL ITEL V 5 5V OV or V Full 4 4 6 intersil ISL43681 ISL43741 Electrical Specifications 5V Sup
3. NOTES 3 Vin Input logic voltage to configure the device in a given state A Between any two switches Leakage parameter is 100 tested at high temp and guaranteed by correlation at 25 C The algebraic convention whereby the most negative value is a minimum and the most positive a maximum is used in this data sheet ARON Ron MAX Ron MIN Flatness is defined as the difference between maximum and minimum value of on resistance over the specified analog signal range 4 intersil ISL43681 ISL43741 Electrical Specifications 12V Supply Unless Otherwise Specified Test Conditions V 10 8V to 13 2V GND OV 4V Vint 0 8V Note 3 TEMP NOTE 4 NOTE 4 PARAMETER TEST CONDITIONS C MIN TYP MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range VANALOG Full 0 5 V V ON Resistance RoN V 10 8V Icom 1 0mA or Vyc 9V 25 37 45 Q See Figure 6 Full 55 Ron Matching Between Channels V 10 8V Icom 1 0mA or Vyc Note 5 25 1 2 2 Q ARON Full 2 Ron Flatness RFLAT ON V 10 8V Icom 1 0mA Vyo or 6V 9V 25 5 7 Q pee Full 7 or OFF Leakage Current V 13 2V Vcom 1V 12V Vio or 12V 1V 25 0 1 0 002 0 1 nA INO OFF Or INC OFF N
4. Digital Control Input Connect to V for Normal NOTE Logic 0 lt 0 8V Logic 1 22 4V with V between 2 7V and Operation Connect to GND to latch the last switch state 10V X Don t Care COM Analog Switch Common Pin NO Analog Switch Normally Open Pin 15143741 ADD _ Address Input Pin LE EN EN ADDB ADDA SWITCH ON N C Internal Connection 0 1 0 X X Last Switch Selected X 0 X X X NONE X X 1 X X NONE 1 1 0 0 0 NOOA 1 1 0 0 1 NO1A NO1p 1 1 0 1 0 NO2 NO2p 1 1 0 1 1 NO34 NO3p NOTE Logic 0 lt 0 8V Logic 1 22 4V with V between 2 7V and 10V X Don t Care 2 intersil ISL43681 ISL43741 Absolute Maximum Ratings eset o e koe ds 0 3 to15V s Ae ame TUR ER 0 3 to15V V O GND iocos ket 15 to 0 3V Input Voltages EN NO NC ADD Note 1 0 3 to V 0 3V Output Voltages COM 1 0 3 to V 0 3V Continuous Current Any 30mA Peak Current NO NC or COM Pulsed 1ms 10 Duty Cycle 100mA ESD Rating HBM Per Mil STD 883 Method 3015 7 gt 2 5kV Operating Conditions Temperature Range ISL43681IR and ISIA3741IR 40 C to 85 C Thermal Information Thermal Resistance Typical Note 2 9C W 20 L
5. V 5 5V V OV ViNH VApp OV or V Full 7 7 Positive Supply Current SwitehiOnor Of Full 1 1 Electrical Specifications 3 3V Supply Test Conditions V 3 0V to 3 6V V GND 2 4V Vinu 0 8V Note 3 Unless Otherwise Specified TEMP MIN MAX PARAMETER TEST CONDITIONS C NOTE 4 TYP NOTE 4 UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range VaNALOG Full 0 V V ON Resistance RoN V 3 0 1 0mA Vyo or Vye 1 5V 25 135 155 Q See Figure 6 Full 200 Ron Matching Between Channels V 3 0V Icom 1 0mA Vno or Vic 1 5V Note 5 25 3 4 8 Q ARON Full 10 Q Ron Flatness RFLAT ON V 8 0V Icom 1 0 Vyno or 0 5V 1V 2V 25 34 40 eee Full 50 Q NO or NC OFF Leakage Current V 3 6V Voom OV 4 5V VNo or Vyc 1V 25 0 1 0 002 0 1 nA INO OFF Or INC OFF Note 7 Full 25 i 25 7 intersil ISL43681 ISL43741 Electrical Specifications 3 3V Supply Test Conditions V 3 0V to 3 6V V GND OV Vinny 2 4V Vin 0 8V Note 3 Unless Otherwise Specified Continued TEMP MIN MAX PARAMETER TEST CONDITIONS C NOTE 4 TYP NOTE 4 UNITS COM OFF Leakage Current V 8 6V Vcom OV 4 5
6. RL 500 15pF f 100kHz 25 s 92 Crosstalk Note 8 5143741 only NO 1Vrms See Figures 5 7 and 20 25 lt 110 dB All Hostile Crosstalk Note 8 25 105 dB 15143741 only POWER SUPPLY CHARACTERISTICS Power Supply Range Full 2 12 V Positive Supply Current l V 3 6V V OV Vapo OV or V Full 7 7 Positive Supply Current Switch Onor Of Full 1 1 8 intersil ISL43681 ISL43741 Test Circuits and Waveforms ISL43681 NO1 NO7 ADDA C 3V tp lt 20ns LOGIC t lt 20ns INPUT ov VNOO 50 SWITCH OUTPUT oy EN LE 15143741 1 NOO NO1 NO3 x EN aND ADDA B Logic input waveform is inverted for switches that have the opposite Repeat test for other switches C includes fixture and stray logic sense capacitance R V V T OU NO or NC Roy FIGURE 1A ENABLE tow topepr MEASUREMENT POINTS FIGURE 1B ENABLE tow toee TEST CIRCUIT 9 intersil ISL43681 ISL43741 Test Circuits and Waveforms continued Noo EN LE ISL43681 NO7 NO1 NO6 3V tr lt 20ns LOGIC tp lt 20ns ADDA C GND EN INPUT ov VNOO SWITCH ouTpuT 0V LE ISL43741 VNOx tTRANS ADDA B GND Logic input waveform is inverted for switches that have the opposite 2 Repeat test for other switches C includes fixture and stray logic
7. V 3 3V 40 60 40 v 0v 100 TT 90 772 I V4 25V 80 70 259 409 40 206 0 1 2 3 4 5 Vcom V FIGURE 12 ON RESISTANCE vs SWITCH VOLTAGE V 5 Voom V 1V ton ns V V FIGURE 14 ENABLE TURN ON TIME vs SUPPLY VOLTAGE 300 Voom V 1V V 0V 250 trans ns a e 100 50 0 2 3 4 5 6 7 8 9 10 11 12 13 V V FIGURE 16 ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE 60 V 12 1 55 V OV 50 45 zs 859C ao z o 35 30 25 C 25 40 C 20 0 2 4 6 8 10 12 FIGURE 13 ON RESISTANCE vs SWITCH VOLTAGE 200 40 C V 5V Voom V 1V 80 85 C 60 25 40 20 409C 0 V V FIGURE 15 ENABLE TURN OFF TIME vs SUPPLY VOLTAGE 250 T VcoM V 1V 200 150 trans ns 100 25 C 85 C 50 40 C 2 3 4 5 6 V V FIGURE 17 ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE 15 intersil ISL43681 ISL43741 Typical Performance Curves TA 25 C Unless Otherwise Specified Continued
8. path and GND Unlike switches with a 13V maximum supply voltage the ISL43681 and ISL43741 15V maximum supply voltage provides plenty of room for the 1096 tolerance of 12V supplies 6V or 12V single supply as well as room for overshoot and noise spikes This family of switches performs equally well when operated with bipolar or single voltage supplies The minimum 13 intersil ISL43681 ISL43741 recommended supply voltage is 2V or 2V It is important to note that the input signal range switching times and on resistance degrade at lower supply voltages Refer to the electrical specification tables and Typical Performance curves for details V and GND power the internal logic thus setting the digital switching point and level shifters The level shifters convert the logic levels to switched V and V signals to drive the analog switch gate terminals Logic Level Thresholds V and GND power the internal logic stages so V has no affect on logic thresholds This switch family is TTL compatible 0 8V and 2 4V over a V supply range of 2 7V to 10V At 12V the V p level is about 3 3V This is still below the CMOS guaranteed high output minimum level of 4V but noise margin is reduced For best results with a 12V supply use a logic family that provides greater than 4V The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails Driving the digital input
9. sense capacitance R V V LL ol OUT NO or NC Ri t FIGURE 1C ADDRESS trRANs MEASUREMENT POINTS FIGURE 1D ADDRESS TEST CIRCUIT FIGURE 1 SWITCHING TIMES 3V LOGIC OFF OFF V INPUT ON EN LE OUT oy NO or NC SWITCH AV ADDX OUTPUT 1nF Ve VouT Q AVourT X CL Repeat test for other switches FIGURE 2A Q MEASUREMENT POINTS FIGURE 2B Q TEST CIRCUIT FIGURE 2 CHARGE INJECTION 10 _imtersil ISL43681 ISL43741 Test Circuits and Waveforms continued tr lt 20ns tf lt 20ns INPUT ov SWITCH 80 OUTPUT Vour ov amp 3 15143741 ADDA B Repeat test for other switches C includes fixture and stray capacitance FIGURE MEASUREMENT POINTS FIGURE TEST CIRCUIT FIGURE 3 BREAK BEFORE MAKE TIME 11 intersil ISL43681 ISL43741 Test Circuits and Waveforms continued ty lt 20ns tmPw 3 F lt 2015 LOGIC INPUT LE 3V INPUT ADD ov gt ton toFF VNOx SWITCH NOT NOS OUTPUT N ov 00 15143741 Logic input waveform is inverted for switches that have the opposite Repeat test for other switches C includes fixture and stray logic sense capacitance R L V V _ OUT NO or NC R Ron FIGURE 4A LATCH ts ty typy MEASUREMENT POINTS FIGURE 4B LATCH ty typw TEST CIRCUIT FIGURE 4 LATCH SETUP AND HOLD TIMES SIGNAL Ro
10. their leakages will vary as the signal varies The difference in the two diode leakages to the V and V pins constitutes the analog signal path leakage current All analog leakage current flows between each pin and one of the supply terminals not to the other switch terminal This is why both sides of a given switch can show leakage currents of the same or opposite polarity There is no connection between the analog signal paths and GND Typical Performance Curves 25 C Unless Otherwise Specified 70 T 7 V 5V Vcom V 1V 60 Icom 1mA 1 50 859 Ron V V FIGURE 10 ON RESISTANCE vs SUPPLY VOLTAGE 120 3 110 1mA 100 COM 30 ANLAN 70 60 ONIN 50 90 80 70 85 C aN Z 60 50 25 40 40 C N 30 60 Vg 5V zc 50 85 C s 30 20 Vg 22V Vg 37 Ron FIGURE 11 RESISTANCE vs SWITCH VOLTAGE 14 intersil ISL43681 ISL43741 Typical Performance Curves TA 25 C Unless Otherwise Specified Continued 225 200 Icom 1mA 175 150 85 C 125 100 25 C V 2 7V 409 V 0V 75 1 _ 160 140 120 85 C 3 ps LA 25 C
11. 4 ARON Full 6 Ron Flatness AT ON Vg 4 5V Icom 2mA Vyo or Vyc 3 OV 25 7 5 9 Q Note 6 Full s 12 NO NC OFF Leakage Current Vg 5 5V Vcom 4 5 VNo or VNc 4 5V 25 0 1 0 002 0 1 nA INO OFF Or INC OFF Note 7 Full 25 25 ak COM OFF Leakage Current Vg 5 5V Vcom 4 5V VNo or VNc 4 5V 25 0 1 0 002 0 1 nA ICOM OFF PE Ful 25 25 nA COM ON Leakage Current Vg 5 5V Voom VNo OF 4 5 Note 7 25 0 1 0 002 0 1 nA ICOM ON Full 2 5 2 5 nA DIGITAL INPUT CHARACTERISTICS Input Voltage High VADDH Full 2 4 Input Voltage Low Vin_ VADDL Full 0 8 Input Current ADDH lAppL ENH Vs 9 5V Vinh VApp OV or V Full 0 5 0 5 IENL Input Current IENH Vs 5 5V VApp OV or V Full 1 5 1 5 Input Current Iw ILEL Vs 5 5V Vinh VApp OV or V Full 4 4 3 intersil 15143681 ISL43741 Electrical Specifications 5V Supply Test Conditions y 4 5V to 5 5V GND OV Vinny 2 4V 0 8V Note 3 Unless Otherwise Specified Continued TEMP NOTE 4 NOTE 4 PARAMETER TEST CONDITIONS C MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Enable Turn ON Time ton 4 5V Vyno or Vc 3 3000 C 35pF 25 5 35 50 ns Vin 0 to 3 See Figure 1 Full 60
12. V Vyno or 1V 25 0 1 0 002 0 1 nA ICOM OFF DOS Full 2 5 25 nA COM ON Leakage Current V 3 6V Vcom Or Vnc Note 7 25 0 1 0 002 0 1 nA ICOM ON Full 2 5 2 5 nA DIGITAL INPUT CHARACTERISTICS Input Voltage High VINH VADDH Full 2 4 E Input Voltage Low Vin_ VADDL Full gt 0 8 Input Current lappL ENH V 3 6V Vapo OV or V Full 0 5 0 5 IENL Input Current IENH V 3 6V OV or V Full 1 5 1 5 Input Current lent ITEL V 3 6V OV or V Full 4 4 DYNAMIC CHARACTERISTICS Enable Turn ON Time ton V 3 0V Vyno or 1 5V 3000 35pF 25 82 100 ns Vin 0 to See Figure 1 Full 120 Enable Turn OFF Time torr V 3 0V Vo or Vyc 1 5V 3000 C 35pF 25 37 50 ns Vin 0 to 3V See Figure 1 Full 60 Address Transition Time trRans V 3 0V VNo or Vyc 1 5V RL 3000 35pF 25 96 120 ns Vin 0 to See Figure 1 Full 145 m Break Before Make Time V 3 6V Vyno or Vnc 1 5V 3000 35pF Full 3 13 ns Vin 0 to 3V See Figure 3 Latch Setup Time ts See Figure 4 25 50 ns Full 60 E ns Latch Hold Time ty See Figure 4 25 0 ns Full 0 ns Latch Pulse Width twpw See Figure 4 25 30 ns Full 40 2 ns Charge Injection Q C 1 0nF OV RG 00 See Figure 2 25 0 3 1 OFF Isolation
13. d 4x4 QFN Package 45 Maximum Junction Temperature Plastic Package 150 C Maximum Storage Temperature Range 65 C to 150 C Maximum Lead Temperature Soldering 10s 300 C Lead Tips Only CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES 1 Signals on NC NO COM ADD EN EN or LE exceeding V or V are clamped by internal diodes Limit forward diode current to maximum current ratings 2 0jA is measured with the component mounted on a high effective thermal conductivity test board with direct die attach See Tech Brief TB379 for details Electrical Specifications 5V Supply Test Conditions Vgyppy 4 5V to 5 5V GND OV 2 4V Vint 0 8V Note 3 Unless Otherwise Specified TEMP NOTE 4 NOTE 4 PARAMETER TEST CONDITIONS C MIN TYP MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range VANALOG Full V V ON Resistance RoN Vs 4 5V Icom 2mA Vno or 25 44 50 Q See Figure 6 Full 80 Ron Matching Between Channels Vs 4 5 Icom 2mA or Note 5 25 1 3
14. ic Package QFN 120 4 4 Micro Lead Frame Plastic Package MLFP 20 LEAD QUAD FLAT NO LEAD PLASTIC PACKAGE COMPLIANT TO JEDEC MO 220VGGD 1 ISSUE C MILLIMETERS lt lt gt SYMBOL MIN NOMINAL MAX NOTES m gt 0 80 0 90 1 00 lii A1 0 05 071 2 gt 2 gt 2 1 00 0 20 REF 7 KR b 0 18 0 23 0 30 5 8 WL 4 00 BSC HZ 4 v D1 3 75 BSC 9 D2 1 95 2 10 2 25 7 8 AS Y Y E 4 00 BSC E1 3 75 BSC 9 E2 1 95 2 10 2 25 7 8 P Y 0 50 BSC Joy yA 0 25 ANY CA A L 0 35 0 60 0 75 8 x L1 0 15 10 EN o x N 20 2 gt lt Nd 3 gt a 5 3 P 0 60 9 lt INE 12 9 Y NI Rev 1 10 02 A y NOTES a 1 Dimensioning and tolerancing conform to ASME Y14 5 1994 Y i Y v A 2 N is the number of terminals ZA 3 Nd and Ne refer to the number of terminals on each D and E A 4 All dimensions in millimeters Angles are in degrees gt lt 5 Dimension b applies to the metallized terminal and is measured 0 between 0 15mm and 0 30mm from the terminal tip 6 The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature eal Y 7 Dimensions D2 and E2 are for the exposed pads which provide A improved electr
15. ical and thermal performance 8 Nominal dimensions are provided to assist with PCB Land Pattern Design efforts see Intersil Technical Brief TB389 Y 9 Features and dimensions A2 A3 D1 E1 P amp 0 are present when 1m Fr Y ME Anvil singulation method is used and not present for saw 7 singulation YY gt A A 10 Depending on the method of lead termination at the edge of the package a maximum 0 15mm pull back L1 maybe present L minus L1 to be equal to or greater than 0 3mm All Intersil U S products are manufactured assembled and tested utilizing 1509000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 17 intersil
16. iis Enable Turn OFF Time torr Vs 4 5V VNo or Vnc 3V 3000 35pF 25 22 35 ns Vin 0 to 3 See Figure 1 Full 40 Address Transition Time trRans Vg 2 4 5V VNo or Vnc 3 RL 3000 35pF 25 43 60 ns Vin 0 to 3 See Figure 1 Full 7 70 WE Break Before Make Time teg Vg 5 5V Vyo or Vyc RL 3000 C 35pF Full 2 7 ns Vin 0 to See Figure 3 Latch Setup Time ts See Figure 4 25 25 ns Full 35 ns Latch Hold Time ty See Figure 4 25 0 ns Full 0 ns Latch Pulse Width twpw See Figure 4 25 15 ns Full 25 ns Charge Injection Q C 1 OV RG 00 See Figure 2 25 0 3 1 pC NO NC OFF Capacitance Corr f 1MHz VNo or Vcom OV See Figure 8 25 3 COM OFF Capacitance Corr f 1MHz Vyo or Vcom OV ISL43681 25 s 21 pF Figure 8 ISL43741 25 12 pF ON Capacitance f 1MHz or Vyc Vcom OV ISL43681 25 5 26 5 pF Figure 8 ISL43741 25 18 pF OFF Isolation 500 15pF f 100kHz 25 92 dB Crosstalk Note 8 ISL43741 only NOx 1 VRMs See Figures 5 7 and 20 25 110 dB All Hostile Crosstalk Note 8 25 105 dB 15143741 only POWER SUPPLY CHARACTERISTICS Power Supply Range Full 2 6 V Positive Supply Current l Vs 5 5V VApp OV or V Switch On or Off Full sf S 7 Negative Supply Current Full 1 1
17. ing Integrator Reset Circuits 1 CAUTION These devices are sensitive to electrostatic discharge follow proper Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2003 All Rights Reserved ISL43681 ISL43741 Pinouts 15143681 QFN TOP VIEW 15143741 QFN TOP VIEW OF NO4 NO2A NO6 NO0A ADDC NO34 ADDB ADDB Truth Tables Ordering Information ISL43681 PART NO TEMP PKG m mE BRAND RANGE C PACKAGE DWG LE EN EN ADDC ADDB ADDA SWITCH 151436811 43681IR 40 85 20 Ld QFN L20 4x4 0 1 0 X X X Last Switch Selected ISLA37411R 437411IR 40 85 20 Ld QFN L20 4x4 X X X X Pin Descriptions X 1 X X X NONE 1 1 0 0 0 0 NOO PIN FUNCTION 1 1 0 0 0 1 NO1 V Positive Power Supply Input 1 1 0 0 1 0 NO2 V Negative Power Supply Input Connect to GND for Single Supply Configurations 1 0 GND Ground Connection g 1 0 0 NO4 EN Digital Control Input Connect to GND for Normal 1 1 0 1 0 1 NO5 Operation Connect to V to turn all switches off 1 1 0 1 1 0 NO6 EN Digital Control Input Connect to V for Normal Operation Connect to GND to turn all switches off 1 1 0 1 1 1 NO7 ES aay
18. intersil Data Sheet Low Voltage Single and Dual Supply 8 to 1 Multiplexer and Differential 4 to 1 Multiplexer The Intersil ISL43681 15143741 devices are precision bidirectional analog switches configured as an 8 channel and a differential 4 channel multiplexer demultiplexer They are designed to operate from a single 2V to 12V supply or from a 2V to 6V supplies The devices have an inhibit and inhibit bar pin to simultaneously open all signal paths The devices also have a latch bar pin to lock in the last switch address ON resistance of 390 with a 5V supply and 1250 with 3 3V supply Each switch can handle rail to rail analog signals The off leakage current is only 0 1nA at 25 C or 2 5nA at 85 C All digital inputs have 0 8V to 2 4V logic thresholds ensuring TTL CMOS logic compatibility when using a single 3 3V or 5V supply or dual 5V supplies The ISL43681 is a single 8 to 1 multiplexer device and the 151443741 is a diff 4 to 1 multiplexer device Table 1 summarizes the performance of these parts TABLE 1 FEATURES AT A GLANCE ISL43681 ISL43741 FN6053 September 2003 Features Fully Specified at 3 3V 5V 5V and 12V Supplies for 10 Tolerances ON Resistance Ron Vs 4 5V 500 ON Resistance Ron Max Vs 1550 Ron Matching Between Channels Vs 5V 20 e Low Charge Injection Vs 5V 1pC Max Single Supp
19. ly 2V to 12V Dual Supply Operation 2V to 6V Fast Switching Action Vs 5V P 38ns OEE Ua ata ae 19ns e Guaranteed Max Off leakage 2 5nA Guaranteed Break Before Make TTL CMOS Compatible Applications Battery Powered Handheld and Portable Equipment Communications Systems SINGLE 8 1 MUX CONFIGURATION DIFF 4 1 MUX 5V Ron 390 5V tow torrF 32ns 18ns 12V Ron 320 12V tow torr 23ns 15ns 5V RoN 650 5V tow torrF 38ns 19ns 3 3V RoN 1250 3 3V tow torE 70ns 32ns Package 20 Ld 4x4 QFN Related Literature Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices SMDs Application Note AN557 Recommended Test Procedures for Analog Switches Application Note AN520 CMOS Analog Multiplexers and Switches Specifications and Application Considerations Application Note AN1034 Analog Switch and Multiplexer Applications Radios Telecom Infrastructure ADSL VDSL Modems Test Equipment Medical Ultrasound Magnetic Resonance Image CT and PET Scanners MRI ATE Electrocardiograph Audio and Video Signal Routing Various Circuits 3V 5V DACs and ADCs Sample and Hold Circuits Operational Amplifier Gain Switching Networks High Frequency Analog Switching High Speed Multiplex
20. n V4 1mA GENERATOR OV or V OV or V FIGURE 5 OFF ISOLATION TEST CIRCUIT FIGURE 6 Ron TEST CIRCUIT 12 intersil ISL43681 ISL43741 Test Circuits and Waveforms continued SIGNAL EN LE GENERATOR ADDX 15143741 or GND FIGURE 7 CROSSTALK TEST CIRCUIT Detailed Description ISL43681 16143741 multiplexers offer precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on resistance 390 and high speed operation ton 38ns torr 19ns with dual supplies They have an inhibit and inhibit bar pin to simultaneously open all signal paths They also have a latch bar pin to lock in the last switch address The devices are especially well suited for applications using 5V supplies With 5V supplies the performance Ron Leakage Charge Injection etc is best in class High frequency applications also benefit from the wide bandwidth and the very high off isolation and crosstalk rejection Supply Sequencing And Overvoltage Protection With any CMOS device proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC All I O pins contain ESD protection diodes from the pin to V and to V see Figure 9 To prevent forward biasing these diodes V and V must be applied before any input signals and input signal
21. ote 7 Full 25 i 25 E COM OFF Leakage Current V 13 2V Voom 12V 1V Vyno or Vyc 1V 12V 25 0 1 0 002 0 1 nA ICOM OFF Full 2 5 25 nA COM ON Leakage Current V 13 2V Vcom 1V 12V Vyno or Vyc 1V 12V 25 0 1 0 002 0 1 nA ICOM ON or floating Note 7 Full 25 25 DIGITAL INPUT CHARACTERISTICS Input Voltage High VADDH Full 3 7 3 3 Input Voltage Low VINL VADDL Full 2 7 0 8 V Input Current lappL lENH V 13 2V Vinh VApp OV or V Full 0 5 0 5 IENL Input Current IENH V 13 2V OV or V Full 21 5 1 5 Input Current IgNi LEL V 13 2V VApp OV or V Full 4 4 DYNAMIC CHARACTERISTICS Enable Turn ON Time ton V 10 8V VNo or Vyc 10V RL 3000 35pF 25 24 40 ns Vin 0 to 4 See Figure 1 Full i 45 d Enable Turn OFF Time torr V 10 8V Vyno or Vyc 10V 3000 35pF 25 15 30 ns Vin 0 to 4 See Figure 1 Full 2 35 nS Address Transition Time trRans V 10 8V Vyno or Vyc 10V 3000 35pF 25 27 50 ns Vin 0 to 4 See Figure 1 Full 55 ie Break Before Make Time Delay tp V 13 2V R 3000 C 35pF Vyno or Vnc 10V Full 2 5 ns Vin 0 to 4 See Figure 3 Latch Setup Time ts See Figure 4 25 25 ns Full 35 S ns Latch Hold Time ty See Figure 4 25 0 ns Full 0 ns Latch Pulse Width twpw See Figure 4 25 15 ns Full 25 ns Cha
22. ply Unless Otherwise Specified Continued Test Conditions V 4 5V to 5 5V V GND OV Viny 2 4V Vint 0 8V Note 3 TEMP MIN MAX PARAMETER TEST CONDITIONS C NOTE 4 TYP NOTE 4 UNITS DYNAMIC CHARACTERISTICS Enable Turn ON Time ton V 4 5V VNo or Vyc 3000 35pF 25 43 60 ns Vin 0 to See Figure 1 Full 70 iis Enable Turn OFF Time torr V 4 5V VNo or 3V RL 3000 C 35pF 25 20 35 ns Vin 0 to See Figure 1 Full i 40 Address Transition Time trRans V 4 5 VNo RL 3000 C 35pF 25 51 70 ns Vin 0 to See Figure 1 Full 35 Break Before Make Time V 5 5V VNo or Vyc 3000 35pF Full 2 9 ns Vin 0 to See Figure 3 Latch Setup Time ts See Figure 4 25 25 ns Full 35 ns Latch Hold Time ty See Figure 4 25 0 ns Full 0 ns Latch Pulse Width twpw See Figure 4 25 15 s ns Full 25 ns Charge Injection Q C 1 OV RG 00 See Figure 2 25 0 6 1 5 pC OFF Isolation RL 500 15pF f 100kHz 25 92 Crosstalk Note 8 18143741 only NOx See Figures 5 7 and 20 25 lt 110 dB All Hostile Crosstalk Note 8 25 105 1 5 dB 15143741 only POWER SUPPLY CHARACTERISTICS Power Supply Range Full 2 12 V Positive Supply Current l
23. rge Injection Q C 1 0nF Vg 00 See Figure 2 25 2 7 5 5 intersil ISL43681 ISL43741 Electrical Specifications 12V Supply Unless Otherwise Specified Continued Test Conditions V 10 8V to 13 2V GND OV Vinny 4V Vint 0 8V Note 3 TEMP NOTE 4 NOTE 4 PARAMETER TEST CONDITIONS C MIN TYP MAX UNITS OFF Isolation 500 15pF f 100kHz 25 2 92 dB See Figure 5 7 and 20 Crosstalk Note 8 ISL43741 only Figu 25 5 lt 110 s dB All Hostile Crosstalk Note 8 25 105 dB 15143741 only NO or NC OFF Capacitance Corr 1MHz Vyo or Vc Vcom OV See Figure 8 25 3 COM OFF Capacitance f 1MHz VNo or Vcom OV ISL43681 25 21 See Fi 8 dE 8 ISL43741 25 12 pF ON Capacitance f 1MHz or Voom OV 15143681 25 26 pF See Figure 8 15143741 25 18 pF POWER SUPPLY CHARACTERISTICS Power Supply Range Full 2 12 V Positive Supply Current l V 13 2 VApp OV or V all channels on or Full 7 7 off Positive Supply Current Full 1 1 Electrical Specifications 5V Supply Unless Otherwise Specified Test Conditions V 4 5V to 5 5V V GND OV 2 4V Vint 0 8V Note 3
24. signals from GND to V with a fast transition time minimizes power dissipation High Frequency Performance In 50Q systems signal response is reasonably flat even past 100MHz see Figures 18 and 19 Figures 18 and 19 also illustrates that the frequency response is very consistent over varying analog signal levels An OFF switch acts like a capacitor and passes higher frequencies with less attenuation resulting in signal feed through from a switch s input to its output Off Isolation is the resistance to this feed through while Crosstalk indicates the amount of feed through from one switch to another Figure 20 details the high Off Isolation and Crosstalk rejection provided by this family At 10MHz Off Isolation is about 500 systems decreasing approximately 20dB per decade as frequency increases Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance Leakage Considerations Reverse ESD protection diodes are internally connected between each analog signal pin and both V and V One of these diodes conducts if any analog signal exceeds V or V Virtually all the analog leakage current comes from the ESD diodes to V or V Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced they are reverse biased differently Each is biased by either V or V and the analog signal This means
25. voltages must remain between V and V If these conditions cannot be guaranteed then one of the following two protection methods should be employed Logic inputs can easily be protected by adding a 1kQ resistor in series with the input see Figure 9 The resistor limits the input current below the threshold that produces permanent damage and the sub microamp input current produces an insignificant voltage drop during normal operation This method is not applicable for the signal path inputs Adding a series resistor to the switch input defeats the purpose of using a low Row switch so two small signal IMPEDANCE ANALYZER FIGURE 8 CAPACITANCE TEST CIRCUIT diodes can be added in series with the supply pins to provide overvoltage protection for all pins see Figure 9 These additional diodes limit the analog signal from 1V below V to 1V above V The low leakage current performance is unaffected by this approach but the switch resistance may increase especially at low supply voltages OPTIONAL PROTECTION RESISTOR OPTIONAL PROTECTION FOR LOGIC DIODE INPUTS OPTIONAL PROTECTION DIODE FIGURE 9 INPUT OVERVOLTAGE PROTECTION Power Supply Considerations The ISL43681 and ISL43741 construction is typical of most CMOS analog switches in that they have three supply pins V V and GND V and V drive the internal CMOS switches and set their analog voltage limits so there are no connections between the analog signal
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intersil ISL43681/ISL43741 handbook