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ALTERA MAX 7000 handbook(3)

1. Global Global Logic Array 000 Clear Clocks 1 D from i A i Parallel Logic 2 O pin ioe Expanders Fast Input Programmable ies i from other Select Register i gt macrocells ONTO NEA mes L Register Bypass ps I to I O oy e gt Control PRN Block DT Q Product e Pic Ex N Term nable LT Select Select 4D CUN m Matrix IM v VCC a uisu a ee Clear Select a Il dis T i Aeee i Shared Logic D to PIA lt 36 Signals from PIA 16 Expander Product Terms Expanders 10 Combinatorial logic is implemented in the logic array which provides five product terms per macrocell The product term select matrix allocates these product terms for use as either primary logic inputs to the OR and XOR gates to implement combinatorial functions or as secondary inputs to the macrocell s register clear preset clock and clock enable control functions Two kinds of expander product terms expanders are available to supplement macrocell logic resources Shareable expanders which are inverted product terms that are fed back into the logic array Parallel expanders which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product term allocation according to the logic requirements of the design For registered functions each macrocell flipflop c
2. Table 35 EPM71928 External Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min Max Min Max Min Max tan Array clock hold time 1 8 3 0 4 0 ns taco1 Array clock to output delay C1 35 pF 7 8 10 0 15 0 ns tacH Array clock high time 3 0 4 0 6 0 ns tac Array clock low time 3 0 4 0 6 0 ns tcppw Minimum pulse width for clear 2 3 0 4 0 6 0 ns and preset topH Output data hold time after C1 35 pF 3 1 0 1 0 1 0 ns clock tent Minimum global clock period 8 0 10 0 13 0 ns font Maximum internal global clock 4 125 0 100 0 76 9 MHz frequency tacnt Minimum array clock period 8 0 10 0 13 0 ns facnt Maximum internal array clock 4 125 0 100 0 76 9 MHz frequency fax Maximum clock frequency 5 166 7 125 0 100 0 MHz Table 36 EPM7192S Internal Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min Max Min Max Min Max tin Input pad and buffer delay 0 3 0 5 2 0 ns tio I O input pad and buffer delay 0 3 0 5 2 0 ns tein Fast input delay 3 2 1 0 2 0 ns tsexp Shared expander delay 4 2 5 0 8 0 ns tpexp Parallel expander delay 1 2 0 8 1 0 ns trap Logic array delay 3 1 5 0 6 0 ns trac Logic control array delay 3 1 5 0 6 0 ns lio Internal output enable delay 0 9 2 0 3 0 ns topi Output buffer and pad delay C1 35 pF 0 5 1 5 4 0 ns top2 Output buffer and pad delay C1 35 pF 6 1 0 2 0 5 0 ns tops Outp
3. Figure 10 MAX 7000 AC Test Conditions Power supply transients can affect AC measurements Simultaneous transitions of multiple outputs should be vec avoided for accurate measurement Threshold tests must not be performed 763 a under AC conditions Large amplitude fast ground current transients normally Device To Test Output System occur as the device outputs discharge the load capacitances When these transients flow through the parasitic inductance between the device ground 250 Q pin and the test system ground 8 06 KQ significant reductions in observable Device input noise immunity can result Numbers in ise and fall brackets are for 2 5 V devices and times 3 ns outputs Numbers without brackets are for 3 3 V devices and outputs C1 includes JIG capacitance MAX 7000 and MAX 7000E devices in OFP packages with 100 or more pins are shipped in special plastic carriers to protect the OFP leads The carrier is used with a prototype development socket and special programming hardware available from Altera This carrier technology makes it possible to program test erase and reprogram a device without exposing the leads to mechanical stress For detailed information and carrier dimensions refer to the OFP Carrier amp Development Socket Data Sheet L gt MAX 7000S devices are not shipped in carriers 25 MAX 7000 Programmable Logic Device Family Data Sheet Op erating Tables 13 throu
4. 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their re spective holders Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make chang es to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers NSAI are advised to obtain the latest version of device specifications before relying on any pub lished information and before placing orders for products or services I S EN ISO 9001 Altera Corporation
5. and are therefore compatible with both 3 3 V and 5 0 V inputs The VCCIO pins can be connected to either a 3 3 V or a 5 0 V power supply depending on the output requirements When the VCCIO pins are connected to a 5 0 V supply the output levels are compatible with 5 0 V systems When Vccjo is connected to a 3 3 V supply the output high is 3 3 V and is therefore compatible with 3 3 V or 5 0 V systems Devices operating with Vccjo levels lower than 4 75 V incur a nominally greater timing delay of top instead of top Open Drain Output Option MAX 7000S Devices Only MAX 70008 devices provide an optional open drain functionally equivalent to open collector output for each I O pin This open drain output enables the device to provide system level control signals e g interrupt and write enable signals that can be asserted by any of several devices It can also provide an additional wired OR plane Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Programming with External Hardware Altera Corporation By using an external 5 0 V pull up resistor output pins on MAX 7000S devices can be set to meet 5 0 V CMOS input voltages When Vccio is 3 3 V setting the open drain option will turn off the output pull up transistor allowing the external pull up resistor to pull the output high enough to meet 5 0 V CMOS input voltages When Veccio is 5 0 V setting the output drain option is not necessary because the pull
6. the program or verify time can be derived as a function of the TCK frequency the number of devices and specific target device s Because different ISP capable devices have a different number of EEPROM cells both the total fixed and total variable times are unique for a single device Programming a Single MAX 7000S Device The time required to program a single MAX 7000S device in system can be calculated from the following formula PROG PPULSE prc frek where tpROG Programming time tpPULSE Sum of the fixed times to erase program and verify the EEPROM cells Cycleprck Number of TCK cycles to program a device frck TCK frequency The ISP times for a stand alone verification of a single MAX 7000S device can be calculated from the following formula CycleyreK t zi VER VPULSE frog where tver Verify time typuLse Sum of the fixed times to verify the EEPROM cells Cycleyrcx Number of TCK cycles to verify a device 18 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The programming times described in Tables 6 through 8 are associated with the worst case method using the enhanced ISP algorithm Table 6 MAX 7000S teyt se amp Cycle rex Values Device Programming Stand Alone Verification fppyi se S Cyclepreg typi se S Cycleyrcx EPM7032S 4 02 342 000 0 03 200 000 EPM7064S 4 50 504 000 0 03 308 000 EPM7128S 5 11 832 000 0 03 528 000 EPM7160S
7. 0 4 5 ns tcu Global clock high time 2 5 3 0 ns teL Global clock low time 2 5 3 0 ns tasu Array clock setup time 2 5 3 0 ns tay Array clock hold time 2 0 2 0 ns taco1 Array clock to output delay C1 35 pF 6 5 7 5 ns tacH Array clock high time 3 0 3 0 ns tac Array clock low time 3 0 3 0 ns tcppw Minimum pulse width for clear and 3 3 0 3 0 ns preset topH Output data hold time after clock C1 35 pF 4 1 0 1 0 ns tont Minimum global clock period 6 6 8 0 ns font Maximum internal global clock 5 151 5 125 0 MHz frequency tACNT Minimum array clock period 6 6 8 0 ns facnt Maximum internal array clock 5 151 5 125 0 MHz frequency fmax Maximum clock frequency 6 200 166 7 MHz Altera Corporation 31 MAX 7000 Programmable Logic Device Family Data Sheet Table 20 MAX 7000 amp MAX 7000E Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade 6 Speed Grade 7 Unit Min Max Min Max tin Input pad and buffer delay 0 4 0 5 ns tio I O input pad and buffer delay 0 4 0 5 ns tein Fast input delay 2 0 8 1 0 ns tsexp Shared expander delay 3 5 4 0 ns tpexp Parallel expander delay 0 8 0 8 ns trap Logic array delay 2 0 3 0 ns trac Logic control array delay 2 0 3 0 ns tioE Internal output enable delay 2 2 0 ns topi Output buffer and pad delay C1 2 35 pF 2 0 2 0 ns Slow slew rate off Vecig 5 0 V lopa Output buffer and pad delay C1 2 35 pF
8. 2 0 ns tFIN Fast input delay 3 4 1 0 2 0 ns tsexp Shared expander delay 3 9 5 0 8 0 ns tpexp Parallel expander delay 1 1 0 8 1 0 ns tLAD Logic array delay 2 6 5 0 6 0 ns liAC Logic control array delay 2 6 5 0 6 0 ns tio Internal output enable delay 0 8 2 0 3 0 ns topi Output buffer and pad delay C1 2 35 pF 0 5 1 5 4 0 ns top2 Output buffer and pad delay C1 35 pF 6 1 0 2 0 5 0 ns top3 Output buffer and pad delay C1 35 pF 5 5 55 8 0 ns tox Output buffer enable delay C1 35 pF 4 0 5 0 6 0 ns tzx2 Output buffer enable delay C1 35 pF 6 4 5 5 5 7 0 ns t2x3 Output buffer enable delay C1 35 pF 9 0 9 0 10 0 ns txz Output buffer disable delay C1 5pF 4 0 5 0 6 0 ns tsu Register setup time 1 1 2 0 4 0 ns ty Register hold time 1 6 3 0 4 0 ns tesu Register setup time of fast 2 4 3 0 2 0 ns input teu Register hold time of fast 0 6 0 5 1 0 ns input tap Register delay 14 2 0 1 0 ns tcomB Combinatorial delay 1 1 2 0 1 0 ns tic Array clock delay 2 9 5 0 6 0 ns ten Register enable time 2 6 5 0 6 0 ns tGLOB Global control delay 2 8 1 0 1 0 ns PRE Register preset time 2 7 3 0 4 0 ns tcin Register clear time 2 7 3 0 4 0 ns tpia PIA delay 7 3 0 1 0 20 ns li pA Low power adder 8 10 0 11 0 13 0 ns 52 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables 1 2 3 4 5 6 7 8 These values are specified under the recommended operating condition
9. 3 3 3 tco ns 4 4 4 5 4 5 5 6 6 fent MHz 151 5 151 5 125 0 125 0 100 0 90 9 90 9 Altera Corporation DS MAX7000 6 7 MAX 7000 Programmable Logic Device Family Data Sheet Table 2 MAX 7000S Device Features Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Usable gates 600 1 250 2 500 3 200 3 750 5 000 Macrocells 32 64 128 160 192 256 Logic array 2 4 8 10 12 16 blocks Maximum 36 68 100 104 124 164 user I O pins tpp ns 5 5 6 6 7 5 7 5 tsu ns 2 9 2 9 3 4 3 4 4 1 3 9 tesu ns 2 5 2 5 2 5 2 5 3 3 tco ns 3 2 3 2 4 3 9 4 7 4 7 font MHz 175 4 175 4 147 1 149 3 125 0 128 2 and More Features Open drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear preset clock and clock enable controls Programmable power saving mode for a reduction of over 50 in each macrocell Configurable expander product term distribution allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic J lead chip carrier PLCC ceramic pin grid array PGA plastic quad flat pack PQFP power quad flat pack ROFP and 1 0 mm thin quad flat pack TQFP packages Programmable security bit for protection of proprietary designs 3 3 V or 5 0 V operation MultiVolt I O interface operation allowing devices to interface with 3 3 V or 5 0 V devices MultiVolt I O operation is not available in
10. 5 35 1 001 000 0 03 640 000 EPM7192S 5 71 1 192 000 0 03 764 000 EPM7256S 6 43 1 603 000 0 03 1 024 000 Tables 7 and 8 show the in system programming and stand alone verification times for several common test clock frequencies Table 7 MAX 70008 In System Programming Times for Different Test Clock Frequencies Device frek Units 10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz EPM7032S 4 06 4 09 4 19 4 36 4 71 5 73 7 44 10 86 s EPM7064S 4 55 4 60 4 76 5 01 5 51 7 02 9 54 14 58 s EPM7128S 5 19 5 27 5 52 5 94 6 77 9 27 13 43 21 75 s EPM7160S 5 45 5 55 5 85 6 35 7 35 10 35 15 36 25 37 S EPM7192S 5 83 5 95 6 30 6 90 8 09 11 67 17 63 29 55 S EPM7256S 6 59 6 75 7 23 8 03 9 64 14 45 22 46 38 49 S Table 8 MAX 7000S Stand Alone Verification Times for Different Test Clock Frequencies Device frek Units 10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz EPM7032S 0 05 0 07 0 13 0 23 0 43 1 03 2 03 4 03 S EPM7064S 0 06 0 09 0 18 0 34 0 64 1 57 3 11 6 19 S EPM7128S 0 08 0 14 0 29 0 56 1 09 2 67 5 31 10 59 S EPM7160S 0 09 0 16 0 35 0 67 1 31 3 23 6 43 12 83 S EPM7192S 0 11 0 18 0 41 0 79 1 56 3 85 7 67 15 31 s EPM7256S 0 13 0 24 0 54 1 06 2 08 5 15 10 27 20 51 S Altera Corporation 19 MAX 7000 Programmable Logic Device Family Data Sheet Programmable Speed Power Control Output
11. Global clock setup time 3 9 7 0 11 0 ns ty Global clock hold time 0 0 0 0 0 0 ns trsu Global clock setup time of fast 3 0 3 0 3 0 ns input tru Global clock hold time of fast 0 0 0 5 0 0 ns input tco1 Global clock to output delay C1 35 pF 4 7 5 0 8 0 ns ton Global clock high time 3 0 4 0 5 0 ns teL Global clock low time 3 0 4 0 5 0 ns tasu Array clock setup time 0 8 2 0 4 0 ns tay Array clock hold time 1 9 3 0 4 0 ns taco1 Array clock to output delay C1 35 pF 7 8 10 0 15 0 ns tacH Array clock high time 3 0 4 0 6 0 ns tac Array clock low time 3 0 4 0 6 0 ns tcppw Minimum pulse width for clear 2 3 0 4 0 6 0 ns and preset topH Output data hold time after C1 2 35 pF 3 1 0 1 0 1 0 ns clock teur Minimum global clock period 7 8 10 0 13 0 ns font Maximum internal global clock 4 128 2 100 0 76 9 MHz frequency tACNT Minimum array clock period 7 8 10 0 13 0 ns facnt Maximum internal array clock 4 128 2 100 0 76 9 MHz frequency fax Maximum clock frequency 5 166 7 125 0 100 0 MHz Altera Corporation 51 MAX 7000 Programmable Logic Device Family Data Sheet Table 38 EPM72568S Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min Max Min Max Min Max tin Input pad and buffer delay 0 3 0 5 2 0 ns tio I O input pad and buffer delay 0 3 0 5
12. Shared expander delay 5 0 5 0 ns tpexp Parallel expander delay 0 8 0 8 ns li AD Logic array delay 5 0 5 0 ns liAC Logic control array delay 5 0 5 0 ns lioE Internal output enable delay 2 2 0 2 0 ns topi Output buffer and pad delay C1 35 pF 1 5 2 0 ns Slow slew rate off Vecio 5 0 V top2 Output buffer and pad delay C1 35 pF 7 2 0 2 5 ns Slow slew rate off Vccio 9 3 V top3 Output buffer and pad delay C1 35 pF 2 5 5 6 0 ns Slow slew rate on Vecio 5 0 Vor 3 3 V tzx1 Output buffer enable delay C1 35 pF 5 0 5 0 ns Slow slew rate off Vccio 5 0 V tox Output buffer enable delay C1 35 pF 7 5 5 5 5 ns Slow slew rate off Vccio 9 3 V tex3 Output buffer enable delay C1 35 pF 2 9 0 9 0 ns Slow slew rate on Vecio 5 0 Vor 3 3 V tyz Output buffer disable delay C1 5pF 5 0 5 0 ns tsu Register setup time 2 0 3 0 ns ty Register hold time 3 0 3 0 ns tesu Register setup time of fast input 2 3 0 3 0 ns teu Register hold time of fast input 2 0 5 0 5 ns tap Register delay 2 0 1 0 ns tcomB Combinatorial delay 2 0 1 0 ns tic Array clock delay 5 0 5 0 ns ten Register enable time 5 0 5 0 ns tGLOB Global control delay 1 0 1 0 ns PRE Register preset time 3 0 3 0 ns tciR Register clear time 3 0 3 0 ns tpi PIA delay 1 0 1 0 ns ti pa Low power adder 8 11 0 11 0 ns 34 Altera Corporation MAX 7000 Programmable Logic Device Fa
13. The fmax values represent the highest frequency for pipelined data 6 Operating conditions Vccjo 3 3 V 1096 for commercial and industrial use 7 For EPM7064S 5 EPM7064S 6 EPM7128S 6 EPM7160S 6 EPM7160S 7 EPM7192S 7 and EPM7256S 7 devices these values are specified for a PIA fan out of one LAB 16 macrocells For each additional LAB fan out in the devices add an additional 0 1 ns to the PIA timing value 8 The tpa parameter must be added to the f ap fj Ac tic ten tsexp tact and tcppw parameters for macrocells running in the low power mode Altera Corporation se 43 MAX 7000 Programmable Logic Device Family Data Sheet Tables 31 and 32 show the EPM7128S AC operating conditions Table 31 EPM7128S External Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 6 7 10 15 Min Max Min Max Min Max Min Max tpp1 Input to non registered output C1 35 pF 6 0 7 5 10 0 15 0 ns tpp2 I O input to non registered C1 35 pF 6 0 7 5 10 0 15 0 ns output tsu Global clock setup time 3 4 6 0 7 0 11 0 ns ty Global clock hold time 0 0 0 0 0 0 0 0 ns tesu Global clock setup time of fast 2 5 3 0 3 0 3 0 ns input tru Global clock hold time of fast 0 0 0 5 0 5 0 0 ns input tco1 Global clock to output delay C1 35 pF 4 0 4 5 5 0 8 0 ns tcu Global clock high time 3 0 3 0 4 0 5 0 ns te Global clock low time
14. following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 7 Version 6 7 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 7 W Reference to AN 88 Using the Jam Language for ISP amp ICR via an Embedded Processor has been replaced by AN 122 Using Jam STAPL for ISP amp ICR via an Embedded Processor Version 6 6 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 6 m Added Tables 6 through 8 W Added Programming Sequence section on page 17 and Programming Times section on page 18 Version 6 5 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 5 W Updated text on page 16 Version 6 4 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 4 m Added Note 5 on page 28 Version 6 3 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 3 E Updated the Open Drain Output Option MAX 7000S Devices Only section on page 20 Altera Corporation Altera Corporation 65 MAX 7000 Programmable Logic Device Family Data Sheet A DTE RYA 101 Innovation Drive San Jose CA 95134 408 544 7000 www altera com Applications Hotline 800 800 EPLD Literature Services literature altera com 66 Copyright
15. for general logic inputs W Global controls that are used for secondary register functions E Direct input paths from I O pins to the registers that are used for fast setup times for MAX 7000E and MAX 7000S devices Macrocells The MAX 7000 macrocell can be individually configured for either sequential or combinatorial logic operation The macrocell consists of three functional blocks the logic array the product term select matrix and the programmable register The macrocell of EPM7032 EPM7064 and EPM7096 devices is shown in Figure 3 Figure 3 EPM7032 EPM7064 amp EPM7096 Device Macrocell Logic Array Y fate Zh 36 Signals from PIA 16 Expander Product Terms Altera Corporation Global Global Clear Clocks From Parallel Logic HEAR Expanders Fast Input Programmable i from other Select Register macrocells Register Bypass De J To I O Control PRN Block ee p s e Product e iud T Term faute Select Select D GERN Matrix pa Clear Select a E De q i Shared Logic to PIA Expanders MAX 7000 Programmable Logic Device Family Data Sheet Figure 4 shows a MAX 7000E and MAX 7000S device macrocell Figure 4 MAX 7000E amp MAX 7000S Device Macrocell
16. has six global output enable signals that are driven by the true or complement of two output enable signals a subset of the I O pins or a subset of the I O macrocells Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 8 1 0 Control Block of MAX 7000 Devices EPM7032 EPM7064 amp EPM7096 Devices vec From Macrocell To PIA 4 MAX 7000E amp MAX 7000S Devices z Dosen pss La d see Six Global Output Enable Signals Lae M ati PIA p et VCC 3 SE Ll o e wv ND To Other I O Pins T From KS Macrocell Open Drain Output 1 e Fast Input to Macrocell 4 Slew Rate Control Register To PIA q Note 1 The open drain output option is available only in MAX 7000S devices Altera Corporation 15 MAX 7000 Programmable Logic Device Family Data Sheet In System Programma bility ISP 16 When the tri state buffer control is connected to ground the output is tri stated high impedance and the I O pin can be used as a dedicated input When the tri state buffer control is connected to Vcc the output is enabled The MAX 7000 architecture provides dual I O feedback in which macrocell and pin feedbacks are independent When an I O pin is configured as an
17. pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimum width if the clear or reset signal incorporates the tz 4r parameter into the signal path This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies for both global and array clocking These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB The fmax values represent the highest frequency for pipelined data Operating conditions Vccjo 3 3 V 10 for commercial and industrial use For EPM7064S 5 EPM7064S 6 EPM7128S 6 EPM7160S 6 EPM7160S 7 EPM7192S 7 and EPM7256S 7 devices these values are specified for a PIA fan out of one LAB 16 macrocells For each additional LAB fan out in these devices add an additional 0 1 ns to the PIA timing value The fr pA parameter must be added to the f Ap fp AC tic ten tsexp tact and tcppw parameters for macrocells running in the low power mode Tables 33 and 34 show the EPM7160S AC operating conditions Table 33 EPM7160S External Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 6 7 10 15 Min Max Min Max Min Max Min Max tpp1 Input to non registered output C1 35 pF 6 0 7 5 10 0 15
18. transition smoothly from user mode to ISP mode The enter ISP stage requires 1 ms 2 Check ID Before any program or verify process the silicon ID is checked The time required to read this silicon ID is relatively small compared to the overall programming time 3 Bulk Erase Erasing the device in system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms 4 Program Programming the device in system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells This process is repeated for each EEPROM address 5 Verify Verifying an Altera device in system involves shifting in addresses applying the read pulse to verify the EEPROM cells and shifting out the data for comparison This process is repeated for each EEPROM address 6 Exit ISP An exit ISP stage ensures that the I O pins transition smoothly from ISP mode to user mode The exit ISP stage requires 1 ms 17 MAX 7000 Programmable Logic Device Family Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements W A pulse time to erase program or read the EEPROM cells W A shifting time based on the test clock TCK frequency and the number of TCK cycles to shift instructions address and data into the device By combining the pulse and shift times for each of the programming stages
19. two sets of parallel expanders the first set includes five product terms and the second set includes four product terms increasing the total delay by 2x IpEXP Two groups of 8 macrocells within each LAB e g macrocells 1 through 8 and 9 through 16 form two chains to lend or borrow parallel expanders A macrocell borrows parallel expanders from lower numbered macrocells For example macrocell 8 can borrow parallel expanders from macrocell 7 from macrocells 7 and 6 or from macrocells 7 6 and 5 Within each group of 8 the lowest numbered macrocell can only lend parallel expanders and the highest numbered macrocell can only borrow them Figure 6 shows how parallel expanders can be borrowed from a neighboring macrocell Figure 6 Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell 36 Signals 16 Shared From Previous Macrocell N Preset j P EU Q4 Macrocell Select Product N Matrix I Term Logic L7 Clock J Clear Preset Product e Macrocell Term z L p Product Select i i Miren I Term Logic NP Clock J Clear Y To Next Macrocell from PIA Expanders Altera Corporation 13 MAX 7000 Programmable Logic Device Family Data Sheet 14 Programmable Interconnect Array L
20. 0 ns tpp2 I O input to non registered C1 35 pF 6 0 7 5 10 0 15 0 ns output tsu Global clock setup time 3 4 4 2 7 0 11 0 ns ty Global clock hold time 0 0 0 0 0 0 0 0 ns tesu Global clock setup time of fast 2 5 3 0 3 0 3 0 ns input tru Global clock hold time of fast 0 0 0 0 0 5 0 0 ns input tco1 Global clock to output delay C1 35 pF 3 9 4 8 5 8 ns ton Global clock high time 3 0 3 0 4 0 5 0 ns teL Global clock low time 3 0 3 0 4 0 5 0 ns tasu Array clock setup time 0 9 1 1 2 0 4 0 ns tan Array clock hold time NA 2 1 3 0 4 0 ns taco1 Array clock to output delay C1 35 pF 6 4 7 9 10 0 15 0 ns tacH Array clock high time 3 0 3 0 4 0 6 0 ns tac Array clock low time 3 0 3 0 4 0 6 0 ns tcppw Minimum pulse width for clear 2 2 5 3 0 4 0 6 0 ns and preset topH Output data hold time after C1 35 pF 3 1 0 1 0 1 0 1 0 ns clock teur Minimum global clock period 6 7 8 2 10 0 13 0 ns font Maximum internal global clock 4 149 3 122 0 100 0 76 9 MHz frequency 46 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 33 EPM7160S External Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 6 7 10 15 Min Max Min Max Min Max Min Max tACNT Minimum array clock period 6 7 8 2 10 0 13 0 ns fac
21. 0E devices as well as JTAG BST circuitry in devices with 128 or more macrocells ISP and an open drain output option See Table 4 Table 4 MAX 7000 Device Features Feature EPM7032 All All EPM7064 MAX 7000E MAX 7000S EPM7096 Devices Devices ISP via JTAG interface JTAG BST circuitry Open drain output option Fast input registers Six global output enables Two global clocks Slew rate control MultiVolt interface 2 Programmable register Parallel expanders Shared expanders Power saving mode Security bit S SN SAS SIAS STN Sa STN SAS SINISISISISIS PCI compliant devices available Notes 1 Available only in EPM71285 EPM7160S EPM7192S and EPM7256S devices only 2 TheMultiVolt I O interface is not available in 44 pin packages 4 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture supports 100 TTL emulation and high density integration of SSI MSI and LSI logic functions The MAX 7000 architecture easily integrates multiple devices ranging from PALs GALs and 22V10s to MACH and pLSI devices MAX 7000 devices are available in a wide range of packages including PLCC PGA PQFP ROFP and TQFP packages See Table 5 Table 5 MAX 7000 Maximum User I 0 Pins Note 1 Device 44 44 44 68 8
22. 3 0 13 0 16 0 ns font Maximum internal global clock 5 76 9 76 9 62 5 MHz frequency tACNT Minimum array clock period 13 0 13 0 16 0 ns facnt Maximum internal array clock 5 76 9 76 9 62 5 MHz frequency fax Maximum clock frequency 6 100 83 3 83 3 MHz Altera Corporation 37 MAX 7000 Programmable Logic Device Family Data Sheet Table 26 MAX 7000 amp MAX 7000E Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 15 15T 20 Min Max Min Max Min Max tin Input pad and buffer delay 2 0 2 0 3 0 ns tio I O input pad and buffer delay 2 0 2 0 3 0 ns tein Fast input delay 2 2 0 4 0 ns tsexp Shared expander delay 8 0 10 0 9 0 ns tpexp Parallel expander delay 1 0 1 0 2 0 ns tLaD Logic array delay 6 0 6 0 8 0 ns tac Logic control array delay 6 0 6 0 8 0 ns tioE Internal output enable delay 2 3 0 4 0 ns topi Output buffer and pad delay C1 35 pF 4 0 4 0 5 0 ns Slow slew rate off Vccio 5 0 V top2 Output buffer and pad delay C1 35 pF 7 5 0 6 0 ns Slow slew rate off Vccio 3 3 V tops Output buffer and pad delay C1 35 pF 2 8 0 9 0 ns Slow slew rate on Vecio 5 0 V or 3 3 V tzx1 Output buffer enable delay C1 35 pF 6 0 6 0 10 0 ns Slow slew rate off Vccio 5 0 V tzx2 Output buffer enable delay C1 35 pF 7
23. 3 0 3 0 4 0 5 0 ns tasu Array clock setup time 0 9 3 0 2 0 4 0 ns tan Array clock hold time 1 8 2 0 5 0 4 0 ns taco1 Array clock to output delay C1 35 pF 6 5 7 5 10 0 15 0 ns tAcH Array clock high time 3 0 3 0 4 0 6 0 ns tac Array clock low time 3 0 3 0 4 0 6 0 ns tcppw Minimum pulse width for clear 2 3 0 3 0 4 0 6 0 ns and preset topH Output data hold time after C1 35 pF 3 1 0 1 0 1 0 1 0 ns clock teur Minimum global clock period 6 8 8 0 10 0 13 0 ns font Maximum internal global clock 4 147 1 125 0 100 0 76 9 MHz frequency tACNT Minimum array clock period 6 8 8 0 10 0 13 0 ns TACNT Maximum internal array clock 4 147 1 125 0 100 0 76 9 MHz frequency fmax Maximum clock frequency 5 166 7 166 7 125 0 100 0 MHz 44 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 32 EPM71288S Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 6 7 10 15 Min Max Min Max Min Max Min Max tin Input pad and buffer delay 0 2 0 5 0 5 2 0 ns tio I O input pad and buffer delay 0 2 0 5 0 5 2 0 ns tein Fast input delay 2 6 1 0 1 0 2 0 ns tsexp Shared expander delay 3 7 4 0 5 0 8 0 ns tpexp Parallel expander delay 1 1 0 8 0 8 1 0 ns trap Logic array delay 3 0 3 0 5 0 6 0 ns trac Logi
24. 3 3 4 0 5 0 ns tio Internal output enable delay 0 7 0 8 1 0 2 0 ns lopi Output buffer and pad delay C1 2 35 pF 0 2 0 3 0 4 1 5 ns lop2 Output buffer and pad delay C1 35 pF 6 0 7 0 8 0 9 2 0 ns top3 Output buffer and pad delay C1 35 pF 5 2 5 3 5 4 5 5 ns lzx1 Output buffer enable delay C1235pF 4 0 4 0 4 0 5 0 ns tzx2 Output buffer enable delay C1 35 pF 6 4 5 4 5 4 5 5 5 ns tzx3 Output buffer enable delay C1 35 pF 9 0 9 0 9 0 9 0 ns tyz Output buffer disable delay C1 5pF 4 0 4 0 4 0 5 0 ns tsu Register setup time 0 8 1 0 1 3 2 0 ns ty Register hold time 1 7 2 0 2 5 3 0 ns tesu Register setup time of fast 1 9 1 8 1 7 3 0 ns input tg Register hold time of fast 0 6 0 7 0 8 0 5 ns input tap Register delay 1 2 1 6 3 9 2 0 ns tcomsB Combinatorial delay 0 9 1 4 1 4 2 0 ns tic Array clock delay 2 7 3 4 4 2 5 0 ns ten Register enable time 2 6 3 3 4 0 5 0 ns teLoB Global control delay 1 6 1 4 1 7 1 0 ns tPRE Register preset time 2 0 2 4 3 0 3 0 ns tcLR Register clear time 2 0 2 4 3 0 3 0 ns 40 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 28 EPM7032S Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max tpia PIA delay 7 14 1 1 1 4 1 0 ns li PA Low power adder 8 12 0 10 0 10 0 11 0 ns Notes to tables 1 These values are specified under the recom
25. 4 100 100 160 160 192 208 208 Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin PLCC POFP TQFP PLCC PLCC PQFP TOFP POFP PGA PGA PQFP ROFP EPM7032 36 36 36 EPM7032S 36 36 EPM7064 36 36 52 68 68 EPM7064S 36 36 68 68 EPM7096 52 64 76 EPM7128E 68 84 100 EPM7128S 68 84 84 2 100 EPM7160E 64 84 104 EPM7160S 64 84 2 104 EPM7192E 124 124 EPM7192S 124 EPM7256E 132 2 164 164 EPM7256S 164 2 164 Notes 1 When the JTAG interface in MAX 7000S devices is used for either boundary scan testing or for ISP four I O pins become JTAG pins 2 Perform a complete thermal analysis before committing a design to this device package For more information see the Operating Requirements for Altera Devices Data Sheet Altera Corporation MAX 7000 devices use CMOS EEPROM cells to implement logic functions The user configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles and can be programmed and erased up to 100 times MAX 7000 Programmable Logic Device Family Data Sheet Functional Description MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells called logic array blocks LABs Each macrocell has a programmable AND fixed OR array and a configurable register wi
26. 44 pin packages Pin compatible with low voltage MAX 7000A and MAX 7000B devices Enhanced features available in MAX 7000E and MAX 7000S devices Six pin or logic driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I O pin to macrocell registers Programmable output slew rate control Software design support and automatic place and route provided by Altera s development system for Windows based PCs and Sun SPARCstation and HP 9000 Series 700 800 workstations Altera Corporation General Description MAX 7000 Programmable Logic Device Family Data Sheet W Additional design entry and simulation support provided by EDIF 200 and 300 netlist files library of parameterized modules LPM Verilog HDL VHDL and other interfaces to popular EDA tools from manufacturers such as Cadence Exemplar Logic Mentor Graphics OrCAD Synopsys and VeriBest E Programming support Altera s Master Programming Unit MPU and programming hardware from third party manufacturers program all MAX 7000 devices The BitBlaster serial download cable ByteBlasterMVTM parallel port download cable and MasterBlaster serial universal serial bus USB download cable program MAX 70008 devices The MAX 7000 family of high density high performance PLDs is based on Altera s second generation MAX architecture Fabrica
27. 7 2 5 2 5 ns Slow slew rate off Vocio 3 3 V tops Output buffer and pad delay C1 35 pF 2 7 0 7 0 ns Slow slew rate on Vecio 5 0Vor3 3V tzx1 Output buffer enable delay C1 35 pF 4 0 4 0 ns Slow slew rate off Vecig 5 0 V tzx2 Output buffer enable delay C1 35 pF 7 4 5 4 5 ns Slow slew rate off Vocio 3 3 V lzx3 Output buffer enable delay C1 35 pF 2 9 0 9 0 ns Slow slew rate on Vccio 5 0Vor3 3V tyz Output buffer disable delay C1 5pF 4 0 4 0 ns tsu Register setup time 3 0 3 0 ns ty Register hold time 1 5 2 0 ns tesu Register setup time of fast input 2 2 5 3 0 ns tey Register hold time of fast input 2 0 5 0 5 ns tap Register delay 0 8 1 0 ns tcomsB Combinatorial delay 0 8 1 0 ns tic Array clock delay 2 5 3 0 ns ten Register enable time 2 0 3 0 ns teLoB Global control delay 0 8 1 0 ns tPRE Register preset time 2 0 2 0 ns torr Register clear time 2 0 2 0 ns tpi PIA delay 0 8 1 0 ns tip Low power adder 8 10 0 10 0 ns 32 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 21 MAX 7000 amp MAX 7000E External Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit MAX 7000E 10P MAX 7000 10 MAX 7000E 10 Min Max Min Max tpp1 Input to non registered output C1 35 p
28. 7 0 11 0 ns Slow slew rate off Vccio 3 3 V tzx3 Output buffer enable delay C1 35 pF 2 10 0 14 0 ns Slow slew rate on Vccio 5 0 Vor 3 3 V tyz Output buffer disable delay C1 5 pF 6 0 6 0 10 0 ns tsu Register setup time 4 0 4 0 4 0 ns tH Register hold time 4 0 4 0 5 0 ns tFsu Register setup time of fast input 2 2 0 4 0 ns tey Register hold time of fast input 2 2 0 3 0 ns tap Register delay 1 0 1 0 1 0 ns tcomB Combinatorial delay 1 0 1 0 1 0 ns tic Array clock delay 6 0 6 0 8 0 ns ten Register enable time 6 0 6 0 8 0 ns tGLOB Global control delay 1 0 1 0 3 0 ns PRE Register preset time 4 0 4 0 4 0 ns tcLR Register clear time 4 0 4 0 4 0 ns tpia PIA delay 2 0 2 0 3 0 ns li PA Low power adder 8 13 0 15 0 15 0 ns 38 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables 1 2 3 4 5 6 7 8 These values are specified under the recommended operating conditions shown in Table 14 See Figure 13 for more information on switching waveforms This parameter applies to MAX 7000E devices only This minimum pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimum width if the clear or reset signal incorporates the t 4p parameter into the signal path This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies
29. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 15 MAX 7000 5 0 V Device DC Operating Conditions Note 9 Symbol Parameter Conditions Min Max Unit Vin High level input voltage 2 0 Vecint 0 5 V Vit Low level input voltage 0 5 8 0 8 V Vou 5 0 V high level TTL output voltage lop 4 mA DC Vecio 4 75 V 10 24 V 3 3 V high level TTL output voltage lop 4 mA DC Vccio 3 00 V 10 24 V 3 3 V high level CMOS output lou 2 0 1 mA DC Vccio 3 0 V 10 Vccio 0 2 V voltage VoL 5 0 V low level TTL output voltage lo 12 mA DC Vecio 4 75 V 11 0 45 V 3 3 V low level TTL output voltage lo 12 mA DC Vecio 3 00 V 11 0 45 V 3 3 V low level CMOS output lo 0 1 mA DC Vccio 3 0 V 11 0 2 V voltage lj Leakage current of dedicated input Vj 0 5 to 5 5 V 11 10 10 uA pins loz I O pin tri state output off state Vi 2 0 5 to 5 5 V 11 12 40 40 uA current Table 16 MAX 7000 5 0 V Device Capacitance EPM7032 EPM7064 amp EPM7096 Devices Note 13 Symbol Parameter Conditions Min Max Unit Cin Input pin capacitance Vin 0 V f 1 0 MHz 12 pF Cio I O pin capacitance Vout 0 V f 1 0 MHz 12 pF Table 17 MAX 7000 5 0 V Device Capacitance MAX 7000E Devices Note 13 Symbol Parameter Conditions Min Max Unit Cin Input pin capacitan
30. Configuration 20 MAX 7000 devices offer a power saving mode that supports low power operation across user defined signal paths or the entire device This feature allows total power dissipation to be reduced by 50 or more because most logic applications require only a small fraction of all gates to operate at maximum frequency The designer can program each individual macrocell in a MAX 7000 device for either high speed i e with the Turbo Bit option turned on or low power i e with the Turbo Bit option turned off operation As a result speed critical paths in the design can run at high speed while the remaining paths can operate at reduced power Macrocells that run at low power incur a nominal timing delay adder tj pa for the t Ap tj Ac tic ten and tcryp tac and tcppw parameters MAX 7000 device outputs can be programmed to meet a variety of system level requirements MultiVolt 1 0 Interface MAX 7000 devices except 44 pin devices support the MultiVolt I O interface feature which allows MAX 7000 devices to interface with systems that have differing supply voltages The 5 0 V devices in all packages can be set for 3 3 V or 5 0 V I O pin operation These devices have one set of VCC pins for internal operation and input buffers VCCINT and another set for I O output drivers VCCIO The VCCINT pins must always be connected to a 5 0 V power supply With a 5 0 V Veep level input voltage thresholds are at TTL levels
31. DISOTDITS Pini2 99992g99999 Pin23 900902209009000 752 Se a Se eee 44 Pin PQFP 44 Pin PLCC g 3 SE c Sous oo009 EEEE ooo83 EEEE Cg Pint 222222202 Pin 34 LIDII 2 VO TD H m vo vo 1 0 TDO 2 1o ANTERA io GND k vo vo EPM7032 H voc vo EPM7032S E vo VO TMS EPM7064 1 0 0 EPM7064S F vorrck 2 veo vo vo 5 GND vo 10 ITIITITIITI Pin 12 9992289299929 Pin23 44 Pin TQFP Notes 1 The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices 2 Altera Corporation JTAG ports are available in MAX 7000S devices only MAX 7000 Programmable Logic Device Family Data Sheet 60 Figure 17 68 Pin Package Pin Out Diagram Package outlines not drawn to scale vO VCCIO 2 VONTDI vO Notes a x S S8 c e X adn wow Oo 52909 s5555 a o o 9eo oeo9s222699909 Onno nnn ooreosowd gneoso9ss S 59829g85 10 60 rivo n 59 vo 12 NB 88YNN 58 GND 13 57 E1VO TDO 2 14 56 Ovo 15 55 Avo 16 54 Evo 17 53 E1 vecio 18 52 Avo 19 51 Avo 20 EPM7064 50 F VO TCK 2 21 49 Ovo 22 EPM7096 48 E GND 23 47 vo 24 46 Avo 25 45 Avo 26 44 vo REMoraAMTHORBRAOLAD SS889598835955899299 ULUUumJ m OoOoooooootooooooooQ 999998992299299999 o o 8 o o9 gt g gt 68 Pin PLCC 1 The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices 2 JTAG ports are available in MAX 7000S device
32. F 10 0 10 0 ns tpp2 I O input to non registered output C1 35 pF 10 0 10 0 ns tsu Global clock setup time 7 0 8 0 ns ty Global clock hold time 0 0 0 0 ns trsu Global clock setup time of fast input 2 3 0 3 0 ns trn Global clock hold time of fast input 2 0 5 0 5 ns tco1 Global clock to output delay C1 35 pF 5 0 5 ns tcu Global clock high time 4 0 4 0 ns teL Global clock low time 4 0 4 0 ns tasu Array clock setup time 2 0 3 0 ns tan Array clock hold time 3 0 3 0 ns taco1 Array clock to output delay C1 35 pF 10 0 10 0 ns tacH Array clock high time 4 0 4 0 ns tacL Array clock low time 4 0 4 0 ns tcppw Minimum pulse width for clear and 3 4 0 4 0 ns preset topH Output data hold time after clock C1 35 pF 4 1 0 1 0 ns teur Minimum global clock period 10 0 10 0 ns font Maximum internal global clock 5 100 0 100 0 MHz frequency tacnt Minimum array clock period 10 0 10 0 ns facnt Maximum internal array clock 5 100 0 100 0 MHz frequency fax Maximum clock frequency 6 125 0 125 0 MHz Altera Corporation 33 MAX 7000 Programmable Logic Device Family Data Sheet Table 22 MAX 7000 amp MAX 7000E Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit MAX 7000E 10P MAX 7000 10 MAX 7000E 10 Min Max Min Max tin Input pad and buffer delay 0 5 1 0 ns tio I O input pad and buffer delay 0 5 1 0 ns tein Fast input delay 2 1 0 1 0 ns tsexp
33. Frequency MHz EPM7192E EPM7256E 500 750 Voc 5 0 V 90 9 MHz Voc 5 0 V Room Temperature Room Temperature 400 L 600 90 9 MHz i 300 7 yi 450 Typical loc High Speed Typical lcc High Speed Active mA Active mA 43 5 MHz 200 800 43 4 MHz Tu 4 Low Power 100 F 150 5 Low Power i 1 L L L L L I L I E 1 1 1 1 L i 0 25 50 75 100 125 0 25 50 75 100 125 Frequency MHz Frequency MHz 56 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 15 shows typical supply current versus frequency for MAX 7000S devices Figure 15 I vs Frequency for MAX 7000S Devices Part 1 of 2 EPM7032S EPM7064S Voc 5 0 V Vcc 50V 60 f Room Temperature 120 F Room Temperature 175 4 MHz 142 9 MHz Typical loc 40 a Typicallog 80 P Active mA High Speed Active mA High Speed 30 60 20 L 58 8 MHz P 56 5 MHz 10 L Low Power 20 L Low Power 1 1 1 L 1 E i 1 0 50 100 150 200 0 50 100 150 200 Frequency MHz Frequency MHz EPM7128S EPM7160S ae Voc 5 0 V Voc 5 0 V Room Temperature 300 Room Temperature 240 149 3 MHz 147 1 MHz 240 F 200 Typical loc go eee ls Typical lcc 180 Active mA High Speed Active mA 120 56 2 MHz bd 56 5 MHz 80 4 40 F Ted Low Power 60 F in Low Power i 1 1 i L 1 1 L 0 50 100 150 200 0 50 100 150 200 Frequency MHz Frequency MHz Altera Corporation 57 MAX 7000 Programmable Lo
34. PM7064S Internal Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max tFsu Register setup time of fast 1 9 1 8 3 0 3 0 ns input tFH Register hold time of fast 0 6 0 7 0 5 0 5 ns input tap Register delay 1 2 1 6 1 0 2 0 ns tcomB Combinatorial delay 0 9 1 0 1 0 2 0 ns tic Array clock delay 2 7 3 3 3 0 5 0 ns ten Register enable time 2 6 3 2 3 0 5 0 ns tGLOB Global control delay 1 6 1 9 1 0 1 0 ns tPRE Register preset time 2 0 2 4 2 0 3 0 ns lcin Register clear time 2 0 2 4 2 0 3 0 ns tpi PIA delay 7 1 1 1 3 1 0 1 0 ns li PA Low power adder 8 12 0 11 0 10 0 11 0 ns Notes to tables 1 These values are specified under the recommended operating conditions shown in Table 14 See Figure 13 for more information on switching waveforms 2 This minimum pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimum width if the clear or reset signal incorporates the fj 4p parameter into the signal path 3 This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies for both global and array clocking 4 These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB 5
35. amp MAX 7000E Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit MAX 7000E 12P MAX 7000 12 MAX 7000E 12 Min Max Min Max tin Input pad and buffer delay 1 0 2 0 ns tio I O input pad and buffer delay 1 0 2 0 ns tein Fast input delay 2 1 0 1 0 ns tsexp Shared expander delay 7 0 7 0 ns tpexp Parallel expander delay 1 0 1 0 ns tLaD Logic array delay 7 0 5 0 ns tac Logic control array delay 5 0 5 0 ns tioE Internal output enable delay 2 2 0 2 0 ns lop Output buffer and pad delay C1 35 pF 1 0 3 0 ns Slow slew rate off Vccio 5 0 V top2 Output buffer and pad delay C1 35 pF 7 2 0 4 0 ns Slow slew rate off Vccio 3 3 V tops Output buffer and pad delay C1 35 pF 2 5 0 7 0 ns Slow slew rate on Vecio 5 0Vor3 3V tzx1 Output buffer enable delay C1 35 pF 6 0 6 0 ns Slow slew rate off tzx2 Output buffer enable delay C1 35 pF 7 7 0 7 0 ns Slow slew rate off lzx3 Output buffer enable delay C1 35 pF 2 10 0 10 0 ns Slow slew rate on Vccio 5 0Vor3 3V tyz Output buffer disable delay C1 5pF 6 0 6 0 ns tsu Register setup time 1 0 4 0 ns tH Register hold time 6 0 4 0 ns tFsu Register setup time of fast input 2 4 0 2 0 ns tFH Register hold time of fast input 2 0 0 2 0 ns tap Register delay 2 0 1 0 ns tcomB Combinatorial delay 2 0 1 0 ns tic Array clock
36. an be individually programmed to implement D T JK or SR operation with programmable clock control The flipflop can be bypassed for combinatorial operation During design entry the designer specifies the desired flipflop type the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Altera Corporation Each programmable register can be clocked in three different modes W By a global clock signal This mode achieves the fastest clock to output performance B By a global clock signal and enabled by an active high clock enable This mode provides an enable on each flipflop while still achieving the fast clock to output performance of the global clock WB By an array clock implemented with a product term In this mode the flipflop can be clocked by signals from buried macrocells or I O pins In EPM7032 EPM7064 and EPM7096 devices the global clock signal is available from a dedicated clock pin GCLK1 as shown in Figure 1 In MAX 7000E and MAX 70008 devices two global clock signals are available As shown in Figure 2 these global clock signals can be the true or the complement of either of the global clock pins GCLK1 or GCLK2 Each register also supports asynchronous preset and clear functions As shown in Figures 3 and 4 the product term select matrix allocates pro
37. ation Note 74 Evaluating Power for Altera Devices The Iccr value which depends on the switching frequency and the application logic is calculated with the following equation IccINT Ax MCrTon Bx MCpgy MCron Cx MCysep x MAX x togr c The parameters in this equation are shown below MCron Number of macrocells with the Turbo Bit option turned on as reported in the MAX PLUS II Report File rpt MCpgy Number of macrocells in the device MCypsggp Total number of macrocells in the design as reported in the MAX PLUS II Report File rpt fax Highest clock frequency to the device togrc Average ratio of logic cells toggling at each clock typically 0 125 A B C Constants shown in Table 39 Altera Corporation 53 MAX 7000 Programmable Logic Device Family Data Sheet 54 Table 39 MAX 7000 I Equation Constants Device A B C EPM7032 1 87 0 52 0 144 EPM7064 1 63 0 74 0 144 EPM7096 1 63 0 74 0 144 EPM7128E 1 17 0 54 0 096 EPM7160E 1 17 0 54 0 096 EPM7192E 1 17 0 54 0 096 EPM7256E 1 17 0 54 0 096 EPM7032S 0 93 0 40 0 040 EPM7064S 0 93 0 40 0 040 EPM7128S 0 93 0 40 0 040 EPM7160S 0 93 0 40 0 040 EPM7192S 0 93 0 40 0 040 EPM7256S 0 93 0 40 0 040 This calculation provides an Icc estimate based on typical conditions using a pattern of a 16 bit loadable enabled up down counter in each LAB with no output load Actual Icc values should be ve
38. c control array delay 3 0 3 0 5 0 6 0 ns tioE Internal output enable delay 0 7 2 0 2 0 3 0 ns lopi Output buffer and pad delay C1 35 pF 0 4 2 0 1 5 4 0 ns top2 Output buffer and pad delay C1 35 pF 6 0 9 2 5 2 0 5 0 ns top3 Output buffer and pad delay C1 35 pF 5 4 7 0 5 5 8 0 ns lzx1 Output buffer enable delay C1 35 pF 4 0 4 0 5 0 6 0 ns tzx2 Output buffer enable delay C1 35 pF 6 4 5 4 5 5 5 7 0 ns tzx3 Output buffer enable delay C1 35 pF 9 0 9 0 9 0 10 0 ns tyz Output buffer disable delay C1 5pF 4 0 4 0 5 0 6 0 ns tsu Register setup time 1 0 3 0 2 0 4 0 ns ty Register hold time 1 7 2 0 5 0 4 0 ns tesy Register setup time of fast 1 9 3 0 3 0 2 0 ns input tey Register hold time of fast 0 6 0 5 0 5 1 0 ns input tap Register delay 1 4 1 0 2 0 1 0 ns tcomsB Combinatorial delay 1 0 1 0 2 0 1 0 ns tic Array clock delay 3 1 3 0 5 0 6 0 ns ten Register enable time 3 0 3 0 5 0 6 0 ns taioB Global control delay 2 0 1 0 1 0 1 0 ns tPRE Register preset time 2 4 2 0 3 0 4 0 ns tcLR Register clear time 2 4 2 0 3 0 4 0 ns tpia PIA delay 7 14 1 0 1 0 20 ns tip Low power adder 8 11 0 10 0 11 0 13 0 ns Altera Corporation 45 MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables 1 2 3 4 5 6 7 8 These values are specified under the recommended operating conditions shown in Table 14 See Figure 13 for more information on switching waveforms This minimum
39. ce Vin 0 V f 1 0 MHz 15 pF Cio I O pin capacitance Vout 0 V f 1 0 MHz 15 pF Table 18 MAX 7000 5 0 V Device Capacitance MAX 7000S Devices Note 13 Symbol Parameter Conditions Min Max Unit CiN Dedicated input pin capacitance Vin 20V f 1 0 MHz 10 pF Cio I O pin capacitance Vout 0 V f 1 0 MHz 10 pF Altera Corporation 27 MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables 1 2 3 4 5 6 7 8 9 10 11 2 13 See the Operating Requirements for Altera Devices Data Sheet Minimum DC input voltage on I O pins is 0 5 V and on 4 dedicated input pins is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for input currents less than 100 mA and periods shorter than 20 ns Numbers in parentheses are for industrial temperature range devices Vcc must rise monotonically The POR time for all 7000S devices does not exceed 300 us The sufficient Vecmr voltage level for POR is 4 5 V The device is fully initialized within the POR time after Vccyyq reaches the sufficient POR voltage level 3 3 V I O operation is not available for 44 pin packages The Vccrsp parameter applies only to MAX 7000S devices During in system programming the minimum DC input voltage is 0 3 V These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26 The parameter is measured with 50 of the outputs each sourcing the speci
40. ck delay 2 9 3 5 5 0 6 0 ns ten Register enable time 2 8 3 4 5 0 6 0 ns ia oB Global control delay 2 0 2 4 1 0 1 0 ns tPRE Register preset time 2 4 3 0 3 0 4 0 ns Altera Corporation 47 MAX 7000 Programmable Logic Device Family Data Sheet Table 34 EPM7160S Internal Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 6 7 10 15 Min Max Min Max Min Max Min Max lcin Register clear time 2 4 3 0 3 0 4 0 ns tpia PIA delay 7 1 6 2 0 1 0 2 0 ns li PA Low power adder 8 11 0 10 0 11 0 13 0 ns Notes to tables 1 Q 3 4 S 6 7 8 These values are specified under the recommended operating conditions shown in Table 14 See Figure 13 for more information on switching waveforms This minimum pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimum width if the clear or reset signal incorporates the t 4p parameter into the signal path This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies for both global and array clocking These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB The fmax values represent the highest frequency for pipelined data Operating conditions Vccjo 3 3 V 10 for comme
41. delay 5 0 5 0 ns ten Register enable time 7 0 5 0 ns tGLoB Global control delay 2 0 0 0 ns PRE Register preset time 4 0 3 0 ns tcLR Register clear time 4 0 3 0 ns tei PIA delay 1 0 1 0 ns li PA Low power adder 8 12 0 12 0 ns 36 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 25 MAX 7000 amp MAX 7000E External Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 15 15T 20 Min Max Min Max Min Max tpp1 Input to non registered output C1 35 pF 15 0 15 0 20 0 ns tpp2 I O input to non registered C1 35 pF 15 0 15 0 20 0 ns output tsu Global clock setup time 11 0 11 0 12 0 ns ty Global clock hold time 0 0 0 0 0 0 ns tesu Global clock setup time of fast 2 3 0 5 0 ns input tru Global clock hold time of fast 2 0 0 0 0 ns input tco1 Global clock to output delay C1 35 pF 8 0 8 0 12 0 ns ton Global clock high time 5 0 6 0 6 0 ns teL Global clock low time 5 0 6 0 6 0 ns tasu Array clock setup time 4 0 4 0 5 0 ns tay Array clock hold time 4 0 4 0 5 0 ns taco1 Array clock to output delay C1 35 pF 15 0 15 0 20 0 ns tacH Array clock high time 6 0 6 5 8 0 ns tac Array clock low time 6 0 6 5 8 0 ns tcppw Minimum pulse width for clear 3 6 0 6 5 8 0 ns and preset topH Output data hold time after C1 2 35 pF 4 1 0 1 0 1 0 ns clock teur Minimum global clock period 1
42. duct terms to control these operations Although the product term driven preset and clear of the register are active high active low control can be obtained by inverting the signal within the logic array In addition each register clear function can be individually driven by the active low dedicated global clear pin GCLRn Upon power up each register in the device will be set to a low state All MAX 7000E and MAX 7000S I O pins have a fast input path to a macrocell register This dedicated path allows a signal to bypass the PIA and combinatorial logic and be driven to an input D flipflop with an extremely fast 2 5 ns input setup time Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell the more complex logic functions require additional product terms Another macrocell can be used to supply the required logic resources however the MAX 7000 architecture also allows both shareable and parallel expander product terms expanders that provide additional product terms directly to any macrocell in the same LAB These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed 11 MAX 7000 Programmable Logic Device Family Data Sheet 12 Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms one from each macrocell wi
43. e 20 160 Pin Package Pin Out Diagram 62 Package outline not drawn to scale rPrmaaomMmnga re Ar Zzs270D QOQOQOOOOOOOQOQOOOO QOOOOOOOOOOOOQOOO OQOOOOOQOOOOOQOOO Geooo OOO CO QOQOQOQ_ OOo QOO9O XX93000 OC 9 9 9 QOOOOOOQOOOQOOOO GOOOOOOOOOQOOOOO 12 34567 8 9 10 11 12 13 14 15 160 Pin PGA eo JENA n 727 c o0 ADIERA EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E 160 Pin PQFP Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 21 192 Pin Package Pin Out Diagram Package outline not drawn to scale UOOOOOOOOOOOOOOOO T OQOOOOOOOOOOOOOOO R GX9 9X XX 9 9 2 eK Q99 9 o 0000 GQO999o N OQO XS M XX X9 t XX OOOO K OOOO EPM7256E OOOO I OOO Bottom OOOO H OOOO Mew OOOO 8 OOOO OQOO F O00 OOO E O00 OOO 1 O00000 GO9 99 QGOOO c GO 90 9 9 9 C C 8 9 9 9 9 9 X9 SOOOOOOOOOOOOOOOO 192 Pin PGA Figure 22 208 Pin Package Pin Out Diagram Package outline not drawn to scale Pin 1 Pin 157 Altera Corporation ccc Pin 53 AN DTE RIAN EPM7256E EPM7256S pump 208 Pin PQFP RQFP Pin 105 63 MAX 7000 Programmable Logic Device Family Data Sheet Revision History 64 The information contained in the MAX 7000 Programmable Logic Device Family Data Sheet version 6 7 supersedes information published in previous versions The
44. fied current The Io parameter refers to high level TTL or CMOS output current The parameter is measured with 50 of the outputs each sinking the specified current The Ior parameter refers to low level TTL PCI or CMOS output current When the JTAG interface is enabled in MAX 70008 devices the input leakage current on the JTAG pins is typically 60 uA Capacitance is measured at 25 C and is sample tested only The oE1 pin has a maximum capacitance of 20 pF Figure 11 shows the typical output drive characteristics of MAX 7000 devices Figure 11 Output Drive Characteristics of 5 0 V MAX 7000 Devices 150 120 Typical lo 90 Output Current mA 60 30 Vecio 5 0 V Room Temperature Vo Output Voltage V 150 120 Typical lo 90 Output Current mA 60 30 Vecio 3 8 V Room Temperature lou L L 833 4 5 1 2 Vo Output Voltage V Timing Model 28 MAX 7000 device timing can be analyzed with the Altera software with a variety of popular industry standard EDA simulators and timing analyzers or with the timing model shown in Figure 12 MAX 7000 devices have fixed internal delays that enable the designer to determine the worst case timing of any design The Altera software provides timing simulation point to point delay prediction and detailed timing analysis for a device wide performance evaluation Altera Corporation MAX 7000 Programmable Logic Device Family Da
45. for both global and array clocking These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB The fmax values represent the highest frequency for pipelined data Operating conditions Veco 3 3 V 1096 for commercial and industrial use The fr p4 parameter must be added to the f Ap fp AC tic ten tsexp tact and tcppw parameters for macrocells running in the low power mode Tables 27 and 28 show the EPM7032S AC operating conditions Table 27 EPM70328 External Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max tppi Input to non registered output C1 35 pF 5 0 6 0 7 5 10 0 ns tpp2 I O input to non registered C1 35 pF 5 0 6 0 75 10 0 ns output tsu Global clock setup time 2 9 4 0 5 0 7 0 ns ty Global clock hold time 0 0 0 0 0 0 0 0 ns tesu Global clock setup time of fast 2 5 2 5 2 5 3 0 ns input tru Global clock hold time of fast 0 0 0 0 0 0 0 5 ns input tco1 Global clock to output delay C1 35 pF 3 2 3 5 4 3 5 0 ns ton Global clock high time 2 0 2 5 3 0 4 0 ns teL Global clock low time 2 0 2 5 3 0 4 0 ns tasu Array clock setup time 0 7 0 9 1 1 2 0 ns tan Array clock hold time 1 8 2 1 2 7 3 0 ns taco1 Array clock to output delay C1 35 pF 5 4 6 6 8 2 10 0 ns tacu Array clock high time 2 5 2 5 3 0 4 0 n
46. gh 18 provide information about absolute maximum ratings recommended operating conditions operating conditions and Condit onditions capacitance for 5 0 V MAX 7000 devices Table 13 MAX 7000 5 0 V Device Absolute Maximum Ratings Note 1 Symbol Parameter Conditions Min Max Unit Voc Supply voltage With respect to ground 2 2 0 7 0 V Vi DC input voltage 2 0 7 0 V lout DC output current per pin 25 25 mA Tera Storage temperature No bias 65 150 C TAMB Ambient temperature Under bias 65 135 C Ty Junction temperature Ceramic packages under bias 150 eC PQFP and RQFP packages under bias 135 eC Table 14 MAX 7000 5 0 V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit Vecint Supply voltage for internal logic and 3 4 5 4 75 5 25 V input buffers 4 50 5 50 Vccio Supply voltage for output drivers 3 4 4 75 5 25 V 5 0 V operation 4 50 5 50 Supply voltage for output drivers 3 4 6 3 00 3 60 V 3 3 V operation 3 00 3 60 Vecisp Supply voltage during ISP 7 4 75 5 25 V Vi Input voltage 0 5 8 Vocint 0 5 V Vo Output voltage 0 Vccio V TA Ambient temperature For commercial use 0 70 C For industrial use 40 85 C Ty Junction temperature For commercial use 0 90 C For industrial use 40 105 C tn Input rise time 40 ns te Input fall time 40 ns 26
47. gic Device Family Data Sheet Figure 15 Ic vs Frequency for MAX 7000S Devices Part 2 of 2 EPM7192S EPM7256S Vcc 5 0 V Vcc 5 0 V 300 L Room Temperature rae Room Temperature 125 0 MHz 128 2 MHz 240 TR High Speed 300 High Speed Typical loc Typical loc Active mA 180 Active mA 200 dd o o bm 7 Low Power 100 F Low Power 60 F 1 1 I 1 1 1 1 1 1 ii 1 1 1 1 L L L 0 25 50 75 100 125 0 25 50 75 100 125 Frequency MHz Frequency MHz Device See the Altera web site http www altera com or the Altera Digital Pin Outs 58 Library for pin out information Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figures 16 through 22 show the package pin out diagrams for MAX 7000 devices Figure 16 44 Pin Package Pin Out Diagram Package outlines not drawn to scale S S Ss g Jono ma us 66090 woud E BEIE ooo ggpop SPERO ping SSS9S22226L2L pr ecoc92 2 586o0 nmunnmununrnrnrnmnrmnrmu 6 54 3 2 1 44 4342 41 40 VOD 9 L vo 2 VO TDI 47 39 h VO vo H 1 O TDO 2 yo r8 38 p VO TDO 2 ND L io GND Ej 10 36 B 0 vo m voc Vo H EPM7032 bi H n vo F IO 2 meres d i EPM7032S 7 E vo 2 VO TMS EPM7032 E vo vo ri 14 EPM7064 32 b vorrei 2 vo Vo TCK 2 vec g 15 EPM7064S 31 h vo vec F vo vo 416 30 h GND vo H GND vo O17 29 B 1 0 vo vo 18 19 20 2122 23 24 25 2627 28 TTT CI
48. input the associated macrocell can be used for buried logic MAX 7000S devices are in system programmable via an industry standard 4 pin Joint Test Action Group JTAG interface IEEE Std 1149 1 1990 ISP allows quick efficient iterations during design development and debugging cycles The MAX 70008 architecture internally generates the high programming voltage required to program EEPROM cells allowing in system programming with only a single 5 0 V power supply During in system programming the I O pins are tri stated and pulled up to eliminate board conflicts The pull up value is nominally 50 k34 ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in circuit test equipment before they are programmed MAX 70008 devices can be programmed by downloading the information via in circuit testers ICT embedded processors or the Altera MasterBlaster ByteBlasterMV ByteBlaster BitBlaster download cables The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable which can program and configure 2 5 V 3 3 V and 5 0 V devices Programming the devices after they are placed on the board eliminates lead damage on high pin count packages e g OFP packages due to device handling and allows devices to be reprogrammed after a system has already shipped to the field For example product upgrades can be performed in the field via software or modem In system programmi
49. lel Expander Delay Logic Array Output Output Pin Global Clock Pin Global Clock at Register Data or Enable Logic Array Output Input or I O Pin Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array Register to PIA to Logic Array Register Output to Pin 30 Combinatorial Mode i y X i lo X i dsgxp 1 tac lap lpgxp gt lcoug i i Global Clock Mode fg iia lcu i it lg g tp gt lt tsu i lu Array Clock Mode tri tach tace gt t gt e otw i W tRo ia lpia lca tpre i iulii X X ie lop Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 19 through 26 show the MAX 7000 and MAX 7000E AC operating conditions Table 19 MAX 7000 amp MAX 7000E External Timing Parameters Note 1 Symbol Parameter Conditions 6 Speed Grade 7 Speed Grade Unit Min Max Min Max tpp1 Input to non registered output C1 35 pF 6 0 7 5 ns tpp2 I O input to non registered output C1 35 pF 6 0 7 5 ns tsu Global clock setup time 5 0 6 0 ns ty Global clock hold time 0 0 0 0 ns tesu Global clock setup time of fast input 2 2 5 3 0 ns tru Global clock hold time of fast input 2 0 5 0 5 ns tco1 Global clock to output delay C1 35pF 4
50. llows the BST data to pass synchronously through a selected device EPM7128S to adjacent devices during normal device operation EPM7160S EPM7192S EPM7256S IDCODE EPM7032S Selects the IDCODE register and places it between TDI and TDO EPM7064S allowing the IDCODE to be serially shifted out of TDO EPM7128S EPM7160S EPM7192S EPM7256S ISP Instructions EPM7032S _ These instructions are used when programming MAX 7000S devices EPM7064S _ via the JTAG ports with the MasterBlaster ByteBlasterMV BitBlaster EPM7128S download cable or using a Jam File jam Jam Byte Code file jbc EPM7160S or Serial Vector Format file svf via an embedded processor or test EPM7192S _ equipment EPM7256S 22 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The instruction register length of MAX 7000S devices is 10 bits Tables 10 and 11 show the boundary scan register length and device IDCODE information for MAX 7000S devices Table 10 MAX 7000S Boundary Scan Register Length Device Boundary Scan Register Length EPM7032S 1 1 EPM7064S 1 1 EPM7128S 288 EPM7160S 312 EPM7192S 360 EPM7256S 480 Note 1 This device does not support JTAG boundary scan testing Selecting either the EXTEST or SAMPLE PRELOAD instruction will select the one bit bypass register Table 11 32 Bit MAX 7000 Device IDCODE Note 1 Device IDCODE 32 Bits Version Part Number 16 Bits Man
51. m width if the clear or reset signal incorporates the t 4p parameter into the signal path 3 This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies for both global and array clocking 4 These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB 5 The fmax values represent the highest frequency for pipelined data 6 Operating conditions Vccjo 3 3 V 10 for commercial and industrial use 7 For EPM7064S 5 EPM7064S 6 EPM7128S 6 EPM7160S 6 EPM7160S 7 EPM7192S 7 and EPM7256S 7 devices these values are specified for a PIA fan out of one LAB 16 macrocells For each additional LAB fan out in these devices add an additional 0 1 ns to the PIA timing value 8 The t p parameter must be added to the f 4p trac tic ten tsexp tact and tcppw parameters for macrocells running in the low power mode 50 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 37 and 38 show the EPM7256S AC operating conditions Table 37 EPM7256S External Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min Max Min Max Min Max tpp1 Input to non registered output C1 35 pF 15 10 0 15 0 ns tpp2 l O input to non registered C1 35 pF 7 5 10 0 15 0 ns output tsu
52. mended operating conditions shown in Table 14 See Figure 13 for more information on switching waveforms 2 This minimum pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimum width if the clear or reset signal incorporates the tz 4r parameter into the signal path 3 This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies for both global and array clocking 4 These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB 5 The fmax values represent the highest frequency for pipelined data 6 Operating conditions Vccro 3 3 V 10 for commercial and industrial use 7 For EPM7064S 5 EPM7064S 6 EPM7128S 6 EPM7160S 6 EPM7160S 7 EPM7192S 7 and EPM7256S 7 devices these values are specified for a PIA fan out of one LAB 16 macrocells For each additional LAB fan out in these devices add an additional 0 1 ns to the PIA timing value 8 The tpa parameter must be added to the f Ap fj Ac tic ten tsexp tact and tcppw parameters for macrocells running in the low power mode Tables 29 and 30 show the EPM7064S AC operating conditions Table 29 EPM7064S External Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Mi
53. mily Data Sheet Table 23 MAX 7000 amp MAX 7000E External Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit MAX 7000E 12P MAX 7000 12 MAX 7000E 12 Min Max Min Max tppi Input to non registered output C1 235 pF 12 0 12 0 ns tpp2 I O input to non registered output C1 35 pF 12 0 12 0 ns tsu Global clock setup time 7 0 10 0 ns ty Global clock hold time 0 0 0 0 ns trsu Global clock setup time of fast input 2 3 0 3 0 ns tru Global clock hold time of fast input 2 0 0 0 0 ns tco1 Global clock to output delay C1 35 pF 6 0 6 0 ns tcu Global clock high time 4 0 4 0 ns teL Global clock low time 4 0 4 0 ns tasu Array clock setup time 3 0 4 0 ns tan Array clock hold time 4 0 4 0 ns taco1 Array clock to output delay C1 35 pF 12 0 12 0 ns tacH Array clock high time 5 0 5 0 ns tac Array clock low time 5 0 5 0 ns tcppw Minimum pulse width for clear and 3 5 0 5 0 ns preset topH Output data hold time after clock C1 35 pF 4 1 0 1 0 ns tent Minimum global clock period 11 0 11 0 ns font Maximum internal global clock 5 90 9 90 9 MHz frequency tACNT Minimum array clock period 11 0 11 0 ns TACNT Maximum internal array clock 5 90 9 90 9 MHz frequency fax Maximum clock frequency 6 125 0 125 0 MHz Altera Corporation 35 MAX 7000 Programmable Logic Device Family Data Sheet Table 24 MAX 7000
54. n Max Min Max tpp1 Input to non registered output C1 35 pF 5 0 6 0 7 5 10 0 ns tpp2 I O input to non registered C1 35 pF 5 0 6 0 7 5 10 0 ns output tsu Global clock setup time 2 9 3 6 6 0 7 0 ns ty Global clock hold time 0 0 0 0 0 0 0 0 ns trsu Global clock setup time of fast 2 5 2 5 3 0 3 0 ns input tru Global clock hold time of fast 0 0 0 0 0 5 0 5 ns input tco1 Global clock to output delay C1 35 pF 3 2 4 0 4 5 5 0 ns tcu Global clock high time 2 0 2 5 3 0 4 0 ns teL Global clock low time 2 0 2 5 3 0 4 0 ns tasu Array clock setup time 0 7 0 9 3 0 2 0 ns taH Array clock hold time 1 8 2 1 2 0 3 0 ns Altera Corporation 41 MAX 7000 Programmable Logic Device Family Data Sheet Table 29 EPM7064S External Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max taco1 Array clock to output delay C1 35 pF 5 4 6 7 7 5 10 0 ns tacH Array clock high time 2 5 2 5 3 0 4 0 ns tacL Array clock low time 2 5 2 5 3 0 4 0 ns tcppw Minimum pulse width for clear 2 2 5 25 3 0 4 0 ns and preset topH Output data hold time after C1 35 pF 3 1 0 1 0 1 0 1 0 ns clock teur Minimum global clock period 5 7 74 8 0 10 0 ns font Maximum internal global clock 4 175 4 140 8 125 0 100 0 MHz frequency tACNT Minimum array clock period 5 7 7 1 8 0 10 0 ns fac
55. ng can be accomplished with either an adaptive or constant algorithm An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit Because some in circuit testers cannot support an adaptive algorithm Altera offers devices tested with a constant algorithm Devices tested to the constant algorithm have an F suffix in the ordering code The Jam Standard Test and Programming Language STAPL can be used to program MAX 7000S devices with in circuit testers PCs or embedded processor Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Altera Corporation For more information on using the Jam language refer to AN 122 Using Jam STAPL for ISP amp ICR via an Embedded Processor The ISP circuitry in MAX 7000S devices is compatible with IEEE Std 1532 specification The IEEE Std 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors Programming Sequence During in system programming instructions addresses and data are shifted into the MAX 7000S device through the TDI input pin Data is shifted out through the TDO output pin and compared against the expected data Programming a pattern into the device requires the following six ISP stages A stand alone verification of a programmed pattern involves only stages 1 2 5 and 6 1 Enter ISP The enter ISP stage ensures that the I O pins
56. nt Maximum internal array clock 4 149 3 122 0 100 0 76 9 MHz frequency fax Maximum clock frequency 5 166 7 166 7 125 0 100 0 MHz Table 34 EPM7160S Internal Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 6 7 10 15 Min Max Min Max Min Max Min Max tin Input pad and buffer delay 0 2 0 3 0 5 2 0 ns tio I O input pad and buffer delay 0 2 0 3 0 5 2 0 ns tein Fast input delay 2 6 3 2 1 0 2 0 ns tsexp Shared expander delay 3 6 4 3 5 0 8 0 ns tpexp Parallel expander delay 1 0 1 3 0 8 1 0 ns trap Logic array delay 2 8 3 4 5 0 6 0 ns trac Logic control array delay 2 8 3 4 5 0 6 0 ns tiog Internal output enable delay 0 7 0 9 2 0 3 0 ns lopi Output buffer and pad delay C1 35 pF 0 4 0 5 1 5 4 0 ns top2 Output buffer and pad delay C1 35 pF 6 0 9 1 0 2 0 5 0 ns top3 Output buffer and pad delay C1 35 pF 5 4 5 5 5 5 8 0 ns tzx1 Output buffer enable delay C1 35 pF 4 0 4 0 5 0 6 0 ns tzx2 Output buffer enable delay C1 35 pF 6 4 5 4 5 5 5 7 0 ns tzx3 Output buffer enable delay C1 35 pF 9 0 9 0 9 0 10 0 ns tyz Output buffer disable delay C1 5pF 4 0 4 0 5 0 6 0 ns tsy Register setup time 1 0 1 2 2 0 4 0 ns ty Register hold time 1 6 2 0 3 0 4 0 ns tesu Register setup time of fast 1 9 2 2 3 0 2 0 ns input tg Register hold time of fast 0 6 0 8 0 5 1 0 ns input tap Register delay 1 3 1 6 2 0 1 0 ns tcomsB Combinatorial delay 1 0 1 3 2 0 1 0 ns tic Array clo
57. nt Maximum internal array clock 4 175 4 140 8 125 0 100 0 MHz frequency fmax Maximum clock frequency 5 250 0 200 0 166 7 125 0 MHz Table 30 EPM7064S Internal Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max tin Input pad and buffer delay 0 2 0 2 0 5 0 5 ns tio I O input pad and buffer delay 0 2 0 2 0 5 0 5 ns tein Fast input delay 2 2 2 6 1 0 1 0 ns tsexp Shared expander delay 3 1 3 8 4 0 5 0 ns tpexp Parallel expander delay 0 9 1 1 0 8 0 8 ns ti AD Logic array delay 2 6 3 2 3 0 5 0 ns tac Logic control array delay 2 5 3 2 3 0 5 0 ns tioE Internal output enable delay 0 7 0 8 2 0 2 0 ns topi Output buffer and pad delay C1 2 35 pF 0 2 0 3 2 0 1 5 ns top2 Output buffer and pad delay C1 35 pF 6 0 7 0 8 2 5 2 0 ns top3 Output buffer and pad delay C1 35 pF 5 2 5 3 7 0 5 5 ns tzx1 Output buffer enable delay C1 35 pF 4 0 4 0 4 0 5 0 ns tzx2 Output buffer enable delay C1 35 pF 6 4 5 4 5 4 5 5 5 ns tzx3 Output buffer enable delay C1 35 pF 9 0 9 0 9 0 9 0 ns txz Output buffer disable delay C1 5pF 4 0 4 0 4 0 5 0 ns tsu Register setup time 0 8 1 0 3 0 2 0 ns ty Register hold time T 2 0 2 0 3 0 ns 42 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 30 E
58. ogic is routed between LABs via the programmable interconnect array PIA This global bus is a programmable path that connects any signal source to any destination on the device All MAX 7000 dedicated inputs I O pins and macrocell outputs feed the PIA which makes the signals available throughout the entire device Only the signals required by each LAB are actually routed from the PIA into the LAB Figure 7 shows how the PIA signals are routed into the LAB An EEPROM cell controls one input to a 2 input AND gate which selects a PIA signal to drive into the LAB Figure 7 PIA Routing PIA Signals While the routing delays of channel based routing schemes in masked or FPGAs are cumulative variable and path dependent the MAX 7000 PIA has a fixed delay The PIA thus eliminates skew between signals and makes timing performance easy to predict 1 0 Control Blocks The I O control block allows each I O pin to be individually configured for input output or bidirectional operation All I O pins have a tri state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or Vcc Figure 8 shows the I O control block for the MAX 7000 family The I O control block of EPM7032 EPM7064 and EPM7096 devices has two global output enable signals that are driven by two dedicated active low output enable pins OE1 and OE2 The I O control block of MAX 7000E and MAX 7000S devices
59. pport from other industry standard PC and UNIX workstation based EDA tools The software runs on Windows based PCs as well as Sun SPARCstation and HP 9000 Series 700 800 workstations For more information on development tools see the MAX PLUS II Programmable Logic Development System amp Software Data Sheet and the Quartus Programmable Logic Development System amp Software Data Sheet The MAX 7000 architecture includes the following elements Logic array blocks Macrocells Expander product terms shareable and parallel Programmable interconnect array I O control blocks Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general purpose inputs or as high speed global control signals clock clear and two output enable signals for each macrocell and I O pin Figure 1 shows the architecture of EPM7032 EPM7064 and EPM7096 devices Figure 1 EPM7032 EPM7064 amp EPM7096 Device Block Diagram INPUT GLCK1 e e INPUT GCLRn e e INPUT OE1 M INPUT OE2 l T vv mi vv LABA LABB dE e Macrocells Macrocells 81016 o 1to 16 17 2 o vO pins x 93 I O pins PE e Macrocells Mac
60. rcial and industrial use For EPM7064S 5 EPM7064S 6 EPM7128S 6 EPM7160S 6 EPM7160S 7 EPM7192S 7 and EPM7256S 7 devices these values are specified for a PIA fan out of one LAB 16 macrocells For each additional LAB fan out in these devices add an additional 0 1 ns to the PIA timing value The f p4 parameter must be added to the f 4p trac tic ten tsexp taci and tcppw parameters for macrocells running in the low power mode Tables 35 and 36 show the EPM7192S AC operating conditions Table 35 EPM7192S External Timing Parameters Part 1 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min Max Min Max Min Max tpp1 Input to non registered output C1 35 pF 7 5 10 0 15 0 ns tpp2 I O input to non registered C1 35 pF T5 10 0 15 0 ns output tsu Global clock setup time 4 1 7 0 11 0 ns ty Global clock hold time 0 0 0 0 0 0 ns tesu Global clock setup time of fast 3 0 3 0 3 0 ns input tru Global clock hold time of fast 0 0 0 5 0 0 ns input tco1 Global clock to output delay C1 35 pF 4 7 5 0 8 0 ns tcu Global clock high time 3 0 4 0 5 0 ns teL Global clock low time 3 0 4 0 5 0 ns tasu Array clock setup time 1 0 2 0 4 0 ns 48 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet
61. rified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 shows typical supply current versus frequency for MAX 7000 devices Figure 14 I vs Frequency for MAX 7000 Devices Part 1 of 2 EPM7032 180 L 140 Typical loc 100 L Active mA 60 20 EPM7096 350 Typical lcc 250 Active mA 150 Voc 5 0 V Room Temperature 151 5 MHz T7 High Speed 60 2 MHz z Te Low Power 1 I 1 il 50 100 150 200 Frequency MHz Voc 5 0 V Room Temperature F 125 MHz um 55 5 MHz P Tine Low Power L L L 50 100 150 Frequency MHz Altera Corporation EPM7064 Typical loc Active mA 300 200 100 Vec 5 0 V Room Temperature Sis High Speed 151 5 MHz 60 2 MHz i Low Power L L L i 50 100 150 200 Frequency MHz 55 MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 Ic vs Frequency for MAX 7000 Devices Part 2 of 2 EPM7128E EPM7160E 500 500 Voc 5 0 V Voc 5 0 V Room Temperature Room Temperature 400 L 400 100 MHz 125 MHz Typical log 300 Typical Igg 300 oF Active mA M Active mA High Speed High Speed 200 200 47 6 MHz 100 L Tes took Low Power jaw Power H 1 1 1 L 1 1 l 0 50 100 150 200 0 50 100 150 200 Frequency MHz
62. rocells a Sisd o 4 o lOpins Seine SEO 64 l O pins Altera Corporation 7 MAX 7000 Programmable Logic Device Family Data Sheet Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices Figure 2 MAX 7000E amp MAX 7000S Device Block Diagram INPUT GCLK1 gt b d INPUT OE2 GCLK2 INPUT OE1 1 d ry te 6 Output Enables INPUT GCLRn 6 Output Enables vY 61016 LABA LAB B 61016 7 Macrocells Macrocells e 61o16l OPins e 1to16 171032 e 610 16 I O Pins e PIA 61016 LABC LABD 61016 36 vo Macrocells Macrocells yo e 610 16 I O Pins e 33 to 48 49 to 64 Control e 6to 16 I O Pins e Block 9 e e I4 e e e The MAX 7000 device architecture is based on the linking of high performance flexible logic array modules called logic array blocks LABs LABs consist of 16 macrocell arrays as shown in Figures 1 and 2 Multiple LABs are linked together via the programmable interconnect array PIA a global bus that is fed by all dedicated inputs I O pins and macrocells 8 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals W 36 signals from the PIA that are used
63. s tac Array clock low time 2 5 2 5 3 0 4 0 ns tcppw Minimum pulse width for clear 2 2 5 25 3 0 4 0 ns and preset topH Output data hold time after C1 35 pF 3 1 0 1 0 1 0 1 0 ns clock teur Minimum global clock period 5 7 7 0 8 6 10 0 ns font Maximum internal global clock 4 175 4 142 9 116 3 100 0 MHz frequency tACNT Minimum array clock period 5 7 7 0 8 6 10 0 ns Altera Corporation 39 MAX 7000 Programmable Logic Device Family Data Sheet Table 27 EPM7U32S External Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max facnt Maximum internal array clock 4 175 4 142 9 116 3 100 0 MHz frequency fax Maximum clock frequency 5 250 0 200 0 166 7 125 0 MHz Table 28 EPM7032S Internal Timing Parameters Note 1 Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min Max Min Max Min Max Min Max tin Input pad and buffer delay 0 2 0 2 0 3 0 5 ns tio I O input pad and buffer delay 0 2 0 2 0 3 0 5 ns tein Fast input delay 2 2 2 1 2 5 1 0 ns tgexp Shared expander delay 3 1 3 8 4 6 5 0 ns tpexp Parallel expander delay 0 9 1 1 1 4 0 8 ns trap Logic array delay 2 6 3 3 4 0 5 0 ns trac Logic control array delay 2 5
64. s only Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 18 84 Pin Package Pin Out Diagram Package outline not drawn to scale INPUT OE2 GCLK2 2 INPUT GLCRn INPUT OE1 INPUT GCLK1 j z o 9 vo C12 VCCIO 18 73 3 vOuTD O 14 72 vo E115 Ole 7 vo E116 A DTE RYA 70 vo E117 69 vo p 18 68 GND E 19 EPM7064 67 vo 20 66 vo gat EPM7064S 65 vo C22 64 3 VOTMS O 23 EPM7096 63 vo C24 62 Vo ae EPM7128E hs VCCIO 26 EPM7128S 60 vo C27 59 vo O 28 EPM7160E 58 vo 029 57 vo 30 EPM7160S 56 vo C31 55 GND o 32 54 BSSSSSSSEISISSESISRZ5RG LIUTLTETLTEI LTETCTCTCI LTETLTCTLT LT LTLTLTCT 99999gc9e2ro9rcoaegooop Se 58 g 8 84 Pin PLCC Notes 1 2 3 JTAG ports are available in MAX 7000S devices only Altera Corporation VOKTDO 3 vo vo vO vo VCCIO vo vo vo VOKTCK 3 vo Vo GND Vo vo Vo 1 0 vo Pins 6 39 46 and 79 are no connect N C pins on EPM7096 EPM7160E and EPM7160S devices The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices 61 MAX 7000 Programmable Logic Device Family Data Sheet Figure 19 100 Pin Package Pin Out Diagram Package outline not drawn to scale NNN noe Emo NOEYM ES EPM7064 EPM7096 E EPM7128E Em zd EPM71288 Em EPM7160E Pin 31 100 Pin PQFP EPM7064S EPM7128S EPM7160S 100 Pin TQFP Figur
65. s shown in Table 14 See Figure 13 for more information on switching waveforms This minimum pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimum width if the clear or reset signal incorporates the fj 4p parameter into the signal ath This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies for both global and array clocking These parameters are measured with a 16 bit loadable enabled up down counter programmed into each LAB The fmax values represent the highest frequency for pipelined data Operating conditions Vccjo 3 3 V 10 for commercial and industrial use For EPM7064S 5 EPM7064S 6 EPM7128S 6 EPM7160S 6 EPM7160S 7 EPM7192S 7 and EPM7256S 7 devices these values are specified for a PIA fan out of one LAB 16 macrocells For each additional LAB fan out in these devices add an additional 0 1 ns to the PIA timing value The t p4 parameter must be added to the tp trac tic ten tsexp tact and tcppw parameters for macrocells running in the low power mode Power Supply power P versus frequency fmax in MHz for MAX 7000 devices Consumption is calculated with the following equation P Pint Pio Ice Vcc Pio The Pio value which depends on the device output load characteristics and switching frequency can be calculated using the guidelines given in Applic
66. t 25 ns typzx JTAG port high impedance to valid output 25 ns typxz JTAG port valid output to high impedance 25 ns tussu Capture register setup time 20 ns tusH Capture register hold time 45 ns tusco Update register clock to output 25 ns tyszx Update register high impedance to valid output 25 ns tysxz Update register valid output to high impedance 25 ns tes For more information see Application Note 39 IEEE 1149 1 JTAG Boundary Scan Testing in Altera Devices 24 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Design Security Generic Testing QFP Carrier amp Development Socket Altera Corporation All MAX 7000 devices contain a programmable security bit that controls access to the data programmed into the device When this bit is programmed a proprietary design implemented in the device cannot be copied or retrieved This feature provides a high level of design security because programmed data within EEPROM cells is invisible The security bit that controls this function as well as all other programmed data is reset only when the device is reprogrammed Each MAX 7000 device is functionally tested Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100 programming yield AC test measurements are taken under conditions equivalent to those shown in Figure 10 Test patterns can be used and then erased during early stages of the production flow
67. ta Sheet Figure 12 MAX 7000 Timing Model Internal Output p gt Enable Delay tio 1 Input Global Control Y gt Delay Delay gt tin teLoB Output gt Parallel Delay Logic Array Expander Delay n l S topi St Delay tpexp top2 2 pE J tpia fub tops KS t Register a Control Delay ud 2 trac t tic 2x3 1 ten VO Shared Delay Fast Expander Delay tio m Input Dela tsexp p y tein 1 Notes 1 Only available in MAX 7000E and MAX 7000S devices 2 Notavailable in 44 pin devices The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device External timing parameters which represent pin to pin timing delays can be calculated as the sum of internal parameters Figure 13 shows the internal timing relationship of internal and external delay parameters u p For more infomration see Application Note 94 Understanding MAX 7000 Timing Altera Corporation 29 MAX 7000 Programmable Logic Device Family Data Sheet Figure 13 Switching Waveforms In amp te lt 3ns Inputs are driven at 3 V for a logic high and 0 V for a logic low All timing Input Pin characteristics are measured at 1 5 V VO Pin PIA Delay Shared Expander Delay Logic Array Input Paral
68. ted with advanced CMOS technology the EEPROM based MAX 7000 family provides 600 to 5 000 usable gates ISP pin to pin delays as fast as 5 ns and counter speeds of up to 175 4 MHz MAX 70008 devices in the 5 6 7 and 10 speed grades as well as MAX 7000 and MAX 7000E devices in 5 6 7 10P and 12P speed grades comply with the PCI Special Interest Group PCI SIG PCI Local Bus Specification Revision 2 2 See Table 3 for available speed grades Table 3 MAX 7000 Speed Grades Device Speed Grade 1 10P 4 e 12P 15T 20 EPM7032 EPM7032S v EPM7064 EPM7064S SSSS e EPM7096 EPM7128bE EPM7128S S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E SN SI PS IS WA EPM7256S L Sh Se SS SS K AL Sr PS SENSES SISISIATSISISIAISE TS INA S IN NE IS Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000E devices including the EPM7128E EPM7160E EPM7192E and EPM7256E devices have several enhanced features additional global clocking additional output enable controls enhanced interconnect resources fast input registers and a programmable slew rate In system programmable MAX 7000 devices called MAX 7000S devices include the EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S and EPM7256S devices MAX 7000S devices have the enhanced features of MAX 700
69. th inverted outputs that feed back into the logic array Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions A small delay tspxp is incurred when shareable expanders are used Figure 5 shows how shareable expanders can feed multiple macrocells Figure 5 Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB o4 Macrocell i Product Term Logic Product Term Select Matrix Macrocell Product Term Logic 36 Signals 6 Shared rom PIA Expanders Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast complex logic functions Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The compiler can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms Each set of five parallel expanders incurs a small incremental timing delay tppxp For example if a macrocell requires 14 product terms the Compiler uses the five dedicated product terms within the macrocell and allocates
70. th independently programmable clock clock enable clear and preset functions To build complex logic functions each macrocell can be supplemented with both shareable expander product terms and high speed parallel expander product terms to provide up to 32 product terms per macrocell The MAX 7000 family provides programmable speed power optimization Speed critical portions of a design can run at high speed full power while the remaining portions run at reduced speed low power This speed power optimization feature enables the designer to configure one or more macrocells to operate at 5096 or lower power while adding only a nominal timing delay MAX 7000E and MAX 7000S devices also provide an option that reduces the slew rate of the output buffers minimizing noise transients when non speed critical signals are switching The output drivers of all MAX 7000 devices except 44 pin devices can be set for either 3 3 V or 5 0 V operation allowing MAX 7000 devices to be used in mixed voltage systems The MAX 7000 family is supported byAltera development systems which are integrated packages that offer schematic text including VHDL Verilog HDL and the Altera Hardware Description Language AHDL and waveform design entry compilation and logic synthesis simulation and timing analysis and device programming The software provides EDIF 2 0 0 and 30 0 LPM VHDL Verilog HDL and other interfaces for additional design entry and simulation su
71. ufacturer s 1 1 Bit 4 Bits Identity 11 Bits 2 EPM7032S 0000 0111 0000 0011 0010 00001101110 EPM7064S 0000 0111 0000 0110 0100 00001101110 EPM7128S 0000 0111 0001 0010 1000 00001101110 EPM7160S 0000 0111 0001 0110 0000 00001101110 EPM7192S 0000 0111 0001 1001 0010 00001101110 EPM7256S 0000 0111 0010 0101 0110 00001101110 e elej jej ej e Notes 1 The most significant bit MSB is on the left 2 The least significant bit LSB for all JTAG IDCODEs is 1 Altera Corporation 23 MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals Figure 9 MAX 7000 JTAG Waveforms TMS TDI Signal to Be Captured Signal to Be Driven C Cx R tycp i tcu t uci tupsu ria ritupn lupzxi 5 i tjpco m gt lt tupxz _ iUssu Usu i M _p Uszxi Usco i tjsxz gt Table 12 shows the JTAG timing parameters and values for MAX 7000S devices Table 12 JTAG Timing Parameters amp Values for MAX 7000S Devices Symbol Parameter Min Max Unit tucp TCKclock period 100 ns t cu TCK clock high time 50 ns tcL TCK clock low time 50 ns typsy JTAG port setup time 20 ns typy JTAG port hold time 45 ns typco JTAG port clock to outpu
72. up transistor will already turn off when the pin exceeds approximately 3 8 V allowing the external pull up resistor to pull the output high enough to meet 5 0 V CMOS input voltages Slew Rate Control The output buffer for each MAX 7000E and MAX 70008 I O pin has an adjustable output slew rate that can be configured for low noise or high speed performance A faster slew rate provides high speed transitions for high performance systems However these fast transitions may introduce noise transients into the system A slow slew rate reduces system noise but adds a nominal delay of 4 to 5 ns In MAX 7000E devices when the Turbo Bit is turned off the slew rate is set for low noise performance For MAX 7000S devices each I O pin has an individual EEPROM bit that controls the slew rate allowing designers to specify the slew rate on a pin by pin basis MAX 7000 devices can be programmed on Windows based PCs with the Altera Logic Programmer card the Master Programming Unit MPU and the appropriate device adapter The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device For more information see the Altera Programming Hardware Data Sheet The Altera development system can use text or waveform format test vectors created with the Text Editor or Waveform Editor to test the programmed device For added design verification designers can perform functional testing to compare the functional beha
73. ut buffer and pad delay C1 35 pF 5 5 5 5 7 0 ns lzx1 Output buffer enable delay C1 35 pF 4 0 5 0 6 0 ns tzx2 Output buffer enable delay C1 35 pF 6 4 5 5 5 7 0 ns tzx3 Output buffer enable delay C1 35 pF 9 0 9 0 10 0 ns tyz Output buffer disable delay C1 5pF 4 0 5 0 6 0 ns tsu Register setup time 3l 2 0 4 0 ns Altera Corporation 49 MAX 7000 Programmable Logic Device Family Data Sheet Table 36 EPM7192S Internal Timing Parameters Part 2 of 2 Note 1 Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min Max Min Max Min Max tH Register hold time 1 7 3 0 4 0 ns tFsu Register setup time of fast 2 3 3 0 2 0 ns input teu Register hold time of fast 0 7 0 5 1 0 ns input tap Register delay 1 4 2 0 1 0 ns tcomB Combinatorial delay 1 2 2 0 1 0 ns tic Array clock delay 3 2 5 0 6 0 ns ten Register enable time 3 1 5 0 6 0 ns tGLOB Global control delay 2 5 1 0 1 0 ns PRE Register preset time 2 7 3 0 4 0 ns lcin Register clear time 2 7 3 0 4 0 ns tpa PIA delay 7 2 4 1 0 2 0 ns li pA Low power adder 8 10 0 11 0 13 0 ns Notes to tables 1 These values are specified under the recommended operating conditions shown in Table 14 See Figure 13 for more information on switching waveforms 2 This minimum pulse width for preset and clear applies for both global clear and array controls The t p4 parameter must be added to this minimu
74. vior of a MAX 7000 device with the results of simulation Moreover Data I O BP Microsystems and other programming hardware manufacturers also provide programming support for Altera devices For more information see the Programming Hardware Manufacturers 21 MAX 7000 Programmable Logic Device Family Data Sheet IEEE Std MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std 1149 1 1990 Table 9 describes the JTAG instructions supported by the 1 149 1 JTAG MAX 7000 family The pin out tables see the Altera web site Boundarv n http www altera com or the Altera Digital Library for pin out ou da y Sca information show the location of the JTAG control pins for each device Su p port If the JTAG interface is not required the JTAG pins are available as user I O pins Table 9 MAX 7000 JTAG Instructions JTAG Instruction Devices Description SAMPLE PRELOAD EPM7128S Allows a snapshot of signals at the device pins to be captured and EPM7160S examined during normal device operation and permits an initial data EPM7192S pattern output at the device pins EPM7256S EXTEST EPM7128S Allows the external circuitry and board level interconnections to be EPM7160S _ tested by forcing a test pattern at the output pins and capturing test EPM7192S _ results at the input pins EPM7256S BYPASS EPM7032S _ Places the 1 bit bypass register between the TDI and TDO pins which EPM7064S _ a
75. ziSEPM 7128EQC 160 12 M fS JA DTE RIA September 2005 ver 6 7 MAX 7000 Programmable Logic Device Family Features Data Sheet High performance EEPROM based programmable logic devices PLDs based on second generation MAX architecture 5 0 V in system programmability ISP through the built in IEEE Std 1149 1 Joint Test Action Group JTAG interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std 1532 Includes 5 0 V MAX 7000 devices and 5 0 V ISP based MAX 7000S devices Built in JTAG boundary scan test BST circuitry in MAX7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5 000 usable gates see Tables 1 and 2 5 ns pin to pin logic delays with up to 175 4 MHz counter frequencies including interconnect PCI compliant devices available For information on in system programmable 3 3 V MAX 7000A or 2 5 V MAX 7000B devices see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet Table 1 MAX 7000 Device Features Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E Usable 600 1 250 1 800 2 500 3 200 3 750 5 000 gates Macrocells 32 64 96 128 160 192 256 Logic array 2 4 6 8 10 12 16 blocks Maximum 36 68 76 100 104 124 164 user I O pins tpp ns 6 6 7 5 7 5 10 12 12 tsu ns 5 5 6 7 tesy ns 2 5 2 5 3 3

ALTERA MAX 7000 handbook(3)

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