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LINEAR TECHNOLOGY - 1 LTC1553 5 handbook

1. Supply Current 12V OUTEN Vec Note 6 Figure 3 15 mA PVcc 12V OUTEN 0 VIDO to VIDA Floating 1 fosc Internal Oscillator Frequency Figure 4 250 300 350 kHz VsawL Vcomp at Minimum Duty Cycle Note 4 VsawH Vcomp at Maximum Duty Cycle Note 4 28 Error Amplifier Open Loop DC Gain Note 7 e 40 9d dB Error Amplifier Transconductance Note 7 e 09 1 6 23 millimho BWerr Error Amplifier 3dB Bandwidth COMP Open Note 4 400 kHz 2 LS HUS LIC 1553 ELECTRICAL CHARACTERISTICS Vee PVcc 12V Ta 25 C unless otherwise noted Note 3 SYMBOL UNITS lIMAX Iss ISSIL ISSHIL ISSHIL tPWRGD PWRBAD FAULT toT Vor VoTDD VSHDN tr tf tNOL Vin VIL Rin ISINK The denotes specifications which apply over the full operating temperature range Note 1 Absolute Maximum Ratings are those values beyond which the life Imax Sink Current Mwx MVo 191 150 w 220 uA Soft Start Source Current Vess OV Vis Ver 13 10 uA Maximum Soft Start Sink Current Veense Vout Vimax Vec Virg OV 30 60 150 Under Current Limit Notes 8 9 Ves Voc Soft Start Sink Current Under Hard Veense OV Vimax Voc OV 20 45 mA Current Limit Hard Current Limit Hold Time Vsense OV Vimax 4V Vel from 5V Note4 500 gs Power Good Response Time VSFNSET from OV to Rated Vout 0 5 1 2 ms Power Good Response
2. 300 C TOP VIEW ORDER PART NUMBER 10159300 LTC1553CSW G PACKAGE SW PACKAGE 20 LEAD PLASTIC SSOP 20 LEAD PLASTIC SO Tymax 125 C Oja 100 C W G Tymax 125 C Oja 100 C W SW Consult factory for Industrial and Military grade parts PACKAGE ORDER INFORMATION ELECTRICAL CHARACTERISTICS Vec DV 12V 25 C unless otherwise noted Note 3 SYMBOL UNITS Voc Supply Voltage Oooo O e 08 J V Ms V VFB Internal Feedback Voltage Note 4 1 265 Vout 1 8V Initial Output Voltage With Respect to Rated Output Voltage Figure 2 27 1 5 27 1 9 mV 2 0V Initial Output Voltage 42 1 5 42 1 5 mV 3 5 Initial Output Voltage 92 71 595 92 1 596 mV 1 8V Initial Output Voltage 36 2 36 4 296 mV 2 0V Initial Output Voltage 56 295 96 296 mV 3 0V Initial Output Voltage 70 2 70 2 mV AVouT Output Load Regulation lout 0 to 14A Note 4 Figure 2 5 mV Output Line Regulation Vin 4 79V to 5 25V lgyr 0 Note 4 Figure 2 mV VPWRGD Positive Power Good Trip Point Above Output Voltage Figure 2 5 7 Negative Power Good Point Below Output Voltage Figure 2 5 Yo Ver FAULT Trip Point Above Output Voltage Figure 2 e 1 15 20 loc Operating Supply Current OUTEN Voc 5V Note 5 Figure 3 800 1200 shutdown Supply Current OUTEN 0 VIDO to VIDA Floating Figure 3 130 250
3. Veense tom PatedVouroov e 20 so 10 FAULT Response Time T om Rated art vo e 20 soo 100 ResponseTime OUTENE VIDO 0 v4 0 Note e 0 JOver Temperature Trip Point OUTENX VIDO to VID4 0 Note 10 Figure 3 19 2 22 Over Temperature Driver Disable VIDO to VID4 0 Note 10 Figure 3 16 17 18 OUTENL VIDO to VID4 0 Note 10 Figure 3 e 08 Driver Rise and Fal Time tH DiWmwipnm Fue m WemmGbwOs ko u 5 VIDO to VIDA Internal Pull Up Resistance e 8 m Note 6 Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates This will vary with the LTC1553 operating frequency supply voltage and the external FETs of a device may be impaired used Note 2 When lrg is taken below GND it will be clamped by an internal diode This pin can handle input currents greater than 100mA below GND without latchup In the positive direction it is not clamped to Vcc or PVcc Note 3 All currents into device pins are positive all currents out of the device pins are negative All voltages are referenced to ground unless otherwise specified Note 4 This parameter is guaranteed by correlation and is not tested directly Note 5 The LTC1553 goes into the shutdown mode if VIDO to VIDA are floating Due to the internal pull up resistors there will be an additional N
4. D LIC 1553 ECHNOLOGY 5 Bit Programmable synchronous switching Regulator Controller for Pentium Il Processor FEATURES DESCRIPTION 9 Bit Digitally Programmable 1 8V to 3 5V Fixed LTC 1553 is a high power high efficiency switching Output Voltage regulator controller optimized for 5V or 12V input to 1 8V Provides All Features Required by the Intel 3 5V output applications Itfeatures a digitally programmable Pentium Il Processor VRM 8 2 DC DC output voltage a precision internal reference and an internal Converter Specification feedback system that provides output accuracy of 1 5 at Flags for Power Good Over Temperature and room temperature and typically 2 over temperature load Overvoltage Fault current and line voltage shifts The LTC 1553 uses a synchro m 19A Output Current Capability from a 5V or 12V Supply nous switching architecture with two external N channel Dual N Channel MOSFET Synchronous Driver output devices providing high efficiency and eliminating the Initial Output Accuracy 1 5 need for a high power high cost P channel device Addition m Excellent Output Accuracy 2 Typ Over Line ally it senses the output current across the on resistance of Load and Temperature Variations the upper N channel FET providing an adjustable current High Efficiency Over 95 Possible limit without an external low value sense resistor B Current Limit Without External sense The LTC1553 free runs at 300kHz
5. Q1 1 SUD50N03 10 30 02 1 x SUD50N03 10 B Q1 2 x SUD50N03 10 20 02 1 x SUD50N03 10 a NO FAN 10 Q1 IS MOUNTED ON 1IN2 COPPER AREA 1533 602 Output Temperature Drift TEMPERATURE C 1553 G05 Error Amplifier Transconductance vs Temperature 100 125 0 9 50 25 0 2 50 75 TEMPERATURE C 1553 G08 Load Regulation 2 825 OUTPUT VOLTAGE V N co e 01234567 8 9 1011 12 13 14 OUTPUT CURRENT A 1533 G03 Over Temperature Trip Point vs Temperature 50 25 0 25 50 75 100 125 TEMPERATURE C 1553 G06 Error Amplifier Open Loop DC Gain vs Temperature 60 S lt Oo e 55 C Ce l 50 7 45 lt oc 40 50 25 0 25 50 75 100 125 TEMPERATURE C 1553 609 LS HUS LIC 1553 TYPICAL PERFORMANCE CHARACTERISTICS Oscillator Frequency vs Temperature OSCILLATOR FREQUENCY kHz 250 50 25 0 25 50 75 100 125 TEMPERATURE C 1553 G10 Maximum G1 Duty Cycle vs Temperature MAXIMUM G1 DUTY CYCLE TEMPERATURE C 1553 G13 PVcc Supply Current vs Gate Capacitance PVcc SUPPLY CURRENT 0 0 2000 GATE CAPACITANCE pF 4000 6000 8000 1553 G16 Vcc OPERATING SUPPLY CURRENT mA Imax SINK CURRENT uA OUTPUT VOLTAGE V Imax Sink Current vs Temperature 50 25 0 25 50 75 100 TEMPERATURE C 125 1553 G11
6. Vcc Operating Supply Current vs Temperature TEMPERATURE C 1553 G14 Output Over Current Protection Q1 2x MTD20NO3HDL Q2 1 x MTD20NO3HDL 0 0 2 4 6 8 10 12 14 16 OUTPUT CURRENT A 1553 G17 SOFT START SOURCE CURRENT uA 5 Soft Start Source Current vs Temperature 50 25 0 2 50 75 100 125 Voc SHUTDOWN SUPPLY CURRENT mA TEMPERATURE C 1553 G12 Vec Shutdown Supply Current vs Temperature 0 50 25 0 25 50 75 100 125 o0mV DIV 9A DIV TEMPERATURE C 1553 G15 Transient Response mus 1553 618 100us DIV AL MYR LIC 1553 PIN FUNCTIONS G2 Pin 1 Gate Drive for the Lower N Channel MOSFET Q2 This output will swing from PVcc to GND It will always be low when G1 is high or when the output is disabled To prevent undershoot during a soft start cycle G2 is held low until G1 first goes high Pin 2 Power Supply for G1 and G2 PVcc must be connected to a potential of at least Vi Vas owyot Vin OV be generated using a simple charge pump connected to the switching node between Q1 and Q2 see Figure 7 oritcan be connected to an auxiliary 12V supply if one exists For applications where Viy 12V PVcc can be generated using a 17V charge pump see Figure 9 GND Pin 3 Power Ground GND should be connected to a low impedance ground plane in close proximity to the source of Q2 SGND Pin 4
7. pull down at Imax Pin 8 Current Limit Sense Pin Connect to the switching node between the source of Q1 and the drain of Q2 If leg drops below Imax when G1 is the LTC1553 will go into current limit The current limit circuit can be disabled by floating jMAx and shorting to Vec through an external 10k resistor For Viy 12V a 15V Zener diode from to GND is recommended to prevent the voltage spike at from exceeding the maximum voltage rating SS Pin 9 Soft Start Connect to an external capacitor to implementa soft start function During moderate overload conditions the soft start capacitor will be discharged slowly in order to reduce the duty cycle In hard current limit the soft start capacitor will be forced low immedi ately and the LTC1553 will rerun a complete soft start cycle Css must be selected such that during power up the current through Q1 will not exceed the current limit value COMP Pin 10 External Compensation The COMP pin is connected directly to the output of the error amplifier and the input of the PWM comparator An RC network is used at this node to compensate the feedback loop to provide optimum transient response OT Pin 11 Over Temperature Fault OT is an open drain output and will be pulled low if OUTEN is less than 2V If OUTEN 0 OT pulls low FAULT Pin 12 Overvoltage Fault FAULT is an open drain output If Vgyr reaches 15 above the nominal output volta
8. and can be synchronized to a faster external clock if desired It includes all the inputs and outputs required to implement a power supply conform ing to the Intel Pentium Il Processor VRM 8 2 DC DC m Fast Transient Response m Available in 20 Lead SSOP and SW Packages Converter Specification APPLICATIONS 47 LTC and LT are registered trademarks of Linear Technology Corporation Power Supply for Pentium SPARC ALPHA and Pentium is a registered trademark of Intel Corporation PA RISC Microprocessors m High Power 5V or 12V to 1 8V 3 5V Regulators TYPICAL APPLICATION E vn VOUT 1 8V TO 3 5V 14A PENTIUM II SYSTEM SILICONIX SUD50N03 10 SANYO 10MV1200GX TCOILTRONICS CTX02 13198 OR PANASONIC 12TS 2R5SP TPSE337M006R0100 Figure 1 5V to 1 8V 3 5V Supply Application HUS LIC 1553 ABSOLUTE MAXIMUM RATINGS Note 1 Supply Voltage s A E 0V quqa 20V Input Voltage leg Note 2 0 3V aasma 0 3 to 13V All Other Inputs 0 3V to 0 3V Digital Output Voltage 0 3 to 13V leg Input Current Notes 2 3 100 Operating Temperature Range 0 C to 70 C storage Temperature Range 65 to 150 C Lead Temperature Soldering 10 sec
9. demands on both the input and the output capacitors During constant load operation a buck converter like the LTC1553 draws Square waves of current from the input supply at the switching frequency The peak current value is equal to the output load current plus 1 2 peak to peak ripple current and the minimum value is zero Most of this current is supplied by the input bypass capacitor The resulting RMS current flow in the input capacitor will heat it up causing premature capacitor failure in extreme cases Maximum RMS current occurs with 50 PWM duty cycle giving an RMS current value equal to lgyr 2 A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation Note that capacitor manufacturers ripple current ratings are often based on only 2000 hours three months lifetime at rated temperature Further derating of the input capacitor ripple current beyond the manufacturer s speci fication is recommended to extend the useful life of the circuit Lower operating temperature will have the largest effect on capacitor longevity The output capacitor in a buck converter sees much less ripple current under steady state conditions than the input capacitor Peak to peak current is equal to that in the inductor usually 10 to 40 of the total load current Output capacitor duty places a premium not on power dissipation but on ESR During an output load transient the output capacitor must supp
10. drop measured across the external MOSFET Q1 at the pin Note that when Viy 12V the pin requires an external Zener to GND to prevent voltage transients at the switching node between Q1 and Q2 from damaging internal structures CC compares the voltage at to the voltage at the Imax pin As the peak current rises the measured voltage across Q1 increases due to the drop across the Rps oy of Q1 When the voltage at drops below Imay indicating that Q1 s drain current has exceeded the maximum level CC starts to pull current out of the external soft start capacitor cutting the duty cycle and controlling the output current level The CC comparator pulls current out of the SS pin in proportion to the voltage difference between lgg and Imax Under minor overload conditions the SS pin will fall gradually creating a time delay before current limit takes effect Very short mild overloads may not affect the output voltage at all More significant overload conditions will allow the SS pin to reach a steady state and the output will remain at a reduced voltage until the overload is removed Serious overloads will generate a large overdrive at CC allowing it to pull SS down quickly and preventing damage to the output components By using the Rps oy of Q1 to measure the output current the current limiting circuit eliminates an expensive dis crete sense resistorthat would otherwise be required This helps minimize the number of compo
11. selected should be chosen based on input and output voltage allowable power dissipation and maximum required out put current In a typical LTC1553 buck converter circuit the average inductor current is equal to the output load current This current is always flowing through either Q1 or Q2 with the power dissipation split up according to the duty cycle 1 Vout VIN bc a2 1 our VIN VIN The Rps on required for a given conduction loss can now be calculated by rearranging the relation IR Vn Pun Vour lux Rps oN o2 hus s in Fano nx My Vour lux Pmax should be calculated based primarily on required efficiency or allowable thermal dissipation A typical high efficiency circuit designed for Pentium II with a 5V input and a 2 8V 11 2A output might allow no more than 4 efficiency loss at full load for each MOSFET Assuming roughly 90 efficiency at this current level this gives a Pmax value of 2 8 11 2 0 9 0 04 1 39W FET and a required Rps on Of 50V 1 39W Rps on ar ae 0 0190 2 8V 11 2a OV 1 39W Rps oN 02 Ew 0 0250 5v 2 8V 11 2a Note also that while the required Rps on values suggest large MOSFETs the dissipation numbers are only 1 39W per device or less large TO 220 packages and heat sinks are not necessarily required in high efficiency applica tions SiliconixSi441
12. 0DY or International Rectifier IRF 413 both in 50 8 or Siliconix SUD50NOS3 or Motorola MTD20NOSHDL both in D PAK are small footprint sur face mount devices with Rps on values below 0 030 at 5V of gate drive that work well in 101553 circuits With higher output voltages the Rps oy of 01 may need to be significantly lower than that for Q2 These conditions can often be met by paralleling two MOSFETs for Q1 and using a single device for Q2 Note that using a higher Pmax value in the Rps on calculations will generally decrease MOSFET cost and circuit efficiency while increasing MOSFET heat sink requirements 14 LS HUS LIC 1553 APPLICATIONS INFORMATION Table 5 Recommended MOSFETs for LTC1553 Applications NUM RATED CURRENT A TYPICAL INPUT Tymax Rps on CAPACITANCE PARTS AT 25 C mQ Ciss pF Siliconix SUD50N03 10 19 15 at 25 C 3200 1 8 175 T0 252 10 at 75 C Siliconix Si4410DY 20 10 at 25 C 2 00 150 8 at 75 C Motorola MTD20NO3HDL 35 20 at 25 C 880 1 67 150 D PAK 16 at 100 C SGS Thomson STD20NO3L 23 20 at 25 C 2300 25 175 D PAK 14 at 100 C Motorola MTB75NO3HDL Ls 75 at 25 C 4025 1 0 150 DD PAK 59 at 100 C IRF IRL3103S 14 56 at 25 C 1600 1 8 175 DD PAK 40 at 100 C IRF IRLZ44 28 50 at 25 C 3300 1 0 175 0 220 36 at 100 C Fuji 25 1388 37 35 at 25 C 1750 2 08 150 0 220 Note Please refer to the manufacturer s data sheet for testing conditions and detail information Inductor Se
13. 482 7117 20 WIDE 0396 TYP NOTE 1 PIN 1 IDENT NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS DIMENSION DOES NOT INCLUDE MOLD FLASH MOLD FLASH SHALL NOT EXCEED 0 006 0 152mm PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 0 010 0 254mm PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable J LINCAD However no responsibility is assumed for its use Linear Technology Corporation makes no represen TECHNOLOGY tation that the interconnection of its circuits as described herein will not infringe on existing patent rights LIC 1553 TYPICAL APPLICATION Voc Vin 12V ioo 1N5817 1N5248B tov 1000uF 4 PENTIUM II SYSTEM LTC1553 VOUT G2 SGND GND SENSE MOTOROLA MTD20NOSHDL SANYO 16MV1000GX TCOILTRONICS CTX02 13199 tT AVX TPSE337M006R0100 1553 F14 Figure 14 External Clock Synchronized 12V to 1 8V 3 5V Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1142 Dual Version of LTC1148 LTC1148 Synchronous Viy lt 20V LTC1149 Synchronous Viv lt 48V for Standard Threshold FETs LTC1159 Synchronous Viv lt 40V for Logic Threshold FETs LTC1266 synchronous N or P Channel FETs Comparator Low Battery Detector LTC1430 Synchronous N Channel FETs Voltage Mode LTC1435 High Efficienc
14. 53 F13 Figure 13 Single Supply LTC1553 5V to 1 8V 3 5V Application with Thermal Monitor AL HUS 21 LIC 1553 PACKAGE DESCRIPTION Dimension in inches millimeters unless otherwise noted G Package 20 Lead Plastic SSOP 0 209 LTC DWG 05 08 1640 0 205 0 212 5 20 5 38 0 8 Y 0 005 0 009 0 022 0 037 x 0 13 0 22 0 55 0 95 DIMENSIONS DO NOT INCLUDE MOLD FLASH MOLD FLASH SHALL NOT EXCEED 0 006 0 152mm PER SIDE DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 0 010 0 254mm PER SIDE 22 0 278 0 289 7 07 7 33 1 0 301 0 311 7 65 7 90 0 068 0 0 8 1 73 1 99 emma E pos 0 0 008 0 010 0 015 0 05 0 21 0 25 0 38 G20 SSOP 0595 HUS LIC 1553 PACKAGE DESCRIPTION Dimension in inches millimeters unless otherwise noted SW Package 20 Lead Plastic Small Outline Wide 0 300 LTC DWG 05 08 1620 0 496 0 512 12 598 13 005 20 19 18 17 16 15 14 13 12 11 0 394 0 419 10 007 10 643 0 291 0 299 Y 7 391 7 595 0 093 0 104 0 037 0 045 TEC EET er PUN 2 362 2 642 0 940 1 143 1 TYP E 0 050 0 009 0 013 1 270 0 004 0 012 0 229 0 330 NOTE 1 TYP 0 102 0 305 0 016 0 050 0 014 0 019 0406 1 270 0356 0
15. IUM II SYSTEM stops all internal switching pulls COMP and SS to ground _ bu internally and turns Q1 and Q2 off OT and PWRGD are RS OUTEN g Corr pulled low and FAULT is left floating In shutdown the woo L T LTC1553 quiescent current will drop to about 130uA The remaining current is used to keep the thermistor sensing ne circuit at OUTEN alive Note that the leakage current of the external MOSFETs may add to the total shutdown current consumed by the circuit especially at elevated temperature OUTEN is less than 1 2V the LTC1553 will enter shutdown Figure 6 OUTEN Pin as a Thermistor Input OUTEN is designed with multiple thresholds to allow it to also be utilized for over temperature protection The power MOSFET operating temperature can be monitored with an external negative temperature coefficient NTC thermistor mounted next to the external MOSFET which is expected to run the hottest often the high side device Q1 Elec The internal oscillator can be synchronized to an external trically the thermistor should form a voltage divider with clock by applying the external clocking signal to the another resistor R1 connected to Their midpoint OUTEN pin The synchronizing range extends from the should be connected to OUTEN see Figure 6 As the initial operating frequency up to 500kHz If the external temperature increases the OUTEN voltage is reduced frequency is much higher than the natural free runn
16. R and raise ripple current capability is to parallel several capacitors Atypical LTC1553 16 HUS LIC 1553 APPLICATIONS INFORMATION application might exhibit 5A input ripple current SANYO OS CON part number 10SA220M 220uF 10V capacitors feature 2 3A allowable ripple current at 85 C three in parallel at the input to withstand the input ripple current will meet the above requirements Similarly AVX TPSE337M006R01 00 330uF 6V have a rated maximum ESR of 0 10 seven in parallel will lower the net output capacitor ESR to 0 0140 For low costapplication SANYO MV GX series of capacitors can be used with acceptable performance Feedback Loop Compensation The LTC1553 voltage feedback loop is compensated at the COMP pin attached to the output node of the internal gm error amplifier The feedback loop can generally be com pensated properly with an RC C network from COMP to GND as shown in Figure 10a Loop stability is affected by the values of the inductor Output capacitor output capacitor ESR error amplifier transconductance and error amplifier compensation net work The inductor and the output capacitor creates a double pole at the frequency _ 1 20 The ESR of the output capacitor forms zero at the frequency 1 ESR 2 The compensation network at the error amplifier output is to provide enough phase margin at the OdB crossover frequency for the overall clo
17. Signal Ground SGND is connected to the low power internal circuitry and should be connected to the negative terminal of the output capacitor where it returns to the ground plane GND and SGND should be shorted right at the L T1553 Vec Pin 5 Power Supply Power for the internal low power circuity Vcc should be wired separately from the drain of Q1 if they share the same supply A 10uF bypass capacitor is recommended from this pin to SGND SENSE Pin 6 Output Voltage Pin Connectto the positive terminal of the output capacitor There is an internal 120k resistor connected from this pin to SGND SENSE is a very sensitive pin foroptimum performance connectan exter nal 0 1uF capacitor from this pin to SGND By connecting a small external resistor between the output capacitor and the SENSE pin the initial output voltage can be raised slightly Since the internal divider has a nominal imped ance of 120kO 12000 series resistor will raise the nominal output voltage by 1 If an external resistor is used the value of the 0 1uF capacitor on the SENSE pin must be greatly reduced or loop phase margin will suffer oet a time constant for the RC combination of approxi mately 0 1us So for example with a 12000 resistor set C 83pF Use a standard 100pF capacitor Imax Pin 7 Current Limit Threshold Current limit is set by the voltage drop across an external resistor connected between the drain of Q1 and Imax There is a 180uA internal
18. can be used with good results However logic level devices will improve efficiency The current drawn from the 12V supply varies with the MOSFETs used and the LTC1553 operating frequency but is generally less than 90mA VIN OPTIONAL FOR gt 5V ad Figure 7 Doubling Charge Pump VIN 1N5817 1N5817 1N5817 10uF 0 1uF p Figure 8 Tripling Charge Pump VIN 1N5817 12V Voc 9v 1N5248B 100 18V Voc PVcc G1 Figure 9 17V Charge Pump for Viy 12V AL HUS 13 LIC 1553 APPLICATIONS INFORMATION The LTC1553 designs that use a 5V Viy voltage and a doubler charge pump to generate PVcc will not provide enough drive voltage to fully enhance standard power MOSFETs Under this condition the effective MOSFET May be quite high raising the dissipation in the FETs and reducing efficiency Logic level FETs are a better choice for 5V only systems as shown in Figure 7 or 12V input systems using the 17V charge pump of Figure 9 They can be fully enhanced with the generated charge pump voltage and will operate at maximum efficiency Note that doubler charge pump designs running from supplies higher than 5V and all tripler charge pump designs should include a Zener clamp diode at to preventtransients from exceeding the absolute maximum rating at that pin See the MOSFET Gate Drive section for more charge pump information Once the threshold voltage has been
19. e SSE eee Table 3 Rated Output Voltage I 1101110 2 5 E PIN i RATED OUTPUT pt of of 1 2 6 With external pull up resistor With respect to the output voltage selected in Table 3 as required by Intel Specification VRM 8 2 T These code selections are disabled in LTC1553 X Don t care VOLTAGE V _ Voo Disabled 1 30 c A Disabled 1 35 1 Disabled t 1 40 Disabled 1 45 0 0 0 0 0 1 Disabled 1 60 0 0 0 Disabled 1 65 Disabled 1 70 0 Disabled 1 75 EN 1 Disabled 1 50 Disabled 1 55 AL HUS d LIC 1553 APPLICATIONS INFORMATION OVERVIEW The LTC1553 is a voltage feedback synchronous switch ing regulator controller see Block Diagram designed for use in high power low voltage step down buck convert ers It is designed to satisfy the requirements of the Intel Pentium Il power supply specification It includes an on chip DAC to control the output voltage a PWM genera tor a precision reference trimmed to 1 two high power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit The LTC1553 includes a current limit sensing circuit that uses the upper external power MOSFET as a current sensing element eliminating the need for an external sense resistor Once the current comparator CC detects an
20. e Upper N Channel MOSFET Q1 This output will swing from PVcc to GND It will always be low when G2 is high or the output is disabled BLOCK DIAGRAM 115 VREF FAULT 1 oT OUTEN MHCL HCL MONO E DISDR SYSTEM POWER DOWN Pp FE COMP 10 A A PWRGD PVcc 20 61 G2 6 SENSE VIDO VID1 VID2 VID3 VID4 VREF 5 VREF 0 7VREF AL MYR LIC 1553 TEST CIRCUITS Voc PVcc 5 12 V 10hF 0 1nF 10uF 0 1uF H P p x4 outen 06 Lot PWRGD 01 oun FAULT 15 A NC T 0T 0U Court 100pF VIDO TO VID4 VIDO TO VID4 g 390 OT 49 1 C1 8 2k EE 150pF Cc 0 1 MF SILICONIX SUD50N03 10 0 01 pF 0 1 uF SANYO 10MV1200GX li 7 Yi tCOILTRONICS CTX02 13198 OR PANASONIC 12TS 2R5SP tt AVX TPSE337M006R0100 1553 F02 Figure 2 Vcc Voc VIDO VID1 VID2 VID3 VID4 10uF VIDO VIDI VID2 VID3 VID4 l OUTEN PWRGD 0 1hF 10hF FAULT LTC1553 epe OT COMP SS 1553 F03 Figure 3 Veo 5V 12V 10uF 0 1hF 10hF T lI T G1 RISE FALL 5000 1701553 SENSE G2 RISE FALL SGND GND 5000pF 50 1553 F04 Figure 4 HUS LIC 1553 FUNCTION TABLES Table 1 OT Logic Table 3 Rated Output Voltage cont OUTEN V OT INPUT PIN RATED OUTPUT Table 2 PWRGD and FAULT Logic INPUT OUTPUT 1 1 95 0 0 0 0 0 Se
21. e Vour volt age PWRGD and FAULT To prevent PWRGD from inter rupting the CPU unnecessarily the LTC 1553 has a built in tpWRBAD delay to prevent noise at the SENSE pin from toggling PWRGD The internal time delay is designed to take about 500us for PWRGD to go low and 1ms for it to recover Once PWRGD goes low the internal circuitry watches for the output voltage to exceed 115 ofthe rated voltage If this happens FAULT will be triggered Once FAULT is triggered G1 and G2 will be forced low immedi ately and the LTC1553 will remain in this state until Voc power supply is recycled or OUTEN is toggled 18 LS HUS LIC 1553 APPLICATIONS INFORMATION 15 VOUT 5 RATED Vout 5 tpwRBAD pe tFAULT PWRGD FAULT 1553 F11 Figure 11 PNRGD and FAULT LAYOUT CONSIDERATIONS When laying out the printed circuit board the following checklist should be used to ensure proper operation of the LTC1553 These items are also illustrated graphically in the layout diagram of Figure 12 The thicker lines show the high current paths Note that at 10A current levels or above current density in the PC board itself is a serious concern Traces carrying high current should be as wide as possible For example a PCB fabricated with 20z copper requires a minimum trace width of 0 15 to carry 10A 1 In general layout should begin with the location of the p
22. e selected value for more than 500us the PWRGD output will be pulled low Once the output has settled within 5 of the selected value for more than 1ms PWRGD will return high THEORY OF OPERATION Primary Feedback Loop The regulator output voltage at the SENSE pin is divided down internally by a resistor divider with a total resistance of approximately 120kQ This divided down voltage is subtracted from a reference voltage supplied by the DAC output The resulting error voltage is amplified by the error amplifier andthe output is compared to the oscillator ramp waveform by the PWM comparator This PWM signal controls the external MOSFETs through G1 and G2 The resulting chopped waveform is filtered by Lo and Cour closing the loop Loop frequency compensation is achieved with an external RC network at the COMP pin which is connected to the output node of the transconductance amplifier MIN MAX Feedback Loops Two additional comparators in the feedback loop provide high speed fault correction in situations where the ERR amplifier may not respond quickly enough MIN compares the feedback signal FB to a voltage 60mV 5 below the internal reference If FB is lower than the threshold of this comparator the MIN comparator overrides the ERR amplifier and forces the loop to full duty cycle which is set by the internal oscillator typically to 84 Similarly the MAX comparator forces the output to 0 duty cycle if FB is more than 5 ab
23. ge FAULT will go low and G1 and G2 will be disabled Once triggered the LTC1553 will remain in this state until the power supply is recycled or the OUTEN pin is toggled If OUTEN 0 FAULT floats or is pulled high by an external resistor PWRGD Pin 13 Power Good This is an open drain signal to indicate validity of output voltage A high indi cates that the output has settled to within 5 of the rated outputfor morethan 1ms PWRGD will go low if the output is out of regulation for more than 500us If OUTEN 0 PWRGD pulls low HUS LIC 1553 PIN FUNCTIONS VIDO VID1 VID2 VID3 VID4 Pins 18 17 16 15 14 Digital Voltage Select TTL inputs used to set the regulated output voltage required by the processor Table 3 There is an internal 20kQ pull up at each pin When all five VID pins are high or floating the chip will shut down OUTEN Pin 19 Output Enable TTL input which enables the output voltage The external MOSFET temperature can be monitored with an external thermistor as shown in Figure 13 When the OUTEN input voltage drops below 2V OT trips As OUTEN drops below 1 7V the drivers are internally disabled to prevent the MOSFETs from heating further If OUTEN is less than 1 2V for longer than 30us the LTC1553 will enter shutdown mode The internal oscillator can be synchronized to a faster external clock by applying the external clocking signal to the OUTEN pin G1 Pin 20 Gate Drive for th
24. his circuit can be useful for standard threshold MOSFETs which demand a higher turn on volt age An 18V Zener diode 1N5248B is recommended with tripler charge pump designs to ensure that PVcc never exceeds the LTC1553 s 20V absolute maximum PVgc voltage This becomes more critical as Viy rises With Viy 12V the doubler circuit of Figure 7 will also exceed the 20V limit Figure 9 shows an alternate 1 V charge pump derived from both the 5V and 12V supplies If the OUTEN pin is low G1 and G2 are both held low to prevent output voltage undershoot As Vcc and power up from a OV condition an internal undervoltage lockup circuit prevents G1 and G2 from going high until Voc reaches about 3 5V If Vcc powers up while is at ground potential the SS is forced to ground potential internally SS clamps the COMP pin low and prevents the drivers from turning on On power up or recovery from thermal shutdown the drivers are designed such that G2 is held low until G1 first goes high Power MOSFETs Two N channel power MOSFETs are required for most LTC1553 circuits They should be selected based prima rily on threshold and on resistance considerations The required MOSFET threshold should be determined based on the available power supply voltages and or the com plexity of the gate driver charge pump scheme In 5V input designs where a 12V supply is used to power standard MOSFETs with specified at Vos 5V or 6V
25. ing Under normal operating conditions the OUTEN should frequency the peak to peak sawtooth amplitude within stay above 2V All circuits will function normally and the the LTC1553 will decrease Since the loop gain is inversely OT pin will remain in a high state If the temperature gets proportional to the amplitude of the sawtooth the com abnormally high the OUTEN pin voltage will eventually pensation network may need to be adjusted slightly Note drop below 2V OT will switch to a logic low providingan that the temperature sensing circuitry does not operate over temperature warning tothe system As OUTEN drops When external synchronization is used below 1 V the LTC1553 disables both FET drivers If longer than 30us Clock Synchronization mode To activate any of these three modes the OUTEN voltage must drop below the respective threshold for 12 AT VIP LIC 1553 APPLICATIONS INFORMATION MOSFET Gate Drive Power for the internal MOSFET drivers is supplied by This supply must be above the input supply voltage by atleast one power MOSFET Veson for efficient opera tion This higher voltage can be supplied with a separate supply orit can be generated using a simple charge pump as shown in Figure 7 The 84 typical maximum duty cycle ensures sufficient off time to refresh the charge pump during each cycle Figure 8 shows a tripling charge pump which provides additional Vas overdrive to the external MOSFETs T
26. lection The inductor is often the largest component inthe LTC1553 design and should be chosen carefully Inductor value and type should be chosen based on output slew rate require ments output ripple requirements and expected peak current Inductor value is primarily controlled by the required current slew rate The maximum rate of rise of current in the inductor is set by its value the input to output voltage differential and the maximum duty cycle of the LTC1553 In a typical 5V input 2 8V output applica tion the maximum current slew rate will be Mu Vour 1 83 A ous where L is the inductor value in uH With proper frequency compensation the combination ofthe inductor and output capacitor will determine the transient recovery time In general a smaller value inductor will improve transient response atthe expense of increased output ripple voltage and inductor core saturation rating A 2uH inductor would have a 0 9A us rise time in this application resulting in a 5 5us delay in responding to a 5A load current step During this 5 5us the difference between the inductor current and the output current must be made up by the output capaci tor causing a temporary voltage droop at the output To minimize this effect the inductor value should usually be in the 1uH to SuH range for most typical 5V input LTC1553 circuits To optimize performance different combinations of input and output voltages and expected loads may re
27. ly all of the additional load current demanded by the load until the LTC1553 can adjust the inductor current to the new value Output capacitor ESR results in a step in the output voltage equal to the ESR value multiplied by the change in load current An 11A load step with a 0 050 ESR output capacitor will result in a550mV output voltage shift this is 19 6 of the output voltage for a 2 8V supply Because of the strong relationship between output capacitor ESR and output load transient response the output capacitor is usually chosen for ESR notfor capacitance value a capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC1553 applications OS CON electrolytic capacitors from SANYO and other manufac turers give excellent performance and have a very high performance size ratio for electrolytic capacitors Surface mount applications can use either electrolytic or dry tantalum capacitors Tantalum capacitors must be surge tested and specified for use in switching power supplies Low cost generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications AVX TPS series surface mount devices are popular surge tested tantalum capacitors that work well in LTC1553 applications A common way to lower ES
28. nents in the high current path Due to switching noise and variation of the actual current limit trip point is not highly accurate The current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions The exact current level where the limiting circuit begins to take effect will vary from unitto unitas the of Q1 varies For a given current limit level the external resistor from Imax to can be determined by Rostoyat RIMAX where Loap Maximum load current InippiE Inductor ripple current Vin vourjlvour I fosc Lo Vu fosc LTC1553 oscillator frequency 300kHz Lo Inductor value Rps onja1 Hot on resistance of Q1 at li limax Internal 18QuA sink current at VIN VOUT 2 g Figure 5 Current Limit Setting 1553 F05 AL MYR 11 LIC 1553 APPLICATIONS INFORMATION Table 4 Recommended Minimum Riwax Resistor vs Maximum Operating Load Current and External MOSFET Q1 MAXIMUM OPERATING SUD50N03 10 MTD20NO3HDL LOAD CURRENT A SUD50N03 10 TWO IN PARALLEL MTD20NOSHDL TWO IN PARALLEL 20 3 9 2 0 7 5 3 6 OUTEN and Thermistor Input Voo Vin The 1701553 includes a low power shutdown mode controlled by the logic at the OUTEN pin A high at OUTEN allows the part to operate normally A low level at OUTEN PENT
29. ote 7 The open loop DC gain and transconductance from the SENSE pin to COMP pin will be 1 265 3 3 and QmerR 1 265 3 3 respectively Note 8 The current limiting amplifier can sink but cannot source current Under normal not current limited operation the output current will be zero Note 9 Under typical soft current limit the net soft start discharge current will be 60pA 10uA 1ss 50pA The soft start sink to source current ratio is designed to be 6 1 Note 10 When VIDO to VIDA are all HIGH the LTC1553 will be forced to shut down internally The OUTEN trip voltages are guaranteed by design for all other input codes 0 25mA pin if any of the VIDO to VIDA pins are pulled low AL HUS LIC 1553 TYPICAL PERFORMANCE CHARACTERISTICS Typical 2 8V Vour Distribution NUMBER OF UNITS 2 795 2 805 2 815 2 825 OUTPUT VOLTAGE V 0 2 7175 2 785 1553 G01 Line Regulation 2 825 REFER TYPICAL APPLICATION 2 820 CIRCUIT FIGURE 1 OUTPUT NO LOAD OUTPUT VOLTAGE V n2 ES a 4 95 5 05 5 15 5 25 INPUT VOLTAGE V 1553 G04 Over Temperature Driver Disable vs Temperature TEMPERATURE C 1553 607 EFFICIENCY ERROR AMPLIFIER TRANSCONDUCTANCE millimho Efficiency vs Load Current TTT EEC H REFER TO TYPICAL APPLICATION CIRCUIT FIGURE 1 100 5 Vin 5V PVcc 12V Vout 2 8V Cour 330uF x7 Lo 2uH 40
30. ove the internal reference To prevent these two comparators from triggering due to noise the MIN and MAX comparators response times are deliber ately controlled so that they take two to three microsec onds to respond These two comparators help prevent extreme output perturbations with fast output transients while allowing the main feedback loop to be optimally compensated for stability 10 LS HUS LIC 1553 APPLICATIONS INFORMATION Soft Start and Current Limit The LTC1553 includes a soft start circuit which is used for initial start up and during current limit operation The SS pin requires an external capacitor to GND with the value determined by the required soft start time An internal 1QuA current source is included to charge the external SS capacitor During start up the COMP pin is clamped to a diode drop above the voltage at the SS pin This prevents the error amplifier ERR from forcing the loop to maxi mum duty cycle The 1701553 will begin to operate at low duty cycle as the SS pin rises above about 1 2V 1 8V As SS continues to rise Qss turns off and the error amplifier begins to regulate the output The MIN compara tor is disabled when soft start is active to prevent it from overriding the soft start function The LTC1553 includes yet another feedback loop to con trol operation in current limit Just before every falling edge of G1 the current comparator CC samples and holds the voltage
31. overcurrent condition the duty cycle is reduced by discharging the soft start capacitor through a voltage controlled current source Under severe overloads or output short circuit conditions the chip will be repeatedly forced into soft start until the short is removed preventing the external components from being damaged Under output overvoltage conditions the MOSFET drivers will be disabled permanently until the chip power supply is recycled or the OUTEN pin is toggled OUTEN can optionally be connected to an external nega tive temperature coefficient NTC thermistor placed near the external MOSFETs orthe microprocessor Three thresh old levels are provided internally When OUTEN drops to 2V OT will trip issuing a warning to the external CPU If the temperature continues to rise and the OUTEN input drops to 1 V the G1 and G2 pins will be forced low If OUTEN is pulled below 1 2V the LTC1553 will go into shutdown mode cutting the supply currentto a minimum If thermal shutdown is not required OUTEN can be con nected to a conventional TTL enable signal The free running 300kHz PWM frequency can be synchronized to afaster external clock connected to OUTEN Adjusting the oscillator frequency can add flexibility in the external component selection See the Clock Synchronization section Output regulation can be monitored with the PWRGD pin which in turn monitors the internal MIN and MAX com parators If the output is 5 beyond th
32. ower devices Be sure to orient the power circuitry so that a clean power flow path is achieved Conductor widths should be maximized and lengths minimized After you are satisfied with the power path the control circuitry should be laid out It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths 2 The GND and SGND pins should be shorted right at the LTC1553 This helps to minimize internal ground disturbances in the LTC1553 and prevents differences in ground potential from disrupting internal circuit operation This connection should then tie into the ground plane ata single point preferably at a fairly quiet point in the circuit such as close to the output capaci tors This is not always practical however due to physical constraints Another reasonably good point to make this connection is between the output capacitors and the source connection of the low side FET Q2 Do nottie this single point ground in the trace run between the low side FET source and the input capacitor ground as this area of the ground plane will be very noisy 3 The small signal resistors and capacitors for frequency compensation and soft start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace Do not connect these parts to the ground plane 4 The Vcc and PVcc decoupling capacitors
33. quire different inductor values Once the required value is known the inductor core type can be chosen based on peak current and efficiency requirements Peak current in the inductor will be equal to the maximum output load current plus half of the peak to peak inductor ripple current Ripple current is set by the inductor value the input and output voltage and the operating frequency The ripple current is approximately equal to Vin Vo ut Vo ur 10 fosc 101553 oscillator frequency 300kHz Lo Inductor value IRIPPLE AL MYR 15 LIC 1553 APPLICATIONS INFORMATION solving this equation with our typical 5V to 2 8V applica tion with a 2uH inductor we get 2 2 0 56 300kHz 2uH Peak inductor current at 11 2A load 11 244 5 1224 The ripple current should generally be between 10 and 40 of the output current The inductor must be able to withstand this peak current without saturating and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss Note that in circuits not employing the current limit function the current in the inductor may rise above this maximum under short circuit or fault conditions the inductor should be sized accordingly to withstand this additional current Inductors with gradual saturation characteristics are often the best choice Input and Output Capacitors A typical LTC1553 design puts significant
34. ralleled 330uF AVX TPS Output Capacitors Table 7 Suggested Compensation Network for 12V Input Application Using Multiple Paralleled 330uF AVX TPS Output Capacitors SR 9 6 4950 22 0 010 96 Tables 6 and 7 show the suggested compensation com ponents for 5V and 12V input applications based on the inductor and output capacitor values The values were calculated using multiple paralleled 330uF AVX TPS series Surface mount tantalum capacitors as the output capaci tor The optimum component values might deviate from the suggested values slightly because of board layout and operating condition differences An alternate output capacitor is the Sanyo MV GX series Using multiple parallel 1500uF Sanyo MV GX capacitors for the output capacitor Table 8 shows the suggested compensation component value for a 5V input application based on the inductor and output capacitor values Table 8 Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 1500uF SANYO MV GX Output Capacitors oun Sr 0 VIDO to VID4 PWRGD and FAULT The digital inputs VIDO to VIDA program the internal DAC which in turn controls the output voltage These digital input controls are intended to be static and are not designed for high speed switching Forcing Vgyr to step from a high to a low voltage by changing the VID pins quickly can cause FAULT to trip Figure 11 shows the relationship between th
35. sed loop transfer function The zero and pole from the compensation network are 1 1 LA oe eee f TT Z and P 2x Rc C1 respectively Figure 10b shows the Bode plot of the overall transfer function The compensation value used in this design is based on the following criteria fey 12f o fj c and fp 5 At the closed loop frequency fco the attenuation due the LC filter and the input resistor divider is compensated by the gain of the PWM modulator and the gain of the error amplifier QmerR Re Although a mathematical approach to frequency compensation can be used the added 1553 F10 Figure 10a Compensation Pin Hook Up few LTC1553 SWITCHING FREQUENCY fco CLOSED LOOP CROSSOVER FREQUENCY LOOP GAIN 20dB DECADE 1553 F10b Figure 10b Bode Plot of the LTC1553 Overall Transfer Function AL HUS 1 LIC 1553 APPLICATIONS INFORMATION complication of input and or output filters unknown capacitor ESR and gross operating point changes with input voltage load current variations all suggest a more practical empirical method This can be done by injecting atransient current atthe load and using an RC network box to iterate toward the final compensation values or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros Table 6 Suggested Compensation Network for 5V Input Application Using Multiple Pa
36. should be as close to the LTC1553 as possible The 10uF bypass capacitors shown at Vec and PVcc will help provide optimum regulation performance 5 he plate of should be connected as close as possible to the drain of the upper MOSFET An addi tional 1uF ceramic capacitor between VIN and power ground is recommended O gt The SENSE pin is very sensitive to pickup from the switching node Care should be taken to isolate SENSE from possible capacitive coupling to the inductor switch ing signal 0 1uF is required between the SENSE pin and the SGND pin next to the LTC1553 OUTEN is a high impedance input and should be externally pulled up to a logic HIGH for normal operation 8 Kelvin sense IMAx and lpg at Q1 drain and source pins AL HUS 19 LIC 1553 APPLICATIONS INFORMATION VOUT OUTEN VIDO VID1 VID2 VID3 VIDA PWRGD FAULT OT Css BOLD LINES INDICATE C1 HIGH CURRENT PATHS 1153 F12 Figure 12 LTC1553 Layout Diagram 20 AL HUS LIC 1553 APPLICATIONS INFORMATION Ciy 1200uF 2 7k 1N5817 y Vcc Imax PVcc 0 1uF PWRGD emn hn MEE NENNEN SYSTEM LTC1553 VOUT SGND GND SENSE DALE NTHS 1206N02 150pF MOUNTTHERMISTER Css 01 SILICONIX SUD50N03 10 IN CLOSE THERMAL T Oh 2 s SANYO 10MV1200GX PROXIMITY TO Q1 tCOILTRONICS CTX02 13198 OR PANASONIC 12TS 2R5SP tt AVX TPSE337M006R0100 15
37. y Low Noise Synchronous Step Down Drive Synchronous N Channel Viy lt 36V owitching Regulator LTC1438 Dual High Efficiency Low Noise Synchronous Step Down Dual LTC1435 with Power On Reset switching Regulator 1553f LT TP 0198 4K PRINTED IN USA 2 Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 LINEAR FAX 408 434 0507 TELEX 499 3977 www linear tech com LINEAR TECHNOLOGY CORPORATION 1997

LINEAR TECHNOLOGY - 1 LTC1553 5 handbook

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