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LINEAR TECHNOLOGY - LTC4101 handbook

1. VSMBALERT 9 9V Vpp 0 2 2 pA VoL CHGEN Output Low Voltage lo 100uA e 0 5 V CHGEN Output Pull Up Current VcHGEN VoL 17 5 10 3 5 Vi CHGEN Input Low Voltage e 0 9 V Vin CHGEN Input High Voltage Vpp 3V e 25 V Vpp 5 5V 3 9 V Power On Reset Duration Vpp Ramp from OV to gt 3V in 5us 100 us SMBus Timing Refer to System Management Bus Specification Revision 1 1 Section 2 1 for Timing Diagrams THIGH SCL Serial Clock High Period IPULL Up 350uA 250pF 9 31 e 4 us Vpp 3V and Vpp 5 5V tiow SCL Serial Clock Low Period IpULL Up 350uA 250pF Rpy 9 31k e 47 15000 us Vpp 3V and Vpp 5 5V tr SDA SCL Rise Time Ci gap 250pF Rpy 9 31k Vpp 3V 1000 ns and Vpp 5 5V tF SDA SCL Fall Time 250pF Rey 9 31k 3V 300 ns and Vpp 5 5V tsu sTA Start Condition Setup Time Vpp 3V and Vpp 5 5V 47 us tup sTA Start Condition Hold Time Vpp 3V and Vpp 5 5V 4 us HD DAT SDA to SCL Falling Edge Hold Time Vpp 3V and Vpp 5 5V e 300 ns Slave Clocking in Data trIMEOUT Time Between Receiving Valid Vpp 3V and Vpp 5 5V e 140 175 210 Sec ChargingCurrent and ChargingVoltage Commands Vote 1 Stresses beyond those listed under Absolute Maximum Ratings temperature range are assured by design characterization and correlation may cause permanent damage to the device Exposure to any Absolute with statistical process controls Maxi
2. e Internal power on reset condition 4101f 15 LTC4101 OPERATION SMBus Accelerator Pull Ups Both SCL and SDA have SMBus accelerator circuits which reduce the rise time on systems with significant capaci tance on the two SMBus signals The dynamic pull up circuitry detects a rising edge on SDA or SCL and applies 1mA to 10mA pull up to when Viy gt 0 8V until Viy Vpp 0 8V external pull up resistors are still required to supply DC current This action allows the bus to meet SMBus rise time requirements with as much as 250pF on each SMBus signal The improved rise time will benefit all of the devices which use the SMBus especially those devices that use the I2C logic levels Note that the dynamic pull up circuits only pull to Vpp so some SMBus devices that are not compliant to the SMBus specifications may still have rise time compliance problems if the SMBus pull up resistors are terminated with voltages higher than Vpp The Control Block The LTC4101 charger operations are handled by the control block This block is capable of charging the se lected battery autonomously or under SMBus Host con trol The control block can request communications with the system management host SMBus Host by asserting SMBALERT 0 this will cause the SMBus Host if present to poll the LTC4101 The control block receives SMBus slave commands from the SMBus interface block The control block al
3. amp 740 FVpcin 20V 45 Vprog 4 1761 4V 4 0 1 1 0 05 10 15 20 25 30 35 40 45 OUTPUT CURRENT A 4101 G02 Battery Leakage Current vs Battery Voltage 40 ov 35 30 25 5 20 15 e 10 amp 5 0 0 5 10 15 20 25 30 SMBus Accelerator Operation Vpp 5V 5 200pF LTC41 01 RPULLU oV tus DIV 4101 609 BATTERY VOLTAGE V 4101 G05 PWM Frequency vs Duty Cycle PROGRAMMED CURRENT 10 DCIN 9V DCIN 12V DCIN 24V 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 DUTY CYCLE Voyr Vin 4101 G03 Efficiency at Vppog 4 208V 00 96 92 88 84 80 76 72 00 05 1 0 1 Low Current Operation 4101 607 0 6 Vpp 5V 4V 0 5 20V Vprog 4 208V 0 4 NO LOW 03 CURRENT MODE gt PROGRAMMED 0 2 CURRENT LOW 0 1 CURRENT MODE 0 0 0 05 0 10 0 15 0 20 0 25 0 30 0 35 0 40 IPRog 4101 G10 LTC4101 TYPICAL PERFORMANCE CHARACTERISTICS 25 uniess otherwise noted Charging Current Error 200 T T Vpp 5V 100 Vocin 20V 0 Vocin 9V w OUTPUT CURRENT ERROR mA 100 200 0 1 2 3
4. Purpose The LTC4101 will use the information sent by this function to properly charge the battery The LTC4101 will only respond to certain alarm bits Writing to this function does not necessarily cause an alarm condition that inhibits battery charging e SMBus Protocol Write Word Input Only the OVER CHARGED ALARM TERMINATE CHARGE ALARM reserved 0x2000 and OVER TEMP ALARM bits are supported by the LTC4101 Writing a one to any of these specified bits will inhibit the charging by the LTC4101 and will set the ALARM INHIBITED bitin the ChargerStatus function The TERMINATE DISCHARGE ALARM REMAINING CAPACITY ALARM REMAINING TIME ALARM and the ERROR bits are ignored by the LTC4101 LTCO h3C Description The SMBus Host uses this command to determine the version number of the LTC4101 and set extended operation modes not defined by the Smart Battery Charger Specification Purpose This function allows the SMBus Host to determine if the battery charger is an LTC4101 Identi fying the manufacturer and version of the Smart Battery Charger permits software to perform tasks specific to a given charger The LTC4101 also provides a means of disabling the LOWI current mode of the 1 e SMBus Protocol Write Word Input The NO_LOWI is the only bit recognized by this function The default value of NO_LOWI is zero The LTC4101 LOWI current mode provides a more accurate average charge current when the
5. 97 3 107 3 mV Charging Current OxOFFC 0x1000 Note 7 Charging Voltage Resolution Guaranteed Monotonic 2 9V lt Vgar lt 5 6V 11 Bits Charging Voltage Granularity 16 mV Charging Voltage Limit 4 206 4 240 4 274 Charging Voltage 0x1090 Note 7 Ryum 10k 1 4 270 4 304 4 338 Charging Voltage 0x10D0 Note 7 33k 1 4 397 4432 4 467 Charging Voltage 0x1150 Note 7 RyuiM 100k 1 4476 4512 4 548 Charging Voltage 0 11 0 Note 7 Rvtim Open or Short to Vpp 5 460 5 504 5 548 Charging Voltage 0x1580 Note 7 LTC4101 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA 25 C 20V Vpp 3 3V 4V unless otherwise noted Note 4 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Levels Vit SCL SDA Input Low Voltage Vpp 3V and Vpp 5 5V e 0 8 V Vin SCL SDA Input High Voltage Vpp 3V and Vpp 5 5V e 21 V VoL SDA Output Low Voltage IPULL Up 350A 0 4 li SCL SDA Input Current Vspa Vsci Vit 1 1 SCL SDA Input Current Vspa Vin 1 1 VoL SMBALERT Output Low Voltage lPuLL up 500A 0 4 SMBALERT Output Pull Up Current VSMBALERT VoL 17 5 10 3 5 SDA SCL SMBALERT Power Down Leakage
6. Schottky to allow it to be pulled to 5V externally SDA Pin 8 SMBus Data Signal from Main host con trolled SMBus External pull up resistor is required SCL Pin 9 SMBus Clock Signal from Main host con trolled SMBus External pull up resistor is required ACP Pin 10 This Output Indicates the Value of the DCDIV Comparator It can be used to indicate whether AC is present or not DCDIV Pin 11 Supply Divider Input This is a high impedance comparator input with a 1 2V threshold rising edge and hysteresis GND Pin 12 Ground for Digital and Analog Circuitry Pin 13 An external resistor is connected between this pin and GND The value of the external resistor programs the range and resolution of the programmed charger current Pin 14 An external resistor is connected between this pin and GND The value of the external resistor programs the range and resolution of the charging voltage 4101f 7 LTC4101 PIN FUNCTIONS THB Pin 15 SafetySignal Force Sense Pin to Smart Battery See description of operation for more detail The maximum allowed combined capacitance on THA THB and SafetySignal is 1nF see Figure 4 A series resistor 54 9k needs to be connected between this pin and the battery s SafetySignal for this circuit to work correctly THA Pin 16 SafetySignal Force Sense Pin to Smart Battery See description of operation for more detail The maximum allowed combined capacitance o
7. from Vc p 0 05V Forward Regulation Voltage VpciN Vci p 25 50 mV Reverse Voltage Turn Off Voltage VpciN Vci p e 60 25 mV INFET ON Clamping Voltage Vpcin VineeT 1 5 5 8 6 5 V OFF Clamping Voltage Vpcin VinreT 25 0 25 Oscillator fosc Regulator Switching Frequency 255 300 345 kHz Regulator Switching Frequency in Drop Out Duty Cycle 2 98 20 25 kHz Regulator Maximum Duty Cycle Vesp VgAT 98 99 Gate Drivers TGATE BGATE VrearE High 1mA 50 mV Vecate High Ci oAD 3000pF 4 5 5 6 10 V VraarE Low Vci P Vraart Ci oap 3000pF 4 5 5 6 10 V Vacate Low lgcATE 1mA 50 mV TGATE Transition Time TGTR TGATE Rise Time Ci oap 3000pF 10 to 90 50 110 ns TGTF TGATE Fall Time Ci oap 3000pF 10 to 90 50 100 ns BGATE Transition Time BGTR BGATE Rise Time Ci oap 3000pF 10 to 90 40 90 ns BGTF BGATE Fall Time Ci oap 3000pF 10 to 90 40 80 ns Vrgare at Shutdown Vci y VraarE 1 100 mV Vgcare at Shutdown lrgATE 14A 100 mV 4101f LTC4101 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at Ta 25 C Vpcin 20V Vpp 3 3V 4V unless otherwise noted Note 4 SYMBOL P
8. 240V Adapter Rating 2 7 L DCIN 0 0330 9V TO 12V 01 DCIN FROMWALL 4 ADAPTER LTC4101 PGND SYSTEM R1 LOAD 4 9k 23 1 Q2 C2 03 10uF x2 3 16V BGATE Q3 D1 2 1 DCIN 4A 100k 04 1 2 Si790IEDN Rsns 0 0250 ms 0 5W 1 10V 3V TO 5 5V SDA SMBALERT 03 SDA 04 SCL SCL C5 0 1 pF ow 1 SafetySignal SMART BATTERY D1 MBRM140T3 D2 D5 SMALL SIGNAL SCHOTTKY Q1 1 2 Si790IEDN Q2 FDS6685 Q3 Si7804DN 4101 TAO2 PART NUMBER DESCRIPTION COMMENTS LTC1760 Smart Battery System Manager Autonomous Power Management and Battery Charging for Two Smart Batteries SMBus Rev 1 1 Compliant LTC4006 Small High Efficiency Fixed Voltage Constant Current Constant Voltage Switching Regulator with Termination Lithium lon Battery Charger Timer AC Adapter Current Limit and SafetySignal Sensor in a Small 16 Pin Package LTC4007 High Efficiency Programmable Voltage Complete Charger for 3 or 4 Cell Li lon Batteries AC Adapter Battery Charger with Termination Current Limit SafetySignal Sensor and Indicator Outputs LTC4008 High Efficiency Programmable Voltage Current Constant Current Constant Voltage Switching Regulator Resistor Voltage Battery Charger Current Programming AC Adapter Current Limit and SafetySignal Sensor LTC4010 High Efficiency Standalone Nickel Battery Charger Complete NiMH NiCd Charger in a 16 Pin TSSOP P
9. 4 CHARGING CURRENT A 4101 G11 Transfer Function of Charger 50 Vpp 5V 0 120A 0 VpciN 9V VpciN 28V OUTPUT VOLTAGE ERROR V ch 100 CHARGING VOLTAGE V 4101 G12 PIN FUNCTIONS TGATE Pin 1 Drives the Top External P MOSFET of the Battery Charger Buck Converter PGND Pin 2 High Current Ground Return for BGATE Driver BGATE Pin 3 Drives the Bottom External N MOSFET of the Battery Charger Buck Converter INFET Pin 4 Drives the Gate of the External Input P MOSFET DCIN Pin 5 External DC Power Source Input Bypass to ground with a 0 1uF capacitor CHGEN Pin 6 Digital Bidirectional Pin to Enable Charger Function This pin is connected as a wired AND bus The following events will cause the POWER_FAIL bit in the ChargerStatus register to become set 1 An external device pulling the CHGEN signal to within 0 9V to GND 2 The AC adapter voltage is not above the battery voltage SMBALERT Pin 7 Active Low Interrupt Output to Host referred to as the SMBALERT signal in the SMBus Revi sion 1 1 specification Signals host that there has been a change of status in the charger registers and that the host should read the LTC4101 status registers to determine if any action on its part is required This signal can be connected to the optional SMBALERT line of the SMBus Open drain with weak current source pull up to Vpp with
10. A reasonable starting point for setting ripple current is Al 0 4 1 Remember the maximum Al occurs at the maximum input voltage The inductor value also has an effect on low current operation The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on Lower inductor values higher Al will cause this to occur at higher load currents which can cause a dip in efficiency in the upper range of low current operation Table 10 Recommended Inductor Values Inductance Imax A Vin Range V 1 2 3 annd 4 lt 7 5 16uH 20 8uH 20 4uH 20 lt 9 0 20uH 20 10uH 20 5 20 lt 12 0 24uH 20 12uH 20 20 lt 15 0 26uH 20 13uH 20 6 5uH 20 lt 28 0 30uH 20 15uH 20 7 5uH 20 RSENSE 0 10 0 050 0 0250 3 Amp uses the same Reense that 4 amps uses Thus the inductance can be the same Choose and inductor who s inductance value is equal to or greater than the value shown Values assume 1 32 RSS result from 20 inductance tolerance and a 25 inductance loss at Imax 2 Inductor ripple current ratio of 0 51 of across RSENSE 3 Voyt is at 4 2V Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the charger a P channel MOSFET for the top main switch and an N channel MOSFET for the bottom syn chronous switch The peak
11. Pin 24 Positive Input to the Input Current Limiting Circuit Block This pin also serves as a power supply for the IC LTC4101 BLOCK DIAGRAM 20uF OSCILLATOR WATCHDOG DETECT ton gm 1m0 19V b CQ Ipc C8 100mV am i5mo DE I 0068 D R5 6 04k C7 0 0015uF 01 id ET ace F 1 2V Ri C1 0 1 re T aL 105A i 7 mna l 7 Vop SMBUS POWER SUPPLY 1 N A k of 7T DCIN 10 BIT i TO HOST AND BATTERY T an spa 81 AND CONTROL liis scL 9 LIMIT 1 18k DECODER 1 Ryum S RiLIM 54 9k TBT ey ee a a E 2 10k Figure 2 4101f LTC4101 TEST CIRCUIT LTC4101 4101 TC01 Bar OC 199 VDAC FOR Wpac 4 176V 0x1050 DCIN 21V CLN CLP 20V Vpp 3 3V OPERATION Overview Refer to Block Diagram The LTC4101 is composed of a battery charger section a charger controller a 10 bit DAC to control charger cur rent an 11 bit DAC to control charger voltage a SafetySignal decoder limit decoder and an SMBus controller block If no battery is present the SafetySignal decoder indicates a RES_OR condition and charging is disabled by the charger controller CHGEN Low Charging will also be disabled if DCDIV is low or the SafetySignal is decoded as RES HOT If a battery is inserted and AC power is con nected the battery will be charged with an 80mA wake up current The wake up c
12. SafetySignal CONTROL RES HOT 4101 F04 Figure 4 SafetySignal Decoder Block 4101f 17 LTC4101 OPERATION When AC is present the LTC4101 samples the value of the SafetySignal and updates the ChargerStatus register ap proximately every 32ms The state machine successively samples the SafetySignal value starting with the RES_OR 2 RES COLD threshold then RES_COLD gt RES_IDEAL threshold RES_IDEAL gt RES_HOT threshold and finally the RES_HOT gt RES_UR threshold Once the SafetySignal range is determined the lower value thresholds are not sampled The SafetySignal decoder block uses the previ ously determined SafetySignal value to provide the appro priate adjustment in threshold to add hysteresis The Rryp resistor value is used to measure the RES_OR gt RES_COLD and RES_COLD gt RES_IDEAL thresholds by connecting the THB pinto Vpp and measuring the voltage resultant on the THA pin The resistor value is used to measure the RES_IDEAL gt RES_HOT and RES_HOT gt RES_UR thresholds by connecting the THA pin to Vpp and measur ing the voltage resultant on the THB pin The SafetySignal decoder block uses a voltage divider network between Vpp and GND to determine SafetySignal range thresholds Since the THA and inputs are sequentially connected to Vpp this provides Vpp noise immunity during SafetySignal measurement When AC power is not available the SafetySignal block supports the following low power
13. if the LTC4101 is to properly sense the value Of RSafetySignal 18 LTC4101 OPERATION The lj jy Decoder Block The value of an external resistor connected from this pin to GND determines one of four current limits that are used for maximum charging current value These limits provide a measure of safety with a hardware restriction on charg ing current which cannot be overridden by software Table 6 1 Trip Points and Ranges The Vij Decoder Block The value of an external resistor connected from this pin to GND determines one of five voltage limits that are applied to the charger output value These limits provide a measure of safety with a hardware restriction on charg ing voltage which cannot be overridden by software Table 7 Vim Trip Points and Ranges See Figure 5 EXTERNAL CONTROLLED EXTERNAL CONTROLLED RESISTOR CHARGING RESISTOR CHARGING VOLTAGE lum VOLTAGE CURRENT RANGE GRANULARITY Ryu VOLTAGE Vout RANGE GRANULARITY Short to GND 0 09Vpp 0 1 1023mA 1 Short to Wem lt 0 09Vyccp 2900 lt Vout 16 10k 1 0 17 lt Vim 0 1 2046mA 2 GND 4240mV lt 0 34Vypp 10k 1 0 17Vypp lt 2900 lt Vour 16mV 33k 1 0 42Wypp lt Vim 0 1 3068mA 4mA lt 0 34Vvpp lt 4304mV lt 0 59V 33k 1 0 42Wyccp lt 2900mV lt Vout 16mV Open gt 250k 0 66Vypp lt Vitim 0 lt 1 lt 4092mA 4
14. to peak gate drive levels are set internally This voltage is typically 6V Consequently logic level threshold MOSFETs must be used Pay close attention to the BVpss specification for the MOSFETs as well many of the logic level MOSFETs are limited to 30V or less Selection criteria for the power MOSFETs include the ON resistance total gate capacitance reverse transfer capacitance Cgss input voltage and maximum output current The charger is operating in continuous mode so the duty cycles for the top and bottom MOSFETs are given by Main Switch Duty Cycle Voyr Viw Synchronous Switch Duty Cycle Vin Vout Vin The MOSFET power dissipations at maximum output Current are given by PMAIN Vour Vin Iyax 1 6AT Rps oN k Vin Imax Crss fosc PSYNC Vin Vour Vin Imax 2 1 8AT Rps ou Where SAT is the temperature dependency of Rps on and k is a constant inversely related to the gate drive current Both MOSFETs have I R losses while the PMAIN equation includes an additional term for transition losses which are highest at high input voltages For lt 20V the high current efficiency generally improves with larger MOS FETs while for Viy gt 20V the transition losses rapidly increase to the point that the use of a higher Rps on device with lower actually provides higher efficiency The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the d
15. 01 PACKAGE DESCRIPTION G Package 24 Lead Plastic SSOP 5 3mm Reference LTC DWG 05 08 1640 Y gggggmmaggaul sse lt E g 24 23 22 21 20 19 18 17 16 15 14 13 78 82 53 57 7 40 8 20 291 323 000000001000 0 42 0 03 1 lt gt lt 0 65 BSC RECOMMENDED SOLDER PAD LAYOUT Y 123456 7 8 9101112 T 5 00 5 60 L 197 220 079 197 221 MAX 0 8 Y Y 0 09 0 25 0 55 0 95 285 de 0035 010 0022 037 s T NOTE fos ms 002 1 CONTROLLING DIMENSION MILLIMETERS MIN MILLIMETERS TYP 624 SSOP 0204 2 DIMENSIONS ARE IN INCHES 3 DRAWING NOT TO SCALE DIMENSIONS DO NOT INCLUDE MOLD FLASH MOLD FLASH SHALL NOT EXCEED 152mm 006 PER SIDE DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 254mm 010 PER SIDE 41011 Information furnished by Linear Technology Corporation is believed to be accurate and reliable y CAR However no responsibility is assumed for its use Linear Technology Corporation makes no represen 2 TECHNOLOGY tation thatthe interconnection of its circuits as described herein will not infringe on existing patent rights LTC4101 TYPICAL APPLICATION LTC4101 Li lon Battery Charger lj jy 4 4
16. 13 Description The SMBus Host uses this command to read the LTC4101 s status bits Purpose Allows the SMBus Host to determine the status and level of the LTC4101 SMBus Protocol Read Word Output The CHARGE_INHIBITED bit reflects the status of the LTC4101 set by the INHIBIT_CHARGE bit in the ChargerMode function The POLLING_ENABLED VOLTAGE_NOTREG and CURRENT_NOTREG are not supported by the LTC4101 The LTC4101 always reports itself as a Level 2 Smart Battery Charger CURRENT_OR bit is set only when ChargingCurrent is set to a value outside the current regulation range of the LTC4101 This bit may be used in conjunction with the INHIBIT_CHARGE bit of the ChargerMode and ChargingCurrent to determine the current capability of the LTC4101 When ChargingCurrent is set to the pro grammatic maximum current 1 the CURRENT_OR bit will be set VOLTAGE_OR bit is set only when ChargingVoltage is set to a value outside the voltage regulation range of the LTC4101 This bit may be used in conjunction with the INHIBIT_CHARGE bit of the ChargerMode and ChargingVoltage to determine the voltage capability of the LTC4101 When ChargingVoltage is set to the programmatic maximum voltage the VOLTAGE_OR bit will be set The RES_OR bit is set only when the SafetySignal resis tance value is greater than 95kQ This indicates that the SafetySignal is to be considered as an open circuit The RES_COLD bit is set only whe
17. ARAMETER CONDITIONS MIN TYP MAX UNITS AC Present Comparator DCDIV Threshold Vpcpiv Rising from 1V 1 4V e 114 1 20 1 26 V DCDIV Hysteresis 25 mV DCDIV Input Bias Current 1 2V 1 1 Vou lacp 2mA 2 V ACP VoL lacp 1mA 0 5 V DCDIV to ACP Delay Vocpiv 1 3V 10 us SafetySignal Decoder SafetySignal Trip RES_COLD RES_OR 11300 1 1nF Note 6 e 95 100 105 kQ 54 90 1 SafetySignal Trip RES_IDEAL RES_COLD 11300 1 Cty 1nF Note 6 285 30 31 5 kQ 54 90 1 SafetySignal RES_HOT RES_IDEAL Rrya 11300 1 Cty 1nF Note 6 2 85 3 315 kQ 54 90 1 SafetySignal Trip RES_UR RES_HOT 11300 1 Cty 1nF Note 6 e 425 500 575 Q 54 90 1 Time Between SafetySignal Measurements DCDIV 1 3V 32 ms DCDIV 1V 250 ms DACs Charging Current Resolution Guaranteed Monotonic Above Imax 16 10 Bits Charging Current Granularity Rium 0 1 mA 10k 1 2 mA 33k 1 4 mA Open or Short to Vpp 4 mA Wake Up Charging Current lyaxe up All Values of M 80 Note 5 mA All Values of Charging Current Limit 9 0 1 97 3 107 3 mV CSP BAT Charging Current OxO3FF 0x0400 Note 7 10k 1 0 2 97 3 107 3 mV Charging Current 0x07FE 0x0800 Note 7 33k 1 0 3A 72 3 82 3 mV Charging Current OXOBFC 0x0C00 Note 7 Open or Short to Vpp 0 44
18. C Junction Temperature Range 40 to 125 C Storage Temperature Range 65 to 150 C Lead Temperature Soldering 10 sec 300 C PACKAGE ORDER INFORMATION TGATE PGND BGATE INFET DCIN CHGEN SMBALERT SDA SCL ACP DCDIV GND TOP VIEW G PACKAGE 24 LEAD PLASTIC SSOP Tymax 125 C Oja 90 C W ORDER PART NUMBER LTC4101EG Order Options Tape and Reel Add TR Lead Free Add PBF Lead Free Tape and Reel Add TRPBF Lead Free Part Marking http www linear com leadfree Consult LTC Marketing for parts specified with wider operating temperature ranges ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA 25 C 20V Vpop 3 3V 4V unless otherwise noted Note 4 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DCIN Operating Range 6 28 V IDCIN DCIN Operating Current Charging Sum of Currents on 3 5 mA DCIN CLP and CLN VTOL Charge Voltage Accuracy Note 2 1 1 1 1 13 1 3 Charge Current Accuracy Note 3 Vesp Target 102 3mV 2 6 Ipac OXFFFF 3 7 Vpp Vpp Operating Voltage OV lt Vpcin lt 28V e 3 5 5 V Shutdown Battery Leakage Current DCIN OV Vei p Vein Vesp VgaT e 15 35 UVLO Undervolt
19. Ni AR LTC4101 TECHNOLOGY smart Battery Charger Controller FEATURES DESCRIPTION Single Chip Smart Battery Charger Controller The LTC 4101 Smart Battery Charger is a single chip 100 Compliant Rev 1 1 SMBus Support Allows charging solution that dramatically simplifies construc for Operation with or without Host tion of an SBS compliant system The LTC4101 imple Up to Charging Current Capability ments a Level 2 charger function whereby the charger can High Efficiency Synchronous Buck Charger be programmed by the battery or by the host A SafetySignal Veat Optimized 3V to 5 5V on the battery being charged is monitored for tempera m SMBus Accelerator Improves SMBus Timing ture connectivity and battery type information The SMBus m Hardware Interrupt and SMBAlert Response interface remains alive when the AC power adapter is Eliminate Interrupt Polling removed and responds to all SMBus activity directed to 0 5V Dropout Voltage Maximum Duty Cycle gt 98 it including SafetySignal status via the ChargerStatus AC Adapter Current Limit Maximizes Charge Rate command The charger also provides an interrupt to the m 0 8 Voltage Accuracy 4 Current Accuracy host whenever a status change is detected e g battery m 10 Bit DAC for Charge Current Programming removal AC adapter connection m 11 Bit DAC for Charger Voltage Programming Charai e ging current and voltage are restricted to chemistry vie inn ae Limits specif
20. OSFET is turned on until either the inductor current trips the current comparator Iggy or the beginning of the next cycle The oscillator uses the equation _ Voci Vear Vocin fosc 10 LTC4101 OPERATION to set the bottom MOSFET on time The result is quasi constant frequency operation the converter frequency remains nearly constant over a wide range of output voltages This activity is diagrammed in Figure 3 OFF TGATE ON ON BGATE OFF INDUCTOR CURRENT 4101 F01 Figure 3 The peak inductor current at which resets the SR latch is controlled by the voltage on Ity 1 is in turn controlled by several loops depending upon the situation at hand The average current control loop converts the voltage between CSP and BAT to a representative current Error amp CA2 compares this current against the desired current programmed by the Ipac at the Ipc pin and adjusts for the desired voltage across The voltage at BAT is divided down by an internal resistor divider set by the VpAc and is used by error amp EA to decrease 1 if the divider voltage is above the 1 19V reference The amplifier CL1 monitors and limits the input current normally from the AC adapter to a preset level 100mV At input current limit CL1 will decrease the lr voltage to reduce charging current An overvoltage comparator OV guards against transient overshoots gt 7 In this case the to
21. The current DAC is a delta sigma modulator which con trols the effective value of an external resistor used to set the current limit of the charger Figure 7 is a simplified diagram of the DAC operation The delta sigma modulatorand switch convertthe ChargingCurrent value received via the SMBus to a variable resistance equal to 1 25Rg_eq ChargingCurrent I_impq Ripc Therefore programmed current is equal to ICHARGE 1 02 3mV Rsense ChargingCurrent IL mpq for ChargingCurrent lt IpRoG FROM CA1 AMP 4101 F07 Figure 7 Current DAC Operation When a value less than 1 16th of the maximum current allowed by 1 is applied to the current DAC input the current DAC enters a different mode of operation called LOWI The current DAC output is pulse width modulated with a high frequency clock having a duty cycle value of 1 8 Therefore the maximum output current provided by the charger is Imax 8 The delta sigma output gates this low duty cycle signal on and off The delta sigma shift registers are then clocked ata slower rate about 45ms bit so that the charger has time to settle to the 8 value The resulting average charging current is equal to that requested by the ChargingCurrent value Note The LOWI mode can be disabled by setting the NO LOWI bit in the LTCO function When wake up is asserted to the current DAC block the delta sigma is then fixed at a value equal to 80mA inde
22. ackage Constant Current Switching Regulator LTC4011 High Efficiency Standalone Nickel Battery Charger Complete NiMH NiCd Charger in a 20 Pin TSSOP Package PowerPath Control Constant Current Switching Regulator LTC4060 Standalone Linear NiMH NiCd Fast Charger Complete NiMH NiCd Charger in a Small Leaded or Leadless 16 Pin Package No Sense Resistor or Blocking Diode Required LTC4100 Smart Battery Charger Controller For Smart Batteries with Voltages Above 5 5V LTC4412 Low Loss PowerPath Controller Very Low Loss Replacement for Power Supply OR ing Diodes Using Minimal External Components Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 FAX 408 434 0507 www linear com 4101f LT 0606 PRINTED IN USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 2006
23. age mV to the LTC4101 Purpose The LTC4101 uses the granularity of the and the value of the ChargingVoltage function to determine its charging voltage supplied to the battery The charging voltage will never be forced beyond the voltage permitted by The ChargingVoltage value will be truncated to the granularity of the Vpac The charging voltage will also be reduced if the battery current exceeds the programmed charging current e SMBus Protocol Write Word Input The CHARGING VOLTAGE is an unsigned 16 bit integer specifying the requested charging voltage in mV The LTC4101 considers any value from 0x0001 through 0 044 the same as writing 0x0000 The following 4101f 14 Une LTC4101 OPERATION table defines the maximum permissible value of CHARGING_VOLTAGE that will not set the VOLTAGE_OR in the ChargerStatus function for a given value of Ry jw Ryu Maximum ChargingVoltage Short to GND 0x1090 4240mV 1 0x10D0 4304mV 33kQ 1 0 1150 4432mV 100 1 0x11A0 4512mV Open or short to Vpp 0x1580 5504mV AlarmWarning h16 Description The Smart Battery acting as a bus master device sends the AlarmWarning message to the LTC4101 to notify it that one or more alarm conditions exist Alarm indications are encoded as bit fields in the Battery s Status register which is then sent to the LTC4101 by this function
24. age Lockout Threshold DCIN Rising Vgar OV e 42 4 7 5 5 V Vpp Power Fail Part Held in Reset Until this Vpp Present 3 V DCIN Current in Shutdown Vergen OV 2 3 mA Current Sense Amplifier CA1 Input Bias Current into BAT Pin 11 66 pA CMSL CA1 14 Input Common Mode Low 0 CMSH CA1 14 Input Common Mode High Vocin 28V e Vciu 0 2 V 4101f 2 A wee LTC4101 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA 25 Vpciy 20V Vpp 3 3V 4V unless otherwise noted Note 4 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Comparators Ingy ITREV Reverse Current Threshold Vcsp Vgar 30 mV Current Sense Amplifier CA2 Transconductance 1 mmho Source Current Measured at 1 4V 40 Sink Current Measured at Vity 1 4V 40 Current Limit Amplifier Transconductance 1 5 mmho Current Limit Threshold 93 100 107 mV CLN Input Bias Current 50 nA Voltage Error Amplifier EA Transconductance 1 mmho Sink Current Measured at Ith 1 4V 36 OVSD Overvoltage Shutdown Threshold as a Percent e 102 107 110 of Programmed Charger Voltage Input P Channel FET Driver INFET DCIN Detection Threshold Vpciu Vci p DCIN Voltage Ramping Up e 0 0 17 0 25 V
25. alue and potentially damage the battery or overload the wall adapter if no input current limiting is provided Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values A higher frequency gener ally results in lower efficiency because of MOSFET gate charge losses In addition the effect of inductor value on Imax A Rsense 1 Reense W Ryn 2 1 ripple current and low current Operation must also be 1023 0100 025 considered The inductor ripple current Al decreases TUE TT 025 T with higher frequency and increases with higher Viy 3 068 0 025 0 5 33k 1 4 092 0 025 0 5 Alt Vout 1 f L Vin Table 8 Common Resistor Values Adapter 7 Adapter Rc Value Re Power Rc Power Rating A Rating A Q 1 Limit A Dissipation W Rating W 1 5 140 0 068 147 0 15 0 25 1 8 1 67 0 062 1 61 0 16 0 25 2 0 1 86 0 051 1 96 0 20 0 25 23 2 14 0 047 2 13 0 21 0 25 2 5 2 33 0 043 2 33 0 23 0 50 27 2 51 0 039 2 56 0 26 0 50 3 0 2 79 0 036 2 79 0 28 0 50 3 3 3 07 0 033 3 07 0 31 0 50 3 6 3 35 0 030 3 35 0 33 0 50 40 3 72 0 027 3 72 0 37 0 50 Rounded to nearest 5 standard step value Many non standard values are popular 22 LTC4101 APPLICATIONS INFORMATION Accepting larger values of Al allows the use of low inductances but results in higher output voltage ripple and greater core losses
26. charge current is less than 1 16 of the full scale Ipac value When the NO_LOWI is set a less accurate 1 algorithm is used to generate the charging current but because the charger is not pulsed on and off it may be preferred SMBus Protocol Read Word Output The NO LOWI indicates the mode of opera tion If clear then the LOWI current mode will be used when the charging current is less than 1 16 of the full scale value The LTC Version Identification will always be 0x4040 for the LTC4101 Alert Response Address ARA Description The SMBus system host uses the Alert Response Address to quickly identify the generator of an SMBALERT event Purpose The LTC4101 will respond to an ARA if the SMBALERT signal is actively pulling down the SMBALERT bus The LTC4101 will follow the prioritization reporting as defined in the System Management Bus Specification Version 1 1 from the SBS Implementers Forum e SMBus Protocol 7 bit Addressable Device Re sponds to an ARA Output The Device Address will be sent to the SMBus system host The LTC4101 Device address is 0x12 or 0x09 if just looking at the 7 bit address field The following events will cause the LTC4101 to pull down the SMBALERT bus through the SMBALERT pin e Change of AC PRESENT in the ChargerStatus function e Change of BATTERY PRESENT inthe ChargerStatus function e Setting ALARM INHIBITED in the ChargerStatus function
27. d ChargingCurrent are rewritten to the LTC4101 power is removed DCDIV Vacp or if a battery is removed The setting of the ALARM INHIBITED will activate the LTC4101 SMBALERT pull down POWER FAIL bit is set if the LTC4101 does not have sufficient DCIN voltage to charge the battery or if an external device is pulling the CHGEN input signal low Charging is disabled whenever this bit is set The setting ofthis bit does not clear the values in the ChargingVoltage and ChargingCurrent function values nor does it neces sarily affect the charging modes of the LTC4101 BATTERY PRESENTis setifa battery is present otherwise it is cleared The LTC4101 uses the SafetySignal in order to determine battery presence If the LTC4101 detects a RES OR condition the BATTERY PRESENT bit is cleared immediately The LTC4101 will not set the BATTERY PRESENT bit until it successfully samples the SafetySignal twice and does not detect a RES OR condi tion on either sampling If AC is not present e g DCDIV Vacp this bit may not be set for up to one half second after the battery is connected to the SafetySignal The ChargingCurrent and ChargingVoltage function values are immediately cleared whenever this bit is cleared Charging will never be allowed if this bit is cleared A change in BATTERY PRESENT will activate the LTC4101 SMBALERT pull down AC_PRESENT is set ifthe voltage on DCDIV is greater than Vacp This does not necessarily indica
28. e lt ea lt ce gt gt a Return Read Values 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 00 1 0 1 0 ChargingCurrent 7 b0001 001 8 h14 Value CHARGING CURRENT 15 0 Permitted Write Values Unsigned integer representing current in mA ChargingVoltage 7 b0001_001 8 h15 Value CHARGING_VOLTAGE 15 0 Permitted i i Write Values Unsigned integer representing voltage in mV AlarmWarning 7 b0001_001 8 h16 Control E 3 5 lt e lt E 2 lt amp 2 8 s ag amp e e SEIS 2 lt gt gt lt gt 3l zl 235 2 io Permitted Write Values 1 0 1 0 1 0 1 0 Ignored LTCO 7 b0001 001 8 h3C Register Reserved LTC4101 s Version Identification Permitted Write Values Ignored 1 0 Ignored Return Read Values 0 1 0 10 0 0 0 0 0 1 0 0 UO Alert Response 7 b0001 100 N A Status LTC4101 s Address Address Not Supported E Read Return Byte Values 1 4101f 13 LTC4101 OPERATION The RES_UR bit is set only when the SafetySignal resis tance value is less than 575Q ALARM_INHIBITED bit is set if a valid AlarmWarning message has been received and charging is inhibited as a result This bit is cleared if both ChargingVoltage an
29. e you never exceed the Pp rating of the device The Schottky diode D1 shown in the Typical Application onthe back page conducts during the dead time between the conduction of the two power MOSFETs This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead time which could cost as much as 1 in efficiency A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current Larger diodes can result in additional transition losses due to their larger junction capacitance The diode may be omitted if the efficiency loss can be tolerated Calculating IC Power Dissipation The power dissipation of the LTC4101 is dependent upon the gate charge of the top and bottom MOSFETs Q2 amp Q3 respectively The gate charge QG is determined from the manufacturer s data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the MOSFET Use 6V for the gate voltage swing and for the drain voltage swing Vocin fosc Ipen Ipp Example 12V fosc 345kHz 25nC 15nC Ipciy SMA Vpp 5 5V lpp 1mA 231mW Soft Start and Undervoltage Lockout The LTC4101 is soft started by the 0 12uF capacitor on the pin On start up pin voltage will rise quickly to 0 5V then ramp up at a rate set by the internal 30pA pull up current and the externa
30. fthe devices connected to the SMBus inputs Therefore it is good design practice to protect the SMBus inputs as shown in Figure 10 TO SYSTEM 4101 F13 Figure 10 Recommended SMBus Transient Protection 4101f 25 LTC4101 APPLICATIONS INFORMATION PCB Layout Considerations For maximum efficiency the switch node rise and fall times should be minimized To prevent magnetic and electrical field radiation and high frequency resonant prob lems proper layout of the components connected to the IC is essential See Figure 11 Here is a PCB layout priority list for proper layout Layout the PCB using this specific order 1 Inputcapacitors need to be placed as close as possible to switching FET s supply and ground connections Shortest copper trace connections possible These parts must be on the same layer of copper Vias must not be used to make this connection 2 Thecontrol IC needs to be close to the switching FET s gate terminals Keep the gate drive signals short for a clean FET drive This includes IC supply pins that con nect to the switching FET source pins The IC can be placed onthe opposite side of the PCB relative to above 3 Place inductor input as close as possible to switching FET s output connection Minimize the surface area of this trace Make the trace width the minimum amount needed to support current no copper fills or pours Avoid running the connection using multiple layers in parallel Min
31. gerStatus function 6 INHIBIT CHARGE is set in the ChargerMode function Clearing INHIBIT CHARGE will cause the LTC4101 to resume charging using the previous ChargingVoltage AND ChargingCurrent function values RESET TO ZERO is set in the ChargerMode function 8 CHGEN pin is pulled low by an external device The LTC4101 will resume charging using the previous ChargingVoltage AND ChargingCurrent function val ues ifthe CHGEN pin is released by the external device 9 Insufficient DCIN voltage to charge the battery The LTC4101 will resume charging using the previous ChargingVoltage AND ChargingCurrent function val ues when there is sufficient DCIN voltage to charge the battery 10 Writing a zero value to ChargingVoltage function 11 Writing a zero value to ChargingCurrent function The SafetySignal Decoder Block This block measures the resistance of the SafetySignal and features high noise immunity at critical trip points The low power standby mode supports only battery presence SMB charger reporting requirements when AC is not present The SafetySignal decoder is shown in Figure 4 The value of is 1 13k and is 54 9k SafetySignal sensing is accomplished by a state machine that reconfiguresthe switches of Figure 4 using THA_SELB and THB_SELB a selectable reference generator and two comparators This circuit has two modes of operation based upon whether AC is present
32. ic limits for improved system safety and reliability Available in a 24 Pin SSOP Package Limits are programmable by two external resistors Addi tionally the maximum average current from the AC adapter APPLICATIONS is programmable to avoid overloading the adapter when Portable Instruments and Computers simultaneously supplying load current and charging current When supplying system load current charging a Data Storage Systems and Battery Backup Servers current is automatically reduced to prevent adapter LT LTC LTM are registered trademarks of Linear Technology Corporation All overload other trademarks are the property of their respective owners Protected by U S Patents i including 6650174 5723970 TYPICAL APPLICATION DCIN 9V to 12V 2A 0 1uF Vear PART 55V LTC4101 gt 5 5v LTC4100 0 050 CHGEN ACP SYSTEM LOAD 5uF SMART BATTERY R 1H SMBALERT SafetySignal Figure 1 1A Smart Battery Charger LTC4101 ABSOLUTE MAXIMUM RATINGS Note 1 Voltage from Vpp to 7V 0 3V Voltage from CHGEN DCDIV SDA SCL SMBALERT to GND 7V 0 3V Voltage from DCIN CLP to GND 32V 0 3V Voltage from GLP to 0 3V POND Writ GND 0 3V CSP 28V 5V Operating Ambient Temperature Range Note 4 40 to 85
33. imize capacitance from this node to any other trace or plane L1 VBAT HIGH FREQUENCY Vn C2 CIRCULATING D1 SWITCH TS TT 101815 Figure 11 High Speed Switching Path 4 Place the output current sense resistor right next to the inductor output but oriented such that the IC s current sense feedbacktraces going to resistor are not long The feedback traces need to be routed together asasingle pair on the same layeratany given time with smallest trace spacing possible Locate any filter component on these traces nextto the and not atthe sense resistor location 5 Place output capacitors next to the sense resistor output and ground 6 Output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground Interfacing with a Selector The LTC4101 is designed to be used with a true analog multiplexer for the SafetySignal sensing path Some se lector ICs from various manufacturers may not implement this Consult LTC applications department for more information Electronic Loads The LTC4101 is designed to work with a real battery Electronic loads will create instability within the LTC4101 preventing accurate programming currents and voltages Consult LTC applications department for more information DIRECTION OF CHARGING CURRENT TO CSP AND BAT Figure 12 Kelvin Sensing of Charging Current 20 LTC41
34. ion can be prevented by utilizing the DCDIV resistor divider set higher than the minimum adapter voltage where full power can be achieved 24 LTC4101 APPLICATIONS INFORMATION Input and Output Capacitors In the 4A Lithium Battery Charger Typical Application on back page the input capacitor C2 is assumed to absorb all input switching ripple current in the converter so it must have adequate ripple current rating Worst case RMS ripple current will be equal to one half of output charging current Actual capacitance value is not critical Solid tantalum low ESR capacitors have high ripple cur rent rating relatively small surface mount package but caution must be used when tantalum capacitors are used for input or output bypass High input surge currents can be created when the adapter is hot plugged to the charger or when a battery is connected to the charger Solid tantalum capacitors have a known failure mechanism when subjected to very high turn on surge currents Only Kemet T495 series of Surge Robust low ESR tantalums are rated for high surge conditions such as battery to ground The relatively high ESR of an aluminum electrolytic for C1 located at the AC adapter input terminal is helpful in reducing ringing during the hot plug event Refer to AN88 for more information The highest possible voltage rating on the capacitor will minimize problems Consult with the manufacturer before use Alternatives incl
35. is registering RES HOT 5 The AC power is no longer present DCDIV Vacp 6 The ALARM INHIBITED becomes set in the ChargerStatus function The CHARGE is set in the ChargerMode function D 8 The CHGEN pin is pulled low by an external device The LTC4101 will resume wake up charging if the CHGEN pin is released by the external device Toggling the CHGEN pin will not reset the timer 9 There is insufficient DCIN voltage to charge the battery The LTC4101 will resume wake up charging when there is sufficient DCIN voltage to charge the battery This condition will not reset the timer 16 LTC4101 OPERATION Controlled Charging Algorithm Overview The following conditions must be met in order to allow controlled charging to start on the LTC4101 1 The ChargingVoltage AND ChargingCurrent func tion must be written to non zero values 2 The SafetySignal must be RES_COLD RES_IDEAL or RES_UR 3 AC must be present This is qualified by DCDIV gt Vacp Thefollowing conditions will stop the Controlled Charging Algorithm and will cause the Battery Charger Controller to stop charging 1 The ChargingCurrent AND ChargingVoltage func tions have not been written for TTIMEOUT 2 The SafetySignal is registering RES OR 3 The SafetySignal is registering RES HOT 4 The AC power is no longer present DCDIV Vacp 5 ALARM INHIBITED is set in the Char
36. l capacitor Battery charging current starts ramping up when voltage reaches 0 8V and full current is achieved with Ir at 2V With a 0 12uF capacitor time to reach full charge current is about 2ms and it is assumed that input voltage to the charger will reach full value in less than 2ms The capacitor can be increased up to 1uF if longer input start up times needed In any switching regulator conventional timer based soft starting can be defeated if the input voltage rises much slower than the time out period This happens because the switching regulators in the battery charger and the computer power supply are typically supplying a fixed amount of power to the load If input voltage comes up slowly compared to the soft start time the regulators will try to deliver full power to the load when the input voltage is still well below its final value If the adapter is current limited it cannot deliver full power at reduced output voltages and the possibility exists for a quasi latch state where the adapter output stays in a current limited state at reduced output voltage For instance if maximum charger plus computer load power is 30W a 15V adapter might be current limited at 2 5A If adapter voltage is less than 30W 2 5A 12V when full power is drawn the adapter voltage will be pulled down by the constant 30W load until it reaches a lower stable state where the switching regulators can no longer supply full load This situat
37. lows the LTC4101 to meet the follow ing Smart Battery controlled Level 2 charger requirements Implements the Smart Battery s critical warning mes sages over the SMBus Operates as an SMBus slave device that responds to ChargingVoltage and ChargingCurrent commands and adjusts the charger output parameters accordingly The host may control charging by disabling the Smart Battery s ability to transmit ChargingCurrent and ChargingVoltage request functions and broadcasting the charging commands tothe LTC4101 overthe SMBus The LTC4101 will still respond to Smart Battery critical warning messages without host intervention PO oo A Wake up Charging Mode The following conditions must be met in order to allow wake up charging of the battery 1 The SafetySignal must be RES_COLD RES_IDEAL or RES_UR 2 AC must be present This is qualified by DCDIV gt Vacp Wake up charging initiates when a newly inserted battery does not send ChargingCurrent and ChargingVoltage functions to the LTC4101 Thefollowing conditions willterminate the Wake up Charg ing Mode 1 A TriMEoUT period is reached when the SafetySignal is RES COLD or RES UR The SafetySignal is registering RES OR Co The successful writing of the ChargingCurrent AND ChargingVoltage function The LTC4101 will proceed to the controlled charging mode after these two func tions are written 4 The SafetySignal
38. mA lt 0 59 lt 4432mV or Short to Vpp 100k 1 0 66Vypp lt 2900mV lt Vout 16mV lt 0 84 4512mV Open or 0 91Vypp lt VyLIM 2900mV lt Vout 16mV Tied to Vpp 5504mV VDD bi lt 1 AC PRESENT HE a 3 0 4101 F05 Figure 5 Simplified Vj jy Circuit Concept lj jy is Similar 4101f 19 LTC4101 OPERATION The Voltage DAC Block Note that the charger output voltage is offset by Vpgr Therefore the value of Vagr is subtracted from the SMBus ChargingVoltage value in order for the output voltage to be programmed properly without offset If the ChargingVoltage value is below the nominal reference voltage of the charger nominally 1 104V the charger output voltage is programmed to zero In addition if the ChargingVoltage value is above the limit set by the pin then the charger output voltage is set to the value determined by the Vj jy resistor and the VOLTAGE OR bit is set These limits are demonstrated in Figure 6 T Ryim 33k gt CHARGER Vgar V N 0 1 2 3 4 5 6 PROGRAMMED VALUE V 4101 F06 NOTE THE LTC4101 CAN BE PROGRAMMED WITH ChargingVoltage FUNCTION VALUES BETWEEN 1 104V AND 2 9V HOWEVER THE BATTERY CHARGER CONTROLLER OUTPUT VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2 9V Figure 6 Transfer Function of Charger The Current DAC Block
39. mum Rating condition for extended periods may affect device Note 5 Current accuracy dependent upon circuit compensation and sense reliabilty and lifetime resistor Note 2 See Test Circuit Note 6 is defined as the sum of capacitance on THA THB and Note 3 Does not include tolerance of current sense resistor SafetySignal Note 4 The LTC4101E is guaranteed to meet performance specifications Note 7 The corresponding overrange bit will be set when a HEX value from 0 C to 85 C Specifications over the 40 to 85 C operating greater than or equal to this value is used 4101f LTC4101 TYPICAL PERFORMANCE CHARACTERISTICS 25 uniess otherwise noted INFET Response Time to Reverse Current Vgs OF PFET 2V DIV Vs OV 1 REVERSE OF PFET 5A DIV lq 0A BS 1 25us DIV FORMED ON DEMOBOARD Vin 15Vp VCHARG CHARGER ON CHARGE 10mA TEST PER p 42V NFET 1 2 Si4925DY 4101 G01 Disconnect Reconnect Battery Load Dump OUTPUT VOLTAGE ERROR VELOAT 1V DIV LOAD STATE N LOAD CURRENT 1A 2A DCI DISCONNECT 12V VeLoaT 4 2V 4101 604 BATTERY LEAKAGE CURRENT uA Output Voltage vs Output Current gt 2 2 ej
40. n THA THB and SafetySignal is 1nF see Figure 4 A series resistor 1130Q needs to be connected between this pin and the battery s SafetySignal for this circuit to work correctly Pin 17 Power Supply Input for the LTC 4101 Digital Circuitry Bypass this pin with 0 1uF Typically between 3 3V and 5Vpc Pin 18 Tap Point of the Programmable Resistor Divider which Provides Battery Voltage Feedback to the Charger Pin 19 Control Signal of the Inner Loop of the Current Mode PWM Higher corresponds to higher charging current in normal operation A 0 0015uF capaci torto GND filters out PWM ripple Typical full scale output current is 40 Nominal voltage range for this pin is OV to 3V Ipc Pin 20 Bypass to GND with a 0 068uF Capacitor CSP Pin 21 Current Amplifier CA1 Input This pin and the BAT pin measure the voltage across the sense resistor to provide the instantaneous current signals re quired for both peak and average current mode operation BAT Pin 22 Battery Sense Input and the Negative Reference for the Current Sense Resistor A bypass ca pacitor of at least 10uF is required CLN Pin 23 Negative Inputto the Input Current Limiting Circuit Block If no current limit function is desired con nect this pin to CLP The threshold is set at 100mV below the voltage at the CLP pin When used to limit supply current a filter is needed to filter out the switching noise CLP
41. n the SafetySignal resistance value is greater than 28 5kQ The SafetySignal indicates a cold battery The RES_COLD bit will be set whenever the RES_OR bit is set The RES_HOT bit is set only when the SafetySignal resistance is less than 3150Q which indicates a hot battery The RES_HOT bit will be set whenever the RES_UR bit is set 4101f 12 LTC4101 OPERATION Table 1 Summary of Supported Charger Functions SMBus Command Data Function Access Address Code Type D15 D14 D13 D12 D11 D10 09 D8 D7 D6 05 D4 D3 D2 D1 DO Lr ChargerSpecinfo 7 b0001 001 8 h11 Info 5 a Reserved CHARGER_SPEC 2 Ej wn Return Read Values 0 Qiu ChargerMode 7 b0001 001 8 112 Control g a Reserved Ro a p te Permitted Write Values Ignored 1 0 1 0 Ign t O ChargerStatus 7 b0001 001 8 h13 Status a m 2 s 5 2 alg a e i uz gt E m 5 i T 5 256 5 1 lhe f lt lt gt c lt e e
42. operating features 1 The SafetySignal is sampled every 250ms or less instead of 32ms 2 A full SafetySignal status is sampled every 30s or less instead of every 32ms The SafetySignal impedance is interpreted according to Table 4 Table 4 SafetySignal State Ranges SafetySignal CHARGE RESISTANCE STATUS BITS DESCRIPTION 0Q to 5000 RES_UR Underrange RES_HOT BATTERY_PRESENT 500Q to 3kQ RES_HOT Hot BATTERY_PRESENT to 30kQ BATTERY_PRESENT Ideal 30kQ to 100kQ RES_COLD Cold BATTERY_PRESENT Above 100kQ RES_OR Overrange RES_COLD Note The underrange detection scheme is a very important feature of the LTC4101 The Rtya Rsatetysignal divider trip point of 0 333 Vpp 1V is well above the 0 047 140mV threshold of a system using a 10k pull up A system using a 10k pull up would not be able to resolve the important underrange to hot transition point with a modest 100mV of ground offset between battery and SafetySignal detection circuitry Such offsets are anticipated when charging at normal current levels The required values for and are shown Table 5 Table 5 SafetySignal External Resistor Values EXTERNAL RESISTOR VALUE Q 1130 1 54 9k 1 Css represents the capacitance between the SafetySignal and GND Css may be added to provide additional noise immunity from transients in the application Css cannot exceed 1nF
43. p MOSFET is turned off until the overvoltage condition is cleared This feature is useful for batteries that load dump themselves by opening their protection switch to perform functions such as calibration or pulse mode charging PWM Watchdog Timer There is a watchdog timer that observes the activity on the TGATE pin If TGATE stops switching for more than 40 5 the watchdog activates and turns off the top MOSFET for about 400ns The watchdog engages to prevent very low frequency operation in dropout a potential source of audible noise when using ceramic input and output capacitors Charger Start Up When the charger is enabled it will not begin switching until the lr voltage exceeds a threshold that assures initial current will be positive This threshold is 5 to 1596 ofthe maximum programmed current After the charger begins switching the various loops will control the current at a level that is higher or lower than the initial current The duration of this transient condition depends upon the loop compensation but is typically less than 1ms SMBus Interface All communications overthe SMBus are interpreted by the SMBus interface block The SMBus interface is a SMBus slave device All internal LTC4101 registers may be up dated and accessed through the SMBus interface and charger controller as required The SMBus protocol is a derivative of the IC bus Reference 2 and How to Use It V1 0 by Philips and S
44. pendent of the setting Input FET The input FET circuit performs two functions It enables the charger if the input voltage is higher than the CLP pin and provides an indication of this condition at both the CHGEN pin and the PWR FAIL bit in the ChargerStatus register It also controls the gate of the input FET to keep a low forward voltage drop when charging and prevents reverse current flow through the input FET If the input voltage is less than Vc p it must go at least 130mV higher than Vc p to activate the charger The CHGEN pin is forced low unless this condition is met The gate of the input FET is driven to a voltage sufficient to keep a low forward voltage drop from drain to source If the voltage between DCIN and CLP drops to less than 25mV 4101f 20 LTC4101 OPERATION the input FET is turned off slowly If the voltage between DCIN and CLP is ever less than 25mV then the input FET is turned off quickly to prevent significant reverse current from flowing inthe input FET In this condition the CHGEN pin is driven low and the charger is disabled The AC Present Block PRESENT The DCDIV pin is used to determine AC presence If the DCDIV voltage is above the DCDIV comparator threshold Vacp then the ACP output pin will be switched to Vpp and the AC PRESENT bit in the ChargerStatus function will be set If the DCDIV voltage is below the DCDIV compara tor threshold minus the DCDIV comparato
45. r mine the resistor value Re 100mV li iw Adapter Min Current Adapter Min Current 7 As is often the case the wall adapter will usually have at leasta 10 current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating see Figure 9 AVERAGE CHARGER CURRENT 0 lt 40ms 4101 F08 Figure 8 Charging Current Waveform in Low Current Mode LTC4101 ADAPTER CURRENT LIMIT 4101 F09 Figure 9 Adapter Current Limiting 4101f 21 LTC4101 APPLICATIONS INFORMATION Charge Termination Issues Batteries with constant current charging and voltage based charger termination might experience problems with reductions of charger current caused by adapter limiting It is recommended that input limiting feature be defeated in such cases Consult the battery manufacturer for information on how your battery terminates charging Setting Output Current Limit Refer to Figure 1 The LTC4101 current DAC and the PWM analog circuitry must coordinate the setting of the charger current Failure to do so will result in incorrect charge currents Table 9 Recommended Resistor Values Warning DO NOT CHANGE THE VALUE OF Rj jy DURING OPERA TION The value must remain fixed and track the value at all times Changing the current setting can result in currents that greatly exceed the requested v
46. r hysteresis then the ACP output pin is switched to GND and the PRESENT bitin the ChargerStatus function is cleared The ACP output pinis designed to drive 2mA continuously Adapter Limiting An important feature of the LTC4101 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter This allows the prod uct to operate at the same time that batteries are being charged without complex load management algorithms Additionally batteries will automatically be charged at the maximum possible rate of which the adapter is capable This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded True analog control is used with closed loop feedback ensuring that adapter load current remains within limits Amplifier CL1 in Figure 9 senses the voltage across connected betweenthe CLP and CLN pins When this voltage exceeds 100mV the amplifier will override programmed charging current to limit adapter current to 100mV Rg A lowpass filter formed by 4 99k and 0 1uF is required to eliminate switching noise Ifthe current limit is not used CLP should be connected to CLP but leave CLN connected to power Setting Input Current Limit To set the input current limit you need to know the minimum wall adapter current rating Subtract 796 for the input current limit tolerance and use that current to dete
47. s information SMBus Protocol Read Word Output The CHARGER_SPEC indicates that the LTC4101 supports Version 1 1 of the Smart Battery Charger Speci fication The SELECTOR_SUPPORT indicates that the LTC4101 does not support the optional Smart Battery Selector Commands ChargerMode h12 Description The SMBus Host uses this command to set the various charger modes The default values are set to allow a Smart Battery and the LTC4101 to work in concert without requiring an SMBus Host Purpose Allows the SMBus Host to configure the charger and change the default modes This is a write only func tion but the value of the mode bit INHIBIT_CHARGE may be determined using the ChargerStatus function e SMBus Protocol Write Word Input The INHIBIT CHARGE bit allows charging to be inhibited without changing the ChargingCurrent and ChargingVoltage values The charging may be resumed by clearing this bit This bit is automatically cleared when power is reapplied or when a battery is reinserted The ENABLE POLLING bitis notsupported by the LTC4101 Values written to this bit are ignored The POR RESET bit sets the LTC4101 to its power on default condition The RESET TO ZERO bit sets the ChargingCurrent and ChargingVoltage values to zero This function ALWAYS clears the ChargingVoltage and ChargingCurrent val ues to zero even if the INHIBIT CHARGE bit is set ChargerStatus h
48. te that the voltage on DCIN is sufficient to charge the battery A change in AC PRESENT will activate the LTC4101 SMBALERT pull down ChargingCurrent h14 Description The Battery System Host or other master de vice sends the desired charging current mA tothe LTC4101 Purpose The LTC4101 uses the granularity of the IpAc and the value of the ChargingCurrent function to determine its charging current supplied to the battery The charging current will never exceed the maximum current permitted by The ChargingCurrent value will be truncated to the granularity of the The charging current will also be reduced if the battery voltage exceeds the programmed charging voltage e SMBus Protocol Write Word Input The CHARGING CURRENT is an unsigned 16 bit integer specifying the requested charging current in mA The following table defines the maximum permissible value of CHARGING CURRENT that will not set the CURRENT ORin the ChargerStatus function for a given value of the Ry iy ChargingCurrent Current Short to GND 0x0000 through OmA through 1023mA 10kQ 1 0x0000 through Ox07FF OmA through 2047mA 33kQ 1 0x0000 through OxOBFF OmA through 3071mA Open or short to Vpp 0x0000 through OxOFFF OmA through 4095mA ChargingVoltage h15 Description The Battery SMBus Host or other master device sends the desired charging volt
49. ude new high capacity ceramic at least 20uF from Tokin United Chemi Con Marcon et al Other alternative capacitors include OSCON capacitors from Sanyo CONNECTOR TO BATTERY VDD The output capacitor C3 is also assumed to absorb output switching current ripple The general formula for capacitor current is V 2906 1 8 DCIN Li f For example VDCIN 12V 4 2V L1 10uH and f 300kHz lays 0 26 EMI considerations usually make it desirable to minimize ripple current in the battery leads and beads or inductors may be added to increase battery impedance at the300kHz switching frequency Switching ripple current splits be tween the battery and the output capacitor depending on the ESR of the output capacitor and the battery imped ance If the ESR of C3 is 0 2Q and the battery impedance is raised to 40 with a bead or inductor only 5 of the current ripple will flow in the battery IRMS Protecting SMBus Inputs The SMBus inputs SCL and SDA are exposed to uncon trolled transient signals whenever a battery is connected to the system If the battery contains a static charge the SMBus inputs are subjected to transients which can cause damage after repeated exposure Also if the battery s positive terminal makes contact to the connector before the negative terminal the SMBus inputs can be forced below ground with the full battery potential causing a potential for latch up in any o
50. urrent is discontinued after trimeout if the SafetySignal is decoded as RES UR or RES COLD and the battery or host doesn t transmit charging commands The SMBus interface and control block receives ChargingCurrent and ChargingVoltage commands via the SMBus If ChargingCurrent and ChargingVoltage command pairs are received within a tr imeour interval the values are stored in the current and voltage DACs and the charger controller asserts the CHGEN line if the decoded SafetySignal value will allow charging to commence ChargingCurrent and ChargingVoltage values are com pared against limits programmed by the limit decoder block if the commands exceed the programmed limits these limits are substituted and overrange flags are set The charger controller will assert SMBALERT whenever a status change is detected namely PRESENT BATTERY PRESENT ALARM INHIBITED or Vpp power fail The host may query the charger viathe SMBus to obtain ChargerStatus information SMBALERT will be deasserted upon a successful read of ChargerStatus or a successful Alert Response Address ARA request Battery Charger Controller The LTC4101 charger controller uses a constant off time current mode step down architecture During normal operation the top MOSFET is turned on each cycle when the oscillator sets the SR latch and turned off when the main current comparator resets the SR latch While the top MOSFET is off the bottom M
51. uty cycle in this switch in nearly 100 The term 1 dAT is generally given fora MOSFET in the form of a normalized Rps on vs temperature curve but 0 005 can be used as an approximation for low voltage MOSFETs Cass Qgp AVps is usually specified in the MOSFET characteristics The constant 2 can be used to estimate the contribu tions of the two terms in the main switch dissipation equation If the charger is to operate in low dropout mode or with a high duty cycle less than 50 then the bottomside N Channel efficiency generally improves with a larger MOSFET Using asymmetrical MOSFETs may achieve cost savings or efficiency gains Both ofthe LTC4101 MOSFET drivers are optimized to take advantage of MOSFETs Qg values of less than 22nC and a TD off delay specification of around 60ns or less Larger FETs may work but you must qualify them and monitor LTC4101 temperature rise 4101f Une 23 LTC4101 APPLICATIONS INFORMATION Using excessively large MOSFETs relative to the Imax charge current they are working with will actually reduce efficiency at lighter current levels with very limited gain at high currents A good place to start looking for a suitable MOSFET in a datasheet is to look for a part with an Ip rating alittle over 2 times the Imax charge current rating For the LTC4101 the P channel FET can typically be scaled down a bit to take advantage of the lower duty cycle limits However make sur
52. ystem Management Bus Specification Version 1 1 from the SBS Implementers Forum for a complete description of the bus protocol requirements All data is clocked into the shift register on the rising edge of SCL All data is clocked out of the shift register on the falling edge of SCL Detection of an SMBus Stop condition or power on reset via the Vpp power fail will reset the SMBus interface to an initial state at any time The LTC4101 command set is interpreted by the SMBus interface and passed onto the charger controller block as control signals or updates to internal registers Description of Supported Battery Charger Functions The functions are described as follows see Table 1 also FunctionName hnn command code Description A brief description of the function Purpose The purpose of the function and an example where appropriate e SMBus Protocol Refer to Section 5 of the Smart Battery Charger specification for more details C is a trademark of Philips Electronics N V http www SBS FORUM org 4101f 11 LTC4101 OPERATION Input Output or Input Output A description of the data supplied to or returned by the function ChargerSpecinfo h11 Description The SMBus Host uses this command to read the LTC4101 s extended status bits Purpose Allows the System Host to determine the speci fication revision the charger supports as well as other extended statu

LINEAR TECHNOLOGY - LTC4101 handbook

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