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FAIRCHILD ISL9N308AD3 ISL9N308AD3ST handbook

1. 1 2 60 Gi 1 0 50 mr E z H lt 5 0 8 E 40 z z E 2 os S 30 E 8 a A E o 0 4 a E 20 i 3 0 2 9 10 9 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 Tc CASE TEMPERATURE C Tc CASE TEMPERATURE C Figure 1 Normalized Power Dissipation vs Figure 2 Maximum Continuous Drain Current vs Ambient Temperature Case Temperature 2 DUTY CYCLE DESCENDING ORDER 1105 r 0 2 L 0 1 ul F 0 05 Q2 oo NS 0 01 Y Za z om Q E 0 1 is P fr T a t ae E to SINGLE PULSE NOTES DUTY FACTOR D ti t PEAK T Pow X Zouc X Royo Tc 0 01 L L Lp oe A G A E 1 1 a oe oe O D A 105 104 10 10 10 10 10 t RECTANGULAR PULSE DURATION s Figure 3 Normalized Maximum Transient Thermal Impedance 1000 le T TTTTTIT a Tc 25 C he ay FOR TEMPERATURES Lee gt ay x ABOVE 25 C DERATE PEAK CURRENT AS FOLLOWS LE 4 z l los Le E Vas 10V 150 3 A Vos 5V Lu n 100 a E Y TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 40 105 104 10 10 10 10 10 t PULSE WIDTH s Figure 4 Peak Current Capability 2002 Fairchild Semiconductor Corporation ISL9N308AD3 ISL9N308AD3ST Rev C 1S QV80 N67ISI QV80 N6 IS
2. 2002 Fairchild Semiconductor Corporation ee FAIRCHILD June eode ee E SEMICONDUCTOR PWM Optimized ISL9N308AD3 ISL9N308ADS3ST N Channel Logic Level UltraFET Trench Power MOSFETs 30V 50A 8mo General Description Features This device employs a new advanced trench MOSFET Fast switching technology and features low gate charge while maintaining low on resistance rps on 0 00640 Typ Vas 10V Optimized for switching applications this device improves ps oN 0 0100 Typ Vas 4 5V the overall efficiency of DC DC converters and allows operation to higher switching frequencies Qy Typ 24nC Vas 5V Applications Qoa Typ 8nC DC DC converters Cigg Typ 2600pF I PAK D PAK P d TO 251AA TO 252 GDS MOSFET Maximum Ratings 1 25 C unless otherwise noted Symbol Parameter Ratings Voss Drain to Source Voltage 30 Gate to Source Voltage 320 Drain Current Continuous Tc 25 C Vas 10V Note 1 50 Continuous Tc 100 C Vas 4 5V Note 1 48 Continuous Tc 25 C Veg 10V Rejc 529C W 14 Pulsed Figure 4 Power dissipation 100 Derate above 25 C 0 67 Ty Tstg Operating and Storage Temperature 55 to 175 Thermal Characteristics Rouc Thermal Resistance Junction to Case TO 252 TO 251 Roua Thermal Resistance Junction to Ambient TO 252 TO 251 Rosa Thermal Resistance Junction to Ambient TO 252 1in copper pad area Package Marking
3. Test Circuits and Waveforms BVpss ip Vps las E pd VARY tp TO OBTAIN a Vpp REQUIRED PEAK las A wo i Ves 4 y gt tp 7 ov 0 IN CMM tav lt Figure 15 Unclamped Energy Test Circuit Figure 16 Unclamped Energy Waveforms 2002 Fairchild Semiconductor Corporation ISL9N308ADS3 ISL9N308ADSST Rev C 1S QV80 N67ISI QV80 N6 ISI Test Circuits and Waveforms continued RL DUT lg REF Figure 17 Gate Charge Test Circuit Figure 19 Switching Time Test Circuit Vpp Qgctor gt ton lt torr ta orF 50 PULSE WIDTH Figure 20 Switching Time Waveforms 2002 Fairchild Semiconductor Corporation ISLON308AD3 ISL9N308AD3ST Rev C LSEGV80EN61SI QV80 N6 ISI Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature Tj and the 125 Roya 33 32 23 84 0 268 Area thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation Ppy in an application Therefore the applications ambient 100 temperature TA C and thermal resistance Reja C W must be reviewed to ensure that Tyy is never exceeded Li Equation 1 mathematically represents the relationship and serves as the basis fo
4. and Ordering Information Device Marking Tape Width Quantity N308AD ISL9N308ADS3ST TO 252AA 330mm 16mm 2500 units N308AD ISL9N308AD3 TO 251AA Tube N A 75 units ISL9N308AD3 ISL9N308AD3ST Rev C LSEGV80EN61SI QV80 N6 ISI Electrical Characteristics 1 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics Bypss Drain to Source Breakdown Voltage Ip 250A Veg OV 30 E V Zero Gate Voltage Drain Current Vps 25V uA Ci 3 Vas 0V Tc 150 250 less Gate to Source Leakage Current Ves 320V 100 nA On Characteristics VGS TH Gate to Source Threshold Voltage Vas Vps lp 250A 1 x 3 Ip 50A Veg 10V E 0 0064 0 008 r Drain to Source On Resistance Q PREN Ip 48A Vag 4 5V 0 010 0 012 Dynamic Characteristics C Input Capacitance 2 2600 F cm an a Vps 15V Vas OV p oss utput Capacitance f 1MHz 520 pF Cnss Reverse Transfer Capacitance 5 225 pF QJ TOT Total Gate Charge at 10V Ves OV to 10V 45 68 nC Qg 5 Total Gate Charge at 5V Vas OV to 5V vpp 15V 24 37 nC Qg TH Threshold Gate Charge Vas 0Vto1V Ilp 2 48A 2 6 4 0 nC Qgs Gate to Source Gate Charge lg 1 0mA 7 nC Gate to Drain Miller Charge Switching Characteristics Vas 4 5V ton Turn On Time la ON Turn On Delay Time t
5. the Electrical Specifications table The points were chosen to depict the compromise between the copper board area the thermal resistance and ultimately the power dissipation Pom Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 RgjA is defined as the natural log of the area times a coefficient added to a constant The area in square inches is the top copper area including the gate and source pads 23 84 Ro 33 32 EQ 2 8JA 0 268 Area EQ Figure 21 Thermal Resistance vs Mounting 0 1 1 10 AREA TOP COPPER AREA in Pad Area 2002 Fairchild Semiconductor Corporation ISL9N308AD3 ISL9N308AD3ST Rev C LSEGV80EN61SI QV80 N6 ISI PSPICE Electrical Model SUBCKT ISL9N308AD3ST 2 13 rev Dec2000 CA 12 8 1 5e 9 CB 15 14 1 75e 9 CIN 6 82 35e 9 DPLCAP 5 LDRAIN wz a DBODY 7 5 DBODYMOD 10 DBREAK 5 11 DBREAKMOD RSECI RLDRAIN DPLCAP 10 5 DPLCAPMOD 51 DBREAK RSLC2 t EBREAK 11 717 1832 7 ESLC i EDS 148581 EGS 13 8 6 81 50 ESG610681 RDRAIN 2 DBODY EVTHRES 6 21 198 1 ESG eee EBREAK A EVTEMP 20 6 18 22 1 a 1 LGATE EVTEMP 2 IT 8 17 1 GATE RGATE lc DN MALO Eum 9 20 1 Oo LDRAIN 2 5 1e 9 RLGATE I MSTRO LGATE 1 9 4 58e 9 cii LSOURCE LSOURCE 3 7 1 47e 9 SOURCE ete MMED 16 6 8 8 MMEDMOD RSOURCE MSTRO 16 6 8 8 MSTROMOD T MWEAK 16 21 8 8 MWEAKMOD ai 3 RBREAK TA 17 18
6. 3 tc1 1e 3 tc2 1e 6 RVTHRES iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e 6 200 5 2002 Fairchild Semiconductor Corporation ISL9N308AD3 ISL9N308AD3ST Rev C 1S QV80 N61ISI QV80 N6 ISI REV 23 Sept 2000 ISL9N308AT CTHERM1 th 6 2 0e 4 CTHERM 6 5 3 0e 3 THERMS 5 4 3 4e 3 THERMA 4 3 4 0e 3 THERMS 3 2 1 0e 2 THERM6 2 tl 5 0e 2 THERM1 th 6 1 5e 3 THERM2 6 5 5 5e 3 THERMS 5 4 5 2e 2 THERMA 4 3 3 5e 1 THERMS 3 2 3 8e 1 RTHERM6 2 tl 4 1e 1 yI O000 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 2 0e 4 ctherm ctherm2 6 5 3 0e 3 ctherm ctherm3 5 4 3 4e 3 ctherm ctherm4 4 3 4 0e 3 ctherm ctherm5 3 2 1 0e 2 ctherm ctherm6 2 tl 5 0e 2 rtherm rtherm1 th 6 1 5e 3 rtherm rtherm2 6 5 5 5e 3 rtherm rtherm3 5 4 5 2e 2 rtherm rtherm4 4 3 3 5e 1 rtherm rtherm5 3 2 3 8e 1 rtherm rtherm6 2 tl 4 1e 1 SPICE Thermal Model SABER Thermal Model SABER thermal model ISL9N308AT RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERMS5 RTHERM6 JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERMS5 CTHERM6 2002 Fairchild Semiconductor Corporation ISLIN308AD3 ISL9N308AD3ST Rev C LSEGV80EN61SI QV80 N6 ISI TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all s
7. 3 VOFF 0 2 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 2 VOFF 0 3 ENDS For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 2002 Fairchild Semiconductor Corporation ISLON308AD3 ISL9N308AD3ST Rev C LSEGV80EN61SI QV80 N6 ISI SABER Electrical Model REV Dec 2000 template ISL9N308AD3ST n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod isl 1 9e 11 nl 1 075 rs 4 2e 3 trs1 9e 4 trs2 1e 6 xti 2 2 cjo 1 1e 9 tt 8e 11 m 0 49 dp model dbreakmod rs 0 17 trs1 1e 3 trs2 8 9e 6 dp model dplcapmod cjo 8 2e 10 isl 10e 30 nl 10 m 0 45 m model mmedmod type _n vto 1 9 kp 3 is 1e 30 tox 1 res rvtemp n18 n19 1 tc1 1 8e 3 tc2 1e 6 res rvthres n22 n8 1 tc1 2 7e 3 tc2 1e 5 spe ebreak n11 n7 n17 n18 32 7 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 Sw vcsp s a n6 n12 n13 n8 model s1amod Sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl m model mstrongmod type n vto 2 35 kp 90 i
8. I 100 T PULSE DURATION 80us DUTY CYCLE 0 5 MAX Vpp 15V 75 50 Ip DRAIN CURRENT A 25 Vas GATE TO SOURCE VOLTAGE V Figure 5 Transfer Characteristics 25 PULSE DURATION 80us DUTY CYCLE 0 5 MAX r lp 32A Tc 25 C 20 roson DRAIN TO SOURCE ON RESISTANCE mo 2 4 6 8 10 Vas GATE TO SOURCE VOLTAGE V Figure 7 Drain to Source On Resistance vs Gate Voltage and Drain Current 1 4 T T Ves Vos lp 2504A NORMALIZED GATE THRESHOLD VOLTAGE o 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C Figure 9 Normalized Gate Threshold Voltage vs Junction Temperature NORMALIZED DRAIN TO SOURCE Ip DRAIN CURRENT A NORMALIZED DRAIN TO SOURCE Typical Characteristic Continued Tc 25 C unless otherwise noted 100 75 50 25 Figure 6 Saturation Characteristics 2 0 1 5 ON RESISTANCE 1 0 Figure 8 Normalized Drain to Source On Resistance vs Junction Temperature 1 2 1 1 1 0 BREAKDOWN VOLTAGE 0 9 Fi Breakdown Voltage vs Junction Temperature PULSE DURATION 80us DUTY CYCLE 0 5 MAX To 25 C 0 5 1 0 1 5 2 0 Vps DRAIN TO SOURCE VOLTAGE V PULSE DURATION 80s DUTY CYCLE 0 5 MAX Vas 10V Ip 50A 80 40 0 40 80 120 160 200 T
9. RLSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2 5e 3 S1B QoS2B RVTEMP RGATE 9 203 4 CA 13 CB 19 RLDRAIN 2 5 10 7 NET m 4 RLGATE 1 9 45 8 VBAT RLSOURCE 37 14 7 ees EDS O RSLC1 551 RSLCMOD 1e 6 s 8 RSLC2 5 50 1e3 22 RSOURCE 8 7 RSOURCEMOD 2 55e 3 RVTHRES RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 200 5 MODEL DBODYMOD D IS 1 9e 11 N 1 075 RS 4 2e 3 TRS1 9e 4 TRS2 1e 6 XTI 22 CJO 1 1e 9 TT 8e 11 M 0 49 MODEL DBREAKMOD D RS 1 7e 1 TRS1 1e 3 TRS2 8 9e 6 MODEL DPLCAPMOD D CJO 8 2e 10 IS 1e 30 N 10 M 0 45 MODEL MMEDMOD NMOS VTO 1 9 KP 318 1e 30 N 10 TOX 2 1L 2 1 MODEL MSTROMOD NMOS VTO 2 35KP 90 IS 1e 30 N 10 TOX 1L MODEL MWEAKMOD NMOS VTO 1 6 KP 0 05 IS 1e 30 N 10 TOX 1 MODEL RBREAKMOD RES TC1 1e 3 TC2 7e 7 MODEL RDRAINMOD RES TC1 7e 3 TC2 1e 5 MODEL RSLCMOD RES TC1 1e 3 TC2 1e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1e 6 MODEL RVTHRESMOD RES TC1 2 7e 3 TC2 1e 5 MODEL RVTEMPMOD RES TC1 1 8e 3 TC2 1e 6 W 1u RG 34 RS 0 1 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 4 0 VOFF 0 8 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 8 VOFF 4 0 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0
10. Rise Time lacoFr Turn Off Delay Time tf Fall Time torr Turn Off Time Switching Characteristics Vos 10V ton Turn On Time ta ON Turn On Delay Time tr Rise Time ta OFF Turn Off Delay Time lr Fall Time torr Turn Off Time Unclamped Inductive Switching Avalanche Time Drain Source Diode Characteristics Vpp 15V Ip 14A Vag 4 5V Reg 6 2 Vpp 15V Ip 14A Vag 10V Rag 6 22 Ip 3 2A L 3 0mH 122 ns 15 ns 67 ns E 35 ns 32 ns 100 ns 71 ns 8 ns 40 ns 64 ns 31 ns 142 ns Vsp Source to Drain Diode Voltage lsp 48A 1 23 x Isp 20A S 1 0 V trr Reverse Recovery Time Isp 48A digp dt 100A us 26 ns QRR Reverse Recovered Charge Isp 48A digp dt 100A us 14 nC Notes 1 TO 251AA coni inuous current limited by package to 35A 2002 Fairchild Semiconductor Corporation ISL9N308AD3 ISL9N308AD3ST Rev C LSEGV80EN61SI QV80 N6 ISI Typical Characteristic To 25 C unless otherwise noted
11. ected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary No Identification Needed Obsolete Formative or In Design First Production Full Production Not In Production 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness This datasheet contains the design specifications for product development Specifications may change in any manner without notice This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev H7
12. r establishing the rating of the part 75 a Po EIL EQ 1 0JA 50 In using surface mount devices such as the TO 252 package the environment in which it is applied will have a 25 significant influence on the part s current and maximum 0 01 power dissipation ratings Precise determination of Ppp is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board 2 The number of copper layers and the thickness of the board The use of external heat sinks The use of thermal vias Air flow and board orientation o a A CO For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in Fairchild provides thermal information to assist the designers preliminary application evaluation Figure 21 defines the Rgj4 for the device as a function of the top copper component side area This is for a horizontally positioned FR 4 board with 10z copper after 1000 seconds of steady state power with no air flow This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve Displayed on the curve are RgjA values listed in
13. s 1e 30 tox 1 m model mweakmod type _n vto 1 6 kp 0 05 is 16 30 tox 1 rs 0 1 sw_vcsp model s1amod ron 1e 5 roff 0 1 von 4 0 voff 0 8 sw_vcsp model s bmod ron 1e 5 roff 0 1 von 0 8 voff 4 0 sw_vcsp model s2amod ron 1e 5 roff 0 1 von 0 3 voff 0 2 LDRAIN Sw vcsp model s2bmod ron 1e 5 roff 0 1 von 0 2 voff 0 3 DPLCAP 5 DRAIN zu 02 c ca n12 n8 1 5e 9 RLDRAIN c cb n15 n14 1 75e 9 e c cin n6 n8 2 35e 9 RSLC2 ISCL dp dbody n7 n5 model dbodymod dp dbreak n5 n11 model dbreakmod 50 DBREAK dp dplcap n10 n5 model dplcapmod p apicap p cap esa RDRAIN n n EVTHRES it n8 n17 1 DolAN a l LGATE EVTEMP Ca ECMWEAK l ldrain n2 n5 1e 9 GATE RGATE 4 78 6 EBREAK ligate n1 n9 4 58e 9 rs wie 9 20 8 ES qMMED lsource n3 n7 1 47e 9 RLGATE Le qMSTRG CIN LSOURCE SoURGE m mmed n16 n6 n8 n8 model mmedmod I 1u w 1u 8 7 SN o3 m mstrong n16 n6 n8 n8 model mstrongmod l 1u w 1u RSOURCE m mweak n16 n21 n8 n8 model mweakmod I 1u w 1u RLSOURCE 12514 S2A i HBRERK res rbreak n17 n18 1 tcl 1e 3 tc2 7e 7 8 H 17 18 res rdrain n50 n16 2 5e 3 tc1 7e 3 tc2 1e 5 res rgate n9 n20 3 4 S1B S2B RVTEMP res rldrain n2 n5 10 CA 18 cB rA 19 res rlgate n1 n9 45 8 t 14 VBAT res rlsource n3 n7 14 7 EGS EDS T res rsic1 n5 n51 1e 6 tc1 1e 3 tc2 1e 6 S 7 res rsic2 n5 n50 1e3 22 res rsource n8 n7 2 55e
14. uch trademarks ACEx Bottomless CoolFET CROSSVOLT DOME EcoSPARK E CMOS EnSigna FACT FACT Quiet Series FAST FASTr DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN FRFET GlobalOptoisolator GTO HiSeC ICM ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC OPTOPLANAR PACMAN SuperSOT 3 POP SuperSOT 6 Power247 SuperSOT 8 PowerTrench SyncFET QFET TinyLogic Qs TruTranslation QT Optoelectronics UHC Quiet Series UltraFET SILENT SWITCHER VCX SMART START SPM Stealth NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably exp
15. y JUNCTION TEMPERATURE C Ip 2504A 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C gure 10 Normalized Drain to Source 2002 Fairchild Semiconductor Corporation ISLON308AD3 ISL9N308AD3ST Rev C 1S QV80 N67ISI QV80 N6 ISI Typical Characteristic Continued Tc 25 C unless otherwise noted C 4000 10 Ciss Cas Cap 5 o T 5 Coss Cps Cap a w 1000 2 o w 6 z o lt a tc LE 2 5 Crss Cop o o lt one o Ww o E S WAVEFORMS IN a 2 DESCENDING ORDER DS lp 48A Vas OV f 1MHz Ip 14A 100 L L L oe D 0 L 0 1 1 10 30 0 10 20 30 40 50 Vps DRAIN TO SOURCE VOLTAGE V Qg GATE CHARGE nC Figure 11 Capacitance vs Drain to Source Figure 12 Gate Charge Waveforms for Constant Voltage Gate Currents 250 T T 350 Vas 4 5V Vpp 15V Ip 14A Vas 10V Vpp 15V Ip 14A 300 200 g 250 ur ul latorF 150 E ta oFF p 200 o o tr 150 x e 100 e t B ta on 100 50 tr 50 LL ee ee TO 0 0 d ON 0 10 20 30 40 50 0 10 20 30 40 50 Ras GATE TO SOURCE RESISTANCE Res GATE TO SOURCE RESISTANCE Figure 13 Switching Time vs Gate Resistance Figure 14 Switching Time vs Gate Resistance

FAIRCHILD ISL9N308AD3 ISL9N308AD3ST handbook

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