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TEXAS TAS5713 ti.com SLOS637 DECEMBER 2009 25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

1. 1 Default values are in bold SOFT MUTE REGISTER 0x06 Writing a 1 to any of the following bits sets the output of the respective channel to 50 duty cycle soft mute Table 11 Soft Mute Register 0x06 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 0 0 0 0 Reserved 1 Soft mute channel 3 0 Soft unmute channel 3 Soft mute channel 2 0 Soft unmute channel 2 1 Soft mute channel 1 0 Soft unmute channel 1 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 47 Product Folder Link s TAS5713 TAS5713 I TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com VOLUME REGISTERS 0x07 0x08 0x09 0x0A Step size is 0 5 dB Master volume 0x07 default is mute Channel 1 volume 0x08 default is 0 dB Channel 2 volume 0x09 default is 0 dB Headphone volume 0x0A default is 0 dB Table 12 Master Volume Table HEX dB HEX dB HEX dB HEX dB HEX dB HEX dB 00 24 30 0 60 24 90 48 CO 72 FO 96 01 23 5 31 0 5 61 24 5 91 48 5 C1 72 5 F1 96 5 02 23 32 1 62 25 92 49 C2 73 F2 97 03 22 5 33 1 5 63 25 5 93 49 5 C3 73 5 F3 97 5 04 22 34 2 64
2. PVDD_D PVDD_D BST_D GVDD_OUT VREG AGND GND DVSS DVDD STEST TAS5713 RESET A o en Oo MCLK ET OSC RES II DVSSO LI SCLK ET SDIN L T 1 VR DIG TI LRCLK CC P0075 09 PIN FUNCTIONS l TEXAS INSTRUMENTS www ti com liek TYPE SV TERMINATION DESCRIPTION NAME NO TOLERANT AGND 30 P Local analog ground for power stage A_SEL_FAULT 14 DIO This pin is monitored on the rising edge of RESET A value of 0 15 kQ pulldown sets the DC device address to 0x34 and a value of 1 15 kO pullup sets it to 0x36 this dual function pin can be programmed to output internal power stage errors AVDD 13 P 3 3 V analog power supply AVSS 9 P Analog 3 3 V supply ground BST_A 4 P High side bootstrap supply for half bridge A BST_B 43 P High side bootstrap supply for half bridge B BST_C 42 P High side bootstrap supply for half bridge C BST_D 33 P High side bootstrap supply for half bridge D DVDD 27 P 3 3 V digital power supply 1 TYPE A analog D 3 3 V digital P power ground decoupling input O output 2 All pullups are weak pullups and all pulldowns are weak pulldowns The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected pullups logic 1 input pulldowns logic 0 input 6 Submit Documentation Feedback Copyright
3. This DAP output mux selects which internal PWM channel is output to the external pins Any channel can be output to any external output pin Bits D21 D20 Selects which PWM channel is output to OUT A Bits D17 D16 Selects which PWM channel is output to OUT B Bits D13 D12 Selects which PWM channel is output to OUT C Bits D09 D08 Selects which PWM channel is output to OUT D Note that channels are encoded so that channel 1 0x00 channel 2 0x01 channel 4 0x03 Table 22 PWM Output Mux Register 0x25 D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 1 Reserved D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 0 Reserved 0 0 Multiplex channel 1 to OUT A 0 1 Multiplex channel 2 to OUT_A 1 0 Multiplex channel 1 to OUT A 1 1 Multiplex channel 2 to OUT A 0 0 Reserved 1 0 0 Multiplex channel 1 to OUT_B 0 1 Multiplex channel 2 to OUT_B 1 0 Multiplex channel 1 to OUT B 1 1 Multiplex channel 2 to OUT_B D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 0 Reserved 1 0 0 Multiplex channel 1 to OUT C 0 Multiplex channel 2 to OUT CO 1 0 Multiplex channel 1 to OUT C 1 Default values are in bold Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TAS5713 55 TAS571
4. 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 ip TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 30 Jan 2010 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Di Type Drawing Qty TAS5713PHPR ACTIVE HTQFP PHP 48 1000 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free ROHS Exempt or Green RoHS amp no Sb Br please check http Avww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous mate
5. 34 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 13 TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 The decimal value of a 3 23 format number can be found by following the weighting shown in Figure 48 If the most significant bit is logic 0 the number is a positive number and the weighting shown yields the correct number If the most significant bit is a logic 1 then the number is a negative number In this case every bit must be inverted a 1 added to the result and then the weighting shown in Figure 49 applied to obtain the magnitude of the negative number 2 Bit 2 Bit 2 Bit 27 Bit 2 Bit d to 4 1 or 0 x 2 1 or 0 x 2 1 or 0 x 2 1 or 0 x 2 1 or 0 x 27 M0126 01 Figure 49 Conversion Weighting Factors 3 23 Format to Floating Point Gain coefficients entered via the 1 C bus must be entered as 32 bit binary numbers The format of the 32 bit number 4 byte or 8 digit hexadecimal number is shown in Figure 50 Sign Fraction Bit Digit 6 Fraction Fraction Fraction Fraction Fraction Integer Digit PTT Digt2 PIE Digt3 PIE Digta PIE digits Digit 1 v u ufu ul u uls x x x x x X X IXIX yxy xp x x x x xp x XI x xp x X X x x o A A A A A A A A Coefficient
6. 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x60 0x61 4 Reserved 0x62 IDF post scale 4 0x0000 0080 0x63 0x6F Reserved 0x0000 0000 0x70 ch1 inline mixer 4 u 31 26 in mix1 25 0 0x0080 0000 Ox71 inline DRC en mixer ch1 4 u 31 26 in_mixdrc_1 25 0 0x0000 0000 3 Reserved registers should not be accessed 42 Submit Documentation Feedback Copyright O 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 I TEXAS INSTRUMENTS www ti com Table 4 Serial Control Interface Register Summary continued TAS5713 SLOS637 DECEMBER 2009 SUBADDRESS REGISTER NAME na CONTENTS MEUS S 0x72 ch1 right channel mixer 4 u 31 26 right mix1 25 0 0x0000 0000 0x73 ch1 left_channel_mixer 4 u 31 26 left_mix_1 25 0 0x0080 0000 0x74 ch2 inline mixer 4 u 31 26 in_mix2 25 0 0x0080 0000 0x75 inline DRC en mixer ch2 4 u 31 26 in_mixdrc_2 25 0 0x0000 0000 0x76 ch2 left chanel mixer 4 u 31 26 left mix1 25 0 0x0000 0000 0x77 ch2 right_channel_mixer 4 u 31 26 right_mix_1 25 0 0x0080 0000 0x78 0xF7 Reserved 9 OxF8 Update dev address key 4 Dev Id Update Key 31 0 Key OxF9A5A5A5 0x0000 0000 OxF9 Update dev address reg 4 u 31 8 New Dev Id 7 0 New Dev Id 0x38 for 0x0000 0036 TAS5713 OxFA OxFF 4 Reserved 0x0000 0000 All DAP coefficients are 3 23 format unless specified otherwise Registers Ox3B through 0x46 should be altered onl
7. 22 025 24 kHz uses bank 1 8 kHz does not use bank 1 8 kHz uses bank 1 11 025 12 kHz does not use bank 1 11 025 12 kHz uses bank 1 1 Default values are in bold Copyright O 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TAS5713 57 TAS5713 SLOS637 DECEMBER 2009 JA TEXAS INSTRUMENTS www ti com Table 24 Bank Switching Command continued D7 D6 D5 D4 D3 D2 D1 DO FUNCTION EQ ON EQ OFF bypass BQ 0 7 of channels 1 and 2 Reserved Ignore bank mapping in bits D31 D8 Use default mapping Use bank mapping in bits D31 D8 L and R can be written independently 2 L and R are ganged for EQ biquads a write to the left channel biquad is also written to the right channel biquad 0x29 0x2F is ganged to 0x30 0x36 Also 0x58 0x5B is ganged to 0x5C 0x5F Reserved No bank switching All updates to DAP Configure bank 1 32 kHz by default Configure bank 2 44 1 48 kHz by default Configure bank 3 other sample rates by default Automatic bank selection Reserved o jo jo o ojoil i joi jo xX oj 2 o 2 o Reserved 2 58 Default values are in bold Submit Documentation Feedback Copyright
8. 26 94 50 C4 74 F4 98 05 21 5 35 2 5 65 26 5 95 50 5 C5 74 5 F5 98 5 06 21 36 3 66 27 96 51 C6 75 F6 99 07 20 5 37 3 5 67 27 5 97 51 5 C7 75 5 F7 99 5 08 20 38 A 68 28 98 52 C8 76 F8 100 09 19 5 39 4 5 69 28 5 99 52 5 C9 76 5 F8 0A 19 3A 5 6A 29 9A 53 CA 77 FA 0B 18 5 3B 5 5 6B 29 5 9B 53 5 CB 77 5 FB DC 18 3C 6 6C 30 9C 54 CC 78 FC OD 17 5 3D 6 5 6D 30 5 9D 54 5 CD 78 5 FD 0E 17 3E 7 6E 31 9E 55 CE 79 FE OF 16 5 3F 7 5 6F 31 5 9F 55 5 CF 79 5 FF 10 16 40 8 70 32 AO 56 DO 80 11 15 5 41 8 5 71 32 5 A1 56 5 D1 80 5 12 15 42 9 72 33 A2 57 D2 81 13 14 5 43 9 5 73 33 5 A3 57 5 D3 81 5 14 14 44 10 74 34 A4 58 D4 82 15 13 5 45 10 5 75 34 5 A5 58 5 D5 82 5 16 13 46 11 76 35 A6 59 D6 83 17 12 5 37 11 5 77 35 5 A7 59 5 D7 83 5 18 12 38 12 78 36 A8 60 D8 84 19 11 5 39 12 5 79 36 5 A9 60 5 D9 84 5 1A 11 4A 13 7A 37 AA 61 DA 85 1B 10 5 4B 13 5 7B 37 5 AB 61 5 DB 85 5 1C 10 4C 14 7C 38 AC 62 DC 86 1D 9 5 4D 14 5 7D 38 5 AD 62 5 DD 86 5 1E 9 4E 15 7E 39 AE 63 DE 87 1F 8 5 4F 15 5 7F 39 5 AF 63 5 DF 87 5 20 8 50 16 80 40 BO 64 EO 88 21 7 5 51 16 5 81 40 5 BI 64 5 E1 88 5 22 7 52 17 82 AI B2 65 E2 89 23 6 5 53 17 5 83 41 5 B3 65 5 E3 89 5 24 6 54 18 84 42 B4 66 E4 90 25 5 5 55 18 5 85 42 5 B5 66 5 E5 90 5 48 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated
9. Product Folder Link s TAS5713 l www ti com TEXAS INSTRUMENTS TAS5713 SLOS637 DECEMBER 2009 Table 12 Master Volume Table continued HEX dB HEX dB HEX dB HEX dB HEX dB HEX dB 26 5 56 19 86 43 B6 67 E6 91 27 4 5 547 19 5 87 43 5 B7 67 5 E7 91 5 28 4 58 20 88 44 B8 68 E8 92 29 3 5 59 20 5 89 44 5 B9 68 5 E9 92 5 2A 3 5A 21 8A 45 BA 69 EA 93 2B 2 5 5B 21 5 8B 45 5 BB 69 5 EB 93 5 2C 2 5C 22 8C 46 BC 70 EC 94 2D 1 5 5D 22 5 8D 46 5 BD 70 5 ED 94 5 2E 1 5E 23 8E 47 BE 71 EE 95 2F 0 5 5F 23 5 8F 47 5 BF 71 5 EF 95 5 VOLUME CONFIGURATION REGISTER 0x0E Bits Volume slew rate used to control volume change and MUTE ramp rates These bits control the D2 D0 number of steps in a volume ramp Volume steps occur at a rate that depends on the sample rate of the ES data as follows Sample rate kHz Approximate ramp rate 8 16 32 125 us step 11 025 22 05 44 1 90 7 us step 12 24 48 83 3 us step Table 13 Volume Control Register 0x0E D7 D6 D5 D4 D3 D2 DI DO FUNCTION 11010 11 01 Reserved 1 0 0 0 Volume slew 512 steps 43 ms volume ramp time at 48 kHz 1 0 0 1 Volume slew 1024 steps 85 ms volume ramp time at 48 kHz 0 1 0 Volume slew 2048 steps 171 ms volume ramp time
10. 0 0 0 0 0 Reserved D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 Channel 1 AD mode 1 Channel 1 BD mode 0 0 0 SDIN L to channel 1 0 0 1 SDIN R to channel 1 0 1 0 Reserved 0 1 1 Reserved m 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Ground 0 to channel 1 1 1 1 Reserved 0 Channel 2 AD mode 1 Channel 2 BD mode 0 0 0 SDIN L to channel 2 0 0 1 SDIN R to channel 2 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Ground 0 to channel 2 1 1 1 Reserved D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 1 1 1 0 1 1 1 Reserved D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 1 1 1 0 0 1 0 Reserved 1 Default values are in bold 54 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 I TEXAS INSTRUMENTS www ti com TAS5713 SLOS637 DECEMBER 2009 CHANNEL 4 SOURCE SELECT REGISTER 0x21 This register selects the channel 4 source Table 21 Subchannel Control Register 0x21 D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 Reserved D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 0 0 0 0 0 0 Reserved D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 1 0 0 0 0 Reserved 0 L R 2 1 Left channel post BQ D7 D6 D5 D4 D3 D2 DO FUNCTION 0 0 0 0 0 0 1 Reserved 1 Default values are in bold PWM OUTPUT MUX REGISTER 0x25
11. 2 5W 1k 10k 20k Frequency Hz Sort 0 001 100 1k 10k 20k 20 100 Frequency Hz Gooi 20 Figure 6 Figure 7 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY 10 PVDD 24V RL 80 Ta 25 C PVDD 18V RL 80 Ta 25 C 0 01 0 001 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency Hz 6003 Frequency Hz Cina Figure 8 Figure 9 14 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 TAS5713 JA TEXAS INSTRUMENTS www ti com SLOS637 DECEMBER 2009 TYPICAL CHARACTERISTICS BTL CONFIGURATION 8 Q continued TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER PVDD 12V RL 80 Ta 25 C PVDD 8V RL 80 Ta 25 C z z t t I I H H 0 01 0 1 1 10 40 0 01 0 1 1 10 40 Output Power W G05 Output Power W GO0B Figure 10 Figure 11 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER PVDD 18V PVDD 24V RL 80 RL 80 Ta 25 C Ta 25 C z z I T H H 0 01 0 1 1 10 40 0 01 0 1 1 10 40 Output Power W G007 Output Power W GODE Figure 12 Figure 13 Submit Documentation Feedback 15 Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 TAS5713 ip TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com TY
12. 50 duty cycle start stop period 31 4 ms 50 duty cycle start stop period 40 4 ms 50 duty cycle start stop period 53 9 ms 50 duty cycle start stop period 70 3 ms 50 duty cycle start stop period 94 2 ms 50 duty cycle start stop period 125 7 ms 50 duty cycle start stop period 164 6 ms 50 duty cycle start stop period 239 4 ms 50 duty cycle start stop period 314 2 ms 50 duty cycle start stop period 403 9 ms 50 duty cycle start stop period 538 6 ms 50 duty cycle start stop period 703 1 ms 50 duty cycle start stop period 942 5 ms 50 duty cycle start stop period 1256 6 ms 50 duty cycle start stop period 1728 1 ms 50 duty cycle start stop period 2513 6 ms 50 duty cycle start stop period 3299 1 ms 50 duty cycle start stop period 4241 7 ms 50 duty cycle start stop period 5655 6 ms 50 duty cycle start stop period 7383 7 ms 50 duty cycle start stop period 9897 3 ms 50 duty cycle start stop period 13 196 4 ms 50 duty cycle start stop period I I aiafjofasjafoaufasasoufajufuausyausjufusiujoqlaolololololololo alialjofasjasjufusliuloqololololololosl o ai ajafasjasjasfuasliso olololo ro 06 oo os lt lt olololo m rlolol rl lolo rlrlol ol rl rlol ol eh ol or lolo O0 0 0 0 0 0 0 Da a 1 Default values are in bold 52 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder
13. Coefficient Coefficient Coefficient Coefficient Coefficient Coefficient Coefficient Digit 8 Digit 7 Digit 6 Digit 5 Digit 4 Digit 3 Digit 2 Digit 1 u unused or don t care bits Digit hexadecimal digit M0127 01 Figure 50 Alignment of 3 23 Coefficient in 32 Bit UC Word Table 2 Sample Calculation for 3 23 Format db Linear Decimal Hex 3 23 Format 0 1 8 388 608 80 0000 1 77 14 917 288 00E3 9EA8 5 0 56 4 717 260 0047 FACC X L 10020 D 8 388 608 x L H dec2hex D 8 Table 3 Sample Calculation for 9 17 Format db Linear Decimal Hex 9 17 Format 0 1 131 072 2 0000 1 77 231 997 3 8A3D 5 0 56 73 400 1 1EB8 X L 100020 D 131072 x L H dec2hex D 8 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Link s TAS5713 Xi TEXAS INSTRUMENTS TAS5713 www ti com SLOS637 DECEMBER 2009 Recommended Use Model 90 6Ly0L d umopiamod gt OOR ETE VLX0 4e1siBo1 ur peuyep se euim dojs ueis NMd ANAS z sos juenbesqns Buiwojjo spuewwoo wu 0 Ajdde jou saop 1 dn jewod qgAqa aaAv Sumoo puewwod uu 1s1y eu 0 saljdde Ajuo 1uiensuoo sy 75 e su OpZ uey JejeeJf eq o seu T z SPUEWILUOI ejnjy pue euinioA MEL SW 4 umop nys pP 4 uonessdo jeuuoN gt uonezyeniu NE adAd
14. Link s TAS5713 l www ti com TEXAS INSTRUMENTS TAS5713 SLOS637 DECEMBER 2009 OSCILLATOR TRIM REGISTER 0x1B The TAS5713 PWM processor contains an internal oscillator to support autodetect of I S clock rates This reduces system cost because an external reference is not required Currently Tl recommends a reference resistor value of 18 2 KO 1 This should be connected between OSC RES and DVSSO Writing 0x00 to register 0x1B enables the trim that was programmed at the factory Note that trim must always be run following reset of the device Table 18 Oscillator Trim Register 0x1B D7 D6 D5 D4 D3 D2 DI DO FUNCTION 1 Reserved 1 0 Oscillator trim not done read only x 1 Oscillator trim done read only 0 010 0 Reserved 1 0 Select factory trim Write a 0 to select factory trim default is 1 1 Factory trim disabled 1 0 Reserved 1 1 BKND_ERR REGISTER 0x1C Default values are in bold When a back end error signal is received from the internal power stage the power stage is reset stopping all PWM activity Subsequently the modulator waits approximately for the time listed in Table 19 before attempting to re start the power stage Table 19 BKND ERR Register 0x1C D7 D6 D5 D4 D3 D2 D1 DO F
15. The bus uses transitions on the data pin SDA while the clock is high to indicate start and stop conditions A high to low transition on SDA indicates a start and a low to high transition indicates a stop Normal data bit transitions must occur within the low time of the clock period These conditions are shown in Figure 41 The master generates the 7 bit slave address and the read write R W bit to open communication with another device and then waits for an acknowledge condition The TAS5713 holds SDA low during the acknowledge clock period to indicate an acknowledgment When this occurs the master transmits the next byte of the sequence Each device is addressed by a unique 7 bit slave address plus R W bit 1 byte All compatible devices share the same signals via a bidirectional bus using a wired AND connection An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus R 3 8 Bit Register Data For 8 Bit Register Data For SDA 7 Bit Slave Address 8 Bit Register Address N Address N Address N A Start Stop T0035 01 Figure 41 Typical IPC Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions When the last word transfers the master generates a stop condition to release the bus A generic data transfer sequence is shown in Figure 41 The 7 bit address for the TAS5713 is 0011 011 0x36 or 0011010 0x34 based on the po
16. all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk an
17. are ovailable at www ti com http www ti com E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations F Customers should contact their board fabrication site for recommended solder mask tolerances and via tenting options for vias placed in the thermal pad 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer
18. signal 4 2 PVDD 8 V 7 THD 1 kHz input signal 4 Po Power output per channel PBTL mode PVDD 12 V R 4Q 18 7 W 10 THD 1 kHz input signal PBTL mode PVDD 12V R 4Q 17 7 7 THD 1 kHz input signal PBTL mode PVDD 18V RL 4Q 41 5 10 THD 1 kHz input signal PBTL mode PVDD 18V RL 4Q 39 7 THD 1 kHz input signal PVDD 18V Po 1W 0 07 THD N Total harmonic distortion noise PVDD 12V Po 1W 0 03 PVDD 8 V Po 1W 0 1 Va Output integrated noise rms A weighted 56 uV Po 0 25 W f 1 kHz BD Mode 82 dB Crosstalk Po 0 25 W f 1 kHz AD Mode 69 dB T 4 A weighted f 1 kHz maximum power at SNR Signal to noise ratio THD 195 106 dB 1 10 SNR is calculated relative to 0 dBFS input level Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 13 TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions unless otherwise noted TEST PARAMETER CONDITIONS MIN TYP MAX UNIT TSCLKIN Frequency SCLK 32 x fs 48 x fs 64 x fs CL 30 pF 1 024 12 288 MHz tsu1 Setup time LRCLK to SCLK rising edge 10 ns thi Hold time LRCLK from SCLK rising edge 10 ns Luz Setup time SDIN to SCLK rising edge 10 ns the Hold time SDIN from SCLK rising edge 10 ns LRCLK frequency 8 48 48 kHz S
19. the left channel and low for the right channel A bit clock running at 32 48 or 64 x fs is used to clock in the data The first bit of data appears on the data lines at the same time LRCLK toggles The data is written MSB first and is valid on the rising edge of the bit clock The DAP masks unused trailing data bit positions 2 Channel Left Justified Stereo Input BEE T Right Channel el NE a AME OOH 99 XXX RADON BODO u_ _ _ X X045 5 T0034 02 NOTE All data presented in 2s complement form with MSB first Figure 35 Left Justified 64 f Format 26 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 lp TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 2 Channel Left Justified Stereo Input 24 Bit Transfer Word Size NGC 7 Right Channel MUU UU JU UU UU LU UIL UYU UL Gi OA T0092 02 NOTE All data presented in 2s complement form with MSB first Figure 36 Left Justified 48 f Format 2 Channel Left Justified Stereo Input PS Chap UUUUUUUKHUUUUUUUIUUUUUUKUUUUULU 9369099909 CS A GAS KOM EMER X8 X ASASASA2XCAS T0266 02 NOTE All data presented in 2s complement form with MSB first Figure 37 Left Justified 32 fs Format Right Justified Right justified RJ timing uses LRCLK to define when the data being transmitted is for the left channel and when Copyrig
20. written to the memory address being accessed After receiving the data byte the TAS5713 again responds with an acknowledge bit Finally the master device transmits a stop condition to complete the single byte data write transfer Start Condition Acknowledge Acknowledge Acknowledge I I FA Pa Aa DOCOC000000000006000000000v I I C Device Address and Subaddress Data Byte Stop Read Write Bit Condition T0036 01 Figure 42 Single Byte Write Transfer Multiple Byte Write A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 43 After receiving each data byte the TAS5713 responds with an acknowledge bit Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge LAN A AA DADA AU OY ASK MK AIK ATX AO SS 1 i CC Device Address and Subaddress First Data Byte Other Data Bytes Last Data Byte Stop Read Write Bit Condition T0036 02 Figure 43 Multiple Byte Write Transfer Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link s TAS5713 Id Ti TAS5713 INSTRUMENIS SLOS637 DECEMBER 2009 www ti com Single Byte Read As shown in Figure 44 a single byte data read transfer begins with the master device transmitting a start condition followed by the DC device address and the read write bit For the data read transfer both a w
21. 0 01 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency Hz cois Frequency Hz Goi Figure 26 Figure 27 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER PVDD 12V PVDD 24V RL 40 RL 40 Ta 25 C Ta 25 C z z Q Q T I E F 0 01 0 1 1 10 50 Output Power W 6017 Output Power W Gote Figure 28 Figure 29 20 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 13 TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 TYPICAL CHARACTERISTICS PBTL CONFIGURATION 4 Q continued OUTPUT POWER EFFICIENCY vs vs SUPPLY VOLTAGE TOTAL OUTPUT POWER RL 40 Ta 25 C THD N 10 PVDD 12V WI Efficiency THD N 1 Output Power 8 10 12 14 16 18 20 22 24 26 0 10 20 30 40 50 60 Supply Voltage V ois Total Output Power W 030 NOTE Dashed lines represent thermally limited regions A Dashed line represents thermally limited regions Figure 30 Figure 31 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com DETAILED DESCRIPTION POWER SUPPLY To facilitate system design the TAS5713 needs only a 3 3 V supply in addition to the typical 18 V power stage supply An internal voltage regulator provides suitable voltage levels for the gate drive circuitry
22. 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 I TEXAS INSTRUMENTS www ti com TAS5713 SLOS637 DECEMBER 2009 PIN FUNCTIONS continued TYPE SV TERMINATION DESCRIPTION NAME NO TOLERANT DVSS 28 P Digital ground DVSSO 17 P Oscillator ground GND 29 P Analog ground for power stage GVDD_OUT 32 P Gate drive internal regulator output LRCLK 20 DI 5 V Pulldown Input serial audio data left right clock sample rate clock MCLK 15 DI 5 V Pulldown Master clock input NC 5 7 No connect OSC RES 16 AO Oscillator trim resistor Connect an 18 2 kO 1 resistor to DVSSO OUT A 1 O Output half bridge A OUT_B 46 O Output half bridge B OUT_C 39 O Output half bridge C OUT_D 36 O Output half bridge D PBTL 8 DI Low means BTL or SE mode high means PBTL mode Information goes directly to power stage PDN 19 DI 5 V Pullup Power down active low PDN prepares the device for loss of power supplies by shutting down the noise shaper and initiating the PWM stop sequence PGND_AB 47 48 P Power ground for half bridges A and B PGND_CD 37 38 P Power ground for half bridges C and D PLL_FLTM 10 AO PLL negative loop filter terminal PLL_FLTP 11 AO PLL positive loop filter terminal PVDD_A 2 3 P Power supply input for half bridge output A PVDD_B 44 45 P Power supply input for half bridge out
23. 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 40 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 I TEXAS INSTRUMENTS www ti com Table 4 Serial Control Interface Register Summary continued TAS5713 SLOS637 DECEMBER 2009 SUBADDRESS REGISTER NAME asa CONTENTS Gel eer ION 0x34 ch2 bq 4 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x35 ch2 bq 5 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x36 ch2 bq 6 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x36 0x3A 4 Reserved 0x3B DRC1 softening filter alpha 8 u 31 26 ae 25 0 0x0008 0000 DRC1 softening filter u 31 26 0e 25 0 0x0078 0000 omega 0x3C DRC1 attack rate 8 0x0000 0100 DRC1 release rate OxFFFF FF00 0x3D 8 Reserved 0x0080 0000 Ox3E DRC2 softening filter alpha 8 u 31 26 ae 25 0 0x0008 0000 DRC2 softening filter u 31 26 0e 25 0
24. 3 SLOS637 DECEMBER 2009 JA TEXAS INSTRUMENTS www ti com Table 22 PWM Output Mux Register 0x25 continued 1 1 Multiplex channel 2 to OUT_C 0 0 Reserved 0 0 Multiplex channel 1 to OUT_D 0 1 Multiplex channel 2 to OUT_D 1 0 Multiplex channel 1 to OUT D 1 1 Multiplex channel 2 to OUT D D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 1 0 0 0 1 0 1 Reserved DRC CONTROL 0x46 Table 23 DRC Control Register 0x46 D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 0 Reserved D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 0 0 0 0 0 0 0 Reserved D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 0 0 0 0 0 0 0 Reserved D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 Reserved 1 Reserved i 0 Reserved 2 0 Reserved 2 0 DRC2 turned OFF DRC2 turned ON 0 DRC1 turned OFF 1 DRC1 turned ON 0 0 0 Reserved 1 Default values are in bold 2 Reserved registers should not be accessed 56 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 l TEXAS INSTRUMENTS www ti com BANK SWITCH AND EQ CONTROL 0x50 TAS5713 SLOS637 DECEMBER 2009 Table 24 Bank Switching C
25. 37 DECEMBER 2009 www ti com DEVICE ID REGISTER 0x01 The device ID register contains the ID code for the firmware revision Table 6 General Status Register 0x01 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 0 0 0 0 0 0 0 Identification code 44 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 I TEXAS INSTRUMENTS www ti com ERROR STATUS REGISTER 0x02 TAS5713 SLOS637 DECEMBER 2009 The error bits are sticky and are not cleared by the hardware This means that the software must clear the register write zeroes and then read them to determine if they are persistent errors Error definitions e MCLK Error MCLK frequency is changing The number of MCLKs per LRCLK is changing e SCLK Error The number of SCLKs per LRCLK is changing LRCLK Error LRCLK frequency is changing Frame slip LRCLK phase is drifting with respect to internal frame sync Table 7 Error Status Register 0x02 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION MCLK error PLL autolock error SCLK error LRCLK error Frame slip Clip indicator Overcurrent overtemperature overvoltage or undervoltage error 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 No errors 1 1 Default values are in bold SYSTEM CONTROL REGISTER 1 0x03 System control r
26. 4 D3 D2 D1 DO FUNCTION 0 Reserved 1 0 Reserved 1 Reserved 1 A 1 Reserved 1 0 PWM channel 4 does not belong to shutdown group 1 PWM channel 4 belongs to shutdown group 0 PWM channel 3 does not belong to shutdown group 1 PWM channel 3 belongs to shutdown group 0 PWM channel 2 does not belong to shutdown group 1 PWM channel 2 belongs to shutdown group O PWM channel 1 does not belong to shutdown group 1 PWM channel 1 belongs to shutdown group 1 Default values are in bold Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 51 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com START STOP PERIOD REGISTER 0x1A This register is used to control the soft start and soft stop period following an enter exit all channel shutdown command or change in the PDN state This helps reduce pops and clicks at start up and shutdown The times are only approximate and vary depending on device activity level and ES clock stability Table 17 Start Stop Period Register 0x1A D7 D6 D5 D4 D3 D2 DI DO FUNCTION D SSTIMER enabled 1 SSTIMER disabled 0 0 Reserved I I I No 50 duty cycle start stop period 16 5 ms 50 duty cycle start stop period 23 9 ms
27. 713 DAP accepts serial data in 16 20 or 24 bit left justified right justified and I S serial data formats PWM SECTION The TAS5713 DAP device uses noise shaping and customized nonlinear correction algorithms to achieve high power efficiency and high performance digital audio reproduction The DAP uses a fourth order noise shaper to increase dynamic range and SNR in the audio band The PWM section accepts 24 bit PCM data from the DAP and outputs two BTL PWM audio output channels The PWM section has individual channel dc blocking filters that can be enabled and disabled The filter cutoff frequency is less than 1 Hz Individual channel de emphasis filters for 44 1 kKHz and 48 kHz are included and can be enabled and disabled Finally the PWM section has an adjustable maximum modulation limit of 93 8 to 99 2 For a detailed description of using audio processing features like DRC and EQ see the User s Guide and TAS570X GDE software development tool documentation SERIAL INTERFACE CONTROL AND TIMING PS Timing IS timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel LRCLK is low for the left channel and high for the right channel A bit clock running at 32 48 or 64 x fs is used to clock in the data There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines The data is written MSB first and is valid on the ris
28. AND EXTERNAL FILTER COMPONENTS TAS5713 SLOS637 DECEMBER 2009 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TMCLKI MCLK freguency 2 8224 24 576 MHz MCLK duty cycle 40 50 60 M Rise fall time for MCLK 5 ns t MCLK LRCLK allowable drift before LRCLK reset 4 MCLKs External PLL filter capacitor C1 SMD 0603 X7R 47 nF External PLL filter capacitor C2 SMD 0603 X7R 4 7 nF External PLL filter resistor R SMD 0603 metal film 470 Q ELECTRICAL CHARACTERISTICS DC Characteristics T4 25 PVCC_x 18 V DVDD AVDD 3 3 V R 8 Q BTL AD mode fs 48 kHz unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vok High level output voltage A_SEL_FAULT and SDA di m 24 V VoL Low level output voltage A_SEL_FAULT and SDA EE os v Ii Low level input current a PVDD SAVDO 75 HA 8 VI gt Vin S DVDD 1 liq High level input current AVDD 3 6V 75 HA 33V It DVDD Normal mode 48 83 3 V su voltage lop 3 3 V supply current AVDD TI Reset RESET low 26 40 mA PDN high Normal mode 41 75 levpp Supply current No load PVDD x Reset RESET low 5 13 mA PDN high Drain to source resistance LS Ty 25 C includes metallization resistance 110 2 f to mQ ER e to source resistance 7 _ 25 C includes metallization resistance 110 I O Protection Vuvp Undervoltage protection limit PVDD falling 7 2 V Vuvp hy
29. Additionally all circuitry requiring a floating voltage supply e g the high side gate drive is accommodated by built in bootstrap circuitry requiring only a few external capacitors In order to provide good electrical and acoustical characteristics the PWM signal path for the output stage is designed as identical independent half bridges For this reason each half bridge has separate bootstrap pins BST_x and power stage supply pins PVDD_x The gate drive voltage GVDD_OUT is derived from the PVDD voltage Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible Inductance between the power supply pins and decoupling capacitors must be avoided For a properly functioning bootstrap circuit a small ceramic capacitor must be connected from each bootstrap pin BST_x to the power stage output pin OUT_x When the power stage output is low the bootstrap capacitor is charged through an internal diode connected between the gate drive regulator output pin GVDD_OUT and the bootstrap pin When the power stage output is high the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high side gate driver In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz it is recommended to use 33 nF X7R ceramic capacitors size 0603 or 0805 for the bootstrap supply These 33 nF capacitors ensure sufficie
30. CLK duty cycle 40 50 60 LRCLK duty cycle 40 50 60 SCLK rising edges between LRCLK rising edges 32 64 ee edge LRCLK clock edge with respect to the falling edge of SCLK 1 4 1 4 Sep Mir Rise fall time for SCLK LRCLK 8 ns ae ie SCLK Input I I I tiedge l ini d a K tout I LRCLK Input 4 the e di tsu2 T0026 04 Figure 2 Slave Mode Serial Data Interface Timing Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com PC SERIAL CONTROL PORT OPERATION Timing characteristics for 1 C Interface signals over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT fscL Frequency SCL No wait states 400 kHz tw H Pulse duration SCL high 0 6 us tw L Pulse duration SCL low 1 3 us tr Rise time SCL and SDA 300 ns t Fall time SCL and SDA 300 ns tsu1 Setup time SDA to SCL 100 ns th Hold time SCL to SDA 0 ns tbuf Bus free time between stop and start conditions 1 3 US tsu2 Setup time SCL to start condition 0 6 us th2 Hold time start condition to SCL 0 6 us Lg Setup time SCL to stop condition 0 6 US CL Load capacitance for each bus line 400 pF ev HE hy i vendo e I I SCL M I tu e al ty T0027 01 to e tour gt gt I 4 L
31. ENTS SLOS637 DECEMBER 2009 www ti com Table 4 Serial Control Interface Register Summary continued SUBADDRESS REGISTER NAME asa CONTENTS Gel eer ION 0x58 ch1 BQ 7 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x59 ch1 BQ 8 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 Ox5A ch4 BQ 0 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x5B ch4 BQ 1 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x5C ch2 BQ 7 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x5D ch2 BQ 8 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 Ox5E ch3 BQ 0 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 Ox5F ch3 BQ 1 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0
32. Id TEXAS INSTRUMENTS www ti com TAS5713 SLOS637 DECEMBER 2009 25 W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC Check for Samples TAS5713 FEATURES e Audio Input Output 25 W Into an 8 O Load From a 20 V Supply Wide PVDD Range From 8 V to 26 V Supports BTL Configuration With 4 O Load Efficient Class D Operation Eliminates Need for Heatsinks One Serial Audio Input Two Audio Channels PC Address Selection Pin Chip Select Single Output Filter PBTL Support Supports 8 kHz to 48 kHz Sample Rate LJ RJ S e Audio PWM Processing Independent Channel Volume Controls With Gain of 24 dB to Mute Programmable Two Band Dynamic Range Control 22 Programmable Biquads for Speaker EQ and Other Audio Processing Features Programmable Coefficients for DRC Filters DC Blocking Filters General Features PC Serial Control Interface Operational Without MCLK Requires Only 3 3 V and PVDD No External Oscillator Internal Oscillator for Automatic Rate Detection Surface Mount 48 Pin 7 mm x 7 mm HTQFP Package Thermal and Short Circuit Protection 106 dB SNR A Weighted AD and BD PWM Mode Support Up to 90 Efficient Benefits EQ Speaker Equalization Improves Audio Performance DRC Dynamic Range Compression Can Be Used As Power Limiter Enables Speaker Protection Easy Listening Night Mode Listening Autoba
33. Interface Control Register 0x04 Format INTERFACE FORMAT LENGTH D7 D4 D3 D2 D1 Do Right justified 16 0000 0 0 0 0 Right justified 20 0000 0 0 0 1 Right justified 24 0000 0 0 1 0 Ps 16 000 0 0 1 1 Ps 20 0000 0 1 0 0 Ps 0 24 0000 0 1 0 1 Left justified 16 0000 0 1 1 0 Left justified 20 0000 0 1 1 1 Left justified 24 0000 1 0 0 0 Reserved 0000 1 0 0 1 Reserved 0000 1 0 1 0 Reserved 0000 1 0 1 1 Reserved 0000 1 1 0 0 Reserved 0000 1 1 0 1 Reserved 0000 1 1 1 0 Reserved 0000 1 1 1 1 1 46 Default values are in bold Submit Documentation Feedback Product Folder Link s TAS5713 Copyright 2009 Texas Instruments Incorporated lp TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 SYSTEM CONTROL REGISTER 2 0x05 When bit D6 is set low the system exits all channel shutdown and starts playing audio otherwise the outputs are shut down hard mute Table 10 System Control Register 2 0x05 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 Mid Z ramp disabled 1 Mid Z ramp enabled 0 Exit all channel shutdown normal operation 1 Enter all channel shutdown hard mute 10 0 01 Reserved 0 Reserved 1 0 A SEL FAULT configured as input A SEL FAULT configured configured as output to function as A_SEL_FAULT pin 0 Reserved 1
34. MAIN S A8 X KAALA T0266 03 Figure 40 Right Justified 32 fs Format Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com PC SERIAL CONTROL INTERFACE The TAS5713 DAP has a bidirectional DC interface that is compatible with the Inter IC IC bus protocol and supports both 100 kHz and 400 kHz data transfer rates for single and multiple byte write and read operations This is a slave only device that does not support a multimaster bus environment or wait state insertion The control interface is used to program the registers of the device and to read device status The DAP supports the standard mode IC bus operation 100 kHz maximum and the fast I C bus operation 400 kHz maximum The DAP performs all DC operations without IC wait cycles General UC Operation The DC bus employs two signals SDA data and SCL clock to communicate between integrated circuits in a system Data is transferred on the bus serially one bit at a time The address and data can be transferred in byte 8 bit format with the most significant bit MSB transferred first In addition each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus
35. ORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY PVDD 18V RL 40 Ta 25 C PVDD 12V RL 40 z Z 0 1 Q Q T T E F 0 01 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency Hz pat Frequency Hz c z Figure 20 Figure 21 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER PVDD 12V PVDD 18V RL 40 RL 40 Ta 25 C Ta 25 C z z Q Q T T E F 0 01 0 1 1 10 40 0 01 0 1 1 10 50 Output Power W 6025 Output Power W 6027 Figure 22 Figure 23 18 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 Te ee TAS5713 www ti com SLOS637 DECEMBER 2009 TYPICAL CHARACTERISTICS BTL CONFIGURATION 4 Q continued CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY y n X Ss x g g 2 D Right to Left O Right to Left Left to Right Left to Right 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency Hz 6023 Frequency Hz Go2 Figure 24 Figure 25 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link s TAS5713 Id Ti TAS5713 KEE SLOS637 DECEMBER 2009 www ti com TYPICAL CHARACTERISTICS PBTL CONFIGURATION 4 Q TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY PVDD 24V RL 40 Ta 25 C PVDD 12V RL 40 Ta 25 C z 0 1 Q Q I I E F
36. OxFFF8 0000 omega Ox3F DRC2 attack rate 8 u 31 26 at 25 0 0x0008 0000 DRC2 release rate u 31 26 rt 25 0 OxFFF8 0000 0x40 DRC1 attack threshold 8 T1 31 0 9 23 format 0x0800 0000 DRC1 release threshold T1 31 0 0x07FF FFFF 0x41 0x42 4 Reserved 0x43 DRC2 attack threshold 8 T2 31 0 9 23 format 0x0080 0000 DRC2 decay threshold T2 81 0 0x0000 0000 0x44 0x45 4 Reserved 0x46 DRC control 4 Description shown in subsequent section 0x0000 0000 0x47 0x4F 4 Reserved 0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000 0x51 Ch 1 output mixer 8 Ch 1 output mix1 1 0x0080 0000 Ch 1 output mix1 0 0x0000 0000 0x52 Ch 2 output mixer 8 Ch 2 output mix2 1 0x0080 0000 Ch 2 output mix2 0 0x0000 0000 0x53 Ch 1 input mixers 16 Channel 1 input mixers can be accessed using 1 C subaddresses 0x70 0x73 using 4 byte access 0x54 Ch 2 input mixers 16 Channel 2 input mixers can be accessed using 1 C subaddresses 0x74 0x77 using 4 byte access 0x56 Output post scale 4 u 31 26 post 25 0 0x0080 0000 0x57 Output pre scale 4 u 31 26 pre 25 0 9 17 format 0x0002 0000 2 Reserved registers should not be accessed Copyright O 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TAS5713 41 TAS5713 I TEXAS INSTRUM
37. PICAL CHARACTERISTICS BTL CONFIGURATION 8 Q continued OUTPUT POWER EFFICIENCY vs vs SUPPLY VOLTAGE TOTAL OUTPUT POWER PVDD 24V s PVDD 18V THD N 10 lt E PVDD 12V o o E a o 5 E PVDD 8V 5 LU Oo THD N 1 8 10 12 14 16 18 20 22 24 26 0 5 10 15 20 25 30 35 40 Supply Voltage V Sang Total Output Power W 6010 NOTE Dashed lines represent thermally limited regions NOTE Dashed lines represent thermally limited regions Figure 14 Figure 15 CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY T T 2 2 x x S S o o o o 2 2 o o Right to Left Left to Right Left to Right Right to Left 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency Hz coti Frequency Hz Go12 Figure 16 Figure 17 16 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 f TONNE TAS5713 www ti com SLOS637 DECEMBER 2009 TYPICAL CHARACTERISTICS BTL CONFIGURATION 8 Q continued CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY e n B 2 x x S S o o o o 2 e O O Right to Left Right to Left Left to Right Left to Right 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency Hz Go 3 Frequency Hz Goia Figure 18 Figure 19 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s TAS5713 Id Ti TAS5713 ISSTRUMENIS SLOS637 DECEMBER 2009 www ti com TYPICAL CHARACTERISTICS BTL CONFIGURATION A O TOTAL HARMONIC DIST
38. QdAG aaAv Figure 51 Recommended Command Sequence Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 36 Product Folder Link s TAS5713 13 TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 AVDD DVDD 3V 0 Z SSS AX SPSS A 2 us PVDD T0420 05 Figure 52 Power Loss Sequence Initialization Sequence Use the following sequence to power up and initialize the device 1 Hold all digital inputs low and ramp up AVDD DVDD to at least 3 V 2 Initialize digital inputs and PVDD supply as follows e Drive RESET 0 PDN 1 and other digital inputs to their desired state while ensuring that all are never more than 2 5 V above AVDD DVDD Wait at least 100 us drive RESET 1 and wait at least another 13 5 ms e Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 us after AVDD DVDD reaches 3 V Then wait at least another 10 us Trim oscillator write 0x00 to register 0x1B and wait at least 50 ms Configure the DAP via I C see Users s Guide for typical values c RO Configure remaining registers 6 Exit shutdown sequence defined below Normal Operation The following are the only events supported during normal operation 1 Writes to master channel volume registers 2 Writes to soft mute register 3 Enter and exit shutdown sequence defined below Note Event 3 is not supported for 240 ms 1 3 x tsan after trim fol
39. S Gel eer ION 0x2B ch1_ba 2 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x2C ch1_ba 3 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x2D ch bq 4 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 Ox2E ch bq 5 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 Ox2F ch bale 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x30 ch2 bq 0 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x31 ch2_ba 1 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x32 ch2 bq 2 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x33 ch2 bq 3 20 u 31 26 b0 25 0 0x0080 0000 u 31
40. UNCTION 0 0 0 0 0 0 0 X Reserved mec 0 1 0 Set back end reset period to 299 ms 0 0 1 1 Set back end reset period to 449 ms 0 1 0 0 Set back end reset period to 598 ms 0 1 0 1 Set back end reset period to 748 ms 0 1 1 0 Set back end reset period to 898 ms 0 1 1 1 Set back end reset period to 1047 ms 1 0 0 0 Set back end reset period to 1197 ms 1 0 0 1 Set back end reset period to 1346 ms 1 0 1 X Set back end reset period to 1496 ms 1 1 X X Set back end reset period to 1496 ms 1 2 Copyright 2009 Texas Instruments Incorporated This register can be written only with a non reserved value Also this register can be written once after the reset Default values are in bold Submit Documentation Feedback Product Folder Link s TAS5713 53 TAS5713 SLOS637 DECEMBER 2009 INPUT MULTIPLEXER REGISTER 0x20 JA TEXAS INSTRUMENTS www ti com This register controls the modulation scheme AD or BD mode as well as the routing of S audio to the internal channels Table 20 Input Multiplexer Register 0x20 D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0
41. W 1 This data was taken using 1 oz 0 035 mm thick trace and copper pad that is soldered directly to a JEDEC standard high k PCB The thermal pad must be soldered to a thermal land on the printed circuit board See the PowerPad Thermally Enhanced Package application report SLMA002 for more information about using the HTQFP thermal pad RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Digital analog supply voltage DVDD AVDD 3 3 3 3 6 V Half bridge supply voltage PVDD_x 8 26 V Vin High level input voltage 5 V tolerant 2 V Vit Low level input voltage 5 V tolerant 0 8 V TA Operating ambient temperature range 0 85 C T 0 Operating junction temperature range 0 125 C RL BTL Load impedance Output filter L 15 pH C 680 nF 4 8 Q RL PBTL Load impedance Output filter L 15 pH C 680 nF 2 4 Q Lo BTL Output filter inductance o aad under 10 uH 1 Continuous operation above the recommended junction temperature may result in reduced reliability and or lifetime of the device PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS PARAMETER TEST CONDITIONS VALUE UNIT 11 025 22 05 44 1 kHz data rate 2 352 8 Output sample rate kHz 48 24 12 8 16 32 kHz data rate 2 384 8 Submit Documentation Feedback Product Folder Link s TAS5713 Copyright 2009 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com PLL INPUT PARAMETERS
42. at Figure 47 DRC Structure Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com BANK SWITCHING The TAS5713 uses an approach called bank switching together with automatic sample rate detection All processing features that must be changed for different sample rates are stored internally in three banks The user can program which sample rates map to each bank By default bank 1 is used in the 32 KHz mode bank 2 is used in the 44 1 48 KHz mode and bank 3 is used for all other rates Combined with the clock rate autodetection feature bank switching allows the TAS5713 to detect automatically a change in the input sample rate and switch to the appropriate bank without any MCU intervention An external controller configures bankable locations 0x29 0x36 0x3A 0x3F and 0x58 0x5F for all three banks during the initialization sequence If automatic bank switching is enabled register 0x50 bits 2 0 then the TAS5713 automatically swaps the coefficients for subsequent sample rate changes avoiding the need for any external controller intervention for a sample rate change By default bits 2 0 have the value 000 indicating that bank switching is disabled In that state updates to bankable locations take immediate effect A write to register 0x50 with bits 2 0 being 001 010 or 011 brings the system into the c
43. at 48 kHz 0 1 1 Volume slew 256 steps 21 ms volume ramp time at 48 kHz 1 X X Reserved 1 Copyright 2009 Texas Instruments Incorporated Default values are in bold Product Folder Link s TAS5713 Submit Documentation Feedback 49 TAS5713 SLOS637 DECEMBER 2009 MODULATION LIMIT REGISTER 0x10 JA TEXAS INSTRUMENTS www ti com Table 14 Modulation Limit Register 0x10 D7 D6 D5 D4 D3 D2 D1 DO MODULATION LIMIT 0 0 0 0 0 Reserved 0 0 0 99 2 0 0 1 98 4 0 1 0 97 7 0 1 1 96 9 1 0 0 96 1 1 0 1 95 3 1 1 0 94 5 1 1 1 93 8 INTERCHANNEL DELAY REGISTERS 0x11 0x12 0x13 and 0x14 Internal PWM Channels 1 2 1 and 2 are mapped into registers 0x11 0x12 0x13 and 0x14 Table 15 Channel Interchannel Delay Register Format BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 DO FUNCTION 0 0 0 0 0 0 Minimum absolute delay 0 DCLK cycles 0 1 1 1 1 1 Maximum positive delay 31 x 4 DCLK cycles 1 0 0 0 0 0 Maximum negative delay 32 x 4 DCLK cycles 0 0 Reserved SUBADDRESS D7 D6 D5 D4 D3 D2 D1 DO Delay value x 4 DCLKs 0x11 1 0 1 0 1 1 Default value for chann
44. cted in either half bridge There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating PWM output multiplexers should be updated to set the device in PBTL mode Output Mux Register 0x25 should be written with a value of 0x01 10 32 45 Also the PWM shutdown register 0x19 should be written with a value of Ox3A DEVICE PROTECTION SYSTEM Overcurrent OC Protection With Current Limiting The device has independent fast reacting current detectors on all high side and low side power stage FETs The detector outputs are closely monitored by two protection systems The first protection system controls the power stage in order to prevent the output current further increasing i e it performs a cycle by cycle current limiting function rather than prematurely shutting down during combinations of high level music transients and extreme 22 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 13 TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 speaker load impedance drops If the high current condition situation persists i e the power stage is being overloaded a second protection system triggers a latching shutdown resulting in the power stage being set in the high impedance Hi Z state The device returns to normal operation once the fault condition i e a short circuit on the output is removed Current limiting and o
45. d that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DLP Products www dlp com Communications and www ti com communications Telecom DSP dsp ti com Computers and www ti com computers Peripherals Clocks and Timers www ti com clocks Consumer Electronics www ti com consumer apps Interface interface ti com Energy www ti com energy Logic logic ti com Industrial www ti com industrial Power Mgmt power ti com Medical www ti com medical Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Space Avionics amp www ti com space avionics defense Defense RF IF and ZigBee Solutions www ti com lprf Video and Imaging www ti com video Wireless www ti com wireless apps Mailing Address Texas Instruments Po
46. egister 1 has several functions Bit D7 If 0 the dc blocking filter for each channel is disabled If 1 the dc blocking filter 3 dB cutoff lt 1 Hz for each channel is enabled default Bit D5 If 0 use soft unmute on recovery from a clock error This is a slow recovery Unmute takes the same time as the volume ramp defined in register OxOE If 1 use hard unmute on recovery from clock error default This is a fast recovery a single step volume ramp Bits D1 DO Select de emphasis Table 8 System Control Register 1 0x03 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION PWM high pass dc blocking disabled PWM high pass dc blocking enabled 1 Reserved 1 Soft unmute on recovery from clock error Hard unmute on recovery from clock error 1 Reserved 1 Reserved 1 Reserved No de emphasis 1 De emphasis for fg 32 kHz De emphasis for fg 44 1 kHz a 2lo e o o De emphasis for fs 48 kHz 1 Default values are in bold Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TAS5713 45 TAS5713 SLOS637 DECEMBER 2009 SERIAL DATA INTERFACE REGISTER 0x04 As shown in Table 9 the TAS5713 supports nine serial data modes The default is 24 bit IS mode JA TEXAS INSTRUMENTS www ti com Table 9 Serial Data
47. el 1 1 0x12 0 1 0 1 0 1 Default value for channel 2 1 0x13 1 0 1 0 1 1 Default value for channel 1 0x14 0 1 0 1 0 1 B Default value for channel 2 1 Default values are in bold ICD settings have high impact on audio performance e g dynamic range THD crosstalk etc Therefore appropriate ICD settings must be used By default the device has ICD settings for the AD mode If used in BD mode then update these registers before coming out of all channel shutdown MODE AD MODE BD MODE 0x11 AC B8 0x12 54 60 0x13 AC AO 0x14 54 48 50 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 lp TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 PWM SHUTDOWN GROUP REGISTER 0x19 Settings of this register determine which PWM channels are active The value should be 0x30 for BTL mode and Ox3A for PBTL mode The default value of this register is 0x30 The functionality of this register is tied to the state of bit D5 in the system control register This register defines which channels belong to the shutdown group SDG If a 1 is set in the shutdown group register that particular channel is not started following an exit out of all channel shutdown command if bit D5 is set to 0 in system control register 2 0x05 Table 16 Shutdown Group Register D7 D6 D5 D
48. el 2 1 Description shown in subsequent section 0x54 0x13 IC delay channel 3 1 Description shown in subsequent section OxAC 0x14 IC delay channel 4 1 Description shown in subsequent section 0x54 0x15 0x19 1 Reserved Ox1A Start stop period register 1 Ox0F 0x1B Oscillator trim register 1 0x82 0x1C BKND_ERR register 1 0x02 0x1D 0x1F 1 Reserved 0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772 0x21 Ch 4 source select register 4 Description shown in subsequent section 0x0000 4303 0x22 0x24 4 Reserved 0x25 PWM MUX register 4 Description shown in subsequent section 0x0102 1345 0x26 0x28 4 Reserved 0x29 ch1_bq 0 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 Ox2A ch1 bq 1 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 1 Reserved registers should not be accessed Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link s TAS5713 TAS5713 I TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com Table 4 Serial Control Interface Register Summary continued SUBADDRESS REGISTER NAME asa CONTENT
49. ht 2009 Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com it is for the right channel LRCLK is high for the left channel and low for the right channel A bit clock running at 32 48 or 64 x fs is used to clock in the data The first bit of data appears on the data 8 bit clock periods for 24 bit data after LRCLK toggles In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions The data is written MSB first and is valid on the rising edge of bit clock The DAP masks unused leading data bit positions 2 Channel Right Justified Sony Format Stereo Input E EE 3 Right Channel MUL UU UL Lu Lu Uy UY UL EX EENS T0034 03 Figure 38 Right Justified 64 fs Format 28 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 lp TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 2 Channel Right Justified Stereo Input 24 Bit Transfer Word Size TWrcre CE Right Channel Lf LU UUW UU LY LT LAT LT UU Ly UA Uy OUL T0092 03 Figure 39 Right Justified 48 f Format 2 Channel Right Justified Sony Format Stereo Input 4 16 Clks pd 16 Clks gt LRCLK Left Channel Right Channel SCLK SCLK MSB LSB MSB LSB 16 Bit Mode QS AEA ASA ASA2 MOMMA IKK
50. ing edge of bit clock The DAP masks unused trailing data bit positions 24 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 j TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 2 Channel CS Philips Format Stereo Input LROLK Note Reversed Phase Left Channel a Channel ui TEEN DO o9 a O BODO mm 1X 05 T0034 01 NOTE All data presented in 2s complement form with MSB first Figure 32 I S 64 f Format 2 Channel IS Philips Format Stereo Input Output 24 Bit Transfer Word Size LROLK Left Channel TTT I i INAIL O O T0092 01 NOTE All data presented in 2s complement form with MSB first Figure 33 l S 48 fs Format Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link s TAS5713 TEXAS INSTRUMENTS TAS5713 i SLOS637 DECEMBER 2009 www ti com 2 Channel IS Philips Format Stereo Input 16 Clks gt lt 16 Clks gt LRCLK Left Channel Right Channel SCLK SCLK di ELLI MSB MSB 16 Bit Mode D0000000400000000060000 00000 T0266 01 NOTE All data presented in 2s complement form with MSB first Figure 34 PS 32 fs Format Left Justified Left justified LJ timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel LRCLK is high for
51. ing free air temperature range unless otherwise noted 1 l TEXAS INSTRUMENTS www ti com VALUE UNIT DVDD AVDD 0 3 to 3 6 V Supply voltage PVDD_x 0 3 to 30 V 3 3 V digital input 0 5 to DVDD 0 5 V Input voltage 5 V tolerant digital input except MCLK 0 5 to DVDD 2 56 5 V tolerant MCLK input 0 5 to AVDD 2 5 OUT_x to PGND_x 320 V BST_x to PGND x 430 V Input clamp current lik 20 mA Output clamp current lox 20 mA Operating free air temperature 0 to 85 C Operating junction temperature range 0 to 150 C Storage temperature range Tsig 40 to 125 C 1 Stresses beyond those listed under absolute ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied Exposure to absolute maximum conditions for extended periods may affect device reliability 3 Maximum pin voltage should not exceed 6 V DISSIPATION RATINGS 5 V tolerant inputs are PDN RESET SCLK LRCLK MCLK SDIN SDA and SCL DC voltage peak ac waveform measured at the pin should be below the allowed limit for all conditions PACKAGE DERATING FACTOR Ta 25 C Ta 45 C Ta 70 C ABOVE Ta 25 C POWER RATING POWER RATING POWER RATING 7 mm x 7 mm HTQFP 40 mW C 5 W 42W 3 2
52. ink s TAS5713 I TEXAS INSTRUMENTS www ti com Table 4 Serial Control Interface Register Summary TAS5713 SLOS637 DECEMBER 2009 SUBADDRESS REGISTER NAME n CONTENTS eg lon A u indicates unused bits 0x00 Clock control register 1 Description shown in subsequent section 0x6C 0x01 Device ID register 1 Description shown in subsequent section 0x43 0x02 Error status register 1 Description shown in subsequent section 0x00 0x03 System control register 1 1 Description shown in subsequent section OxAO 0x04 Serial data interface 1 Description shown in subsequent section 0x05 register 0x05 System control register 2 1 Description shown in subsequent section 0x40 0x06 Soft mute register 1 Description shown in subsequent section 0x00 0x07 Master volume 1 Description shown in subsequent section OxFF mute 0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 0 dB 0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 0 dB 0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 0 dB OXOB OXOD 1 Reserved OxOE Volume configuration 1 Description shown in subsequent section 0x91 register OXOF 1 Reserved 0x10 Modulation limit register 1 Description shown in subsequent section 0x02 0x11 IC delay channel 1 1 Description shown in subsequent section OxAC 0x12 IC delay chann
53. ith an acknowledge bit after receiving each data byte Repeat Start Condition Start i Not Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge P Ee ALA A e DODO RK IPC Device Address and Subaddress IC Device Address and First Data Byte Other Data Bytes Last Data Byte Stop Read Write Bit Read Write Bit Condition T0036 04 Figure 45 Multiple Byte Read Transfer 32 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 Te MERE TAS5713 www ti com SLOS637 DECEMBER 2009 Dynamic Range Control DRC The DRC scheme has a single threshold offset and slope all programmable There is one ganged DRC for the high band left right channels and one DRC for the low band left right channels The DRC input output diagram is shown in Figure 46 1 1 Transfer Function Output Level dB Implemented Transfer Function T Input Level dB M0091 03 Professional quality dynamic range compression automatically adjusts volume to flatten volume level Each DRC has adjustable threshold levels Programmable energy attack and decay time constants Transparent compression compressors can attack fast enough to avoid apparent clipping before engaging and decay times can be set slow enough to avoid pumping Figure 46 Dynamic Range Control B0265 04 T 9 23 format all other DRC coefficients are 3 23 form
54. larity of the A SEL FAULT pin The TAS5713 address can be changed from 0x36 to 0x38 by writing 0x38 to device address register OxF9 Single and Multiple Byte Transfers The serial control interface supports both single byte and multiple byte read write operations for subaddresses 0x00 to Ox1F However for the subaddresses 0x20 to OxFF the serial control interface supports only multiple byte read write operations in multiples of 4 bytes During multiple byte read operations the DAP responds with data a byte at a time starting at the subaddress assigned as long as the master device continues to respond with acknowledges If a particular subaddress does not contain 32 bits the unused bits are read as logic O 30 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 lp TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 During multiple byte write operations the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress For example if a write command is received for a biquad subaddress the DAP must receive five 32 bit words If fewer than five 32 bit data words have been received when a stop command or another start command is received the received data is discarded Supplying a subaddress for each subaddress transaction is referred to as random I C addressing The TAS5713 also supports sequential DC add
55. lowing AVDD DVDD powerup ramp where tsta is specified by register 0x14 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Link s TAS5713 JA TEXAS TAS5713 INSTRUMENTS SLOS637 DECEMBER 2009 www ti com Shutdown Sequence Enter Write 0x40 to register 0x05 Wait at least 1 ms 1 3 x tstop where tsiop is specified by register 0x1A If desired reconfigure by returning to step 4 of initialization sequence Write 0x00 to register 0x05 exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD DVDD powerup ramp Wait at least 1 ms 1 3 x tstan where tstan is specified by register 0x14 Proceed with normal operation Power Down Sequence Use the following sequence to powerdown the device and its supplies 1 If time permits enter shutdown sequence defined above else in case of sudden power loss assert PDN 0 and wait at least 2 ms Assert RESET 0 Drive digital inputs low and ramp down PVDD supply as follows e Drive all digital inputs low after RESET has been low for at least 2 us e Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at least 2 us 4 Ramp down AVDD DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2 5 V below the digital inputs 38 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder L
56. n is signaled by the A_SEL_FAULT pin going low see Table 1 A latched version of this pin is available on D1 of register 0x02 This bit can be reset only by an I C write Table 1 A_SEL FAULT Output States A_SEL_FAULT DESCRIPTION 0 Overcurrent OC or undervoltage UVP error or overtemperature error OTE or overvoltage error 1 No faults normal operation SSTIMER FUNCTIONALITY The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all channel shutdown The capacitor on the SSTIMER pin is slowly charged through an internal current source and the charge time determines the rate at which the output transitions from a near zero duty cycle to the desired duty cycle This allows for a smooth transition that minimizes audible pops and clicks When the part is shut down the drivers are placed in the high impedance state and transition slowly down through a 3 KQ resistor similarly minimizing pops and clicks The shutdown transition time is independent of the SSTIMER pin capacitance Larger capacitors increase the start up time while capacitors smaller than 2 2 nF decrease the start up time The SSTIMER pin should be left floating for BD modulation CLOCK AUTODETECTION AND PLL The TAS5713 is an I S slave device It accepts MCLK SCLK and LRCLK The digital audio processor DAP supports all the sample rates and MCLK rates that are defined in the clock control
57. nk Switching Preload Coefficients for Different Sample Rates No Need to Write New Coefficients to the Part When Sample Rate Changes Autodetect Automatically Detects Sample Rate Changes No Need for External Microprocessor Intervention DESCRIPTION The TAS5713 is a 25 W efficient digital audio power amplifier for driving stereo bridge tied speakers One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders The device accepts a wide range of input data and data rates A fully programmable data path routes these channels to the internal speaker drivers The TAS5713 is a slave only device receiving all clocks from external sources The TAS5713 operates with a PWM carrier between a 384 kHz switching rate and a 352 KHz switching rate depending on the input sample rate Oversampling combined with a fourth order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz A Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PowerPad is a trademark of Texas Instruments PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production proce
58. nt energy storage even during minimal PWM duty cycles to keep the high side power stage FET LDMOS fully turned on during the remaining part of the PWM cycle Special attention should be paid to the power stage power supply this includes component selection PCB placement and routing As indicated each half bridge has independent power stage supply pins PVDD x For optimal electrical performance EMI compliance and system reliability it is important that each PVDD_x pin is decoupled with a 100 nF X7R ceramic capacitor placed as close as possible to each supply pin The TAS5713 is fully protected against erroneous power stage turnon due to parasitic gate charging PC CHIP SELECT A SEL FAULT is an input pin during power up It can be pulled high 15 kQ pullup or low 15 KO pulldown High indicates an TC subaddress of 0x36 and low a subaddress of 0x34 DC Device Address Change Procedure e Write to device address change enable register 0xF8 with a value of OXF9 A5 A5 A5 e Write to device register OXF9 with a value of 0x0000 00XX where XX is the new address Any writes after that should use the new device address XX SINGLE FILTER PBTL MODE The TAS5713 supports parallel BTL PBTL mode with OUT_A OUT_B and OUT_C OUT_D connected before the LC filter In order to put the part in PBTL configuration drive PBTL pin 8 HIGH This synchronizes the turnoff of half bridges A and B and similarly C D if an overcurrent condition is dete
59. oefficient bank update state update bank1 update bank2 or update bank3 respectively Any subsequent write to bankable locations updates the coefficient banks stored outside the DAP After updating all the three banks the system controller should issue a write to register 0x50 with bits 2 0 being 100 this changes the system state to automatic bank switching mode In automatic bank switching mode the TAS5713 automatically swaps banks based on the sample rate Command sequences for updating DAP coefficients can be summarized as follows 1 Bank switching disabled default DAP coefficient writes take immediate effect and are not influenced by subsequent sample rate changes OR Bank switching enabled a Update bank 1 mode Write 001 to bits 2 0 of register 0x50 Load the 32 kHz coefficients b Update bank 2 mode Write 010 to bits 2 0 of register 0x50 Load the 48 kHz coefficients c Update bank 3 mode Write 011 to bits 2 0 of register 0x50 Load the other coefficients d Enable automatic bank switching by writing 100 to bits 2 0 of reg 0x50 26 Bit 3 23 Number Format All mixer gain coefficients are 26 bit coefficients using a 3 23 number format Numbers formatted as 3 23 numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point This is shown in Figure 48 Sign Bit v v S_XX XXXX_XXXX_XXXX_XXXX_XXXX_XXX M0125 01 Figure 48 3 23 Format
60. ommand D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 32 kHz does not use bank 3 32 kHz uses bank 3 Reserved Reserved 44 1 48 kHz does not use bank 3 44 1 48 kHz uses bank 3 16 kHz does not use bank 3 16 kHz uses bank 3 22 025 24 kHz does not use bank 3 22 025 24 kHz uses bank 3 8 kHz does not use bank 3 8 kHz uses bank 3 11 025 kHz 12 does not use bank 3 11 025 12 kHz uses bank 3 D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 32 kHz does not use bank 2 32 kHz uses bank 2 Reserved Reserved 44 1 48 kHz does not use bank 2 44 1 48 kHz uses bank 2 16 kHz does not use bank 2 16 kHz uses bank 2 22 025 24 kHz does not use bank 2 22 025 24 kHz uses bank 2 8 kHz does not use bank 2 8 kHz uses bank 2 11 025 12 kHz does not use bank 2 11 025 12 kHz uses bank 2 D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 32 kHz does not use bank 1 32 kHz uses bank 1 Reserved Reserved 44 1 48 kHz does not use bank 1 44 1 48 kHz uses bank 1 16 kHz does not use bank 1 16 kHz uses bank 1 22 025 24 kHz does not use bank 1
61. owerPAD PLASTIC QUAD FLATPACK Thermal Pad See Note D X Gage Plane T IF Seating Plane ba 0 08 4146927 B 08 03 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com lt http www ti com gt E Falls within JEDEC MS 026 PowerPAD is a trademark of Texas Instruments da TEXAS INSTRUMENTS www ti com i THERMAL PAD MECHANICAL DATA INSTRUMENTS www ti com PHP S POFP G48 HERMAL INFORMATION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board PCB The thermal pad must be soldered directly to the PCB After soldering the PCB can be used as a heatsink In addition through the
62. product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids
63. put B PVDD_C 40 41 P Power supply input for half bridge output C PVDD_D 34 35 P Power supply input for half bridge output D RESET 25 DI 5 V Pullup Reset active low A system reset is generated by applying a logic low to this pin RESET is an asynchronous control signal that restores the DAP to its default conditions and places the PWM in the hard mute high impedance state SCL 24 DI 5 V IC serial control clock input SCLK 21 DI 5 V Pulldown Serial audio data clock shift clock SCLK is the serial audio port input data bit clock SDA 23 DIO 5 V C serial control data interface input output SDIN 22 DI 5 V Pulldown Serial audio data input SDIN supports three discrete stereo data formats SSTIMER 6 Al Controls ramp time of OUT_x to minimize pop Leave this pin floating for BD mode Requires capacitor of 2 2 nF to GND in AD mode The capacitor determines the ramp time STEST 26 DI Factory test pin Connect directly to DVSS VR_ANA 12 P Internally regulated 1 8 V analog supply voltage This pin must not be used to power external devices VR_DIG 18 P Internally regulated 1 8 V digital supply voltage This pin must not be used to power external devices VREG 31 P Digital regulator output Not to be used for powering external circuitry Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link s TAS5713 TAS5713 SLOS637 DECE MBER 2009 ABSOLUTE MAXIMUM RATINGS over operat
64. register The TAS5713 checks to verify that SCLK is a specific value of 32 fs 48 fs or 64 fs The DAP only supports a 1 x fs LRCLK The timing relationship of these clocks to SDIN is shown in subsequent sections The clock section uses MCLK or the internal oscillator clock when MCLK is unstable out of range or absent to produce the internal clock DCLK running at 512 times the PWM switching frequency The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s TAS5713 TAS5713 Ij TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com The TAS5713 has robust clock error handling that uses the built in trimmed oscillator clock to quickly detect changes errors Once the system detects a clock change error it mutes the audio through a single step mute and then forces PLL to limp using the internal oscillator as a reference clock Once the clocks are stable the system autodetects the new rate and revert to normal operation During this process the default volume is restored in a single step also called hard unmute The ramp process can be programmed to ramp back slowly also called soft unmute as defined in volume register OxOE SERIAL DATA INTERFACE Serial data is input on SDIN The PWM outputs are derived from SDIN The TAS5
65. ressing For write transactions if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow a sequential 1 C write transaction has taken place and the data for all 16 subaddresses is successfully received by the TAS5713 For I C sequential write transactions the subaddress then serves as the start address and the amount of data subsequently transmitted before a stop or start is transmitted determines how many subaddresses are written As was true for random addressing sequential addressing requires that a complete set of data be transmitted If only a partial set of data is written to the last subaddress the data for the last subaddress is discarded However all other data written is accepted only the incomplete data is discarded Single Byte Write As shown in Figure 42 a single byte data write transfer begins with the master device transmitting a start condition followed by the IC device address and the read write bit The read write bit determines the direction of the data transfer For a data write transfer the read write bit is a 0 After receiving the correct I C device address and the read write bit the DAP responds with an acknowledge bit Next the master transmits the address byte or bytes corresponding to the TAS5713 internal memory address being accessed After receiving the address byte the TAS5713 again responds with an acknowledge bit Next the master device transmits the data byte to be
66. rials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited info
67. rite followed by a read are actually done Initially a write is done to transfer the address byte or bytes of the internal memory address to be read As a result the read write bit becomes a 0 After receiving the TAS5713 address and the read write bit TAS5713 responds with an acknowledge bit In addition after sending the internal memory address byte or bytes the master device transmits another start condition followed by the TAS5713 address and the read write bit again This time the read write bit becomes a 1 indicating a read transfer After receiving the address and the read write bit the TAS5713 again responds with an acknowledge bit Next the TAS5713 transmits the data byte from the memory address being read After receiving the data byte the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer Repeat Start Start Condition Not Condition Acknowledge Acknowledge Acknowledge Acknowledge I I i OM PALI FAX PA OLIO CIO HAKONE W CA I I Ke Device Address and Subaddress Ke Device Address and Data Byte Stop Read Write Bit Read Write Bit Condition T0036 03 Figure 44 Single Byte Read Transfer Multiple Byte Read A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TAS5713 to the master device as shown in Figure 45 Except for the last data byte the master device responds w
68. rmation may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 20 Jul 2010 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Reel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness v Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPQ Reel Reel AO BO KO P1 W Pin1 Type Drawing Diameter Width mm mm mm mm mm Quadrant mm W1 mm TAS5713PHPR HTQFP PHP 48 1000 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 20 Jul 2010 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TAS5713PHPR HTQFP PHP 48 1000 346 0 346 0 33 0 Pack Materials Page 2 MECHANICAL DATA PHP S PQFP G48 P
69. ssing does not necessarily include testing of all parameters Copyright 2009 Texas Instruments Incorporated TAS5713 ip TEXAS INSTRUMENTS SLOS637 DECEMBER 2009 www ti com A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam ir a during storage or handling to prevent electrostatic damage to the MOS gates SIMPLIFIED APPLICATION DIAGRAM 3 3V 8 V 26 V AVDD DVDD Digital Audio Source ie Left Control Inputs Loop Filter PLL_FLTM B0264 10 1 See the TAS5713 User s Guide for loop filter values Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 li TEXAS INSTRUMENTS www ti com FUNCTIONAL VIEW SDIN Digital Audio Processor DAP MCLK Sample Rate SCLK Autodetect LRCLK and PLL SDA M Serial SCL Control Terminal Control Click and Pop Control Microcontroller Based System Control Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 TAS5713 SLOS637 DECEMBER 2009 Protection Logic B0262 06 Submit Documentation Feedback 3 TAS5713 SLOS637 DECEMBER 2009 JA TEXAS INSTRUMENTS www ti com E g E o Oo z z D Dx FAULT Under voltage Protection Protec
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71. st Undervoltage protection limit PVDD rising 7 6 V OTE Overtemperature error 150 C 3 Extra temperature drop o OTEuvsr required to recover from error 30 C OLPC Overload protection counter fpwm 384 kHz 0 63 ms loc Overcurrent limit protection 4 5 A loct Overcurrent response time 150 ns R Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap 3 KO PD the output of each half bridge capacitor charge 1 Ju for the PBTL pin has a maximum limit of 200 pA due to an internal pulldown on the pin 2 This does not include bond wire or pin resistance 3 Specified by design Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 Submit Documentation Feedback 9 TAS5713 SLOS637 DECEMBER 2009 AC Characteristics BTL PBTL PVDD x 18 V BTL AD mode fs 48 KHz R 8 Q Rocp 22 KO Cgsr 33 nF audio frequency 1 kHz AES17 filter fpwm 384 kHz TA 25 C unless otherwise specified All performance is in accordance with recommended operating conditions unless otherwise specified JA TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PVDD 18 V 10 THD 1 kHz input signal 21 5 PVDD 18 V 7 THD 1 kHz input signal 20 3 PVDD 12 V 10 THD 1 kHz input signal 9 6 PVDD 12 V 7 THD 1 kHz input signal 9 1 PVDD 8 V 10 THD 1 kHz input
72. tion X AGND and VO Logic x GND Protection sull x BST D x PVDD D d GVDD x PGND CD Regulator x GVDD_OUT x BST C x PVDD_C x PGND CD x BsT B x PVDD_B GVDD x PGND AB Regulator id x BST A x PVDD A x PGND AB B0034 06 Figure 1 Power Stage Functional Block Diagram Submit Documentation Feedback Product Folder Link s TAS5713 Copyright 2009 Texas Instruments Incorporated 13 TEXAS TAS5713 INSTRUMENTS www ti com SLOS637 DECEMBER 2009 DAP Process Structure PC Subaddress in Red B 0x72 e 2BQ We Q gt 0x71 DRC Ox46 0 n 0x74 v2im1 Vol2 2BQ 69 9 e Gi gt 5C 5D Fc 7 fc 56 0x75 VDISTB VDISTA Ld 2BQ BE 5F Vol DRC Ox46 1 5A 5B A B0321 09 Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link s TAS5713 TAS5713 SLOS637 DECEMBER 2009 PIN ASSIGNMENT OUT_A PVDD_A PVDD_A BST_A NC SSTIMER NC PBTL AVSS PLL_FLTM PGND_AB PGND_AB OUT_B DEVICE INFORMATION PHP Package Top View PVDD_B PVDD_B BST B BST C PVDD C PVDD C QUT C PGND CD PGND CD A ON o Om asa ON eo PLL FLTP VR ANA N AVDD II A_SEL_FAULT UI OUT_D
73. u LG Ade i I I SDA I Start Stop Condition Condition T0028 01 Figure 4 Start and Stop Conditions Timing 12 Submit Documentation Feedback Copyright 2009 Texas Instruments Incorporated Product Folder Link s TAS5713 Te Mee TAS5713 www ti com SLOS637 DECEMBER 2009 RESET TIMING RESET Control signal parameters over recommended operating conditions unless otherwise noted Please refer to Recommended Use Model section on usage of all terminals PARAMETER MIN TYP MAX UNIT tw RESET Pulse duration RESET active 100 us LSC ready Time to enable FC 12 0 m RESET I GE luREsET C Active C Active I HK lati2C ready bh System Initialization Enable via 1 C T0421 01 NOTES On power up it is recommended that the TAS5713 RESET be held LOW for at least 100 us after DVDD has reached 3 V If RESET is asserted LOW while PDN is LOW then RESET must continue to be held LOW for at least 100 ps after PDN is deasserted HIGH Figure 5 Reset Timing Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TAS5713 Id Ti TAS5713 KEE SLOS637 DECEMBER 2009 www ti com TYPICAL CHARACTERISTICS BTL CONFIGURATION 8 Q TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY 10 PVDD 8V PVDD 12V RL 80 RL 80 Ta 25 C Po
74. use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMA002 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMA004 Both documents are available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration 36 25 37 24 48 Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206329 8 K 10 08 LAND PATTERN H AJ DSO G48 PowerPAD Note D Pin Example Board Layout 0 127mm Thick Stencil Design E
75. vercurrent protection are not independent for half bridges That is if the bridge tied load between half bridges A and B causes an overcurrent fault half bridges A B C and D are shut down Overtemperature Protection The TAS5713 has an overtemperature protection system If the device junction temperature exceeds 150 C nominal the device is put into thermal shutdown resulting in all half bridge outputs being set in the high impedance Hi Z state and A_SEL FAULT being asserted low The TAS5713 recovers automatically once the temperature drops approximately 30 C Undervoltage Protection UVP and Power On Reset POR The UVP and POR circuits of the TAS5713 fully protect the device in any power up down and brownout situation While powering up the POR circuit resets the overload circuit OLP and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 7 6 V and 2 7 V respectively Although PVDD and AVDD are independently monitored a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half bridge outputs immediately being set in the high impedance Hi Z state and A_SEL_FAULT being asserted low FAULT INDICATION A_SEL_FAULT is an input pin during power up This pin can be programmed after RESET to be an output by writing 1 to bit 0 of I C register 0x05 In that mode the A_SEL_FAULT pin has the definition shown in Table 1 Any fault resulting in device shutdow
76. xample Via pattern and copper pad size Reference table below for other may vary depending on layout constraints solder pa ee ote E Sai haga 44x05 Via Keep Out ST Aa pe 44x0 5 0 4mm x 0 6mm EE 1 Y Non Solder Mask Defined Pad Example Solder Mask Opening Note F Center Power Pad Solder Stencil Opening Pad Geometry Note C NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Publication IPC 7351 is recommended for alternate designs D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 SLMA004 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents
77. y during the initialization phase CLOCK CONTROL REGISTER 0x00 The clocks and data rates are automatically determined by the TAS5713 The clock control register contains the autodetected clock status Bits D7 D5 reflect the sample rate Bits D4 D2 reflect the MCLK frequency Table 5 Clock Control Register 0x00 D N EI o D eo D4 D3 D2 D1 DO FUNCTION fg 32 kHz sample rate Reserved Reserved fs 44 1 48 kHz sample rate 2 fs 16 kHz sample rate fg 22 05 24 kHz sample rate fs 8 kHz sample rate i 0 0 00o nm 00 ICC OO Oo CH I I I I I fg 11 025 12 kHz sample rate MCLK frequency 64 x fg 9 MCLK frequency 128 x fg 9 MCLK frequency 192 x fg 4 MCLK frequency 256 x fs 2 5 MCLK frequency 384 x fs MCLK frequency 512 x fs Reserved I I I sl Al olololo lolo sl lolo HO O O Oo I I Reserved Reserved ER ES ERA ER EA Reserved Reserved registers should not be accessed Default values are in bold Only available for 44 1 kHz and 48 kHz rates Rate only available for 32 44 1 48 KHz sample rates Not available at 8 kHz GRANI Copyright 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TAS5713 43 TAS5713 Ij TEXAS INSTRUMENTS SLOS6

TEXAS TAS5713 ti.com SLOS637 DECEMBER 2009 25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

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