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TOSHIBA TMP87C874F TMP87CH74F handbook

1. seapd f y gt 135 18m 2 p EA y A8 1412 J83uno dn 314 91 62 5 3012 2 quawaunseaw 8 B U3DIA asind uid 121 S3ELNI 401281ep jeubis 5121 B d e 5 apow 1ndino Ddd o DLINI Qt o 4 44 5 2 55 U in i NAN uawasnseaw yapim asind 3 74 67 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 5 2 Control The timer counter 1 is controlled by a timer counter 1 control register TC1CR and two 16 bit timer registers TREG1A and TREG1B Reset does not affect TREG1A and TREG1B TREGIA 15 14 13 12 1 10 7 6 5 4 3 2 1 0 0010 00114 00114 TREG1A 00101 Write only onm TREG1B 0013 TREG1B 00123 Read Write Write available in only PPG output mode TCICR TCIM 00141 Initial value 0000 0000 timer external trigger timer event counter mode window mode mode select pulse width measurement mode PPG output mode 00 internal clock fc 2 fs 2 Hz TC1 01 internal clock 2 source clock select 10 internal clock fc 2 11 external clock TC1 pin input 00 stop amp counter clear TC1 01 command start start control 10 reserved 11 external trigger start software capture control 1 software capture trigger Note 3 pulse width measurement control
2. Address example SP 023 0238 SP Ww SP 023C PC 0230 PCH 22 PSW PSW PSW SP gt 023F At acceptance At execution At execution At execution of an ofaninterrupt gt of a push of a pop gt interrupt return Instruction Instruction Instruction General purpose registers save restore using data transfer instructions Data transfer instructions can be used to save only a specific general purpose register during processing of a single interrupt Example Saving restoring a register using data transfer instructions FINO S GSAVA Save A register interrupt processing Ib A x GSAVA Restore A register RETI Return from interrupt service The interrupt return instructions RETI RETN perform the following operations The contents of the program counter and the The contents of the program counter and program status word are restored from the program status word are restored from the stack stack The stack pointer is incremented 3 times The stack pointer is incremented 3 times The interrupt master enable flag is set to 1 3 The interrupt master enable flag is set to 1 only when a non maskable interrupt is accepted in interrupt enable status However the interrupt master enable flag remains at 0 when so clear by an interrupt service program Interrupt requests are sampled during the final cycle of the instruction
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4. cs Wb adm ynan asiou oBp3 lt N3OLNI C OLN LOMLNI ANSANI TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example 3 Tests an interrupt latch TEST IL 7 ifIL7 1 then jump JR F SSET 2 Interrupt Enable Register EIR The interrupt enable register EIR enables and disables the acceptance of interrupts except for the pseudo non maskable interrupts software and watchdog timer interrupts Pseudo non maskable interrupts are accepted regardless of the contents of the EIR however the pseudo non maskable interrupts cannot be nested more than once at the same time For example the watchdog timer interrupt is not accepted during the software interrupt service The EIR consists of an interrupt master enable flag IMF and the individual interrupt enable flags EF This register is assigned to addresses 003A 003By in the SFR can be read and written by an instruction including read modify write instructions such as bit manipulation instructions D Interrupt Master enable Flag IMF The interrupt master enable flag IMF enables and disables the acceptance of all interrupts except for pseudo non maskable interrupts Clearing this flag to 0 disables the acceptance of all maskable interrupts Setting to 1 enables the acceptance of interrupts When an interrupt is accepted this flag is cleared to 0 to temporarily disable the acceptance o
5. 1 Interrupt Enable TBT period A B D E F G Hs Time Base Timer Control Register a Configuration b Time Base Timer Interrupt Figure 2 14 Time Base Timer 3 74 64 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 TBTCR 2 3 1 0 00380 mes 8489 rere C 0550 0 Time base timer 0 Disable TBTEN Eg enable disable 1 Enable fc 223 fs 21 Hz fc 22 fs 2 fc 218 or fs 28 Time base timer interrupt fc 21 or 18 26 frequency select fc 23 or 5 25 fc 27 or 15 24 fe 2 16 23 fc 29 15 2 Note fc High frequency clock Hz fs Low frequency clock Hz don t care Figure 2 15 Time Base Timer and Divider Output Control Register Table 2 1 Time Base Timer Interrupt Frequency NORMAL1 2 IDLE1 2 mode Interrupt Frequency SLOW SLEEP mode DV7CK 1 At fc 8 MHz At fs 32 768 kHz 0 95 Hz 3 81 122 07 488 28 976 56 1953 12 3906 25 15625 3 74 65 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 4 Divider Output DVO A 50 duty pulse can be output using the divider output circuit which is useful for piezo electric buzzer drive Divider output is from pin P13 DVO The P13 output latch should be set to 1 and then the P13 should be configured as an output mode Divider output circuit is controlled by the control register TBTCR shown in Figure 2 12 7 6 5 4 3 2 1 0 e vem owa even
6. Twh m1 source TwH 1fsource td depends on a value set in 00244 NCS Figure 2 33 Example of remote control waveform by timer 3 in capture mode 3 74 80 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 8 8 bit Timer Counter 2 8 1 Configuration fc 21 or fs 23 overflow 27 1 fc 23 2 Timer F F 4 4 45 S A B Timer Counter 4 Control Register 98 bit Timer Register 4 TC4M 11 2 Multiplexer CMP Comparator INTTC4 TC4M interrupt Figure 2 34 Timer Counter 4 3 74 81 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 8 2 Control The timer counter 4 is controlled by a timer counter 4 control register TCACR and an 8 bit timer register TREG4 Reset does not affect TREG4 0013 Write only 2 0016 Initial value 0050 0000 00 Timer mode 01 Reserved 10 Programmable divider output PDO mode 11 Pulse width modulation PWM output mode TCA operating mode select 00 Internal clock fc 2 or fs 2 Hz 01 Internal clock 2 10 Internal clock fc 2 11 External clock TC4 pin input 1 0 Stop amp clear Tc4 Tc4 trol 00 Clear 01 Toggle 10 Set 11 Note3 TC4 source clock select Timer F F 4 control fc High frequency clock Hz fs Low frequency clock Hz don t care Set the operating mode the source clock selection the timer F F 4 control and the edge selection INT4ES when the
7. 4 5 to 5 5V 30 to 70 C In NORMAL1 2 modes In IDLE 1 2 modes 5 Machine Cycle Time In SLOW mode 117 6 133 3 In SLEEP mode High Level Clock Pulse Width For external clock operation Low Level Clock Pulse Width Ninput 8 MHz High Level Clock Pulse Width twsy For external clock operation Low Level Clock Pulse Width tws input fs 32 768 kHz Oscillation Frequency KYOCERA KBR8 0M Ceramic Resonator KYOCERA KBR4 0MS 30pF 4MHz PARAMETER Oscillator High frequency MURATA _ CSA oome CSA 4 00MG Oscillation 8MHz TOYOCOM 210B 8 0000 Crystal Oscillator 20pF 20pF 4MHz TOYOCOM 204B 4 0000 Low frequency Crystal Oscillator 32 768 KHz NDK MX 38T 15pF Oscillation XIN XOUT ee e 1 High frequency Oscillation 2 Low frequency Oscillation Note An electrical shield by metal shield plate on the surface of IC package should be recommendable in order to prevent the device from the high electric fieldstress applied from CRT Cathode Ray Tube for continuous reliable operation 3 74 131 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 3 74 132
8. 7 Start stop condition generation A start condition and the slave address and the direction bit written to the data buffer register are output on the bus by writing 1 to the MST TRX and BB when the BB bit 5 in SBICR2 is 0 It is necessary to set 1 to ACK beforehand SCL pin P Start slave address and the direction bit Acknowledge condition signal Figure 2 44 Start Condition Generation and Slave Address Generation 4 1 1 1 1 1 1 1 1 1 r 1 1 1 L 3 74 90 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 When the BB is 1 sequence of generating a stop condition is started by writeng 1 to the MST TRX and and 0 to the BB Do not modify the contents of MST TRX BB and PIN until a stop condition is generated on a bus Stop condition Figure 2 45 Stop Condition Generation The bus condition can be indicated by reading the contetns of the BB bit 5 in SBISR The BB is set to 1 when a start condition on a bus is detected and is cleared to 0 when a stop condition is detected 8 Interrupt service request cancel When a serial bus interface interrupt request INTSBI occurs the PIN bit 4 in SBISR is cleared to 0 During the timer that the PIN is 0 the SCL pin is pulled down to the low level The PIN is cleared to 0 when 1 word of data is transmitted or received Either writing reading data to from the SBIDBR sets the PIN to 1 The time from the PIN being set to
9. EIR 003A 003 SET EIRH 4 12 1 15 14 13 12 11 10 115 dL42 003Dy IL 003Cy Initial Value 00000000 000000 EF45 EF14 EF43 EF12 EF44 EF40 EFg EIRy 003 EIR 003Ay Initial Value 00000000 0000 0 Note 1 Do not use any read modify write instruction such as bit manipulation for clearing IL Note 2 Do not dear IL to 0 by an instruction Note 3 Do not set IMF to 1 during non maskable interrupt service program Figure 1 23 Interrupt Latch IL and Interrupt Enable Register EIR 3 74 30 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 9 1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an instruction Interrupt acceptance sequence requires 8 machine cycles 4 us at fc 8 MHz in the NORMAL mode after the completion of the current instruction execution The interrupt service task terminates upon execution of an interrupt return instruction RETI for maskable interrupts or RETN for pseudo non maskable interrupts 1 Interrupt acceptance processing is as follows D The interrupt master enable flag IMF is cleared to 0 to temporarily disable the acceptance of any following maskable interrupts When a non maskable interrupt is accepted the acceptance of any following interrupts is temporarily disabled The interrupt latch IL for
10. command start TC1 pininput Internal clock Up counter 1 counter INTTC1 interrupt clear b Negative Logic INT3ES 1 Figure 2 23 Window Mode Timing Chart 5 Pulse width measurement mode Counting is started by the external trigger set to external trigger start by TC1S The trigger can be selected either the rising or falling edge of the TC1 pin input The source clock is used an internal clock On the next falling rising edge the counter contents are transferred to TREG1B and an INTTC1 interrupt is generated The counter is cleared when the single edge capture mode is set When double edge capture is set the counter continues and at the next rising falling edge the counter contents are again transferred to TREG1B If a falling rising edge capture value is required it is necessary to read out TREG1B contents until a rising falling edge is detected Falling or rising edge is selected with INT3ES and single edge or double edge is selected with MCAP1 bit 6 in TC1CR 3 74 71 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 count start TC1 pin input INT3ES 0 Internal clock Up counter Applications High or low pulse width measurement a Single Edge Capture TC1 pininput Internal clock Up counter TREG1B INTTC1 Applications D Period Frequency measurement 2 Duty measurement b Double Edge Capture Figure 2 24 Pulse Width Measurement Mode Timing Cha
11. don t care Edge detection during switching edge selection is invalid Do not change EINTCR only when IMF 0 After changing EINTCR interrupt latches of external interrupt inputs must be cleared to 0 using load instruction In order to change of external interrupt input by rewriting the contents of INT2ES and INT3ES INT4ES during NORMAL1 2 mode clear interrupt latches of external interrupt inputs INT2 and INT3 1 after 8 machine cycles from the time of rewriting During SLOW mode 3 machine cycles required In order to change an edge of timer counter input by rewriting the contents of INT2ES and INT3ES INT4ES during NORMAL1 2 mode rewrite the contents after timer counter is stopped TC s 0 that is interrupt disable state Then clear interrupt laches of external interrupt inputs INT2 and INT3 after 8 machine cycles from the time of rewriting to change to interrupt enable state Finally state timer counter During SLOW mode 3 machine cycles are required Example When changing TC1 pin inputs edge in external trigger timer mode from rising edge to falling edge LD TCICR 01001000B TC1S lt 00 stop TC1 DI IMF lt 0 disable interrupt service LD EINTCR 00000100B INT2ES lt 1 change edge selection 8 machine cycles LD ILL 01111111B 107 lt 0 clear interrupt latch EI IMF lt 1 enable interrupt service LD TCICR 01111000B TC1S 11 start TC1 If changing the contents of INTTES during NORMAL 1
12. external trigger timer control 1 double edge capture 1 single edge capture 0 trigger start 1 trigger start amp stop PPG output control 0 continuous pulse 1 single pulse timer F F1 control for PPG output mode Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note2 Writing to the low byte of the timer registers TREGTA TREG1B the comparison is inhibited until the high byte TREG1By is written 3 Set the mode source clock edge INT2ES PPG control and timer F F control when TC1 stops TC1S 00 Note4 Software capture can be used in only timer and event counter modes Note 5 Values to be loaded to timer registers must satisfy the following condition TREG1A gt TREG1B gt 0 PPG output mode gt 0 others Note6 Always write 0 to TFF1 except the PPG output mode Note7 TCICR is a write only register which cannot be accessed by any read modify write instruction such as bit operate etc Note8 TREG1B cannot be written after setting to PPG output mode Figure 2 19 Timer Registers and TC1 Control Register 2 5 3 Function Timer counter 1 has six operating modes timer external trigger timer event counter window pulse width measurement programmable pulse generator output mode 1 Timer Mode In this mode counting up is performed using the internal clock The contents of TREG1A are compared with the contents of up counter If a
13. 1 until the SCL pin is released takes ow In the address recognition mode ALS 0 the PIN is cleared to 0 when the received slave address is the same as the value set at the I2CAR or when a GENERAL CALL is received all 8 bit data are 0 after a start condition Although the PIN bit 4 in SBICR2 can be set to 1 by the program the PIN is not set to 0 when 0 is written 9 Serial bus interface operating mode The SBIM bits 3 2 in SBICR2 is used to specify the serial bus interface operation mode Set the SBIM to 10 when used in the I2C bus mode Switch a mode to port after making sure that a bus is free 10 Arbitration lost detection monitor Attached ADDITIONAL INFORMATION showed in SECTION 8 describe more detail and some notice for usage of I2C Bus Please read carefully it if you are going to use I2C Bus function in your application system Since more than one master device can exist simultaneously on a bus in the I2C bus mode a bus arbitration procedure is implemented in order to guarantee the contents of transferred data Data on the SDA line is used for bus arbitration of the I2C bus The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus Master 1 and Master 2 output the same data until point a After Master 1 outputs 1 and Master 2 0 the SDA line of the bus is wired AND and the SDA line is pulled down to the low level by Master 2 When the SCL li
14. KOK e X e Aes As A AdoA da A da A ds A de INTSBI interrupt _ request SBIDBR __________ __________ Write transmitted Read received Write transmitted Read received data a data c data b data d Figure 2 61 Transmit Receive Mode Example Internal clock 3 74 104 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 SCK pin SIOF bit gt Min 4 fc s n NORMAL mode IDLE mode Figure 2 62 Transmitted Data Hold Time at End of Transmit Receive 3 74 105 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 10 Serial Interface SIO1 SIO2 The 87C874 H74 each have clocked synchronous 8 bit serial interface 5101 Each serial interface has an 8 byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data The serial interfaces are connected to external devices via pins P02 SO 1 P01 511 POO SCK1 for 5101 The serial interface pins are also used as port PQ When used as serial interface pins the output latches of these pins should be set to 1 In the transmit mode pins 1 be used as normal I O ports and in the receive mode the pins P02 can be used as normal I O ports 2 10 1 Configuration SIO control status registers SIOCR1 SIO1SR SIO1CR2 Transmit and receive data buffer 8 bytes in DBR SO pin Serial data output 8 bit transfer 4 bit transfer SI pin Serial data input INTSI
15. stops TC4S 0 TFF4 must be set to 11 in the timer and event counter modes Values to be loaded to the timer register must satisfy the following condition TREG4 gt 0 and TREG4 are write only registers and must not be used with of read modify write instructions Figure 2 35 Timer Register 4 and TC4 Control Register 2 8 3 Function The timer counter 4 has four operating modes timer event counter programmable divider output and PWM output mode 1 Timer Mode In this mode the internal clock is used for counting up The contents of TREG4 are compared with the contents of up counter If a match is found a timer counter 4 interrupt INTTC4 is generated and the up counter is cleared to 0 Counting up resumes after the up counter is cleared Table 2 6 Source Clock Internal Clock for Timer Counter 4 Maximini senina dine NORMAL 2 IDLE1 2 mode SLOW SLEEP mode _ DV7CK 0 DV7CK 1 fc 8 MHz fs 32 768 kHz fc 8 MHz fs 32 768 kHz fc 2 Hz fs 2 Hz 15 22 Hz 256 ys 244 14 ys 62 2 ms fc 27 16 ps 23 1216 5 3 74 82 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 Programmable Divider Output PDO Mode The internal clock is used for counting up The contents of TREGA are compared with the contents of the up counter Timer F F 4 output is toggled and the counter is cleared each time a match is found Timer F F 4 output is inverted and output to the PDO P44 pin This
16. 0 Output latches of I O ports Interrupt individual enable flags EF 0 Refer of o 1 11 1 External Reset Input When the RESET pin is held at low for at least 3 machine cycles 12 fc s with the power supply voltage within the operating voltage range and oscillation VDD stable a reset is applied and the internal state is typ 220 kQ initialized When the RESET pin input goes high the reset operation is released and the program execution starts at the vector address stored at addresses FFFFy The RESET pin contains a Schmitt trigger hysteresis Figure 1 30 Simple Power on with an internal pull up resistor A simple power on Reset Circuitry reset can be applied by connecting an external capacitor and a diode Interrupt latches IL 1 11 2 Address Trap Reset If a CPU malfunction occurs and an attempt is made to fetch an instruction from the RAM or the SFR area addresses 87C874 H74 0040 023 an address trap reset will be generated Then the RESET output will go low The reset time is 12 fc s 1 5 us at 8 MHz Instruction resetrelease instruction at address execution Address trap is occurred RESET output L output K 1 12 fc s Note 1 OS 023 Note2 During reset release reset vector is read out and an instruction at address is fetched and decoded Figure 1 31 Address Trap Reset 1 11 3 Watchdog Timer Reset Refer to Section 1 10 Wat
17. Jejuno ysanbau wayshs aseajay EWJON D gt Z e sSouppe uononasu uonn exe uononansu Je1uno2 ysanbau 1dnujeiu op 15 5 sseJppe 13 99 ejduiex3 14616 epojyu ejeJedo uonnoexe V CHDSAS 135 ysanba 1 op 1545 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 3 SLOW mode SLOW mode is controlled by the system control register 2 and the timer counter 2 a Switching from NORMAL2 mode to SLOW mode First set SYSCK bit 5 in SYSCR2 to switch the main system clock to the low frequency clock Next clear XEN bit 7 in SYSCR2 to turn off high frequency oscillation Note The high frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly Always turn off oscillation of high frequency clock when switching from SLOW mode to STOP mode When the low frequency clock oscillation is unstable wait until oscillation stabilizes before performing the above operations The timer counter 2 TC2 can conveniently be used to confirm that low frequency clock oscillation has stabilized Example1 Switching from NORMAL2 mode SLOW mode SET SYSCR2 5 SYSCK lt 1 Switch
18. TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 8 4 Operating Mode Control 1 STOP mode STOP1 STOP2 STOP mode is controlled by the system control register 1 SYSCR1 and the STOP pin input The STOP pin is also used both as a port P20 and an INT5 external interrupt input 5 pin STOP mode is started by setting STOP bit 7 in SYSCR1 to 1 During STOP mode the following status is maintained D Oscillations are turned off and all internal operations are halted The data memory registers and port output latches are all held in the status in effect before STOP mode was entered The port output can be select either output hold or high impedance by setting OUTEN bit 4 in SYSCR1 The divider of the timing generator is cleared to 0 The program counter holds the address of the instruction following the instruction which started STOP mode STOP mode includes a level sensitive release mode and an edge sensitive release mode either of which can be selected with RELM bit 6 in SYSCR1 a Level sensitive release mode RELM 1 In this mode STOP mode is released by setting the STOP pin high This mode is used for capacitor back up when the main power supply is cut off and for long term battery back up When the STOP pin input is high executing an instruction which starts the STOP mode will not place in the STOP mode but instead will immediately start the release sequence warm up Thus to start the STOP mode in the level sensitive re
19. Timer counter 2 011 f c 23 source clock select 100 fc Note 5 101 fs 110 Reserved 111 External clock TC2 pin input Timer counter 2 0 Stop and counter clear 25 start control 1 Start fc High frequency clock Hz fs Low frequency clock Hz don t care When writing to the low byte of timer register 2 TREG2 the comparison is inhibited until the high byte TREG2 is written After writing to the high byte any match during 1 machine cycle instruction execution cycle is ignored Set the mode and source clock when timer counter stops 25 0 Valuesto be loaded to the timer register must satisfy the following condition TREG2 gt O TREG2 5 gt 0 when warm up fc can be selected as the source clock only in the timer mode during the SLOW mode Always write 0 to bit 0 in TC2CR TC2CR and TREG2 are write only registers and must not be used with any of the read modify write instructions Figure 2 28 Timer Register 2 and TC2 Control Register 2 6 3 Function The timer counter 2 has three operating modes timer event counter and window modes Also timer counter 2 is used for warm up when switching from SLOW mode to NORMAL2 mode 1 Timer Mode In this mode the internal clock is used for counting up The contents of TREG2 are compared with the contents of up counter If a match is found a timer counter 2 interrupt INTTC2 is generated and the counter is cleared Counting up is resumed afte
20. When the LRB is 1 a receiver does not request data Implement the process to generate a stop condition and terminate data transfer When the LRB is 0 the receiver requests new data When the next transmitted data is other than 8 bits set the BC and write the transmitted data to the SBIDBR After writing the data the PIN becomes 1 a serial clock pulse is generated for transferring a new 1 word of data from the SCL pin and then the 1 word data is transmitted After the data is transmitted an INTSBI interrupt request occurs The PIN becomes 0 and the SCL pin is pulled down to the low level If the data to be transferred is more than one word in length repeat the procedure from the LRB checking above 3 74 94 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Write to SBIDBR SCL pin SDA pin Acknowledge signal PIN from receiver INTSBI 4 interrupt request Figure 2 49 Example when BC 000 ACK 2 1 When the is 0 Receiver mode When the next transmitted data is other than 8 bits set the BC again Set the ACK to 1 and read the received data from the SBIDBR data which is read immediately after a slave address is sent is undefined After the data is read the PIN becomes 1 The 87C874 H74 outputs a serial clock pulse to the SCL to transfer new 1 word of data and sets the SDA pin to 0 at the acknowledge signal timing An INTSBI interrupt request occurs and the PIN becomes 0 Then
21. and a display control circuit used to automatically transfer display data to the output port The segment and the digit as it is the VFT drive circuit which included in the usual products are not allocated The segment and the digit can be freely allocated in the timing TO to T15 which is specified according to the display tube types and the layout 2 12 1 1 2 3 4 5 6 2 12 2 Functions 37 high breakdown voltage output buffers built in Large current output pin typ 20mA 16 0 to V15 Middle current output typ 8mA 21 V16 to V36 There is also the VKK pin used for the VFT drive power supply The dynamic lighting system makes it possible to select 1 to 16 digits TO to T15 by program Pins not used for VFT driver can be used as general purpose ports Pinscan be selected using the VSEL bits 4 to 0 in control register1 bit by bit Display data 80 bytes in DBR are automatically transferred to the VFT output pin Brightness level can be adjusted in 8 steps using the dimmer function Four types fc 212 to fc 29 of display time can be selected Configuration Internal bus Display data memory 80 bytes in DBR Output data latch High breakdown voltage output V34 V35 V36 Figure 2 51 3 74 118 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 12 3 Control The VFT driver circuit is controlled by the VFT control registers VFTCR1 VFTCR2 Reading VFTSR determines the VFT oper
22. gero Citial value Oro 0 0036 DVOCK TBTCK DVOEN Divider output enable disable a Disable Enable fc 2 or fs 25 Hz Divider output DVO a fc 2 or f5 24 frequency selection 10 fc 2 or fs 2 11 fe 219 46 22 Note fc High frequency clock Hz fs Low frequency clock Hz don tcare Figure 2 16 Divider Output Control Register Example 1kHz pulse output at fc 8 MHz SET P1 3 P13 output latch 1 LD P1CR 00001000B Configures P13 as an output mode LD TBTCR 10000000B DVOEN 1 DVOCK 00 Table 2 2 Frequency of Divider Output DVOCK Frequency of Atfc 8 MHz 32 768 kHz Divider Output fs 2 0 976 kHz 1 024 kHz fs 2 1 953 2 048 1 23 3 906 4 096 fs 2 7 812 8 192 output latch output enable data output fc 213 or fs 25 fc 212 or fs 24 fc 211 fs 23 P13 output latch fc 210 or fs 22 DVOEN Divider output control register a Configuration b Timing Chart Figure 2 17 Divider Output 3 74 66 TMP87C874 H74 UNDER DEVELOPMENT TOSHIBA 193uno 18ull 781 6 841614 990435 934 815341 WLOSML My LOU 40304edUJO BION Y Y 48358521 10414603 ig1unoo jault 1923002 1331 14925 vi53ul 815381 4212 12818p ayqeus 81 vi S4aysiBas 319 91 32121
23. section 2 12 6 Port Function The output latches initialized to 0 during reset When a read instruction for port PD is executed bit 7 to 5 in PD read in as undefined data TEST STOP OUTEN control Data input Data output VFT driver output Outputlatch control VFT driver output 1 4100 don t PD4 PD3 PD2 PD1 PDO A 001Dy V36 V35 V34 V33 V32 Initial value 0 0000 Figure 2 13 PD PE PF Ports 3 74 63 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 3 Time Base Timer TBT The time base timer generates time base for key scanning dynamic displaying etc It also provides a time base timer interrupt INTTBT The time base timer is controlled by the control register TBTCR shown in Figure 2 15 An INTTBT is generated on the first rising edge of source clock the divider output of the timing generator after the time base timer has been enabled The divider is not cleared by the program therefore only the first interrupt may be generated ahead of the set interrupt period The interrupt frequency TBTCK must be selected with the time base timer disabled both frequency selection and enabling can be performed simultaneously Example Setsthe time base timer frequency to fc 216 Hz and enables an INTTBT interrupt LD TBTCR 00001010B SET EIRL 6 INTTBT interrupt request edge Source clock detector TBTEN ME INTTBT
24. starting from the least significant bit LSB When the data is transferred to the shift register the SBIDBR becomes empty The INTSBI buffer empty interrupt request is generated to request new data When the internal clock is used the serial clock will stop and automatic wait function will be initiated if new data is not loaded to the data buffer register after the specified 8 bit data is transmitted When new data is written automatic wait function is canceled When the external clock is used data should be written to the SBIDBR before new data is shifted The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the SBIDBR by the interrupt service program When the transmit is started after the SIOF goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK Transmitting data is ended by cleaning the SIOS to 0 by the buffer empty interrupt service program or setting the SIOINH to 1 When the SIOS is cleared the transmitted mode ends when all data is output In order to confirm if data is surely transmitted by the program set the SIOF bit 3 in the SBISR to be sensed The SIOF is cleared to 0 when transmitting is complete When the SIOINH is set transmitting data stops The SIOF turns 07 When the external clock is used it is also necessary to clear the SIOS to 0 before new data is shifted otherwise
25. 0 PortPD VFT output and usual input output are controlled by VSEL of VFT control register in bits When a pin which is pulled down to pin is used as usual output or input the following cautions are required When outputting When level L is output a port which is pulled down to pin is voltage Such processes as clamping with the diode as shown in figure 2 86 a are necessary to prevent pin voltage applying to the external circuit b When inputting When the external data is input the port output latch is cleared to 07 The input threshold is the same as that of the other usual input output port However it is necessary to drive RK typ 80 kQ sufficiently because of pulled down to pin VKK Atoutput b Atinput Figure 2 86 External Circuit Interface 3 74 124 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 INPUT OUTPUT CIRCUITRY 1 Control pins The input output circuitries of the 87C874 H74 control pins are shown below Please specify either the single clock mode oscillation only XIN XOUT or the dual clock mode oscillation both XIN XOUT and XTIN XTOUT by a code NM1 or NM2 as an option for an operating mode during reset CONTROL PIN INPUT OUTPUT CIRCUITRY and code REMARKS Osc enable Resonator connecting pins high frequency XIN NPP Re 12MQ XOUT Ro 1 5 typ Osc enable Resonator connecting pins low frequency XTIN Re 6MQ typ XTOUT Ro 220kQ
26. 0 cannot be disabled by the EF therefore if disablement is necessary either the external interrupt function of the INTO pin must be disabled with the INTOEN in the external interrupt control register EINTCR or interrupt processing must be avoided by the program FFF2y 3 74 31 TOSHIBA UNDER DEVELOPMENT 87 874 74 Example 1 Disables an external interrupt 0 using INTOEN LD EINTCR 000000008 0 Example 2 Disables the processing of external interrupt 0 under the software control using bit 0 at address 00 0 as the interrupt processing disable switch PINTO TEST OOFOH 0 Return without interrupt processing if 00F0p o 1 JRS T SINTO RETI SINTO Interrupt processing RETI VINTO DW PINTO 2 General purpose registers save restore processing During interrupt acceptance processing the program counter and the program status word are automatically saved on the stack but not the accumulator and other registers These registers are saved by the program if necessary Also when nesting multiple interrupt services it is necessary to avoid using the same data memory area for saving registers The following method is used to save restore the general purpose registers D General purpose register save restore by register bank changeover The general purpose registers can be saved at high speed by switching to a register bank thatis not in use Normally bank 0 is used for the main task and
27. 244 Note 1K bit 1024 bit 3 74 108 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 automatically wait function 7 gt spese LE LE LI LLL UU UT LU SO1 pin output Written transmit data to the DBR Figure 2 66 Clock Source Internal Clock External Clock An external clock connected to the SCK1 pin is used as the serial clock In this case the SCK1 output latch must be set to 1 To ensure shifting a pulse width of at least 4 machine cycles is required Thus the maximum transfer speed is 244K bit s at fc 8 MHz SCK pin input tsckL tsckH tsckH gt 4 tcyc Note tcyc 4 fc In NORAML1 2 IDLE1 2 modes 4 fs In SLOW SLEEP modes b Shift edge The leading edge is used to transmit and the trailing edge is used to receive Leading Edge Transmitted data are shifted on the leading edge of the serial clock falling edge of the SCK1 pin input output Trailing Edge Received data are shifted on the trailing edge of the serial clock rising edge of the SCK1 pin input output SCK1 pin Shift register iig a Leading Edge Shift register dris pet Gee 2103 3210 Mv Note don tcare b Trailing Edge Figure 2 67 Shift Edge 2 Number of Bits to Transfer Either 4 bit or 8 bit serial transfer can be selected When 4 bit serial transfer is selected only the lower 4 bits of the transmit receive data buffer register are used The upper 4 bi
28. 55 iH eem os es Note Clock frequency fc Supply voltage range is specified in NORMAL 1 2 mode and IDLE 1 2 mode 3 74 128 TOSHIBA UNDER DEVELOPMENT 87 874 74 How to calculate power consumption With the TMP87C874 H74 a pull down resistor Rk 80 kQ typ can be built into a VFT driver using mask option The share of VFT driver loss VFT driver output loss pull down resistor Rk loss in power consumption Pmax is high When using a fluorescent display tube with a large number of segments the maximum power consumption Pd must not be exceeded power consumption Pmax operating power consumption normal output port loss VFT driver loss Where operating power consumption VDDxIDD LED output loss lot3 Xx VoL VFT driver loss driver output loss pull down resistor Rk loss Example When Ta 10 to 50 C When using a fluorescent display tube with a conventional type and a fluorescent display tube with segment output 3 digit output 15 25 V is used Operating conditions VDD 5V t 10 fc 8 MHz dimmer time DIM 14 16 x tseg Power consumption Pmax 1 2 3 Where 1 Operating power consumption VppX Ipp 5 5 16 88 mW 2 LED output 10mAx 1 0 V x 4 40 mW when using four LED 3 VFT driver loss segmentpin 3 mA x 2 V x number of segments X 6mW x X digit pin 15 2 14 16 DIM 26 25 mW Rk lo
29. 74 52 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Address 0 80 Do not access reserved areas by the program Cannot be accessed Display date buffer When defining address 003F with assembler symbols use GPSW and GRBS Write only registers and interrupt latches cannot use the read modify write instructions bit manipulation instructions such as SET CLR etc and logical operation instructions such as reserved AND OR etc Transmit and receive data buffer b Data Buffer Registers Figure 2 1 b SFR amp DBR 2 2 OPorts The 87C874 H74 each have 13 parallel input output ports 89pins each as follows SR Primary Function Secondary Functions 8 bit I O port Serial port input output Port P1 8 bit I O port External interrupt input timer counter input and divider output Port P2 3 bit I O port Low frequency resonator connections external interrupt input and STOP mode release signal input Port P3 4 bit I O port Serial bus interface 3 74 53 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Ports PO P1 P2 P3 P4 P5 P6 P7 P8 P9 and PD can also use secondary function Each output port contains a latch which holds the output data Input ports excluding P4 do not have latches so the external input data should either be held externally until read or reading should be performed several times before processing Figure 2 2 shows input output timing examples External data is read from an port in the
30. A DEC BC JRS F SRAMCLR 3 74 8 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Address 0 00404 Register bank 0 or Register bank 1 0050 Registerbank2 Register bank 3 0060 Registerbank4 _ Registerbank5 0070 Registerbank6 Register bank 7 0080 _ Register bank 8 Register bank 9 Direct addressing area 0090 Registerbank10 Register bank 11 00A0 Registerbank12 Register bank 13 00 0 Register bank 14 Register bank 15 a oe ee 00DO 00 0 00 0 0100 0110 0120 0130 0140 0230 Figure 1 4 Data Memory 3 74 9 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 5 General purpose Register Banks The general purpose registers are mapped into addresses 0040 0 the data memory as shown Figure 1 4 There are 16 register banks and each bank contains eight 8 bit registers W A B C D E H and L Figure 1 5 shows the general purpose register bank configuration bank 13 00A8 to bank 12 00A0 to 00 7 bank 4 0060 to 0067 bank 3 0058 to 005 bank 2 0050 to 0057 H L bank 1 0048 to 004 0047 00461 bank 0 0040 to 00474 Configuration b Address assignments of registers Figure 1 5 General purpose Register Banks In addition to access in 8 bit units the registers can also be accessed in 16 bit units as the register pairs WA BC DE and HL Besides its function as a
31. Acknowledge mode specification Writ 1 returned to transmitter rite SWRST Initiate a internal of SBI 1 initialized Clearing 0 after initialized rite 181 8 kHz 105 3 kHz 57 1 kHz 29 9kHz 8 MHz OutputonSCLpin Write Serial clock selection 15 3kHz only 7 72 kHz 3 88kHz reserved fc High frequency clock Hz don t care Set the BC to 000 before switching to 8 bit SIO bus mode SBICRI is write only registers which cannot any of in read modify write instruction such as bit operate etc Serial Bus Interface Data Buffer Register SBIDBR 7 6 5 4 00214 Read Write For writing transmitted data start from the MSB bit 7 Cannot read the data which was written into SBIDBR since a write data buffer and a read data buffer are independent in SBIDBR Therefore cannot access it any of in read modify write instructions such as bit operate etc 2 bus Address Register 7 6 5 4 3 1 0 I2CAR Slave address 87C874 H74 slave address selection Address recognition mode 0 Slave address recognition rite ALS PDDE ix only specification 1 Non slave address recognition Note I2CARis write only register which cannot access any of in read modify write instruction such as bit operate etc Figure 2 40 Serial Bus Interface Control Register 1 Serial Bus Interface Data Buffer Register and I2C Bus Address Register In The I2C Bus Mode 3 74 87 TOSHIBA UNDER
32. An analog input voltage is sampled at intervals of four cycles after starting A D conversion 2 Reading of A D conversion result After the end of conversion read the conversion result from the ADCDR The EOCF is automatically cleared to 0 when reading the ADCDR Undefined value is read in A D conversion 3 74 116 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 3 A D conversion in STOP mode When the MCU places in the STOP mode during the A D conversion the conversion is terminated and the ADCDR contents become indefinite After returning from STOP mode EOCF is kept to be cleared to 0 However if the STOP mode is started after the end of conversion 1 the ADCDR contents are held conversion time conversion time 184 fc s 184 fc s p _ ESTEE AA A A A read start read start start Figure 2 77 A D Conversion Timing Chart Example AIN SELECT LD ADCCR 00100100B Selects AINA A D CONVERT START SET ADCCR 6 ADS 1 SLOOP TEST ADCCR 7 1 JRS T SLOOP RESULT DATA READ LD 9EH ADCDR Conversion result H VAREF VASS 253 254 255 256 Analog input voltage 256 Figure2 78 Analog Input Voltage vs A D Conversion Result typ 3 74 117 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 12 Vacuum Fluorescent Tube VFT Driver Circuit The 87C874 H74 features built in high breakdown voltage output buffers for directly driving fluorescent tubes
33. B 3 74 92 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 11 Slave address match detection monitor 12 13 The AAS bit 2 in 58158 is set to 1 in the slave mode in the address recognition mode ALS 0 or when receiving a slave address with the same value that sets a GENERAL CALL or I2CAR When the ALS is 1 the AAS is set to 1 after receiving the first 1 word of data The AAS is cleared to 0 by after writing reading data to from a data buffer register GENERAL CALL detection monitor The ADO bit 1 in SBISR is set to 1 in the slave mode when all 8 bit data received immediately after a start condition are 0 The ADO is cleared to 0 when a start or stop condition is detected on the bus Last received bit monitor The SDA value stored at the rising edge of the SCL line is set to the LRB bit 0 in SBISR When the contents of the LRB are read immediately after an INTSBI interrupt request is generated in the acknowledge mode and ACK signal is read 3 74 93 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 9 5 Data Transfer I2C bus Mode 1 Device Initialization Set the CHS SCK in the SBICR1 Specify 0 to bits 7 to 5 3 Set a slave address and the ALS ALS 2 0 when an addressing format to the I2CAR After confirming that input signals via port are high level for specifying the default setting to a slave receiver mode clear 0 to the MST TRX and BB in the SBICR2 1 to the PIN 10
34. Operating mode CPU core High frequency Low frequency Peripherals time turning on oscillation turning off operate operate Affc s oscillation Note 1 turning off halt ed halt oscillation reset reset turning on t High frequency operate Affe s oscillation High and or Low s IDLE2 turning on halt Note 1 oscillation Single Clock SLOW turning off Low frequency Low frequency SLEEP oscillation Note 2 Dual Clock 4 fs s turning off Snore oscillation Note 1 The Vacuum Fluorescent Tube VFT driver circuit are halted Figure 1 14 Operating Mode Transition Diagram 3 74 19 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 System Control Register 1 7 6 5 4 3 2 0038 initial value 0000 00 0 CPU core and peripherals remain active STOP mode start 1 CPU core and peripherals are halted start STOP mode RELM Release method 0 Edge sensitive release for STOP mode 1 Level sensitive release RETM Operating mode 1 Return to NORMAL mode after STOP mode Return to SLOW mode OUTEN Port output control Y High impedance during STOP mode Remain unchanged 3x2 7 fc or 3x21 fs s 2 fc or 2 fs Reserved Warming up time at releasing STOP mode Always set to 0 when transiting from NORMAL1 mode to STOP1 mode and from Normal2 mode to STOP2 mode Always set RETM to 1 when transiting from SLOW mode to STOP2 mode When STOP mode is released with RESET pin input a return is made t
35. S1 state of the read cycle during execution of the read instruction This timing can not be recognized from outside so that transient input such as chattering must be processed by the program Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I O port fetch cycle fetch cycle read cycle fetch cycle fetch cycle write cycle lt gt lt gt lt gt gt lt gt lt gt Instruction SO 51 52 S3 SO 51 52 53 50 51 52 53 Instruction __20_ 51 S2 S3 50 S1 52 53 SO 51 52 53 execution Ex LD A execution Ex LD x A EA Input i Output latch__ pul se a Input Timing b Output Timing Note The positions of the read and write cycles may vary depending on the instruction Figure 2 2 Input Output Timing Example When reading an I O port except programmable I O ports and P1 whether the pin input data or the output latch contents are read depends on the instructions as shown below 1 Instructions that read the output latch contents D XCH r src amp LD pp b CLR SET CPL src b ADD ADDC SUB SUBB AND OR XOR src n CLR SET CPL pp g src side of ADD ADDC SUB SUBB AND OR XOR src HL LD src b CF 2 Instructions that read the pin input data D Instructions other than the above 1 HL side of ADD ADDC SUB SUBB AND OR XOR src HL 3 74 54 TOSHIBA UNDER DEVELOPMENT
36. TMP87C874 H74 2 2 1 Port PO P07 Port PO is an 8 bit general purpose input output port which can be configured as either an input or an output in one bit unit under software control Input output mode is specified by the corresponding bit in the port PO input output control register POCR Port PO is configured as an input if its corresponding POCR bit is cleared to 0 and as an output if its corresponding POCR bit is set to 1 During reset POCR is initialized to 0 which configures port PO as input The PO output latches are also initialized to 0 Data is written into the output latch regardless of POCR contents Therefore initial output data should be written into the output latch before setting POCR PO 00008 POCR 000 5 OUTEN POCRi Data output Data output output latch Control output Control input Note i 7to0 5 PO2 PO1 POO Initial value 0000 0000 911 SCK1 7 6 5 4 3 2 1 0 Initial value 0000 0000 control for port PO Figure 2 3 Port and POCR Example Setting the upper 4 bits of port PO as an input port and the lower 4 bits as an output port Initial output data are 10102 LD 00001010B Setsinitial data to PO output latches LD 000011118 Setsthe port input output mode Note The port set to the input mode reads the state of the pin input When the port is used both in input and in output modes the outpu
37. Transmit Receive Mode Example 8 bit 1word internal clock SCK1 pin l SIOF l 501 pin 516 tsopu min 4 fc s In the NORMAL1 2 IDLE1 2 modes min 4 fs s In the SLOW SLEEPmodes Figure 2 73 Transmitted Data Hold Time at End of Transmit receive 3 74 114 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 11 8 bit A D Converter ADC The 87C874 H74 each have an 8 channel multiplexed input 8 bit successive approximate type A D converter with sample and hold 2 11 1 Configuration Ladder resistors 1 Cur E IC DEC 5 7 i L1 vass 1 STOP ERES AINDS gt Tap Decoder VAREF 0 40 oe 5 Reference p i Voltage 1 O i i 1M AIN1 1 i i 8 j j i Aine O i E i 1 AIN7 O i i Analog i Comparator AIN10 __ _ E 5 j Sampling Successive Approximate Circuit clock Shift clock AINDS Control Circuit 6 35 ADS ET EOCF P4 ADCCR ADCDR P4 P5 input output control register A D Converter control register A D Conversion result register Figure 2 74 A D Converter 2 11 2 Control The A D converter is controlled by an A D converter control register ADCCR A D Conversion Result Register 7 6 5 ADCDR Read only 3 74 115 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 A D Converter Control Register 3 2 1 0 7 6 5 4 ADCCR 2 000 AINDS SAIN Ini
38. VSEL and VFT control register 2 VFTCR2 sets dimmer timer DIM and state STA BLK of VFTCR1 must be set to 1 The segments and the digits are not fixed so that they can be freely allocated However the number of states must be specified according to the number of digits of VFT which you use Thought the layout of VFT display mode is freely allocated the followings are recommended usually large current output VO to V15 is used for a digit and middle current output V16 to V36 is used for a segment See Display operation in section 2 12 4 for display timing and data setting procedures 3 74 120 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 Display data setting Data are converted into VFT display data by instructions The converted data stored in the display data buffer addresses OF80 to OFCF in DBR are automatically transferred to the VFT driver circuit then transferred to the high breakdown voltage output buffer Thus to change the display pattern just change the data in the display data buffer Bits in the VFT segment dot and display data area correspond one to one When data are set to 1 the segments corresponding to the bits light The display data buffer is assigned to the DBR area shown in Figure 2 82 The display data buffer can not be used as data memory output pin VO to V7 V8 to 15 V16 to V23 V24 to V31 V32 to V36 Figure 2 82 VFT Display Data Buffer Memory DBR 2 12 4 Display Operation As the
39. a low power consumption oscillator is input to the STOP pin In the edge sensitive release mode STOP mode is started even when the STOP pin input is high Example Starting STOP mode operation in the edge sensitive release mode PINTS SYSCR1 00000000B OUTEN 0 specifies high impedance DI IMF lt 0 disables interrupt service SET SYSCR1 STOP STOP lt activates stop mode LDW IL 1111011101010111B 1L11 7 5 3 O Clears interrupt latehes El IMF lt 1 enables interrupt service STOR pin NORMAL STOP Warm up STOP operation operation AMAL NORMAL operation 70 operation STOP mode started by the program STOP 5 released by the hardware at the rising Figure 1 17 Edge sensitive Release Mode STOP mode is released by the following sequence In the dual clock mode When returning to NORMAL2 both the high frequency and low frequency clock oscillators are turned on when returning to SLOW mode only the low frequency clock oscillator is turned on When returning to Normal 1 only the high frequency clock oscillator is turned on Q A warming up period is inserted to allow oscillation time to stabilize During warm up all internal operations remain halted Two different warming up times can be selected with WUT bits 2 and 3 in SYSCR1 as determined by the resonator characteristics amp When the warming up time has elapsed normal operation resumes with the instructi
40. banks 1 to 15 are assigned to interrupt service tasks To increase the efficiency of data memory utilization the same bank is assigned for interrupt sources which are not nested The switched bank is automatically restored by executing an interrupt return instruction RETI or RETN Therefore it is not necessary for a program to save the RBS Example Register Bank Changeover PINTxx wb RBS Switches to bank n 1 xs at 8 MHz interrupt processing main task acceptance of interrupt bankm _ Interrupt service task 3 Switch to bank n by LD RBS n or INC GRBS instruction Restore bank automatically by RETI RETN instruction a Saving Restoring by register bank changeover Restores bank and Returns main task acceptance of interrupt interrupt service task restoring registers b Saving Restoring using push pop or data transfer instructions Figure 1 25 Saving Restoring General purpose Registers General purpose register save restore using push and pop instructions To save only a specific register and when the same interrupt source occurs more than once the general purpose registers can be saved restored using push pop instructions 3 74 32 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example Register save using push and pop instructions PINTxx PUSH WA Save WA register pair interrupt processing POP WA Restore WA register pair RETI Return
41. basic clock which provides the system clocks supplied to the CPU core and on chip peripheral hardware It contains two oscillation circuits one for the high frequency clock and one for the low frequency clock Power consumption can be reduced by switching of the system clock controller to low power operation based on the low frequency clock The high frequency fc and low frequency fs clocks can be easily obtained by connecting a resonator between the XIN XOUT and XTIN XTOUT pins respectively Clock input from an external oscillator is also possible In this case external clock is applied to the XIN XTIN pin with the XOUT XTOUT pin not connected High frequency clock Low frequency clock XOUT XTOUT XTIN gt Crystal Ceramic b External oscillator c Crystal d External oscillator resonator Figure 1 10 Examples of Resonator Connection Accurate Adjustment of the Oscillation Frequency Although no hardware to externally and directly monitor the basic clock pulse is not provided the oscillation frequency can be adjusted by providing a program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse With a system requiring adjustment of the oscillation frequency the adjusting program must be created beforehand Example To output the high frequency oscillation frequency adjusting monitor pulse to P13 DVO pin SFCCHK LD 1 00001000B Configures
42. buffer in 4 bit or 8 bit blocks The receiving mode ends when the transfer is completed SIOF is cleared to 0 when receiving is ended and thus can be sensed by program to confirm that receiving has ended Note The buffer contents are lost when the transfer mode is switched 1f it should become necessary to switch the transfer mode end receiving by clearing SIOS to 0 read the last data and then switch the transfer mode 3 74 112 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 4 clear silos 9 SEF 1 1 pin output 511 pin input A 22 25 boX b b2X bs A baX bs A be A br INTSIO interrupt DBR Read out Figure 2 71 Receive Mode Example 8 bit 1 word internal clock c 8 bit Transmit Receive Mode After setting the control registers to the 8 bit transmit receive mode write the data to be transmitted first to the data buffer registers DBR After that enable transceiving by setting SIOS to 1 When transmitting the data are output from the 501 pin at leading edges of the serial clock When receiving the data are input to the SI pin at the trailing edges of the serial clock 8 bit data are transferred from the shift register to the data buffer register An INTSIO interrupt is generated when the number of data words specified with the BUF has been transferred The interrupt service program reads the received data from the data buffer register and then writes the data to
43. buffer register Figure 2 38 Serial Bus Interface SBI 2 9 2 Control The following registers are used for control and operation status monitoring when using the serial bus interface SBI Serial bus interface control register 1 SBICR1 Serial bus interface control register 2 SBICR2 Serial bus interface data buffer register SBIDBR 2C bus address register I2CAR Serial bus interface status register SBISR The above registers differ depending on an mode to be used Refer to Section 2 9 4 bus mode control and 2 9 6 Clocked synchronous 8 bit SIO mode control 3 74 85 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 9 3 The Data Format in The I2C Bus Mode The data format when using the 87C874 H74 in the I2C bus mode are shown in figure 2 39 a Addressing format 1 to 8 bits gt 1 lt 1 to 8 bits 1 lt 1 or more Start condition Direction bit Acknowledge bit Stop condition Figure 2 39 Data Format in I2C Bus Mode 3 74 86 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 9 4 I2C Bus Mode Control The following registers are used for control and operation status monitoring when using the serial bus interface 581 in the 12 bus mode Serial Bus Interface Control Register 1 SBICR1 7 6 5 4 3 2 1 0 0200 BC __ initial value 0000 0000 Number of transferred bits 9 2 3 4 5 6 0 TETUER not returned to transmitter Read
44. can be programmably selected to the STOP pin After the warming up period is completed the execution resumes with the next instruction which follows the STOP mode start instruction 3 74 17 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 Dual clock mode Both the high frequency and low frequency oscillation circuits are used in this mode P21 XTIN and P22 XTOUT pins cannot be used as input output ports The main system clock is obtained from the high frequency clock in NORMAL2 and IDLE2 modes and is obtained from the low frequency clock in SLOW and SLEEP modes The machine cycle time is 4 s 0 5 us at fc 8 MHz in NORMAL2 and IDLE2 modes and 4 fs s 122 us at fs2 32 768 kHz SLOW and SLEEP modes Note that the 87PM75 is placed in the single clock mode during reset To use the dual clock mode the low frequency oscillator should be turned on by executing SET SYSCR2 XTEN instruction NORMAL2 mode In this mode the CPU core is operated using the high frequency clock The on chip peripherals are operated on the high frequency clock and or low frequency clock In case that the dual clock mode has been selected as an option the 87C874 H74 are placed in this mode after reset SLOW mode This mode can be used to reduce power consumption by turning off oscillation of the high frequency clock The CPU core and on chip peripherals are operated using the low frequency clock Switching back and forth between NORMAL2
45. counters Within WDT detection time LD WDTCR2 4EH Clears the binary counters Watchdog Timer Control Register 1 0 00344 wor Initial value 1001 Watchdog timer on 223 fc detection time 10 27 fc 1 27 fc 1 WDTOUT cannot be set to 1 by program after clearing WDTOUT to 0 Note2 fc High frequency clock Hz Low frequency clock Hz don t care Note3 WDICR1 isa write only register and must not be used with any of the read modify write instructions Note4 Disable the watchdog timer or clear the counter just before switching to STOP mode When the counter is cleared just before switching to STOP mode clear the counter again subsequently to releasing STOP mode Watchdog Timer Control Register 2 6 5 4 3 2 1 WDTCR2 00354 Initial value xxx Watchdog timer binary counter clear clear code Biy Watchdog timer disable disable code others Invalid Watchdog timer control code write register WDTCR2 Note1 The disable code is invalid unless written when WDTEN 0 Note2 don tcare Figure 1 28 Watchdog Timer Control Registers Table 1 4 Watchdog Timer Detection Time Operating mode Detection time NORMAL1 NORMAL2 SLOW At fc 8 MHz At fs 32 768 kHz 25 s 2 fc 2 7 fs 4 1945 277 fc 2 fc 2715 1 048 ms 2 fc 2 fe 294 fs 262 1 ms 29 4 29140 27 5 65 5 ms 2 Watchdog Timer Enable T
46. data buffer display data buffer Entry area for page call instructions Vector table for vector call instructions 16 vectors 32 bytes Vector table for interrupts reset 16 vectors 87CH74 87C874 Figure 1 1 Memory Address Maps 3 74 5 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 2 Program Memory ROM The 87C874 has a 8K x 8 bit addresses 000 the 87CH74 has a 16K x 8 bit address 8000 of program memory mask programmed ROM Addresses in the program memory can also be used for special purposes 1 Interrupt Reset vector table addresses FFEQW FFFFH This table consists of a reset vector and 16 interrupt vectors 2 bytes vector These vectors store a reset start address and interrupt service routine entry addresses 2 Vector table for vector call instructions addresses FFCOH FFDFy This table stores call vectors subroutine entry address 2 bytes vector for the vector call instructions CALLV n There are 16 vectors The CALLV instruction increases memory efficiency when utilized for frequently used subroutine calls called from 3 or more locations 3 Entry area addresses FFOOY FFFFy for page call instructions This is the subroutine entry address area for the page call instructions n Addresses FFOO FFBFy are normally used because address FFCOW FFFF are used for the vector tables Programs and fixed data are stored in the program memo
47. driver output Note 1 7100 e T 00084 v23 v22 v21 V20 v19 v18 i v17 i Vie initial value 0000 0000 Figure 2 11 P8 Port 2 2 10 Port P9 P97 P90 Port P9 is an 8 bit high breakdown voltage input output port and also used as a driver output which can directly drive vacuum fluorescent tube VFT When used as an input port or a VFT driver output the output latch should be cleared to 0 The output latches are initialized to 0 during reset Pins which are not set for driver output be used as normal I O port refer to section 2 12 6 Port Function It is recommended that pins P97 to P90 should be used as segment output CMP MCMP TEST others STOP OUTEN Data input Data output Note i 7to0 VFT driver output ae i Initial value 0000 0000 H Figure 2 12 Port P9 3 74 62 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 11 PD 4 PDO Ports PD are high breakdown voltage input output ports and are also used as VFT driver outputs which can directly drive vacuum fluorescent tube VFT The segment and the input output port are specified by VSEL bit 5 to 0 of VFT driver control register VFTCR1 At reset VSEL is cleared to 0 and used as the input output port When used as an input port or a VFT driver output the output latch should be cleared to 0 Pins which are not set driver output can be used as normal I O port refer to
48. input with INTOEN bit 6 in EINTCR During reset the pin P10 INTO is configured as an input port P10 STOP OUTEN P1CRi Data input Data output output latch Control output Control input Note 1 7100 P1 P17 p16 P15 P13 P12 P11 P10 0001 ana 107 DVO 989 i i INTO Initial value 0000 0000 7 6 5 4 3 2 1 0 Initial value Quod uc p 0000 0000 0 Input mode P1CR f P1 O control for port 1 Output mode Figure 2 4 Port P1 and P1CR Example Sets P17 P16 and P14 as output ports P13 and P11 as input ports and the others as function pins Internal output data is 1 for the P17 and P14 pins and 0 for the P16 pin LD EINTCR 010000008 1 LD P1 10111111B 2 176 1 P1461 P16 lt 0 LD P1CR 11010000B Note The port set to the input mode reads the state of the pin input When the port is used both in input and in output modes the output latch data of the port set to the input mode may be rewritten by execution of the bit manipulation instruction 3 74 56 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 3 Port P2 P22 P20 Port P2 is a 3 bit input output port It is also used as an external interrupt SET CLR CPL others TEST others input and low frequency crystal Datainput connection pins When used as an input port or the secondary function output pin the output latch should be set to co
49. listed in Table 1 4 They applied to the INT2 pin when it is used for both edge interrupts INT3 INT3 P15 TC1 IMF EF41 1 INT3ES 0 INT3ES 1 For falling or rising edge pulses INT3W 0 less than 7 fc s are cancelled as noise Pulses equal to or more than 24 fc s are regarded as signals Same applies to pin TC1 at one edge IMF EF 1 INT3W 1 Noise cancellation conditions are INT3W 1 Note 2 as listed in Table 1 4 They applied to the INT3 pin when it is used for both edge interrupts INT4 INT4 P17 TC3 IMF EF41 1 INT4ES 0 INTAES 1 For falling or rising edge pulses INT4W 0 less than 7 fc s are cancelled as noise Pulses equal to or more than 24 fc s are regarded as signals Same applies to pin TC3 at one edge IMF 1 INT4W 1 Noise cancellation conditions are INT4W 1 Note 2 as listed in Table 1 4 They are applied to the INT4 pin is used for both edge interrupts To detect remote control signals using timer 3 in capture mode the INT4 pin is used for both edge interrupts 206 imr eris t thysteresisinputy 0000 3 74 35 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 The noise rejection function is turned off for INTO INT1 INT2 INT3 INT4 INT5 used in SLOW and SLEEP modes Also the noise reject times are not constant for pulses input while transiting between operating modes NORMAL2 lt SLOW To detect the edge at which an interr
50. mode can be used for 50 duty pulse output Timer F F 4 can be initialized by program and it is initialized to 0 during reset An INTTCA interrupt is generated each time the PDO output is toggled Example Output a 1024 Hz pulse at fc 2 4 194304 MHz SET P1 4 P14 output latch lt 1 LD P1CR 00010000BH Sets P14 output mode LD TREG4 10H 1 2048 27 fc 104 LD TC4CR 00010010B Starts TC4 TREG4 Timer F F 4 PDO pin output INTTC4 interrupt Figure 2 36 Timing Chart for PDO Mode 3 Pulse Width Modulation PWM Output Mode PWM output with a resolution of 8 bits is possible The internal clock is used for counting up The contents of TREG4 are compared with the contents of up counter If a match is found the timer F F 4 output is toggled The counter continues counting And when an overflow occurs the timer is again toggled and the counter is cleared Timer F F 4 output is inverted and output to the PWM P44 pin An INTTC4 interrupt is generated when an overflow occurs TREG4 is configured a 2 stage shift register and during output will not switch until one output cycle is completed even if TREG4 is overwritten therefore output can be altered continuously Also the first time TREGA is shifted by setting TCAS bit 4 in TCACR to 1 after data are loaded to TREG4 3 74 83 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Internal clock Up
51. the interrupt source accepted is cleared to 0 The contents of the program counter return address and the program status word are saved pushed on the stack The entry address of the interrupt service program is read from the vector table and the entry address is loaded to the program counter The instruction stored at the entry address of the interrupt service program is executed Interrupt service task 1 1 machine cycle Il BN Interrup signal Instruction execution PC 2 1 Ae D n Note a return address b entry address c address which the RETI instruction is stored Note2 The maximum response time from when an IL is set until an interrupt acceptance processing starts is 38 fc or 38 fs s Figure 1 24 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Example Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address D2034 D2044 A maskable interrupt is not accepted until the IMF is set to 1 even if a maskable interrupt of higher priority than that of the current interrupt being serviced When nested interrupt service is necessary the IMF is set to 1 in the interrupt service program In this case acceptable interrupt sources are selectively enabled by the individual interrupt enable flags However an acceptance of external interrupt
52. 0064 ve va Initial value 0000 0000 Figure 2 9 P6 Port 2 2 8 Port P7 P77 P70 Port P7 are 8 bit high breakdown voltage input output ports and are also used as VFT driver outputs which can directly drive vacuum fluorescent tube VFT When used as an input port or a VFT driver output the output latch should be cleared to 0 The output latches are initialized to 0 during reset Pins which are not set for driver output can be used as normal I O port refer to section 2 12 6 Port Function It is recommended that pins P77 to P70 should be used as VFT driver output CMP MCMP TEST STOP OUTEN control Data input Data output VFT driver output P7 5 5 00078 v15 via i v13 i v12 v11 i v10 Initial value 0000 0000 Figure 2 10 P7 Port 3 74 61 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 9 Port P8 P87 P80 Port P8 are 8 bit high breakdown voltage input output ports and are also used as VFT driver outputs which can directly drive vacuum fluorescent tube VFT When used as an input port or a VFT driver output the output latch should be cleared to 0 The output latches are initialized to 0 during reset Pins which are not set for VFT driver output can be used as normal I O port refer to section 2 12 6 Port Function It is recommended that pins P87 to P80 should be used as driver output CMP MCMP TEST STOP OUTEN Data input Data output VFT
53. 2 Watchdog Timer Control Registers Figure 1 27 Watchdog Timer Configuration 1 10 2 Watchdog Timer Control Figure 1 28 shows the watchdog timer control registers WDTCR1 WDTCR2 The watchdog timer is automatically enabled after reset 1 Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows D Setting the detection time selecting output and clearing the binary counter Repeatedly clearing the binary counter within the setting detection time If a CPU malfunction occurs for any cause the watchdog timer output will become active on the rise of an overflow from the binary counters unless the binary counters are cleared At this time when WDTOUT 1 a reset is generated which drives the RESET pin low to reset the internal hardware and the external circuits When WDTOUT 0 a watchdog timer interrupt INTWDT is generated The watchdog timer temporarily stops counting in STOP mode including warm up or IDLE mode and automatically restarts continues counting when STOP IDLE mode is released 3 74 48 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example Setsthe watchdog timer detection time to 221 fc s and resets the CPU malfunction LD WDTCR2 4EH Clearsthe binary counters LD WDTCR1 00001101B WDTT 10 WDTOUTc 1 LD WDTCR2 4EH Clears the binary counters Within WDT always clear immediately after changing WDTT detection time LD WDTCR2 4EH Clears the binary
54. 2 Vpp 4 5V 10 1 6 Output Low Current PO P10 to P14 P2 4 5 1 0 V Output High Current Vpp 4 5 V 2 4V N e ES I gt 3 3 3 Ww e N Supply Current in Vpp 5 5V NORMAL 1 2 modes 8 MHz Supply Current in fs 32 768 kHz IDLE 1 2 modes Vin 5 3 V 0 2 V Supply Current in PEY 3 0 V SLOW mode fs 32 768 kHz PA Supply Current in Vin 2 8 V 0 2 V 30 SLEEP mode Supply Current in Vpp 5 5 05 10 pA STOP mode Vin 5 3 V 0 2 V Typical values show those at Topr 225 2 5V Input Current Ij ling The current through resistor is not included when the input resistor pull up pull down is contained input Current l na The current when the pull down register is not connected by the mask option A D CONVERSION CHARACTERISTICS Vss 0 4 5 to 6 0 V Topr 30 to 70 C PARAMETER SYMBOL CONDITIONS Min ___ Max UNIT L vsere Analog Reference Voltage Varer 7 Vass 2 5V V Analog Input Voltage 1 Ves 7 Ve V quse Analog Supply Current Varer 5 5 V Vass 0 0 V Nonlinearity Error 5 0V Vss 0 0V Zero Point Error 5 000V Full Scale Error Vass 0 000V Total Error Note Total errors includes all errors except quantization error 3 74 130 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 A C CHARACTERISTICS OV
55. 2 mode interrupt latch of external interrupt input INT1 must be cleared after 14 machine cycles when INTTNC 1 or 50 machine cycles when 0 from the time of changing During SLOW mode 3 machine cycles are required Figure 1 26 a External Interrupt Control Register 1 3 74 38 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 External Interrupt Control Register 2 ep Pu 4 3 e TH INT2W INT2 both edge selection 2 Refer to INT2ES Both edge detection INT2EDT Flag indicating an interrupt at Interrupt at selected edge or no interrupt selected edge non selected i Interrupt at non selected edge edge when INT2W 1 for both edge interrupts initial value 0000 00 x 000 No noise cancellation 001 Cancels 26 fc x 7 6 fc as noise 010 Cancels 27 fc x 7 6 fc as noise 011 Cancels 28 fc x 7 6 fc as noise 100 Cancels 29 fc x 7 6 fc as noise 101 Cancels 210 fc x 7 6 fc as noise 110 Cancels 21 fc x 7 6 fc as noise 111 Cancels 212 fc x 7 6 fc as noise INT2DET INT2 interrupt detection flag 0 Nointerrupt 1 Interrupt Note 1 INT2EDT and NCS2 are valid only when the INT2W bit in EINTCR2 0025 is set to 1 Therefore when INT2W 0 the digital noise filter set by the 52 bit is disabled Note 2 Do not changing the contents of INT2ES bit 2 in 00374 when INT2W is set to 1 both edge detention If changing the contents of INT2ES d
56. 7 1 1 1 NT2DET 0025H bit2 Read point of INT3DET 1 1 NT2EDT 0025H bit6 Read point of INT2EDT 1 2 2 When the initial state of the 2 is low after reset Reset INT2ES 0 edge INT2W DI El f 1 instruction L7 003CH bit7 1 1 Clear point of L7 t 1 1 Read point of INT2EDT 3 74 45 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 Operation with setting modifying external interrupt control register EINTCR after reset 1 Case3 When the initial state of the INT2 pin is low after reset low at edge switchover from rising to falling Reset INT2ES rising edge falling edge INT2W EI DI DI instruction Clear point of 1L 7 T 1 1 T NT2DET 0025H bit2 Read point of INT2DET 2 Case4 When the initial state of the INT2 pin is high after reset high at edge switchover from rising to falling Reset 1 2 5 rising edge falling edge INT2W p S INT2 terminal EI DI DI El f instruction 117 003CH bit7 1 1 1 1 1 1 1 i 1 Clear point of L7 T t t 1 1 1 1 INT2DET 0025H bit2 Read point of INT2DET 1 1 1 INT2EDT 0025H bit6 Read point of INT2EDT t 1 1 3 74 46 T
57. A are compared with the contents of up counter If a match is found an INTTC1 interrupt is generated and the counter is cleared The maximum applied frequency is fc 24 Hz in NORMAL1 2 or IDLE1 2 mode and fs 24 Hz in SLOW or SLEEP mode Setting SCAP1 to 1 transferres the current contents of up counter to TREG1B software capture function SCAP is automatically cleared after capturing Command start TC1 pin input falling edge select INT3ES 1 Up counter TREG1A Counter INTTC1 interrupt detect clear Figure 2 22 Event Counter Mode Timing Chart INT3ES 1 3 74 70 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 4 Window mode Counting up is performed on the rising edge of the pulse that is the logical AND ed product of the TC1 pin input window pulse and an internal clock The contents of TREG1A are compared with the contents of up counter If a match is found an INTTC1 interrupt is generated and the counter is cleared Positive or negative logic for the TC1 pin input can be selected with INT3ES Setting SCAP1 to 1 transferes the current contents of up counter to TREG1B It is necessary that the maximum applied frequency TC1 input be such that the counter value can be analyzed by the program That is the frequency must be considerably slower than the selected internal clock command start TC1 pin input Internal clock Up counter TREGIA INTTC1 interrupt a Positive Logic INT3ES 0
58. C2CR 10H Stops TC2 CLR SYSCR2 5 5 5 6 0 Switches the main system clock to the high frequency clcok RETI VINTTC2 DW PINTTC2 INTTC2 vector table 3 74 26 S9poI N MOIS Pu ZIVINHON 941 Uaamyag 2 1 941614 ZTVINYON 291 or dn MOS 1 uonn exe S CH2SAS 412 L 282545 135 uononajsu N3X 2SAS Aduanba M0 fouanbeuy ubiH SPO MOTS eur 07 Buryoy ms CIVINHON AAOTS uonn exe uononasu N3X 2SAS ees M07 1 eene TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 9 Interrupt Controller 87C874 H74 each have a total of 15 interrupt sources 6 externals and 9 internals Nested interrupt control with priorities is also possible Two of the internal sources are pseudo non maskable interrupts the remainder are all maskable interrupts Interrupt latches IL that hold the interrupt requests are provided for interrupt sources Each interrupt vector is independent The interrupt latch is set to 1 when an interrupt request is generated and requests the CPU to accept the interrupt The acceptance of maskable interrupts c
59. CS 1 0 1 INT2W 1 and NCS 1 1 0 INT2W 1 and NCS 1 1 1 INT3W 0 falling or rising edge INT3W 1 and NCS 0 0 0 INT3W 1 and NCS 0 0 1 INT3W 1 and NCS 0 1 0 INT3W 1 and NCS 0 1 1 INT3W 1 and NCS 1 0 0 INT3W 1 and NCS 1 0 1 INT3W 1 and NCS 1 1 0 INT3W 1 and NCS 1 1 1 INTAW 0 falling or rising edge INTAW 1 and NCS 0 0 0 INTAW 1 and NCS 0 0 1 INTAW 1 and NCS 0 1 0 INT4W 1 and NCS 0 1 1 INT4W 1 and NCS 1 0 0 INT4W 1 and NCS 1 0 1 INT4W 1 and NCS 1 1 0 INT4W 1 and NCS 1 1 1 3 74 36 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 INTO INT5 input tintL tintH gt Note 4 5 gt tINTL tINTH Note6 The pulse width both H and L level for input to the INTO and INT5 pins must be over 1 machine cycle Note7 When 0 interrupt latch IL is not set even if a falling edge is detected for INTO pin input Note8 When high impedance is specified for port output in stop mode port input is forcibly fixed to low level internally Thus interrupt latches of external interrupt inputs except INT5 P20 STOP which are also used as ports may be set to 1 To specify high impedance for port output in stop mode first disable interrupt service IMF 20 activate stop mode After releasing stop mode clear
60. DEVELOPMENT TMP87C874 H74 Serial Bus Interface Control Register 2 7 6 5 4 3 2 SBICR2 00234 PIN sem 0 1 0 initial value 0001 00 MST Master slave selection Write 0 Slave Transmitter receiver selection Write 0 Receiver status monitor Read 1 Start condition Write Bus busy Read Cancel interrupt service request Write 0 Write Interrupt service requested Read Status monitor Read 1 Cancel interrupt service request Write canceled Read 00 Port mode serial bus interface output disable Serial bus interface operating mode 01 SIO mode selection 10 C bus mode 11 Reserved Write only don t Switch a mode to port after confirming that the bus is free Switch a mode to I2Cbus mode after confiming that input signals via port are high level SBICR2 has write only register bits which can not access any of in read modify write instructions such as bit operate etc 7 6 5 4 3 2 1 0 SBISR TRX BB H AL Arbitration loss detection monitor Arbitration loss detected 0 1 i i AAS Slave address match detection monitor 9 1 Slave address match or GENERAL CALL detected Read ADO GENERALCALL detection monitor 0 only 1 GENERAL CALL detected LRB Lastreceived bit monitor 0 Last received bit 0 1 Lastreceived bit 1 Figure 2 41 Serial 20 Interface Control Register 2 and Serial Bus Interface Status Registe
61. ER DEVELOPMENT TMP87C874 H74 External Interrupt Control Register 4 4 3 00a wv initial value 0000 00 INTAW INT4 both edge selection 2 Refer to INTAES Both edge detection INT4EDT Flag indicating an interrupt at Interrupt at selected edge or no interrupt selected edge non selected i Interrupt at non selected edge edge when INTAW 1 for both edge interrupts Noise cancellation time select 000 No noise cancellation for INT4 digital noise filter 001 Cancels 26 fc x 7 6 fc as noise valid only when INTAW z 1 010 Cancels 27 fc x 7 6 fc as noise 011 Cancels 28 fc x 7 6 fc as noise 100 Cancels 29 fc x 7 6 fc as noise 101 Cancels 219 fc x 7 6 fc as noise 110 Cancels 211 fc x 7 6 fc as noise 111 Cancels 212 fc x 7 6 fc as noise INTADET INT4 interrupt detection flag 0 Nointerrupt 1 Interrupt Note 1 INT4EDT and NCS4 are valid only when the INTAW bit in EINTCRA 0024 is set to 1 Therefore when INTAW 0 the digital noise filter set by the NCS4 bit is disabled Note 2 Do not changing the contents of INTES bit 4 in 00374 when INT4W is set to 1 both edge detention If changing the contents of INT4ES during INTAW is set to 1 according to Note 3 4 5 at Figure 1 26 a Figure 1 26 b External Interrupt Control Register 2 3 74 40 3dnueu 043005 gt
62. ER DEVELOPMENT TMP87C874 H74 Note When STOP mode is released with a low hold voltage the following cautions must be observed The power supply voltage must be at the operating voltage level before releasing the STOP mode The RESET pin input must also be high rising together with the power supply voltage In this case if an external time constant circuit has been connected the RESET pin input voltage will increase at a slower rate than the power supply voltage At this time there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non inverting high level input voltage hysteresis input 2 IDLE mode IDLE1 IDLE2 SLEEP IDLE mode is controlled by the system control register 2 and maskable interrupts The following status is maintained during IDLE mode V Starting IDLE mode by instruction D Operation of the CPU and watchdog timer is halted The on chip peripherals continue to CPU WDT are halted operate The data memory CPU registers and port output latches are all held in the status in effect before IDLE mode was entered 8 The program counter holds the address of No high the instruction following the instruction which started IDLE mode Interrupt request Example Starting IDLE mode Normal Yes elease mode SET SYSCR2 4 IDLEC1 No IDLE mode includes a normal release mode and an interrupt release mode Selection is made with the Yes Interrupt release mode interrup
63. L is also used to read out fixed data ROM data stored in the program memory The register offset PC relative addressing PC A instructions can also be used and the code conversion table look up and n way multiple direction jump processing can easily be programmed 3 74 6 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example 1 Loads the ROM contents at the address specified by the HL register pair contents into the accumulator HL A000 LD A HL AROM HL Example2 Converts BCD to 7 segment code common anode LED When 05g 924 is output to port PO after executing the following program LD PC A ADD A TABLE 4 PO lt ROM TABLE A JRS T SNEXT TABLE DB OF9H OBOH 99H 92H 82H OD8H 98H isa header address of ADD instruction DB is a byte data difinition instruction Example3 N way multiple jump in accordance with the contents of accumulator 0S S 3 SHLC A if A200 then PC C234 JP PC A if A 014 then PCcC3784 if A202 then PC DA37y if 034 then PC lt E1B0 DW 0C234H 0C378H 0DA37H OE1BOH Note DW is a word data definition instruction 1 3 Program Counter PC The program counter PC is a 16 bit register which indicates the program memory address where the instruction to be executed next is stored After reset the user defined reset vector stored in the vector table addresses FFFFy and is loaded into the PC ther
64. MARKS initial Hi Z itial Hi Source open drain output High breakdown voltage 80 typ R 1kQ typ R1 200 typ 3 74 127 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Vss OV Supply Voltage f __ 93t65 DTI DM NUR P2 P3 P4 P5 XOUT RESET mpm Source open drain ports 40 to 0 3 40 to Vpp 0 3 UR emen is M eds P15to 17 P5 Output Current Total PO P10 to P14 P2 P6 P7 8 P9 PD Soldering Temperature time 26060 mu Operating Temperature Teer lx Note Power Dissipation For PD it is necessary to decrease 14 3 mw C RECOMMENDED OPERATING CONDITIONS Vss OV 30 to 70 C PARAMETER SYMBOL PINS CONDITIONS UNIT NORMAL 1 2 modes 2 modes fc 8 MHz 4 IDLE1 2 modes Supply Voltage SLOW mode 32 768 kHz sieePmode SLEEP ISLEEPmode STOP mode Output Voltage Em Source open Source open drain ports prs Vno 38 38 Except hysteresis input 2 0 70 VppZ4 5V Input High Voltage Hysteresis input Von x0 75 0 75 lt 45 2 080 Except hysteresis input Von x0 30 x 0 30 Vpp 24 5 Input Low Voltage Hysteresis input pee x0 25 Vppz 4 5Vto5 5V cee 2o 27
65. O1 interrupt request Serial clock SCK1 pin Serial clock 1 0 Figure 2 63 Serial Interfaces 2 10 2 Control The serial interfaces are controlled by SIO1 control registers SIO1CR1 SIO1CR2 The serial interface status can be determined by reading SIO status registers 510 1SR The transmit and receive data buffer is controlled by the BUF bits 2 0 in SIO1CR2 The data buffer is assigned to addresses 8 OFFFy for 5101 the DBR area and can continuously transfer up to 8 words bytes or nibbles at one time When the specified number of words has been transferred a buffer empty in the transmit mode or a buffer full in the receive mode or transmit receive mode interrupt INTSIO 1 is generated When the internal clock is used as the serial clock in the 8 bit receive mode and the 8 bit transmit receive mode a fixed interval wait can be applied to the serial clock for each word transferred Four different wait times can be selected with WAIT bits 4 and 3 in SIO1CR2 3 74 106 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 SIO Control Registers 1 aoe 3 2 1 0 00254 Initial value 0000 0000 S SIO Indicate transfer start stop Stop Start SIOINH Continue abort transfer Continuetranster Abort transfer automatically cleared after abort 8 bit transmit mode 4 bit transmit mode Transfer mode select 8 bit transmit receive mode 8 bit receive mode 4 bit receive mode 000 Internal clock fc 2 or
66. OSHIBA UNDER DEVELOPMENT TMP87C874 H74 3 Case5 Case 5 When the initial state of the INT2 pin is high after reset low at edge switchover from rising to falling Reset 4 INT2ES rising edge falling edge EN t inon selected instruction immediately lafter edge 1 117 1 t t t 1 Read point of INT2DET 1 t INT2EDT 0025H bit6 1 Read point of INT2EDT 1 1 4 Case6 When the initial state of the INT2 pin is low after reset high at edge switchover from rising to falling Reset 1 INT2ES rising edge falling edge INT2W 1 DI El f instruction Clear point of I L7 t 1 1 Read point of INT2DET t T INT7EDT 0025H bit6 Read point of INT7EDT t 3 74 47 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 10 Watchdog Timer WDT The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like and resumes the CPU to the normal state The watchdog timer signal for detecting malfunction can be selected either as a reset output or a non maskable interrupt request However selection is possible only once after reset At first the reset output is selected When the watchdog timer is not being used for malfunction detection it can be used as a timer to generate an interrupt at fixed intervals 1 10 1 Watchdog Timer Configuration reset release signal from T G internal reset writing clear code WDTCR1 WDTCR
67. RMAL 1 2 or IDLE 1 2 mode the maximum time from the edge of input signal until the IL is set is as follows 0 1 INT1 pin 49 fc s when 1 193 fc s when 2 INT2 pin 25 fc s when 0025 25 fc s when 40025 26 fc x 8 5 19 fc s when 0025 27 fc x 8 5 19 fc s when 0025 28 fc x 8 5 19 fc s when 0025 23 fc x 8 5 19 fc s when 0025 210 fc x 8 5 19 fc s when 0025 21110 x 8 5 19 fc s when 00254 212 fc x 8 5 19 fc s when 0025 3 INT3 pin 25 fc s when 0026 25 fc s when 0026 26 fc x 8 5 19 fc s when 0026 27 fc x 8 5 19 fc s when 0026 28 fc x 8 5 19 fc s when 0026 29 fc 8 5 19 fc s when 40026 219 fc x 8 5 19 fc s when 0026 211 fc x 8 5 19 fc s when 0026 212 fc x 8 5 19 fc s when 0026 4 INT4 pin 25 fc s when 0024 25 fc s when 0024 26 fc x 8 5 19 fc s when 0024 27 fc 8 5 19 fc s when 0024 28 fc x 8 5 19 fc s when 0024 2310 x 8 5 19 fc s when 00244 210 fc x 8 5 19 fc s when 0024 21 fc x 8 5 19 fc s when 0024 212 fc x 8 5 19 fc s when 0024 INT2W 0 falling or rising edge INT2W 1 and NCS 0 0 0 INT2W 1 and NCS 0 0 1 INT2W 1 and NCS 0 1 0 INT2W 1 and NCS 0 1 1 INT2W 1 and NCS 1 0 0 INT2W 1 and N
68. SW There are 3 instructions LD RBS n PUSH PSW and POP PSW to access the PSW The PSW can be also operated by the memory access instruction Example1 Incrementing the RBS INC 003FH RBS lt 1 Example2 Reading the RBS LD A 003FH A PSW lt RBS A7 aFlags Highly efficient programming and high speed task switching are possible by using bank changeover to save registers during interrupt and to transfer parameters during subroutine processing During interrupt the PSW is automatically saved onto the stack The bank used before the interrupt was accepted is restored automatically by executing an interrupt return instruction RETI RETN therefore there is no need for the RBS save restore software processing The TLCS 870 Series supports a maximum of 15 interrupt sources One bank is assigned to the main program and one bank can be assigned to each source Also to increase the efficiency of data memory usage assign the same bank to interrupt sources which are not nested Example Saving restoring registers during interrupt task using bank changeover PINT1 LD RBS n RBS Bank changeover Maskable interrupt return Bank restoring 3 74 11 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 6 Program Status Word PSW The program status word PSW consists of a register bank selector RBS and four flags and the PSW is assigned to address 003Fy in the SFR The RBS can be read and written using
69. TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 CMOS 8 BIT MICROCONTROLLER TMP87C874F TMP87CH74F The 87C874 CH74 are the high speed and high performance 8 bit single chip microcomputers These MCU contain 8 bit A D conversion inputs and a VFT Vacuum Fluorescent Tube driver on a chip RAM PACKAGE MCU TMP87C874F 8K x 8 bit 512 x 8 bit QFP80 P 1420 0 80B TMP87PM74F TMP87CH74F 16K x 8 bit FEATURES 8 bit single chip microcomputer TLCS 870 Series Instruction execution time 0 5 ws at 8 MHz 122 5 at 32 768 kHz QFP80 P 1420 0 80B 412 basic instructions e Multiplication and Division 8 bits x 8 bits 16 bits 8 bits Bit manipulations Set Clear Complement Load Store Test Exclusive OR e 16 bit data operations 1 byte jump subroutine call Short relative jump Vector call 15 interrupt sources External 6 Internal 9 sources have independent latches each and nested interrupt control is available 3 edge selectable external interrupts with noise reject High speed task switching by register bank changeover 11 Input Output ports 71 pins TMP87C874F High current output 16 pins typ 20 mA TMP87CH74F Two 16 bit Timer Counters TMP87PM74F Timer Eventcounter programmable pulse generator output Pulse width measurement External trigger timer Window modes Two 8 bit Timer Counters Timer Event counter Capture Pulse width duty measurement PWM output P
70. above mentioned the segment and the digit are not allocated After setting of the display timing for the number of digits according to the using VFT and storing the segment and digit data according to the respective timings clearing BLK in VFTCR1 to 0 starts VFT display Figure 2 83 shows the VFT drive pulse and Figure 2 84 85 show the display operation Dimmer time DIM TO SEG DEG 2 One display time tdisp Figure 2 83 VFT Drive Waveform and Display timing 3 74 121 TMP87C874 H74 UNDER DEVELOPMENT TOSHIBA 2 12 5 Example of Display operation 1 For Conventional type for 1 timing Data must be set to output the pins which are specified to the digit in sequence The following figure shows a data allocation of the display data buffer DBR and the output timing when VFT of 10 digits is used and VO to V9 pins are allocated as the digit outputs When data is first When using the conventional type VFT the output timing of the digits is specified to output 1 digit written by the data buffer which corresponds to the digit pin it is unnecessary to rewrite the data later 1 0 0 0 0 0 0 0 0 0 0 SEG Write change by display data Figure 2 84 Example of Conventional type VFT driver pulse 3 74 122 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 For Grid scan type VFT When using the grid scan type VFT two or more grids must be simultaneously selected to turn the display pattern which conta
71. ack depth is limited only by the free data memory size For more details on the stack see section 1 7 Stack and Stack Pointer The 87C874 H74 cannot execute programs placed in the data memory When the program counter indicates a data memory address a bus error occurs and an address trap reset applies The RESET pin goes low during the address trap reset 3 74 7 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example1 If bit 2 at data memory address 00 0 is 1 00 is written to data memory at address 00 otherwise FFy is written to the data memory at address 00 TEST 00C0H 2 if 00C0 2 0 then jump JRS T SZERO CLR 00E3H 00 3 lt 00 385 5 52 LD 00E3H OFFH 00E34 SNEXT Example2 Increments the contents of data memory at address 00 5 and clears to 004 when 10 is exceeded INC 00F5H 00F5 00F5 1 AND 00 5 OFH OOF5y lt 00 5 0 The data memory contents become unstable when the power supply is turned on therefore the data memory should be initialized by an initialization routine Note that the general purpuse registers are mapped in the RAM therefore do not clear RAM at the current bank addresses Example1 Clears RAM to 004 except the bank 0 87C874 H74 LD HL 0048H Setsstart address to HL register pair LD A H Sets initial data 005 to A register LD BC 01F7H Sets number of byte to BC register pair SRAMCLR LD HL
72. an be selectively enabled and disabled by the program using the interrupt master enable flag IMF and the individual interrupt enable flags EF When two or more interrupts are generated simultaneously the interrupt is accepted in the highest priority order as determined by the hardware Figure 1 22 shows the interrupt controller Table 1 2 Interrupt Sources Reset _________ 0 Pseudo nor maskable IMF 1 INTOEN Internal INTTC1 16 bit TC1 interrupt IMF EF42 1 External INT1 External interrupt 2 1 INTTBT Time Base Timer interrupt IMF EFgz 1 1 Interrupt Latches IL 15 2 Interrupt latches are provided for each source except for a software interrupt The latch isset to 1 when an interrupt request is generated and requests the CPU to accept the interrupt The latch is cleared to 0 just after the interrupt is accepted All interrupt latches are initialized to 0 during reset Interrupt latches are assigned to addresses 003Cy and 003D in the SFR Each latch can be cleared to Q0 individually by an instruction however the read modify write instruction such as bit manipulation or operation instructions cannot be used Do not clear the 1 gt for a watchdog timer intlerrupt to 0 Thus interrupt requests can be canceled and initialized by the program Note that interrupt latches cannot be set to 1 by any instruction The contents
73. and SLOW modes is performed by the system control register 2 IDLE2 mode In this mode the internal oscillation circuits remain active The CPU and the watchdog timer are halted however on chip peripherals operate using the high frequency clock and or the low frequency clock Starting and releasing of IDLE2 mode are the same as for IDLE1 mode except that operation returns to NORMAL2 mode SLEEP mode In this mode the internal oscillation circuit of the low frequency clock remains active The CPU the watchdog timer and the internal oscillation circuit of the high frequency clock are halted however on chip peripherals operate using the low frequency clock Starting and releasing of SLEEP mode is the same as for IDLE1 mode except that operation returns to SLOW mode STOP2 mode As in STOP1 mode all system operations are halted in this mode 3 74 18 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 RESET1 reset release software software age SONATE gt gt IDLE1 NORMAL1 STOP1 mode mode mode interrupt STOP pin input a Single clock mode RESET2 reset release software IDLE2 NORMAL2 mode p mode interrupt soft jJ STOP pin STOP2 27 d 22 2 mode war a SLEEP SLOW 227 uu software interrupt b Dual clock mode NORMAL1 and NORMAL2 modes are generically called NORMAL STOP1 and STOP2 are called STOP and IDLE1 IDLE2 and SLEEP are called IDLE Note2 There is not RESET2 in the 87PM74
74. aster device and a slave device during transferring data The following explains how to restart when the 87C874 H74 is in the master mode Specify 0 to the MST TRX and BB and 1 to the PIN and release the bus The SDA pin retains the high level and the SCL pin is released Since a stop condition is not generated on a bus a bus is assumed to be in a busy state from other devices Check the BB until it becomes 0 to check that the SCL pin of the 87C874 H74 is released Check the LRB until it becomes 1 to check that the SCL line of a bus is not pulled down to the low level by other devices After confirming that a bus stays in a free state generate a start condition with procedure 2 In order to meet setup time when restarting take at least 4 7 us of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition 0 MST 1 MST 0 TRX 1 2 TRX 0 BB 1 BB 1 PIN 1 Start condition SCL Bus SCL pin 87C874 H74 SDA pin Figure 2 53 Timing Diagram when Restarting the 87C874 H74 3 74 97 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 9 6 Clocked synchronous 8 bit SIO Mode Control The following registers are used for control and operation status monitoring when using the serial bus interface 581 in the clocked synchronous 8 bit SIO mode Serial Bus Interface Control Register 1 SBICR1 7 6 5 4 3 2 1 0 0020 s
75. ata is read and next data is written When the external clock is used since the shift operation is synchronized with the external clock received data is read and transmitted data is written before new shift operation is executed The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read and transmitted data is written When the transmit is started after the SIOF goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK Transmitting receiving data is ended by cleaning the SIOS to 0 by the INTSBI interrupt service program or setting the SIOINH to 1 When the SIOS is cleared received data is transferred to the SBIDBR in complete blocks The transmit receive mode ends when the transfer is complete In order to confirm if data is surely transmitted received by the program set the SIOF bit 3 in 58158 to be sensed The SIOF becomes 0 after transmitting receiving is complete When the SIOINH is set transmitting receiving data stops The SIOF turns 0 When the transfer mode is switched the SBIDBR contents are lost In case that the mode needs to be switched conclude transmitting receiving data by clearing the SIOS to 0 read the last data and then switch the transfer mode Clear 5105 SCKO pin A 1 1 1 NU 00 pin 50 pin ZA
76. ating status Switching the mode from NORMAL1 2 to SLOW or STOP puts the driver circuit into blanking state BLK is set to 1 and EXEY is cleared to 0 values set in the VFT control registers except BLK and EKEY are maintained and sets segment outputs and digit outputs are cleared to 0 Thus ports P6 to P9 PD function as general purpose output ports with pull down VFT control register 1 1 7 6 5 4 3 2 1 0 0029 initial value 1000 0000 Display enable write only Display time select tdisp 29 Display time of 1 digit 210 fc 10 211 11 212 fc Automatic display select 00000 32 V31to V0 When using VFT driver 00001 33 V32 to V0 automatic display V31 to 00010 34 V33 to VO VO are only used to output 00011 35 V34 to V0 VFT 00100 36 V35 to Pins which are not selected 00101 37 V36 to VO by the output pins other than the above mentioned pins can be used as general purpose input output pins When using as a general purpose input output pin the display data which corresponds to the pin must be set to 0 Note1 fc high frequency clock Note2 VFTCRI is write only register which cannot use any of in read modify write instruction such as bit operate etc Figure 2 80 VFT Control Register 1 3 74 119 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 VFT control register 2 VFTCR2 002A ini
77. be transmitted The data buffer register is used for both transmitting and receiving therefore always write the data to be transmitted after reading the received data When the transmit is started after the SIOF goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK1 When the internal clock is used a wait is initiated until the received data are read and the next data are written When an external clock is used the shift operation is synchronized with the external clock therefore it is necessary to read the received data and write the data to be transmitted next before starting the next shift operation When an external clock is used the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written Clear SIOS to 0 to enable the transmit mode When SIOS is cleared the current data are transferred to the data buffer register in 8 bit blocks The transmit mode ends when the transfer is completed SIOF is cleared to 0 when receiving is ended and thus can be sensed by program to confirm that receiving has ended 3 74 113 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 lt clear 5105 SEF SCK1 pin output SO1 pin 511 pin A 8 o e Ks A EK A doA dA da ds A de 97 INTSIO interrupt IL DBR A write a read out c write b read out d Figure 2 72
78. being executed Thus the next interrupt can be accepted immediately after the interrupt return instruction is executed Note When the interrupt processing time is longer than the interrupt request generation time the interrupt service task is performed but not the main task 3 74 33 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 9 2 Software Interrupt INTSW Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing INTSW is highest prioritized interrupt However if processing of a non maskable interrupt is already underway executing the SWI instruction will not generate a software interrupt but will result in the same operation as the NOP instruction Thus the SWI instruction behaves like the NOP instruction Use the SWI instruction only for detection of the address error or for debugging D Address Error Detection FFy is read if for some cause such as noise the CPU attempts to fetch an instruction from a non existent memory address Code FFy is the SWI instruction so a software interrupt is generated and an address error is detected The address error detection range can be further expanded by writing FFy to unused areas of the program memory the address trap reset is generated in case that an instruction is fetched from RAM or SFR areas Note The fetch data from addresses 7 80 to 7 test ROM area for 87C874 H74 is not FF 2 Debugging Debugging effic
79. bus mode in order to drive a bus with a wired AND a master device which pulls down a clock pulse to low will in the first place invalidate a clock pulse of another master device which generates a high level clock pulse The master device with a high level clock pulse needs to detect the situation and implement the following procedure The 87C874 H74 have a clock synchronization function for normal data transfer even when more than one master exists on a bus The example explains clock synchronization procedures when two masters simultaneously exist on a bus SCL pin Master 1 L pin M r2 SCL pin Master 2 Count reset Count reset SCL Bus Figure 2 43 Clock Synchronization 3 74 89 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 As Master 1 pulls down the SCL pin to the low level at point a the SCL line of the bus becomes the low level After detecting this situation Master 2 resets counting a clock pulse in the high level and sets the SCL pin to the low level Master 1 finishes counting a clock pulse in the low level at point b and sets the SCL pin to the high level Since Master 2 holds the SCL line of the bus at the low level Master 1 waits for counting a clock pulse in the high level After Master 2 sets a clock pulse to the high level at point c and detects the SCL line of the bus at the high level Master 1 starts counting a clock pulse in the high level The clock pulse on the bus is deteminded by the master de
80. chdog Timer 1 11 4 System Clock Reset Clearing both XEN and XTEN bits 7 and 6 in SYSCR2 to 0 stops both high frequency and low frequency oscillation and causes the MCU to deadlock This can be prevented by automatically generating a reset signal whenever XTEN 0 is detected to continue the oscillation Then the RESET pin output goes low from high impedance The reset time is 12 fc s 1 5 at 8 MHz 3 74 51 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 1 ON CHIP PERIPHERALS FUNCTIONS Special Function Registers SFR and Data Buffer Registers DBR The TLCS 870 Series uses the memory mapped I O system and all peripheral control and data transfers are performed through the special function registers SFR and data buffer registers DBR The SFR are mapped to addresses 0000 003 and the DBR to addresses OF 80H OFFFy Figure 2 1 shows the 87C874 H74 SFRs and DBRs Address PO port 00204 SBICR1 SBI control 1 21 SBIDBR SBI Data Buffer reserved reserved ister bank selector a Special Function Registers Do not access reserved areas by the program Cannot be accessed When defining address 003F with assembler symbols use GPSW and GRBS Write only registers and interrupt latches cannot use the read modify write instructions bit manipulation instructions such as SET CLR etc and logical operation instructions such as AND OR etc Figure 2 1 a SFR amp DBR 3
81. clock When one word of data has been received it is transferred from the shift register to the data buffer register DBR When the number of words specified with the BUF has been received an INTSIO buffer full interrupt is generated to request that these data be read out The data are then read from the data buffer registers by the interrupt service program When the internal clock is used and the previous data are not read from the data buffer register before the next data are received the serial clock will stop and an automatic wait will be initiated until the data are read A wait will not be initiated if even one data word has been read Note Waits are also canceled by reading a DBR not being used as a received data buffer register is read therefore during SIO do not use such DBR for other applications When an external clock is used the shift operation is synchronized with the external clock therefore the previous data are read before the next data are transferred to the data buffer register If the previous data have not been read the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled When an external clock is used the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read Clear SIOS to 0 to end receiving When SIOS is cleared the current data are transferred to the
82. counter TREG4 Timer F F 4 PWM pin INTTC4 interrupt H 1 period gt Figure 2 37 Timing Chart for PWM Mode Table 2 7 PWM Output Mode Resolution Maximum setting time NORMAL1 2 IDLE1 2 mode oves SLEEP mode pv7ck 1_ 1 fc 8 MHz fs 32 768 kHz fc 8 MHz fs 32 768 kHz fc 2 Hz fs 2 Hz fs 2 Hz 256 xs 244 14 ys fc 27 fc 27 16 fc 22 fc 22 3 74 84 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 9 Serial Bus Interface SBI The 87C874 H74 each have a 1 channel serial bus interface which employs a clocked synchronous 8 bit serial bus interface and an 2 bus a bus system by Philips The serial interface is connected to an external device through P31 SDA and P30 SCL in the I2C bus mode and through P32 P31 500 and P30 510 in the clocked synchronous 8 bit SIO mode The serial bus interface pins are also used for the P3 port When used for serial bus interface pins set the P3 output latches of these pins to 1 When not used for serial bus interface pins the pin is used as a normal I O port 2 9 1 Configuration INTSBI interrupt clock control Divider SIO Transfer data control 12 bus control clock circuit sync d rejection Control circuit 2 bus data control Noise rejection SDA SBICR2 SBISR SBICR1 SCL SIO SBI control register 2 12C bus SBI data SBI control register 1 SBI status register address register
83. device or when a GENERAL CALL is received and data transfer is complete after matching a received slave address In the master mode the 87C874 H74 operate in a slave mode if it is losing arbitration An INTSBI interrupt request occurs when word data transfer terminates after losing arbitration When an INTSBI interrupt request occurs the PIN bit 4 in the SBICR2 is reset and the SCL pin is pulled down to the low level Either reading writing from to the SBIDBR or setting the PIN to 1 releases the SCL pin after taking ti ow time In the slave mode the 87C874 H74 operate either in normal slave mode or in slave mode after losing arbitration Check the AL bit 3 in the SBISR the TRX bit 6 in the SBISR the AAS bit 2 in the SBISR and the ADO bit 1 in the SBISR and implements processes according to conditions listed in the next table Table 2 8 Operation in the Slave Mode The 87C874 H74 loses arbitration when Set the number of bitsin 1 wordtotheBC transmitting a slave address and receives a and write transmitted data to the SBIDBR slave address of which the value of the direction bit sent from another master is In the slave receiver mode the 87C874 H74 receives a slave address of which the value of the direction bit sent from the master is In the slave transmitter mode 1 word data Check the LRB If the LRB is set to 1 set is transmitted the PIN to 1 since the receiver does not request next data Then clear t
84. dummy data is transmitted and operation ends 3 74 100 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Clear 5105 SEF SCKO pin output 00 pin INTSIO interrupt request SBIDBR a Interral clock Write transmitted data Clear SIOS SEF SCKO pin Input 500 pin NO aX a asX 2 bL bs Ao INTSBI interrupt request SBIDBR X5 A b External clock Write transmitted data Figure 2 58 Transfer Mode Example 5100 transfer end command External clock STEST1 TEST SBISR SEF IfSEF 1 then loop JRS 5 5 1 5 5 2 TEST P3 6 IfSCKz0 then loop JRS T STEST2 LD SBICR1 00000111B 5105 lt 0 3 74 101 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 SCK pin SIOF SO pin lt m tsopu Min 3 5 fc s In normal mode IDLE mode Figure 2 59 Transmitted Data Hold Time at End of Transmit 8 bit receive mode Set a control register to a receive mode and the SIOS to 1 for switching to a receive mode Data is received from the SI pin to the shift register in synchronous with the serial clock starting from the least significant bit LSB When the 8 bit data is received the data is transferred from the shift register to the SBIDBR The INTSBI buffer full interrupt request is generated to request of reading the received data The data is then read from the SBIDBR by the interrupt service program When the interna
85. e unless the timer counter 1 is set to the PPG output mode with TC1M Internal clock PU UW UUW UU UU UT command start Up counter PPG output Note m gt n INTTC1 Pulse count start external trigger start TC1 pin input trigger 99 Internal clock Up counter PPG output Note m n INTTC1 Applications One shot pulse output b Single Figure 2 25 PPG Output Mode Timing Chart 3 74 73 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 P12 output latch Data output TC1CR write strobe reset match with TREG1B match with TREG1A INTTC1 interrupt Figure 2 26 PPG Output 2 6 16 bit Timer Counter 2 TC2 2 6 1 Configuration TC2 pin 16 bit up counter source clock comparator INTTC2 interrupt match detect control Timer Counter 2 control register 16 bit timer register 2 TREG2H TREG2L write strobe write strobe Figure 2 27 Timer Counter 2 TC2 3 74 74 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 6 2 Control The timer counter 2 is controlled by a timer counter 2 control register TC2CR and a 16 bit timer register 2 TREG2 Reset does not affect TREG2 2 14 13 12 11 10 4 3 0016 0013 2 00174 TREG2 00164 write only Initial value 00 00 0 7 Timer counter 2 operating 0 Timer Event counter mode TC2M mode select 1 Window mode write only 000 Internal clock fc 2 or fs 2 Hz 001 fc 2 or fs 25 010 fc 2
86. e stack pointer LD WDTCR1 00001000B WDTOUT lt 0 1 10 4 Watchdog Timer Reset If the watchdog timer output becomes active a reset is generated which drives the RESET pin sink open drain output low to reset the internal hardware and the external circuits The reset output time is 12 fc s 1 5 ws at fc 8 MHz The high frequency clock oscillator also turns on when a watchdog timer reset is generated in SLOW mode 296 s 274 WDTT 118 Binary counter 1X2 3 0 1 2 3 A Overflow INTWDT interrupt WDT reset output 1 i Jeu output writes to WDTCR2 Figure 1 29 Watchdog Timer Interrupt Reset 1 11 Reset Circuit The 87C874 H74 each have four types of reset generation procedures an external reset input an address trap reset a watchdog timer reset and a system clock reset Table 1 5 shows on chip hardware initialization by reset action The internal source reset circuit watchdog timer reset address trap reset and system clock reset is not initialized when power is turned on Thus output from the RESET pin may go low 12 fc s 1 5 5 at 8 MHz when power is turned on 3 74 50 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Table 1 5 Initializing Internal Status by Reset Action On chip Hardware Initial Value On chip Hardware Initial Value Register bank selector RBS Jump status flag JF 0 1 le fl IMF Refer to I O port nterruptmaster enable flag UMF
87. e1ep apis auo uon a1ep u1oq D I F1NI 92 19 11614 043005 3dnu483u uyoq Jo uisu 043005 143930 VYDLNis 42 ge 1 pefes gt 329191 anjea ynan uonoefaa asiou epis auo eles s ou eles asiou jo en eA 5202 5 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Notes on the usage of INT2 INT3 INT4 pin external interrupt The functions of only INT2 are described INT3 and INT4 have the same functions as INT2 When using the INT2 pin for one edge either rising or falling An interrupt generated from the INT2 pin can be detected by reading the interrupt latch IL7 The greatest care must be taken in setting or rewriting the external interrupt control register EINTCR 0037H For details see Figure 1 26 a note 2 3 4 5 and accordance with the using instructions When using the INT2 pin for both edges rising and falling When using the INT2 pin for both edges rising or falling set bit 7 INT3W in EINTCR2 5500254 to 1 To detect the edge at which an interrupt is ge
88. ed the SP is preincremented when a return or a pop instruction is executed Figure 1 8 shows the stacking order The SP is not initialized hardware wise but requires initialization by an initialize routine sets the highest stack address LD SP mn LD SP gg and LD gg SP are the SP access instructions mn 16 bit immediate data gg register pair MSB LSB 1514131211109 876543210 Figure 1 7 Stack Pointer Example 1 To initialize the SP LD SP 023FH 5 23 Example 2 To read the SP LD HL SP At acceptance 1 of interrupt At execution of or At execution of a CALL CALLV CALLP at execution of At execution of 2 instruction a SWI instruction a RET instruction instruction 0040 SP before execution 023 SP after 043F execution 023D a Stacking order b Stack depth Figure 1 8 Stack 1 8 System Clock Controller The system clock controller consists of a clock generator a timing generator and a stand by controller Timing generator control register Clock TBTCR generator High frequency Timing Stand by controller clock oscillator generator System clocks Low frequency 0038 00394 clock oscillator SYSCR1 SYSCR2 Clock generator control System control registers Figure 1 9 System Clock Controller 3 74 14 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 8 1 Clock Generator The clock generator generates the
89. efore program execution is possible from any desired address For example when CO and are stored at addresses and FFFEy respectively the execution starts from address after reset The TLCS 870 Series utilizes pipelined processing instruction pre fetch therefore the PC always indicates 2 addresses in advance For example while a 1 byte instruction stored at address C123 is being executed the PC contains 125 MSB LSB 1914131211109 0 7 6 5 43 219 3 Program Counter PC a Configuration b Timing chart of PC Contents and Instruction Execution Figure 1 3 Program Counter 1 4 Data Memory RAM The 87C874 H74 have 512 x 8 bits addresses 0040 023 of data memory static RAM Figure 1 4 shows the data memory map Addresses 0000 00 are used as a direct addressing area to enhance instructions which utilize this addressing mode therefore addresses 0040 OOFFy in the data memory can also be used for user flags or user counters General purpose register banks 8 registers x 16 banks are also assigned to the 128 bytes of addresses 0040 00 Access as data memory is still possible even when being used for registers For example when the contents of the data memory at address 00401 is read out the contents of the accumulator in the bank 0 are also read out The stack can be located anywhere within the data memory except the register bank area The st
90. ent for detecting remote control receive waveform To detect and measure the low or high level width of waveforms input from INT4 or TC3 set timer 3 to capture mode and INT4 TC3 input edge detect to both edges Figure 2 33 is a timing chart of when timer 3 is used in capture mode Numbers to 18 in Figure 2 33 are described below Set INT4 TC3 edge detect to both edges In Figure 2 33 INT4ES 1 falling edge is selected and INT4W 1 both edge detect enable Change INT4ES and INTAW bits at 00244 only when IMF 0 After changing EINTCR interrupt latches of external interrupts must be cleared to 0 using load instruction 2 Wake up timer 3 and enable timer 3 soft capture Then the timer 3 counter starts free running Also enable timer 3 interrupts EFg 1 At the selected falling edge of the INT4 TC3 input pin the current counter value is fetched to TREG3A and the counter is zero cleared At the same time a timer 3 interrupt is generated The interrupt processing routine for the timer 3 interrupt sets 2 in the interrupt enable register EIR to 1 and clears EFg to 0 so that INT4 can be detected at the non selected rising edge of INT4 TC3 input D TREG3B and TREG3A are read next because after a timer 3 interrupt by capture to TREG3A is generated capture overflow detect is halted until the next TREG3A read Reading TREG3A by the interrupt processing routine resumes capture overflow detect D Timer coun
91. errupt 640 counts later LDW TREG2 0280H Sets TREG2 SET EIRH EF14 INTTC2 interrupt enable EI LD TC2CR 00111100B Starts TC2 3 Window Mode In this mode counting up is performed on the rising edge of the pulse that is the logical AND ed product of the TC2 pin input window pulse and an internal clock The internal clock is selected with TC2CK The contents of TREG2 are compared with the contents of up counter If a match is found an INTTC2 interrupt is generated and the up counter is cleared to 0 It is necessary that the maximum applied frequency TC2 input be such that the counter value can be analyzed by the program That is the frequency must be considerably slower than the selected internal clock TC2 pin input Internal clock Up counter TREG2 INTTC2 interrupt Figure 2 29 Window Mode Timing Chart 3 74 76 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 7 8 Bit Timer Counter 3 TC3 2 7 1 Configuration inhibit rising Edge Capture gt detector falling INTTC3 control H 2 TC3M INT3ES 5 TC3 pin 187 D fc 212 or 6 24 IA source clock 8 bit upkounter overflow 210 or fs 22 B fc 27 Cs match capture capture gt TREG3B mA C SCAP 8 bit Timer Register 3A 3B Timer Counter 3 Control Register Figure 2 30 Timer Counter 3 2 7 2 Control TREG3A 00184 Read Write TREG3B 00194 Initial value 0 0 00 0 001Ay Ti
92. es the main system clock to the low frequency clock CLR SYSCR2 7 XEN O turns off high frequency oscillation Example2 Switching to SLOW mode after low frequency clock oscillation has stabilized LD TC2CR 14H Sets TC2 mode timer mode source clock fs LDW TREG2 8000H Sets warming up time according to Xtal characteristics SET EF14 Enable INTTC2 interrupt LD TC2CR 34H Starts TC2 PINTTC2 LD TC2CR 10H Stops 2 SET SYSCR2 5 SYSCKe 1 CLR SYSCR2 7 0 RETI VINTTC2 DW PINTTC2 INTTC2 vector table b Switching from SLOW mode to NORMAL2 mode First set XEN bit 7 in SYSCR2 to turn on the high frequency oscillation When time for stabilization warm up has been taken by the timer counter 2 TC2 clear SYSCK bit 5 in SYSCR2 to switch the main system clock to the high frequency clock SLOW mode can also be released by setting the RESET pin low which immediately performs the reset operation After reset the 87CC78 H78 K78 M78 are placed in NORMAL mode Example Switching from SLOW mode to NORMAL2 mode fc 8 MHz warming up time is about 7 9 ms SET SYSCR2 7 1 turns on high frequency oscillation LD TC2CR 10H Sets TC2 mode timer mode source clack fc LD TREG2 1 OF8H Sets the warming up time according to frequency and resonator characteristics SET EF14 Enable INTTC2 interrupt LD TC2CR Starts TC2 PINTTC2 LD T
93. f maskable interrupts After execution of the interrupt service program this flag is set to 1 by the maskable interrupt return instruction RETI to again enable the acceptance of interrupts If an interrupt request has already been occurred interrupt service starts immediately after execution of the RETI instruction Pseudo non maskable interrupts are returned by the RETN instruction In this case the IMF is set to 1 only when pseudo non maskable interrupt service is started with interrupt acceptance enabled IMF 1 Note that the IMF remains 0 when cleared by the interrupt service program The IMF is assigned to bit 0 at address 003A in the SFR and can be read and written by instruction The IMF is normally set and cleared by the EI and DI instructions and the IMF is initialized to 0 during reset Note Do not IMF to 1 during non maskable interrupt service programs Individual interrupt Enable Flags 15 EF These flags enable and disable the acceptance of individual maskable interrupts except for an external interrupt 0 Setting the corresponding bit of an individual interrupt enable flag to 1 enables acceptance of an interrupt setting the bit to 0 disables acceptance Example 1 Sets EF for individual interrupt enable and sets IMF to 1 LDW EIR 1110100010100001B EFy1 EFs lt 1 Example 2 Sets an individual interrupt enable flag to 1 IL 003C 003Dy
94. fs 25 Hz 001 Internal clock fc 2 Hng Serial clock select 010 Internal clock fc 2 SCK pin 011 Internal clock 2 111 External clock input from SCK pin Note 1 fc High frequency clock Hz fs Low frequency clock Hz Note2 Set 5105 to 0 and SIOINH to 1 when setting the transfer mode or serial clock Note 3 SIO1CRT is write only register which cannot access of in read modify write instruction such as bit operate etc SIO1 Control Registers 2 SIO1CR2 7 6 5 4 3 2 1 0 00288 war euF Initial value 0 0000 Tp no WAIT D 2Tp WAIT Wait control 4Tp WAIT 8Tp Buffer address used SIO 1 word transfer OFF8y 2 words transfer OFF8 OFF9 3 words transfer OFF8 OFFA 4 words transfer OFF8 OFFBy 5 words transfer OFF8 6 words transfer OFF8 OFFD 7 words transfer OFF8 8 words transfer OFF8 OFFFy Number of transfer words Note1 don tcare Note2 WAITis valid only in the 8 bit transmit receive and 8 bit receive modes Note3 Tg frametime data transfer time 3 74 107 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Note4 The lower 4 bits of each buffer are used during 4 bit transfers Zeros 0 are stored to the upper 4bits when receiving Note5 Transmitting starts at the lowest address Received data are also stored starting from the lowest address to the highest add
95. general purpose register the register also has the following functions 1 A WA The A register functions as an 8 bit accumulator and WA the register pair functions as a 16 bit accumulator W is high byte and A is low byte Registers other than A can also be used as accumulators for 8 bit operations Examples D ADD A B AddsB contents to A contents and stores the result into A SUB WA 1234H Subtracts 1234 from WA contents and stores the result into WA 9 SUB E A Subtracts A contents from E contents and stores the result into E 2 HL DE The HL and DE specify a memory address The HL register pair functions as data pointer HL index register HL d base register HL C and the DE register pair function as a data pointer DE The HL also has an auto post increment and auto pre decrement functions This function simplifies multiple digit data processing software LIFO last in first out processing etc Example 1 LD A HL Loadsthe memory contents at the address specified by HL into A e LD A HL 52H Loadsthe memory contents at the address specified by the value obtained by adding 524 to HL contents into A LD Loads the memory contents at the address specified by the value obtained by adding the register C contents to HL contents into A LD A HL Loads the memory contents at the address specified by HL into A Then increments HL LD A HL Decrements HL Then loads the memor
96. he TRX to 0 release the bus If the LRB is cleared to 0 set the number of bits a word to the BC and write transmitted data to the SBIDBR since the receiver requests next data Read the SBIDBR for setting the PIN to 1 transmitting a slave address and receives a reading dummy data or write 1 to the slave address or GENERAL CALL of which PIN the value of the direction bit sent from another master is 0 ME 87C874 H74 loses arbitration when a slave address data and terminates transferring word data 1 0 In the slave receiver mode the 87C874 H74 receives a slave address or GENERAL CALL of which the value of the direction bit sent from the master is 0 andreedreceved data from the SBIDBR terminates receiving of 1 word data and read received data from the SBIDBR 3 74 96 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 4 Stop Condition Generation When the BB is 1 a sequence of generating a stop condition is started by writing 1 to the MST TRX and PIN and 0 to the BB Do not modify the contents of the MST TRX BB PIN until a stop condition is generated on a bus When a SCL line of bus is pulled down by other devices the 87C874 H74 generates a stop condition after they release a SCL line 1 2 SCL pin SDA pin PIN BB Read Figure 2 52 Stop Condition Generation 5 Restart Restart is used to change the direction of data transfer between a m
97. he serial clock starting with the least significant bit LSB As soon as the LSB has been output the data are transferred from the data buffer register to the shift register When the final data bit has been transferred and the data buffer register is empty an INTSIO buffer empty interrupt is generated to request the next transmitted data When the internal clock is used the serial clock will stop and an automatic wait will be initiated if the next transmitted data are not loaded to the data buffer register by the time the number of data words specified with the BUF has been transmitted Writing even one word of data cancels the automatic wait therefore when transmitting two or more words always write the next word before transmission of the previous word is completed Note Waits are also canceled by writing to a DBR not being used as a transmit data buffer register therefore during SIO do not use such DBR for other applications When an external clock is used the data must be written to the data buffer register before shifting next data Thus the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program 3 74 110 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 When the transmit is started after the SIOF goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK1 The trans
98. he watchdog timer is enabled by setting WDTEN bit 3 in WDTCR1 to 1 WDTEN is initialized to 1 during reset so the watchdog timer operates immediately after reset is released Example Enables watchdog timer LD WDTCR1 00001000B WDTENe 3 74 49 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 3 Watchdog Timer Disable The watchdog timer is disabled by writing the disable code 1 to WDTCR2 after clearing WDTEN bit 3 in WDTCR1 to 0 The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTEN is cleared to 0 The watchdog timer is halted temporarily in STOP mode including warm up and IDLE mode and restarts automaticallyafter STOP or IDLE mode is released During disabling the watchdog timer the binary counters are cleared Example Disables watchdog timer LDW WDTCR1 0B101H 0 WDTCR2 disable code 1 10 3 Watchdog Timer Interrupt INTWDT This is a pseudo non maskable interrupt which can be accepted regardless of the contents of the EIR If a watchdog timer interrupt or a software interrupt is already accepted however the new watchdog timer interrupt waits until the previous interrupt processing is completed the end of the RETN instruction execution The stack pointer SP should be initialized before using the watchdog timer output as an interrupt source with WDTOUT Example Watchdog timer interrupt setting up LD SP 023FH Setsth
99. hese components in an 12 C system provided that the system conforms to the I C Standard Specification as defined by Philips 3 74 1 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 PIN ASSIGNMENTS TOP VIEW QFP80 RN SO V Y O00 1 HHEHHHHRHEBHEHRRHBH IMN O V24 P90 L Irjes 030 ied din a n dn DAT TT SETS S 2 V25 p01 Tse 3L V26 P92 E67 3 VASS V27 P93 15468 37 lt gt P53 AIN13 V28 P94 L LLjes 36m P52 AIN12 v29 95 110470 P51 AINT 430 P96 20471 P50 AIN10 v31 097 CET 72 33 0 847 32 00 T1173 P46 AING V33 0174 31 P45 AINS v34 L rri s sq P44 v35 C1176 29111 P43 AIN3 v36 077 28 LI 1 7 P42 AIN2 VKK 0101478 27 1 1 AINI Poo 211179 26111 P40 1 0 SI 25 2 32 5 0 1 8 ee P Eg BLOCK DIAGRAM Ports P67 P77 P87 P97 PDO to to to to to P60 P70 P80 P90 PDA VDD Power Supply VSS VFT Power VKK Supply Program Counter Program Reset I O RESET Memory ROM M System Controller Test Pin TEST Standby Controller Registe
100. his mode both the CPU core and on chip peripherals operate using the high frequency clock In the case where the single clock mode has been selected as an option the 87C874 H74 are placed in this mode after reset IDLE1 mode In this mode the internal oscillation circuit remains active The CPU and the watchdog timer are halted however on chip peripherals remain active operate using the high frequency clock IDLE1 mode is started by setting IDLE bit in the system control register 2 SYSCR2 and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on chip peripherals or external interrupt inputs When IMF interrupt master enable flag is 1 interrupt enable the execution will resume upon acceptance of the interrupt and the operation will return to normal after the interrupt service is completed When IMF is 0 interrupt disable the execution will resume with the instruction which follows IDLE mode start instruction STOP1 mode In this mode the internal oscillation circuit is turned off causing all system operations to be halted The internal status immediately prior to the halt is held with the lowest power consumption during this mode The output status of all output ports can be set to either output hold or high impedance under software control STOP1 mode is started by setting STOP bit in the system control register 1 SYSCR1 and STOP1 mode is released by an input either level sensitive or edge sensitive
101. iency can be increased by placing the SWI instruction at the software break point setting address 3 74 34 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 9 3 External Interrupts The 87C874 H74 each have six external interrupt inputs INTO INT1 INT2 INT3 INT4 and INT5 Four of these are equipped with digital noise rejection circuits pulse inputs of less than a certain time are eliminated as noise Edge selection is also possible with INT1 INT2 INT3 and INT4 The INTO P10 pin can be configured as either an external interrupt input pin or an input output port and is configured as an input port during reset Edge selection noise rejection control and INTO P10 pin function selection are performed by the external interrupt control register EINTCR When INTOEN 0 the IL3 will not be set even if the falling edge of INTO pin input is detected Table 1 3 a External Interrupts Secondary Enable __ Secondary function pin unction pin conditions falling INT1 INT1 P11 IMF EF5 1 INTIES 0 INT1ES 1 Pulses of less than 15 fc or 63 fc s are eliminated as noise Pulses of equal to or more than 48 fc or 192 fc s are regarded as be signals INT2 INT2 IMF EF7 1 INT2ES 0 INT2bES 1 For falling or rising edge pulses of INT2W 0 less than 7 fc s are eliminated as noise Pulses of equal to or more than 24 fc s are regarded as signals IMF EF7 1 INT2W 1 Noise cancellation conditions are INT2W 1 Note 2 as
102. ins two or more grids on Additionally the timing and the data must be determined to set the grid scan mode as follows When the display pattern which is fully set in the respective grids is turned on only the grids which correspond as ever must be scanned in sequence to turn on the display pattern timing of T8 to T3 in the following figure When the display pattern which contains two or more grids is turned on two or more corresponding grids are simultaneously selected to turn on the display pattern timing of T2 to TO in the following figure SEG ato g Dig 1 to 6 51 52 53 54 Figure 2 85 Grid Scan Display Vacuum Fluorescent Tube Ware 3 74 123 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 12 6 Port Function 1 High breakdown voltage buffer To drive fluorescent display tube clears the port output latch to 0 The port output latch is initialized to 0 at reset It is recommended that ports P6 P7 P8 and P9 should be used as VFT driver output Precaution for using as general purpose pins are follows Note When not using a pin which is pulled down to pin Vex RK typ 80 it must be set to open It is necessary to clear the port output latch and the data buffer memory DBR to 0 D PortsP6 to P9 When a part of P6 to P9 is used as the input output pin VFT driver in operation the data buffer memory DBR of the segment which is also used as the input output pin must be cleared to
103. interrupt latches using load instruction then enable interrupt service Example Activating stop mode LD SYSCR1 010000008 OUTEN 0 specifies high impedance DI IMF 0 disables interrupt service SET SYSCR1 STOP 5 1 activates stop mode LDW IL 1110011101010111B IL12 11 7 5 3 0 clears interrupt latches enables interrupt service EI Table 1 3 b Noise reject condition for INT2 INT3 INT4 both edge interrupt 0024 0025 0026 max pulse width min pulse width NCS2 x2 NCS1x1 NCS0x0 for noise reject for immediate signal o 1 TEN o i omna ZEN ee 02840 sf 2 ERU eee umm RRT sf Note In SLOW mode set NCS x 2 1 0 0 0 0 In SLOW mode the digital noise filter in the above table is disabled 3 74 37 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 EINTCR 3 0037 E 2410 NTS TE Eg Initial value 0050 0008 Pulses of less than 63 fc 5 eliminated as noise Noise reject timeselect Pulses of less than 15 fc s are eliminated as noise Au 0 P10 input output port INTOEN P10 INTO pin configuration AED INTOEN Pronto pin configuration 1 INTO pin Port P10 should be set to an input mode INT4 ES NIS E INT4 to INT1 edge select 2 INT1 ES diu fc High frequency clock Hz
104. ios 20 Initial value 0000 000 SIOS Indicate transfer start stop 0 Stop 1 Start SIOINH Continue abort transfer 0 Continue transfer 1 Abort transfer automatically cleared after abort SIOM Transfer mode select 00 8 bit transmit mode 01 reserved 10 8 bit transmit receive mode 11 8 bit receive mode fg25 250 kHz fc 26 125 2 fo 27 62 5 kHz 128 31 25 kHz at fc 8 MHz Gag fe 29 15 62 kHz fg210 7 81 kHz fe 211 3 90 kHz External clock input from SCK pin Serial clock select Note1 don tcare Note2 Set SIOS to 0 when setting the transfer mode or serial clock Note3 SBICRI is write only register which cannot access any of in read modify write instruction such as bit operate etc Serial Bus Interface Data Buffer Register SBIDBR 7 6 5 4 3 2 00216 Read Write Note Cannotread the data which was written into SBIDBR since a write data buffer and a read buffer are independent in SBIDBR Therefore cannot access it any of in read modify write instruction such as bit operate etc Serial Bus Interface Control Register 2 SBICR2 Initial value 00 Port mode serial bus interface output disable Serial bus interface operation mode SIO mode selection 12C bus mode reserved SBIM 1 don tcare Note2 Switch a mode to port after data transfer is complete Note3 Switch a mode to SIO mode after confirming that in
105. is 0 otherwise the ZF is cleared to 0 This flag is set to 1 when the upper 8 bits of the product are 004 during the multiplication instruction MUL and when 00g for the remainder during the division instruction DIV otherwise it is cleared to 0 2 Carry flag CF The CF is set to 1 when a carry out of the MSB most significant bit of the result occurred during addition or when a borrow into the MSB of the result occurred during subtraction otherwise the CF is cleared to 0 During division this flag is set to 1 when the divisor is 00 divided by zero error or when the quotient is 100 or higher overflow error otherwise it is cleared The CF is also affected during the shift rotate instructions SHLC SHRC ROLC and RORC The data shifted out from a register is set to the CF This flag is also a 1 bit register a boolean accumulator for the bit manipulation instructions Set clear complement are possible with the CF manipulation instructions Example1 Bit manipulation LD CF 0007 5 00015 0007 5 z 009 0 XOR CF 009AH 0 LD 0001H 2 CF Example2 Arithmetic right shift LD CF A 7 RORC A 3 Half carry flag HF The HF is set to 1 when a carry occurred between bits 3 and 4 of the operation result during an 8 bit addition or when a borrow occurred from bit 4 into bit 3 of the result during an 8 bit subtraction otherwise the HF is cleared to 0 This flag is useful in the decimal adjust
106. l clock is used the serial clock will stop and automatic wait function will be initiated until the received data is read from the SBIDBR When the external clock is used since shift operation is synchronized with the clock pulse provided externally the received data should be read before new data is transferred to the SBIDBR If the received data is not read further data to be received is canceled The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read When the transmit is started after the SIOF goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK Receiving data is ended by clearing the SIOS to 0 by the buffer full interrupt service program or setting the SIOINH to 1 When the SIOS is cleared received data is transferred to the SBIDBR in complete blocks The received mode ends when the transfer is complete In order to confirm if data is surely received by the program set the SIOF bit 3 in SBIDBR to be sensed The SIOF is cleared to 0 when receiving is complete After confirming that receiving has ended the last data is read When the SIOINH is set receiving data stops The SIOF turns 0 the received data becomes invalid therefore no need to read it Note When the transfer mode is switched the SBIDBR contents are lost In case that the mode needs to be swi
107. lease mode it is necessary for the program to first confirm that the STOP pin input is low The following method can be used for confirmation Using an external interrupt input INT5 INT5 is a falling edge sensitive input Example Starting STOP mode with an INT5 interrupt PINTS TEST P2 0 Toreject noise STOP mode does not start if port P20 is at high JRS F SINT5 LD SYSCR1 01000000B Sets up the level sensitive release mode SET SYSCR1 7 Starts STOP mede LDW IL 1111011101010111B 1IL11 7 5 3 lt 0 Clears interrupt latehes SINT5 RETI STOP pin Ce 1 NORMAL operation operation Warm up operation Confirm by program that the STOP mode is released by the hardware STOP pin input is low and start STOP mode Always released if the STOP pin input is high Figure 1 16 Level sensitive Release Mode Note When changing to the level sensitive release mode from the edge sensitive release mode the release mode is not switched until a rising edge of the STOP pin input is detected 3 74 21 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 b Edge sensitive release mode RELM 0 In this mode STOP mode is released by a rising edge of the STOP pin input This is used in applications where a relatively short program is executed repeatedly at periodic intervals This periodic signal for example a clock from
108. lied to the SCKO pin is used as the serial clock In order to ensure shift operation a pulse width of at least 4 machine cycles is required for both high and low levels in the serial clock The maximum data transfer frequency is 250 kHz fc 8 MHz SCKO pin tsckH gt 4 tcyc Note 4 fc in NORMAL mode IDLE mode Figure 2 56 The Maximum Data Transfer Frequency in The External Clock Input b Shift edge The leading edge is used to transmit data and the trailing edge is used to receive data Leading edge Data is shifted on the leading edge of the serial clock at a falling edge of the SCKO pin input output Trailing edge Data is shifted on the trailing edge of the serial clock at a rising edge of the SCKO pin input output 3 74 99 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 SCKO pin 00 pin Shift register ereman amanan IT CE a Leading edge SCKO pin L4 L4 L4 L L4 L4 L4 L4 510 pin b Trailing edge Note don t care Figure 2 57 Shift Edge 2 Transfer mode The SIOM bits 5 and 4 in SBICR is used to select a transmit receive or transmit receive mode a 8 bittransmit mode Set a control register to a transmit mode and write data to the SBIDBR After the data is written set the SIOS to 1 to start data transfer The transmitted data is transferred from the SBIDBR to the shift register and output to the SOO pin in synchronous with the serial clock
109. m clock The minimum instruction execution unit is called an machine cycle There are a total of 10 different types of instructions for the TLCS 870 Series ranging from 1 cycle instructions which require one machine cycle for execution to 10 cycle instructions which require 10 machine cycles forexecution A machine cycle consists of 4 states 50 53 and each state consists of one main system clock 3 74 16 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 or 1 fs s e Main System Clock fm State a 1 1 1 re Machine gt 0 5 at fc 8 MHz 122 ys at fs 32 768 kHz Figure 1 13 Machine Cycle 1 8 3 Stand by Controller The stand by controller starts and stops the oscillation circuits for the high frequency and low frequency clocks and switches the main system clock There are two operating modes single clock and dual clock These modes are controlled by the system control registers SYSCR1 SYSCR2 Figure 1 14 shows the operating mode transition diagram and Figure 1 15 shows the system control registers Either the single clock or the dual clock mode can be selected by an option during reset 1 Single clock mode Only the oscillation circuit for the high frequency clock is used and P21 XTIN and P22 XTOUT pins are used as input output ports In the single clock mode the machine cycle time is 4 s 0 5 us at 8 MHz NORMAL1 mode In t
110. match is found an INTTC1 interrupt is generated and the counter is cleared to 0 Counting up resumes after the counteriscleared The current contents of up counter can be transfered to TREG1B by setting SCAP1 bit 6 in TC1CR to 1 software capture function SCAP1 is automatically cleared to 0 after capaturing 3 74 68 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Table 2 3 Timer Counter 1 Source Clock Internal Clock Maximum time setting NORMAL1 2 IDLE1 2 modes SLOW SLEEP mod modes DV7CK 20 DV7CK 1 At fc 8 MHz At fs 32 768 kHz At fc 8 MHz At fs 32 768 kHz fc 23 Hz fc 23 Hz 1 5 65 5 ms fc 27 fc 2 16 pus 1 0 s fc 2 5 2 15 23 Hz 256 us 244 14 us 16 8 s Example 1 Sets the timer mode with source clock fs 23 Hz and generates an interrupt 1s later at fs 32 768 kHz LDW TREG1A 1000H Sets the timer register 1 5 23 10005 SET EIRL EF4 INTTC1 interrupt enable El LD 00010000B Starts TC1 Example 2 Software capture LD TC1CR 01010000B 5 16 1 Captures LD WA TREG1B Readscaptured value Command start 1 1 Up counter 0 0 7 TREGIA E Counter INTTC1 interrupt detect clear a Timer Source clock Up counter b Software Capture Figure 2 20 Timer Mode Timing Chart 2 External Trigger Timer mode In this mode counting up is started by an external trigger This trigger is the edge of the TC1 pin i
111. ment for BCD operations adjustments using the DAA or DAS r instructions 3 74 12 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example BCD operation The A becomes 47 after executing the following program when A 19 B 28H ADD A B Ac4ly 1 DAA A 1 064 47 decimal adjust 4 Jump status flag JF Zero or carry information is set to the JF after operation e g INC ADD CMP TEST The JF provides the jump condition for conditional jump instructions JRS T F 2 JR T F 2 d TorFisacondition code Jump is performed if the JF is 1 for a true condition T or the JF is 0 for a false condition F The JF is set to 1 after executing the load exchange swap nibble rotate jump instruction so that JRS T 2 d and JR T 2 d can be regarded as an unconditional jump instruction Example Jump status flag and conditional jump instruction INC A JRS T SLABLE1 Jump when a carry is caused by the immediately preceding operation instruction LD A HL JRS T SLABLE2 JF isset to 1 by the immediately preceding instruction making it an unconditional jump instruction Example accumulator and flags will become as shown below after executing the following instructions when the WA register pair the HL register pair the data memory at address 00 5 the carry flag and the half carry flag contents being 219 00 5 7 1 and 0 re
112. mer counter 3 0 Timer event counter TC3M operation mode set 1 Capture 00 Internal clock fc 2 or fs 2 Hz Timer counter 3 01 Internal clock fc 2 or fs 2 Read only source clock select Internal clock fc 2 External clock TC3 pin input 1C3S Timer counter 3 Ms Stop amp clear start select Start i daa High frequency clock Hz fs Low frequency clock Hz don t care Set the mode the source clock and the edge selection INT3ES when the TC3 stops TC3S 0 Values to be loaded into timer register 3A must satisfy the following condition TREG3A gt 0 in the timer event counter mode TC3CR is a write only register and must not be used with any of read modify write instructions Figure 2 31 Timer Register 3A 3B and TC3 Control Register 3 74 77 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 The timer counter 3 is controlled by a timer counter 3 control register TC3CR and two 8 bit timer registers TREG3A and TREG3B Reset does not affect these timer registers 2 7 3 Function The timer counter 3 has three operating modes timer event counter and capture mode 1 Timer Mode In this mode the internal clock is used for counting up The contents of TREG3A are compared with the contents of up counter If a match is found a timer counter 3 interrupt INTTC3 is generated and the up counter is cleared Counting up resumes after the up counter is cleared The current conte
113. mission is ended by clearing SIOS to 0 at the time that the final bit of the data being shifted out has been transferred That the transmission has ended can be determined from the status of SIOF bit 7 510155 because SIOF is cleared to 0 when a transfer is completed When an external clock is used it is also necessary to clear SIOS to 0 before shifting the next data otherwise dummy data will be transmitted and the operation will end _ clear 5105 SEF SCK1 pin output 2 bo A baX bs A b7 INTSIO interrupt DBR A write write b a Internal Clock E 5105 3 SCK1 pin output 01 pin ash a7X bo bX 5 baX bs INTSIO interrupt DBR b External Clock write write a b Figure 2 69 Transfer Mode Example 8 bit 1 Word Transfer 3 74 111 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 SCK1 pin SIOF l 501 pin 756 3 5 fc s In the NORMAL1 2 IDLE1 2 modes min 3 5 6 s In the SLOW SLEEP modes Figure 2 70 Transmitted Data Hold Time at End of Transmit b 4 bit and 8 bit Receive Modes After setting the control registers to the receive mode set SIOS to 1 to enable receiving The data are then transferred to the shift register via the SI1 pin in synchronous with the serial
114. n the dual clock mode During NORMAL2 IDLE2 mode SYSCK 0 an input clock to the 7th stage of the divider can be selected either fc 28 or fs with DV7CK During SLOW or SLEEP mode SYSCK 1 fs is automatically input to the 7th stage To input clock to the 1st stage is stopped output from the 1st to 6th stages is also stopped machine cycles main system clock generator machine cycle counters states SYSCK r i prescaler divider divider fc 28 N gemens fH Ja 017197 8 clock fs Low frequency clock MPX Timer II _ Reset circuit Stand by controller LT E counters lt a Watchdog 2 02 2 153 Timer Time Base Timer Serial lt gt interfaces am VFT driver Divider circuit output circuit Note MPX Multiplexer Figure 1 11 Configuration of Timing Generator 7 6 5 4 3 2 1 0 irse qu Selection of input clock to 0 28 Hz RW the 7th stage of the divider 1 fs RAN 0036p Note1 fc high frequency clock Hz low frequency clock Hz don t care Note2 Donotset DV7CK to 1 in the single clock mode Note3 Donotset DV7CK to 1 before low frequency clock is stable in the dual clock mode Figure 1 12 Timing Generator Control Register 2 Machine Cycle Instruction execution and on chip peripheral hardware operation are synchronized with the main syste
115. n to keep the accuracy in A D conversion Executing an input instruction on port P4 when the A D converter is in use reads 0 at pins set for analog input 1 or 0 at pins not set for analog input depending on the pin input level Analog input STOP OUTEN AINDS SAIN P6CRi read Data input Data output P4 1 P47 P46 P45 i P42 P41 PAO 00044 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AINO Initial value 0000 0000 Initial value 0000 0000 input mode control for port output mode Figure 2 7 Port P4 Note The port set to the input mode reads the state of the pin input When the port is used both in input and in output modes the output latch data of the port set to the input mode may be rewritten by execution of the bit manipulation instruction 3 74 59 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 6 Port P5 P57 P50 Ports P5 is an 8 bit input output port which can be configured as an input or an output in one bit unit under software control Input output mode is specified by the corresponding bit in the port P5 input output control register P5CR At reset is set to 0 and AINDS is cleared to 0 Thus P5 becomes an analog input port At the same time the output latch of port P5 is initialized to 0 P5CR is a write only register Pins not used for analog input can be used as I O ports But do not execute the output instructio
116. n to keep the accuracy in A D conversion Executing an input instruction on port P5 when the A D converter is in use reads 0 at pins set for analog input 1 or 0 at pins not set for analog input depending on the pin input level Analog input STOP OUTEN AINDS SAIN P6CRi read Data input Data output Note i 3to0 P53 P52 P51 P50 T 00054 AIN13 AIN12 AIN11 AIN10 Initial value 0000 0000 Initial value 0000 input mode output mode Figure 2 8 Port P5 Note The port set to the input mode reads the state of the pin input When the port is used both in input and in output modes the output latch data of the port set to the input mode may be rewritten by execution of the bit manipulation instruction 3 74 60 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 7 Port P6 P67 P60 Port P6 are 8 bit high breakdown voltage input output ports and are also used as VFT driver outputs which can directly drive vacuum fluorescent tube VFT When used as an input port or a VFT driver output the output latch should be cleared to 0 The output latches are initialized to 0 during reset Pins which are not set for VFT driver output can be used as normal I O port refer to section 2 12 6 Port Function It is recommended that pins P67 to P60 should be used as VFT driver output MCMP TEST STOP OUTEN Data input Data output VFT driver output P6 0
117. ne of the bus is pulled up at point b the slave device reads data on the SDA line that is data in Master 2 Data transmitted from Master 1 becomes invalid The state in Master 1 is called arbitration lost A master device which loses arbitration releases the SDA pin in order not to effect data transmitted from other masters with arbitration When more than one master sends the same data at the first word arbitration occurs continuously after the second word 3 74 91 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 SDA Bus Figure 2 46 Arbitration Lost The 87C874 H74 compare levels of the SDA line of the bus with those of the 87C874 H74 SDA pin at the rising edge of the SCL line If the levels are unmatched arbitration is lost and the AL bit 3 in SBISR is set to 1 When the AL is set to 1 the MST and TRX are reset to 0 and the mode is switched to a slave receiver mode The 87C874 H74 generate the clock pulse until data when the AL is 1 is transmitted The AL is reset to 0 by writing reading data to from the SBIDBR or writing data to the SBICR2 SCL pin Master 2 XD7A X X DOA ND7A D6A DSA Clock pulse generated SCL pin 1 2 3 4 5 6 7 8 9 Master B SDA pin Fix SDA pin to high level as losing arbitration MST TRX Accessed to SBIDBR SBICR2 Figure 2 47 Example of when 87C874 H74 are a Master
118. nerated read bit 6 INT2EDT in EINTCR2 4500254 that is at the beginning of the interrupt processing routine INT2EDT is valid only for both edge interrupts INT2W 1 INT2EDT isset to 1 by an interrupt as the non selected edge cleared to 0 after read automatically For both edge interrupts rising or falling edge is selected by setting modifying bit 2 INT2ES in EINTCR 400374 When rising edge is selected INT2ES 0 bit INT2EDT 490025 is set to 1 when a falling edge is detected at the INT2 pin That is remains O if rising edge is detected When falling edge is selected INT2ES 1 bit 6 in INT2EDT 0025 is set to 1 when a rising edge is detected at the INT2 pin That is remains 0 at falling edge The greatest care must be taken in setting or rewriting the external interrupt control register EINTCR 0037H For details see Figure 1 26 a note 2 3 4 5 and 6 in accordance with the using instructions 3 74 44 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Operation description for INT2 both edge interrupt in use 1 Operation without setting modifying external interrupt control register EINTCR after reset For both edge interrupts rising edge is selected INT2ES 0 and fixed 1 Case1 When the initial state of the INT2 pin is high after reset Reset INT2ES 20 Keep rising edge INT2W INT2 terminal DI ED f instruction L7 003CH bit7 Clear point of L
119. nput Eitherthe rising or falling edge can be selected with INT3ES Edge selection is the same as for the external interrupt input INT3 pin Source clock is used an internal clock selected with TC1CK The contents of TREG1A is compared with the contents of up counter If a match is found an INTTC1 interrupt is generated and the counter is cleared to 0 and halted The counter is restarted by the selected edge of the TC1 pin input The TC1 pin input has the same noise rejection as the INT3 pin therefore pulses of 7 fc s or less are rejected as noise A pulse width of 24 fc s or more is required for edge detection in NORMAL1 2 or IDLE1 2 mode The noise rejection circuit is turned off in SLOW and SLEEP modes But a pulse width of A fs s or more is required 3 74 69 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 count start count restart TC1 pininput A trigger trigger INT3ES 0 Internal clock ILIU LEUU UU LILI LU LLL LL 1 Up counter 1 INTTC1 a Trigger Start METT 0 count count count start clear start TC1 pin input trigger trigger trigger rising edge select INT3ES 0 Internal clock Up counter TREG1A INTTC1 b Trigger Start amp Stop METT1 1 Figure 2 21 External Trigger Timer Mode Timing Chart 3 Event Counter Mode In this mode events are counted on the edge of the TC1 pin input Either the rising or falling edge can be selected with INT3ES in EINTCR The contents of TREG1
120. ntrol input 1 During reset the output latches pata input are initialized to 1 A low frequency crystal 32 768 kHz is connected to pins P21 XTIN and P22 22 output XTOUT in the dual clock mode In the single clock mode pins P21 and P22 can be used as normal input output ports It is recommended that the P20 pin should be used as an external interrupt input a STOP mode release Note don tare signal input or an input port If used as an output port the interrupt latch is set on the falling edge of the output pulse When a read instruction for port P2 is executed bits 7 to 3 in P2 read in as undefined data Initial value 111 Data input 00024 Figure 2 5 Port P2 3 74 57 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 4 Port P3 P32 P30 Port P3 is an 3 bit input output port and is also used as serial bus interface SBI input output Input output mode is specified by the corresponding bit in the port P3 input output control register P3CR Port P3 is configured as an input if its corresponding P3CR bit is cleared to 0 and as an output if its corresponding P3CR bit is set to 1 During reset P3CR is initialized to 0 which configures port as input The output latches are also initialized to 0 Port is also used as a serial bus interface input output When used as a secondary function pin set P3 to the output mode using P3 port input output control register PSCR to c
121. nts of up counter are loaded into TREG3B by setting SCAP bit 6 in TC3CR to 1 SCAP is automatically cleared after capturing Table 2 5 Source Clock Internal Clock for Timer Counter 3 Maximum setting time NORMAL1 2 IDLE1 2 mode SLOW SLEEP mode DV7CK 0 DV7CK 1 fc 8 MHz fs 32 768 kHz fc 8 MHz fs 32 768 kHz fc 2 Hz fs 2 Hz fs 2 Hz 488 28 5 124 5 ms fc 2 fs 2 122 07 5 31 1 ms fc 27 2 Event Counter Mode In this mode the TC3 pin input pulses are used for counting up Either the rising or falling edge can be selected with INT3ES bit 3 in EINTCR The contents of TREG3A are compared with the contents of the up counter If a match is found an INTTC3 interrupt is generated and the counter is cleared The maximum applied frequency is fc 2 Hz in the NORMAL1 2 or IDLE1 2 mode fs 2 Hz in SLOW or SLEEP mode Two or more machine cycles are required for both the H and L levels of the pulse width The current contents of up counter are loaded into TREG3B by setting SCAP bit 6 in TC3CR to 1 SCAP is automatically cleared after capturing Example Generates an interrupt every 0 5 s inputing 50Hz pulses to the TC3 pin LD TC3CR 00001100 Sets TC3 mode source clock LD TREG3A 19H 0 5s 1 50 25 19 LD TC3CR 00011100B Start TC3 3 Capture Mode The pulse width period and duty of the TC3 pin input are measured in this mode which can be used in decoding the rem
122. o NORMAL mode regardless of the RETM contents fc high frequency clock Hz fs low frequency clock Hz don t care Bits 1 and 0 in 5 5 are read as undefined data when a read instruction is executed In STOP operation by setting OUTEN 0 an internal input is always set to 0 so that an interrupt of the falling edge may be set System Control Register 2 7 6 ES 3 2 0 0039 5 SYSCK IDLE 1 Initial value 10 100 s x High frequency oscillator Turn off oscillation control Turn on oscillation Low frequency oscillator 0 Turn off oscillation XTEN control 1 Turn on oscillation RAW Main system clock select write main system clock monitor read 0 CPU and watchdog timer remain active IDLE IDLE mode start CPU and watchdog timer are stopped start IDLE mode A reset is applied RESET pin output goes low if both XEN and XTEN are cleared to 0 Do not clear to 0 when SYSCK 20 and do not clear XTEN to 0 when SYSCK 1 WDT watchdog timer don t care Bits 3 0 in SYSCR2 are always read in as 1 when a read instruction is executed 9 High frequency clock Low frequency clock An optional initial value can be selected for XTEN Always specify when ordering ES engineering sample operating mode after reset 0 Single clock mode NORMAL 1 1 Dual clock mode 12 Figure 1 15 System Control Registers 3 74 20
123. of interrupt latches can be read out by an instruction Therefore testing interrupt requests by software is possible Example 1 Clears interrupt latches LDW IL 1110100000111111B 112 1166 0 Example 2 Reads interrupt latches LD WA IL WelLu 3 74 28 aba 5195 uononasul sem Ajuo NLY gt 951AI9s 3dna493ut Buunp 13 S 4 ejqeu3 1 4011 1dnuieiu aseajay lt 1enbei a He 1 1 1senbai sydnuejui ajqexsew uoN jsenbaa 3dnaje1u 55 o g 411044409 140 4914 zz L 941614 18584 eu183ut 0 OF S4e9 YOIYM 13 1140 193s1Boy ajqeug 40 1934 eqouns uononasul Ie I ie e Blo wo x nw seuxe1idnueiu Jeysibey Sydnuj83u t E ZYDLNII 4JaysiBay 041102 eu193X3 YOLNIA apum 97 14 lt Q HOSNI LOISLNI pafas asiou jeuibiq ynan asiou jeuibiq V2LLNI I8S 1NI 32efe4 asiou uonpejes IN _
124. of these ports can be individually configured as an input or an output under software control When used as a analog input the must be set to 0 4 bit programmable input output ports tri state Each bit of these ports can be individually configured as an input or an output under software control When used as a analog input the PSCR must be set to 0 Four 8 bit high brackdown voltage output ports with the latch When used as a VFT driver output the latch must be cleared to 0 5 bit high breakdown voltage output ports with the latch When used as a VFT driver output the latch must be cleared to 0 3 74 3 External interrupt input 4 or Timer Counter 3 input External interrupt input 0 Resonator connecting pins 32 768 kHz For inputting external clock XTIN is used and XTOUT is opened External interrupt input 5 or STOP mode release signal input SIOO serial clock input output I Cbus serial data input output or 5100 serial data output I2Cbus serial clock input output or 5100 serial data Input A D converter analog inputs A D converter analog inputs VFT driver outputs TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 PIN NAME Input Output FUNCTION XIN XOUT Input Output Resonator connecting pins for high frequency clock For inputting external clock XIN is used and XOUT is opened EeEF Reset signal input or watchdog timer output address trap reset output system RESET 1 0 clock
125. on following the STOP mode start instruction e g SET SYSCR1 7 The start is made after the divider of the timing generator is cleared to 0 Table 1 1 Warming up Time example Return to NORMAL1 mode Return to SLOW mode At cz4 194304MHz At fc 8MHz At fs 32 768 kHz 3x2 fc s 375 ms 196 6 ms 3x2 fs 750 ms 125 65 5 2 fs The warming up time is obtained by dividing the basic clock by the divider therefore the warming up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released Thus the warming up time must be considered an approximate value STOP mode can also be released by setting the RESET pin low which immediately performs the normal reset operation 3 74 22 aseajay HEIS PON 4015 81 1 941614 asea ay PON 4015 9 XN 0 HWY 222 yndino Hed esseppe 3e e sseyppe3e uononaasul 210151 uonn exe Jey uor2najsul Jejuno Ue160Jg 15 5 uo uin ijjo uan 11020 10161150 1 dn uiue M e 5 pe1e o 1H2SAS LIS YLM 34838 HEIS 4016 Japiaig indino 0 N31n0 Z IH u on naisu ue160Jg WaysAs uo uum 2042111250 uim TOSHIBA UND
126. ontrol input output by the output data P3 is sink open drain with input output control At 1 of the output data a pin isset to Hi z and enabled to input When a read instruction for port P3 is executed bit 7 to 3 in P3 read in asundefined data STOP OUTEN P3CRi Data input Data output Output latch Control output Control input P Note 1 don tcare Note 2 2100 0 P32 P31 P30 SCL SDA SIO 500 5CK0 Initial value 111 3 2 1 0 mp Initial value 000 0 Input mode P3CR If P 1 Output mode Figure 2 6 Port P3 Note The port set to the input mode reads the state of the pin input When the port s used both in input and in output modes the output latch data of the port set to the input mode may be rewritten by execution of the bit manipulation instruction 3 74 58 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 5 Port P4 P47 P40 Ports P4 is an 8 bit input output port which can be configured as an input or an output in one bit unit under software control Input output mode is specified by the corresponding bit in the port P4 input output control register P4CR At reset PACR is set to 0 and AINDS is cleared to 0 Thus P4 becomes an analog input port At the same time the output latch of port is initialized to 0 is a write only register Pins not used for analog input can be used as I O ports But do not execute the output instructio
127. ote control signals etc The counter is free running by the internal clock On the rising falling edge of the TC3 pin input the current contents of counter is loaded into TREG3A then the up counter is cleared and an INTTC3 interrupt is generated On the falling rising edge of the TC3 pin input the current contents of the counter is loaded into the TREG3B In this case counting continues At the next rising falling edge of the pin input the current contents of counter are loaded into TREG3A then the counter is cleared again and an interrupt is generated If the counter overflows before the edge is detected FFy isset to the TREG3A and an overflow interrupt INTTC3 is generated During interrupt processing it can be determined whether or not there is an overflow by checking whether or not the TREG3A value is FFy Also after an interrupt capture to TREG3A or overflow detection is generated capture and overflow detection are halted until TREG3A has been read out however the counter continues 3 74 78 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Up counter AA Gd 63 7069 Ed 3 pin input A YO 5 TREG3A T capture S capture overflow INTTC3 interrupt Reading TREG3A TREG3B Figure 2 32 Timing Chart for Capture Mode INT3ES 0 INT4 TC3 input pulse width measurem
128. port P13 as an output SET P1 3 P13 output latch 1 output waveform LD TBTCR 111000008 Enables divider output JRS T Loops endless 4 lt 1024 1 8 2 Timing Generator The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware The timing generator provides the following functions D Generation of main system clock 2 Generation of divider output DVO pulses Generation of source clocks for time base timer Generation of source clocks for watchdog timer Generation of internal source clocks for timer counters TC1 Generation of internal clocks for serial interfaces SIO and HSO Generation of source clocks for driver circuit Generation of warm up clocks for releasing STOP mode Generation of a clock for releasing reset output 1 Configuration of Timing Generator The timing generator consists of a 21 stage divider with a divided by 4 prescaler a main system clock generator and machine cycle counters An input clock to the 7th stage of the divider depends on 3 74 15 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 the operating mode and DV7CK bit 4 in TBTCR shown in Figure 1 11 as follows During reset and upon releasing STOP mode the divider is cleared to 0 however the prescaler is not cleared D In the single clock mode A divided by 256 of high frequency clock fc 28 is input to the 7th stage of the divider Q I
129. put signal via port is high level Note4 SBICR2 is write only register which cannot access any of in read modify write instruction such as bit operate etc Serial Bus Interface Status Register SBISR CHEA E 00234 age i 1 stor ser Serial transfer operating status 0 Transfer terminated monitor 1 Transfer in process Shift operating status monitor 0 Shift operation terminated 1 Shift operation in process Figure 2 54 Control Register Data Buffer Register Status Register in SIO Mode 3 74 98 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 Serial clock a Clock source The SCK bits 2 to 0 SBICR1 is used to select the following functions D Internal clock In an internal clock mode any of seven frequencies can be selected The serial clock is output to the outside on the SCKO pin The SCKO pin becomes a high level when data transfer starts When writing in the transmit mode or reading in the receive mode data cannot follow the serial clock rate an automatic wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is complete automatic wait function SCK pin output 2 1 2 e 171 lel 1 2 3 SOpinoutput Nav Cas Xe CX 4 2 8 transmitted Figure 2 55 Automatic Wait Function External clock SCK 111 An external clock supp
130. r 7 Inst R t XIN Interfaces esonator 57007 Connectiong VXOUT 22 Bl WT P22 VAREF P47 AIN7 P53 AIN13 P17 P07 P32 to VASS to to to to to P20 P40 AINO P50 AIN10 P10 POO P30 Vo Ports Ports 3 74 2 TOSHIBA PIN FUNCTION UNDER DEVELOPMENT TMP87C874 H74 PIN NAME Input Output FUNCTION 10 Output Input VO 1 0 VO Input VO I O Output VO 1 0 Input Output VO Input 10 I O l O Output VO 1 O Input toP40 AINo O Input P53 AIN13 toP50 10 Input Output P97 V31 to P90 V24 PD4 V36 toPDO V32 Two 8 bit programmable input output ports tri state Each bit of these ports can be individually configured as an input or an output under software control When used as a SIO input output an External interrupt input a timer counter input the latch must be set to 0 When used as a PPG output or divider output the latch must be set to 1 3 bit input output port with latch When used as input port or external interrupt input STOP mode release signal input the latch must be set to pi odd 3 bit programmable input output ports Sink open drain Each bit of these ports can be individually configured as an input or an output under software control When used as a 12 input output the latch must be set to 1 8 bit programmable input output ports tri state Each bit
131. r In The 12 Bus Mode 3 74 88 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 Acknowledge mode specification Set the ACK bit 4 in SBICR1 to 1 for operation in the acknowledge mode The 87C874 H74 generate an additional clock pulse for an acknowledge signal when operating in the master mode In the transmitter mode during the clock pulse cycle the SDA pin is released in order to receive the acknowledge signal from the receiver In the receiver mode during the clock pulse cycle the SDA pin is set to the low level in order to generate the acknowledge signal Reset the ACK for operation in the non acknowledge mode The 87C874 H74 do not generate a clock pulse for the acknowledge signal when operating in the master mode 2 Number of transfer bits The BC bits 7 to 5 in SBICR1 is used to select a number of bits for transmitting and receiving data Since the BC is cleared to 000 as a start condition a slave address and direction bit transmissions are always executed in 8 bits Other than these the BC retains a specified value 3 Serial clock a Clock source The SCK bits 2 to 0 in SBICR1 is used to select a maximum transfer frequency output from the SCL pin in the master mode ty gt lt tow lt 5 SCK bits2 to 0 in the SBICR1 27 7 tHIGH 2 ffc 12 fc fscl 1 tLow tuin Note fc High frequency clock Figure 2 42 Clock Source b Clock synchronization In the I2C
132. r the counter is cleared Also when fc is selected as the source clock during SLOW mode the lower 11 bits of TREG2 are ignored and an INTTC2 interrupt is generated by matching the upper 5 bits Thus in this case only the 2 setting is necessary 3 74 75 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Table 2 4 Source Clock Internal Clock for Timer Counter 2 Resolution Maximum time setting NORMAL1 2 IDLE1 2 mode SLOW mode SLEEP mode DV7CK 0 DV7CK 1 At fc 8 MHz At fs 32 768 kHz At fc 8 MHz At fs 32 768 kHz fc 22 Hz fs 2 Hz fs 2 Hz fs 25 Hz 1 s 18 2 h fc 2 16 25 15 25 1 25 0 98 5 i 1 07 min fc 2 fc 28 fc 22 1 23 fc Note fs fs 30 5 ys Note fc can be used only in the timer mode Example Sets the timer mode with source clock fc 23 Hz and generates an interrupt every 25 ms at fc 8 MHz LDW TREG2 61A8H Sets TREG2 25 ms 23 fc 61 8 SET EIRH EF14 INTTC2 interrupt enable EI LD TC2CR 00101100B Starts TC2 2 Event Counter Mode In this mode events are counted on the rising edge of the TC2 pin input The contents of TREG2 are compared with the contents of the up counter If a match is found an INTTC2 interrupt is generated and the counter is cleared The maximum frequency applied to the TC2 pin is fc 24 Hz in NORMAL1 2 or IDLE1 2 mode and fs 24 Hz in SLOW or SLEEP mode Example Sets the event counter mode and generates an INTT2 int
133. reset outputted TEST Test pin for out going test Be tied to low VDD VSS 5V GND Power Supply VFT driver power supply VAREF VASS Analog reference voltage inputs High Low 3 74 4 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 OPERATIONAL DESCRIPTION 1 CPU CORE FUNCTIONS The CPU core consists of a CPU asystem clock controller an interrupt controller and a watchdog timer This section provides a description of the CPU core the program memory ROM the data memory RAM and the reset circuit 11 Memory Address The TLCS 870 Series is capable of addressing 64K bytes of memory Figure 1 1 shows the memory address maps of the 87C874 H74 In the TLCS 870 Series the memory is organized 4 address spaces ROM RAM SFR and DBR It uses a memory mapped I O system and all I O registers are mapped in the SFR DBR address spaces There are 16 banks of general purpose registers The register banks are also assigned to the first 128 bytes of the RAM address space Register banks 128 bytes 128 bytes 8 registers x 16 banks 896 bytes Read Only Memory includes Program memory Random Access Memory includes Data memory Stack General purpose register banks Special Function Register includes ports 128 bytes Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word Data Buffer Register includes 5 446128 bytes F 510
134. ress For example in the case of SIO the first buffer address transmitted is OFF8 Note6 The value to be loaded to BUF is held after transfer is completed Note7 SIO1CR2 are write only registers which cannot access any of in read modify write instruction such as bit operate etc 5101 SIO2 Status Registers SIO1SR 7 E 5 4 3 2 1 0 00204 SIOF sEF uni 2 2 SIOF Serial transfer operating m Transfer terminated status monitor Transfer in process read only SEF Shift operating status 0 Shift operation terminated monitor 1 Shift operation in process Figure 2 64 SIO Control Registers and Status Registers 1 Serial Clock a Clock Source SCK bits 2 0 in SIO1CR1 is able to select the following D Internal Clock Any of four frequencies can be selected The serial clock is output to the outside on the SCK1 pin The SCK pin goes high when transfer starts When data writing in the transmit mode or reading in the receive mode or the transmit receive mode cannot keep up with the serial clock rate there is a wait function that automatically stops the serial clock and holds the next shift operation until the read write processing is completed Table 2 9 Serial Clock Rate Serial clock Maximum transfer rate NORMAL1 2 IDLE1 2 mode SLOW SLEEP mode DV7CK 0 DV7CK 1 At fc 8 MHz At fs 32 768 kHz fc 29 fs 2 Hz 0 95 Kbit s fc 28 30 5 fc 2 122 fc 25
135. rogrammable divider output modes Time Base Timer Interrupt frequency 1 Hz 16384 kHz Divider output function frequency 1kHzto 8 kHz Watchdog Timer e Interrupt source reset output programmable 8 bit Serial Interface e With 8 bytes transmit receive data buffer Internal external serial clock and 4 8 bit mode Serial bus Interface 12 8 bit SIO modes 8 bit successive approximate type A D converter with sample and hold e 12 analog inputs Conversion time 23 us at 8 MHz Vacuum Fluorescent Tube Driver automatic display Programmable grid scan High breakdown voltage ports max 40V 37 bits Dual clock operation e Single Dual clock mode option Five Power saving operating modes STOP mode Oscillation stops Battery Capacitor back up Port output hold High impedance SLOW mode Low power consumption operation using low frequency clock 32 768 kHz IDLE1 mode CPU stops and Peripherals operate using high frequency clock Release by interrupts IDLE2 mode CPU stops and Peripherals operate using high and low frequency clock Release by interrupts SLEEP mode CPU stops and Peripherals operate using low frequency clock Release by interrupts Wide operating voltage 2 7 to 5 5 V at 32 768 kHz 4 5 to 5 5 V at 8 MHz 32 768 kHz Emulation Pod BM87CM75F0A Purchase of TOSHIBA I C components conveys a license under the Philips I C Patent Rights to use t
136. rt Example Duty measurement Resolution 27 Hz CLR INTTC1C 0 INTTC1 service switch initial setting LD EINTCR 00000000B Sets the rise edge at the INT3 edge LD TC1CR 00000110B Setsthe TC1 mode and source clock SET EIRL 4 Enables INTTC1 El LD TC1CR 00110110B Starts TC1 with an external trigger PINTTC1 CPL INTTC1C O Complements service switch JRS F SINTTC1 LD HPULSE TREG1BL Reads TREG1B LD HPULSE 1 TREG1BH RETI SINTTC1 LD WIDTH TREG1BL Reads TREG1B Period LD WIDTH 1 TREG1BH VINTTC1 DW PINTTC1 3 74 72 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 6 Programmable Pulse Generate PPG output mode Counting is started by an edge of the TC1 pin input either the rising or falling edge can be selected or by a command The source clock is used an internal clock First the contents of TREG1B are compared with the contents of the up counter If a match is found timer F F1 output is toggled Next timer F F1 is again toggled and the counter is cleared by matching with TREG1A An INTTC1 interrupt is generated at this time Timer F F output is connected to the P12 PPG pin In the case of PPG output set the P12 output latch to 1 and configure as an output with P1CR4 Timer F F1 is cleared to 0 during reset The timer F F1 value can also be set by program and either a positive or negative logic pulse output is available Also writing to the TREG1B is not possibl
137. ry The instruction to be executed next is read from the address indicated by the current contents of the program counter PC There are relative jump and absolute jump instructions The concepts of page or bank boundaries are not used in the program memory concerning any jump instruction Address ROM Example The relationship between the 8000 contents jump instructions and the PC D 5 bit PC relative jump JRS cc 2 d i tc NA E8C4H 185 T 2 08H and Call group When 1 the jump is made to instructions Interrupt which is 084 added to the contents of the Reset PC The PC contains the address of the instruction being executed 2 7BH PC FF7Bu therefore in this case the PC contents are E8C4y 2 8 call vector L CALLV OH 856 call vector H 8 bit PC relative jump JR cc 2 d E8C4H Z 2 80H When ZF 1 the jump is made to E8464 which is FF80q4 128 added to the current contents of the PC interrupt vector D 68 PC D3684 interrupt vector D3 16 bit absolute jump E8C4H 0 235 An unconditional jump is made to address 235 The absolute jump instruction can jump anywhere within the entire 64K byte space reset vector L RESET PC lt CO3E reset vector Figure 1 2 Program Memory Map In the TLCS 870 Series the same instruction used to access the data memory e g LD A H
138. spectively Flag after execution i CF HF JF PZF i ROLC RORC ADD 0F508H MUL SET A 5 1 7 Stack and Stack Pointer 1 7 1 Stack The stack provides the area in which the return address or status etc are saved before a jump is performed to the processing routine during the execution of a subroutine call instruction or the acceptance of an interrupt On a subroutine call instruction the contents of the PC the return address is saved on an interrupt acceptance the contents of the PC and the PSW are saved the PSW is pushed first followed by PCy and Therefore a subroutine call occupies two bytes on the stack an interrupt occupies three bytes When returning from the processing routine executing a subroutine return instruction RET restores the contents to the PC from the stack executing an interrupt return instruction RETI RETN restores the contents to the PC and the PSW the PC is popped first followed by PCy and PSW The stack can be located anywhere within the data memory space except the register bank area therefore the stack depth is limited only by the free data memory size 3 74 13 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 1 7 2 Stack Pointer SP The stack pointer SP is a 16 bit register containing the address of the next free locations on the stack The SP is postdecremented when a subroutine call or a push instruction is executed or when interrupt is accept
139. ss 5 5 25 V 2 50 x number of segments X 1 18 605 mW x X 1 Therefore Pmax 88 mW 48 mW 6 mW x X 18 605 mWx X 1 152 605 mW 24 605X Maximum power consumption Pd when Ta 50 C is determined by the following equation PD 1200 mW 14 3 x 25 842 5 mW The number of segments X which can be lit is PD gt Pmax 842 5 mW gt 152 605 24 605 X 28 gt X Thus a fluorescent display tube with less than 28 segments be used If a fluorescent display tube with 28 segments or more is used either a pull down resistor must be attached externally or the number of segments to be lit must be kept to less than 28 by software 3 74 129 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 D C CHARACTERISTICS 20 V 30 to 70 C PARAMETER PINS CONDITIONS Min Max UNIT Hysteresis Voltage Hysteresis input re ens rae TEST uA Open drain ports Tri state ports 5 5 t Input Current RESET STOP Vix 5 5 V 0 V PD ports Note3 Input Resistance RESET Po 100 Pull down Resistance Source open drain ports Sink open drain ports Output Leakage Source open drain ports and tri Current state Sork 5 5 Vour 32V 2 220 450 Tri state ports 5 5 V Vout 5 5V 0V Tri state ports Vpp 24 5 lou 0 7 mA Output High Voltage P8 P9 PD 4 5 8mA Output Low Voltage Except XOUT PO P10 to P14 P
140. t continues The counter value m is fetched to TREG3B at the next non selected rising edge At this time INT4 is generated Simultaneously bit 6 in INT4EDT 0024 is set to 1 The interrupt processing routine for INT4 enables timer 3 interrupts and disables INT4 interrupts to detect the next edge selected edge at 05 D Same as 2 resumes next capture overflow detect TREG3B value m read at is necessary to determine in Figure 2 33 At 3 0024 is read bit 6 INTAEDT and bit 2 INTAEDT are set to 1 After read bits 6 and 2 are both cleared 5 16 Timer 3 count continues The counter value n is fetched to TREG3A at the next selected rising edge The counter is zero cleared At the same time INT4 is generated 8 Interrupt processing for INT4 resumes at the next capture overflow detect as at D TwH is determined by TREG3A value n and TREG3B value m read at 3 74 79 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Counter value o 30037 40024 35 1 SCAP 1 INT4ES 1 INTAW 1 lt TwL TuL INT4 TC3 input A 2 EL 1 L1 1 itd td INT4 INT4EDT 00244 bit6 v RD 0024 23 EEE For detecting For measuring For detecting RD 0019 TREG3B on overflow overflow b For meauring RD 0018 TREG3A TwH Y Y Note fsource depends on a value set in 001A
141. t latch data of the port set to the input mode may be rewritten by execution of the bit manipulation instruction 3 74 55 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 2 2 Port P1 P17 P10 Port P1 is an 8 bit input output port which can be configured as an input or an output in one bit unit under software control Input output mode is specified by the corresponding bit in the port P1 input output control register P1CR Port P1 is configured as an input if its corresponding bit is cleared to 0 and as an output if its corresponding P1CR bit is set to 1 During reset P1CR is initialized to 0 which configures port P1 as an input The P1 output latches are also initialized to 0 Data is written into the output latch regardless of P1CR contents Therfore initial output data should be written into the output latch before setting P1CR Port P1 is also used as an external interrupt input a timer counter input output and a divider output When used as a secondary function pin the input pins should be set to the input mode and the output pins should be set to the output mode and beforehand the output latch should be set to 1 It is recommended that pins P11 and P15 P16 P17 should be used as external interrupt inputs timer counter input or input ports The interrupt latch is set on the rising or falling edge of the output when used as output ports Pin P10 INTO can be configured as either an I O port or an external interrupt
142. t master enable flag IMF Releasing the IDLE mode returns from IDLE1 to NORMAL1 from IDLE2 to NORMAL2 and from SLEEP to SLOW mode Execution of the a Normal release mode IMF 0 instruction which follows the IDLE mode start IDLE mode is released by any interrupt source instruction enabled by the individual interrupt enable flag EF or an external interrupt 0 INTO pin request Execution resumes with the instruction following the IDLE mode start instruction e g SET Figure 1 19 IDLE Mode SYSCR2 4 b Interrupt release mode IMF 1 IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag EF or an external interrupt 0 INTO pin request After the interrupt is processed the execution resumes from the instruction following the instruction which started IDLE mode IDLE mode can also be released by setting the RESET pin low which immediately performs the reset operation After reset the 87C874 H74 are placed in NORMAL mode Note When a watchdog timer interrupt is generated immediately before IDLE mode is started the watchdog timer interrupt will be processed but IDLE mode will not be started 3 74 24 702 1 941614 aseajay PON 9 apo Jo uonn exe uononJajsu
143. tched conclude receiving data by clearing the SIOS to 0 read the last data and then switch the mode 3 74 102 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 P Cear 5105 1 SEF MENS ba SCK pin output SI pin INTSBI interrupt request SBIDBR Read received data Read received data Figure 2 60 Receive Mode Example Internal clock 3 74 103 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 c 8 bittransmit receive mode Set a control register to a transmit receive mode and write data to the SBIDBR After the data is written set the SIOS to 1 to start transmitting receiving When transmitting the data is output from the SO pin on the leading edges in synchronous with the serial clock starting from the least significant bit LSB When receiving the data is input to the SI pin on the trailing edges of the serial clock 8 bit data is transferred from the shift register to the SBIDBR and the INTSBI interrupt request occurs The interrupt service program reads the received data from the shift register to the SBIDBR and the INTSBI interrupt request occurs The interrupt service program reads the received data from the data buffer register and writes data to be transmitted The SBIDBR is used for both transmitting and receiving Transmitted data should always be written after received data is read When the internal clock is used automatic wait function is initiated until received d
144. the 87C874 H74 pulls down the SCL pin to the low level The 87C874 H74 output a clock pulse for 1 word of data transfer and the acknowledge signal each time that received data is read from the SBIDBR INTSBI Cn interrupt request m Figure 2 50 Example when BC 000 ACK 1 In order to terminate transmitting data to a transmitter clear the ACK to 0 before reading data which is 1 word before the last data to be received The last data does not generate a clock pulse for the acknowledge signal After the data is transmitted and an interrupt request has occurred set the BC to 001 and read the data The 87C874 H74 generates a clock pulse for a 1 bit data transfer Since the master device is a receiver the SDA line of the bus keeps the high level The transmitter receives the high level signal as an ACK signal The receiver indicates to the transmitter that data transfer is complete After 1 bit data is received and an interrupt request has occurred the 87C874 H74 generates a stop condition and terminates data transfer 3 74 95 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Acknowledge signal sent to a transmitter INTSBI interrupt request 0 SACK 001 gt BC Read SBIDBR Read SBIDBR Figure 2 51 Termination of Data Transfer in Master Receiver Mode b When the MST is 0 Slave mode In the slave mode an INTSBI interrupt request occurs when the 87C874 H74 receive a slave address or a GENERAL CALL from the master
145. the memory access instruction LD A 003FH LD 003FH A however the flags can only be read When writing to the PSW the change specified by the instruction is made without writing data to the flags For example when the instruction LD 003FH 05H is executed 5 is written to the RBS and the JF isset to 1 but the other flags are not affected PUSH PSW and POP PSW are the PSW access instructions 1 6 1 Register Bank Selector RBS The register bank selector RBS is a 4 bit register used to select general purpose register banks For example when RBS 2 bank 2 is currently selected During reset the RBS is initialized to 0 Figure 1 6 PSW Flags RBS Configuration 1 6 2 Flags The flags are configured with the upper 4 bits a zero flag a carry flag a half carry flag and a jump status flag The flags are set or cleared under conditions specified by the instruction These flags except the half carry flag are used as jump condition cc for conditional jump instructions JR cc 2 d JRS cc 2 d After reset the jump status flag is initialized to 1 other flags are not affected 1 Zero flag ZF The ZF is set to 1 if the operation result or the transfer data is 004 for 8 bit operations and data transfers 0000y for 16 bit operations otherwise the ZF is cleared to 0 During the bit manipulation instruction SET CLR and CPL the ZF is set to 1 if the contents of the specified bit
146. tial value 000 0000 15 16 x tdisp 5 14 16 x tdisp 5 12 16 x tdisp s 10 16 x tdisp s 8 16 x tdisp s 6 16 x tdisp s 4 16 x tdisp 5 2 16 x tdisp 5 1 display mode 2 display mode T1 to TO 3 display mode 72 to TO 4 display mode 3 to TO 5 display mode T4 to TO 6display mode T5 to TO 7 display mode T6 to TO 8display mode 7 to TO 9 display mode T8 to TO 10 display mode T9 to TO 11 display mode T10 to TO 12 display mode T11 to TO 13 display mode T12 to TO 14 display mode T13 to TO 15display mode T14 to TO 16 display mode T15 to TO Dimmer time select Number of state display VFTCR2 is write only register which cannot use any of in read modify write instruction such as bit operate etc Even if a number of the display digit is set a pin which is equal to the digit dose not output It is necessary to write data to the data buffer which corresponds to the digit according to the display timing TO to T15 don t care WAIT VFT operational status VFT display in operation read monitor VFT display operation disabled only Figure 2 81 VFT control Register 2 VFT status register 1 Setting of Display mode VFT display mode is set by VFT control register 1 VFTCR1 and VFT control register 2 VFTCR2 VFT control register 1 VFTCR1 sets 1 display time tdisp and the number of display lines
147. tial value 0000 0000 3 0 23 ps at fc 8 MHz Conversion time select 1 92 ps at fc 8 MHz ADS A D conversion start 3 1 A D conversion start EOCF End of A D conversion flag 0 Under conversion or Before conversion 1 End of conversion don t Analog input selection 0 Enabl nable AINDS Analog input control anos 1 Disable Select analog input when A D converter stops The ADS is automatically cleared to 0 after starting conversion The EOCF is cleared to 0 when reading the ADCDR The EOCF is read only Figure 2 76 A D converter control register and A D conversion result register 2 11 3 Operation Apply analog reference voltage to pins VAREF and VASS 1 Start of A D conversion First set the corressponding and 5 bit to 0 for analog input Clear the AINDS bit 4 in ADCCR to 0 and select one of eight analog input AIN13 AINO with the SAIN bits 3 0 in ADCCR The pin that is not used as an analog input can be used as regular input output pins During conversion do not perform output instruction to maintain a precision for all of the pins A D conversion is started by setting the ADS bit 6 in ADCCR to 1 Conversion is accomplished in 46 machine cycles 184 fc s When fc is 8 MHz it needs 23 5 The EOCF bit 7 in ADCCR isset to 1 at end of conversion Setting ADS to 1 in A D conversion starts converting over again
148. to the SBIM and 0 to bits 0 and 1 2 Start Condition and Slave Address Generation Confirm a bus free status when BB 0 Set the ACK to 1 and specify a slave address and a direction bit to be transmitted to the SBIDBR When the BB is 0 the start condition are generated and the slave address and the direction bit which are set to the SBIDBR are output on a bus by writing 1 to the MST TRX BB and PIN A slave device receives these data and pulls down the SDA line of the bus to the low level at the acknowledge signal timing An INTSBI interrupt request occurs at the 9th falling edge of the SCL clock cycle and the PIN is cleared to 0 The SCL pin is pulled down to the low level while the PIN is 04 When interrupt request occurs the changes by the hardware according to the direction bit only when an acknowledge signal is returned from the slave device SCL pin SDA pin Acknowledge Start condition Slave address direction bit signal from a lave device PIN INTSBI e interrupt request Figure 2 48 Start Condition Generation and Slave Address Transfer 3 1 word Data Transfer Check the MST by the INTSBI interrupt process after a 1 word data transfer is completed and determine whether the mode is a master or slave a When the MST is 1 Master mode Check the TRX and determine whether the mode is a transmitter or receiver D When the is 1 Transmitter mode Check the LRB
149. ts are cleared to 0 when receiving The data is transferred in sequence starting at the least significant bit LSB 3 74 109 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 3 Number of Words to Transfer Up to 8 words consisting of 4 bits of data 4 bit serial transfer or 8 bits 8 bit serial transfer of data can be transferred continuously The number of words to be transferred is loaded to BUF in SIOBCR An INTSIO interrupt is generated when the specified number of words has been transferred If the number of words is to be changed during transfer the serial interface must be stopped before making the change SCK1 pin 01 pin INTSIO interrupt a 1 Word Transmit scs 501 pin VX X X XP XE XE XE Xa Xa Ka INTSIO interrupt b 3 Words Transmit sce OM LE LE LI LI LILI LU 511 pin INTSIO interrupt c 3 Words Receive Figure 2 68 Number of Bits to Transfer Example 4 bit serial transfer 4 Transfer Mode SIOM bits 5 in SIO1CR1 is used to select the transmit receive or transmit receive mode a 4 bit and 8 bit Transmit Modes In these modes the SIO1CR1 is set to the transmit mode and then the data to be transmitted first are written to the data buffer registers DBR After the data are written the transmission is started by setting SIOS to 1 The data are then output sequentially to the SO pin in synchronous with t
150. typ VDD Sink open drain output Rin Hysteresis input R RESET Address trap reset Pull up resistor Watchdog imer rese D lt Rin 2220kQ System clock reset R 1 roH STOF NTS R Hysteresis input P20 R z1kQ 5 5 Pull down resistor TEST Rin 70 typ z1kQ Note The TEST of the 87 74 does not have a pull down resistor Note2 The 87PM74 is placed in the single clock mode during reset and the input output circuitries are the code NMI type 3 74 125 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 D Input Output Ports The input output circuitries of the 87C874 H74 input output ports are shown below any one of the circuitries can be chosen by a code A or D as a mask option yo INPUT OUTPUT CIRCUITRY CODE REMARKS initial Hi Z YDB Tri state I O Hysteresis input High current output disable PO P10 to P14 R 1kQ typ initial Hi Z Sink open drain output High current output R 1kQ initial Hi Z Sink open drain output Hysteresis input 34 R 1kQ initial Hi Z Tri state 1 disable initial Hi Z Source open drain output High breakdown voltage 80 typ R1 200 typ Note The input output circuitries of the 87PM74 I O ports are the code A type 3 74 126 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 2 Input Output Ports PORT 2 emere INPUT OUTPUT CIRCUITRY and CODE RE
151. upt is generated read bit 6 INT2EDT EINTCR2 00253 bit 6 INT3EDT in EINTCR3 00263 bit 6 INTAEDT in EINTCR4 0024 that is at the beginning of the Note 1 Note2 interrupt processing routine INT2EDT INT3EDT INT4EDT is valid only for both edge interrupts INT2W 1 1 INTAW 1 INT2EDT INT3EDT INTAEDT is set to 1 by an interrupt as the naon selected edge cleared to 0 after read automatically For both edge interrupts rising or falling edge is selected by setting modifying bit 2 INT2ES bit 3 INT3ES bit 4 INTAES in EINTCR 700374 When rising edge is selected INT3ES 0 bit 6 in INT3EDT 00265 is set to 1 when a falling edge is detected at the INT3 pin That is remains 0 if rising edge is detected When falling edge is selected INT3ES 1 bit 6 INT3EDT 00264 is set to 1 when a rising edge is detected at the INT3 pin That is remains 0 at falling edge Note 3 Note4 TC1 pin change INT3W to 1 The noise rejection function is also affected for timer counter input TC1 and TC3 pins Noise cancellation pulse receive conditions for timer counter are as described below When the P15 pin is used for TC1 input INT3W must be cleared to 0 Do not TC3pin When INTSW 0 less than 7 fc s noise cancellation and 24 fc s or more pulse receive For when INT3W z 1 see Table 1 4 Note 5 If a noiseless signal is input to the external interrupt pin in the NO
152. uring INT2W is set to 1 according to Note 3 4 5 at Figure 1 26 a Noise cancellation time select for INT2 digital noise filter valid only when INT2W 1 External Interrupt Control Register 3 EE 4 3 0207 initial value 0000 0055 INT3W INT3 both edge selection EE Refer to INT3ES Both edge detection INT3EDT Flag indicating an interrupt at Interrupt at selected edge or no interrupt selected edge non selected Interrupt at non selected edge edge when INT3W 1 for both edge interrupts 000 No noise cancellation 001 Cancels 26 fc x 7 6 fc as noise 010 Cancels 27 fc x 7 6 fc as noise 011 Cancels 28 fc x 7 6 fc as noise 100 Cancels 29 fc x 7 6 fc as noise 101 Cancels 219 fc x 7 6 fc as noise 110 Cancels 211 fc x 7 6 fc as noise 111 Cancels 212 fc x 7 6 fc as noise INT3DET INT3 interrupt detection flag 0 Nointerrupt 1 Interrupt Note 1 INT3EDT and 53 are valid only when the INT3W bit in EINTCR3 0026 is set to 1 Therefore when INT3W 0 the digital noise filter set by the NCS3 bit is disabled Note 2 Do not changing the contents of INT3ES bit 3 in 00374 when INT3W is set to 1 both edge detention If changing the contents of INT3ES during INT2W is set to 1 according to Note 3 4 5 at Figure 1 26 a Noise cancellation time select for INT3 digital noise filter valid only when INT3W 1 3 74 39 TOSHIBA UND
153. vice with the shortest high level period and the master device with the longest low level period from among those master devices connected to the bus 4 Slave address and address recognition mode specification When the 87C874 H74 are used as a slave device set the slave address and ALS to the I2CAR Set 0 to the ALS for the address recognition mode 5 Master slave selection Set the MST bit 7 in SBICR2 to 1 for operating the 87C874 H74 as a master device Reset the MST for operation as a slave device The MST is cleared to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost 6 Transmitter receiver selection Set the TRX bit SBICR2 to 1 for operating the 87C874 H74 as a transmitter Reset the TRX for operation as a receiver When data with an addressing format is transferred in the slave mode when a slave address with the same value that an I2CAR or a GENERAL CALL is received the TRX is set to 1 if the direction bit RAV sent from the master device is 1 and is cleared to 0 if the bit is 0 In the master mode after an acknowledge signal is returned from the slave device with the hardware the is set to 0 if a transmitted direction bit is 1 and set to 1 if it is 0 When an acknowledge signal is not returned the current condition is maintained The TRX is cleared to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost
154. y contents at the address specified by new HL into A The TLCS 870 Series can transfer data directly memory to memory and operate directly between memory data and memory data This facilitates the programming of block processing 3 74 10 TOSHIBA UNDER DEVELOPMENT TMP87C874 H74 Example 2 Block transfer LD B n 1 Sets number of bytes to transfer 1 to B LD HL DSTA Setsdestination address to HL LD DE SRCA Setssource address to DE SLOOP LD HL DE HL lt DE INC HL INC DE DEC B JRS F SLOOP 3 B C BC Registers B and C can be used as 8 bit buffers or counters and the BC register pair can be used as a 16 bit buffer or counter The C register functions as an offset register for register offset index addressing refer to example 1 above and as a divisor register for the division instruction DIV gg C Example 1 Repeat processing Sets as the number of repetitions to B SREPEAT processing n 1 times processing DEC B JRS F SREPEAT Example2 Unsigned integer division 16 bit 8 bit DIV WA C Divides the WA contents by the C contents places the quotient A and the remainder in W The general purpose register banks are selected by the 4 bit register bank selector RBS During reset the RBS is initialized to 0 The bank selected by the RBS is called the current bank Together with the flag the RBS is assigned to address 003Fy in the SFR as the program status word P

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TOSHIBA TMP87C874F TMP87CH74F handbook

TOSHIBA TMP87C874F TMP87CH74F handbook

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